Method for manufacturing a semiconductor body, semiconductor body and power semiconductor device

Abstract

According to one embodiment, a method for manufacturing a semiconductor body (10) comprises the steps of providing a first semiconductor layer (1) made of SiC, the further step of introducing carbon into the first semiconductor layer such that at least a portion of the first semiconductor layer is at least one C-rich region (11), and growing a second semiconductor layer (2) made of SiC on the first semiconductor layer comprising the at least one C-rich region.

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor body, a semiconductor body, and a power semiconductor device. Summary of the Invention [Problem to be solved by the invention]

[0002] There is a need for improved methods for manufacturing semiconductor bodies, for example methods that allow for manufacturing semiconductor bodies having high charge carrier mobility. A further object to be achieved is to provide improved semiconductor bodies, for example having high charge carrier mobility. Another object to be achieved is to provide a power semiconductor device comprising such a semiconductor body. [Means for solving the problem]

[0003] SUMMARY OF THE INVENTION Embodiments of the present disclosure relate to improved methods for manufacturing a semiconductor body, improved semiconductor bodies, and improved power semiconductor devices.

[0004] According to one embodiment, a method for manufacturing a semiconductor body comprises the steps of providing a first semiconductor layer made of silicon carbide, SiC for short, and the further step of introducing carbon, C for short, into the first semiconductor layer such that at least a portion of the first semiconductor layer has at least one carbon-rich region, C-rich region for short, and growing a second semiconductor layer made of SiC on the first semiconductor layer comprising the at least one C-rich region.

[0005] The present invention is based, inter alia, on the recognition that carbon vacancies are the most important point defects in SiC, e.g., n-type 4H-SiC. 1 / 2 and E.H. 6 / 7 These give rise to two electrically active levels within the band gap, labeled Z, located at 0.65 eV and 1.6 eV below the conduction band edge, respectively. 1 / 2is known to be a recombination center and affects the lifetime of bipolar devices.

[0006] The inventors have conceived the idea of ​​forming at least one C-rich region inside the semiconductor layer sequence, which eventually releases carbon from interstitials, which then anneals carbon vacancies. Due to the fact that at least one C-rich region is formed during the formation of the semiconductor layer sequence, i.e., after the first semiconductor layer is provided and before the second semiconductor layer is grown, the C-rich region can be formed inside the semiconductor layer sequence, thereby more efficiently providing carbon from carbon interstitials to all regions of the semiconductor layer sequence.

[0007] Furthermore, forming at least one C-rich region during the formation of the semiconductor layer sequence, as proposed herein, is advantageous compared to forming a C-rich region after the semiconductor layer sequence has been fully grown. This is because, in the second case, forming a C-rich region inside the semiconductor layer sequence must be performed by deep C ion implantation, which requires high implantation energy. This makes the process expensive and also amorphizes the crystal, thus creating a more electrically active level. The method proposed herein is cheaper and gentler than deep ion implantation, i.e., it creates a much lower activity level.

[0008] The first semiconductor layer may be provided, for example, as a continuous layer without interruption. Providing the first semiconductor layer may include growing, for example, epitaxially growing, the first semiconductor layer on a substrate. The first semiconductor layer may be grown by chemical vapor deposition, abbreviated as CVD. The substrate may be, for example, SiC. The substrate may be doped, for example, n-doped. The doping concentration in the substrate may be at least 10 18 cm -3 may be.

[0009] The thickness of the first semiconductor layer may be, for example, at least 1 μm, at least 2 μm, or at least 5 μm. Additionally or alternatively, the thickness of the first semiconductor layer may be up to 30 μm or up to 20 μm. The thickness of the substrate may be greater than the thickness of the first semiconductor layer. For example, the thickness of the substrate may be at least 100 μm, at least 300 μm, and / or up to 600 μm or up to 400 μm.

[0010] In this specification, the thickness of a layer, region, or substrate is intended to be its extent in the vertical direction, i.e., perpendicular to the main extension plane of the first semiconductor layer. The SiC of the different semiconductor layers and / or substrates referred to in this specification is, for example, 4H-SiC, in particular n-doped 4H-SiC.

[0011] The first semiconductor layer may be doped, for example, n-doped. For example, the average and / or maximum doping concentration of the first semiconductor layer may be at least one order of magnitude, or at least two orders of magnitude, or at least three orders of magnitude less than the average and / or minimum doping concentration of the substrate. For example, the average doping concentration of the first semiconductor layer may be 10 14 cm -3 ~10 17 cm -3 The first semiconductor layer may already be n-doped when provided, for example, the first semiconductor layer is doped during its growth.

[0012] The step of introducing carbon into the first semiconductor layer is performed so that at least a portion of the first semiconductor layer becomes at least one C-rich region. In this specification, a C-rich region is understood as a region in which the carbon concentration is higher than that of an ideal SiC crystal. In the C-rich region, additional carbon atoms (C atoms) or carbon ions (C ions) are located, for example, in interstitial sites.

[0013] For example, a C-rich region is defined herein as a region in which the minimum and / or average concentration of C atoms or C ions in interstitial sites is at least 100 times, or at least 1000 times, or at least 10000 times greater than the maximum and / or average concentration in the remainder of the first semiconductor layer or in the first semiconductor layer before the carbon-introducing step is performed, respectively. Carbon in interstitial sites is typically charged, and therefore it is primarily C ions in interstitial sites.

[0014] As used herein, a minimum concentration in or of a region or layer etc. is intended to be the lowest concentration that can be found in that region, layer etc. Accordingly, a maximum concentration in or of a region, layer etc. is intended to be the highest concentration that can be found in that region, layer etc. An average concentration in or of a region, layer etc. is the concentration averaged over the entire volume of that region, layer etc.

[0015] For example, only a portion of the first semiconductor layer, rather than the entirety thereof, becomes a C-rich region. In one example, only the exposed surface region through which carbon enters the first semiconductor layer becomes C-rich. For example, up to 10%, or up to 5%, or up to 1% of the volume of the first semiconductor layer becomes at least one C-rich region.

[0016] "At least one C-rich region" means that only one contiguous region of the first semiconductor layer is a C-rich region, or alternatively, that multiple spatially separated regions of the first semiconductor layer are each a C-rich region. All features disclosed herein for one C-rich region are also disclosed for all other C-rich regions.

[0017] The introduction of carbon into the first semiconductor layer can be done by C ion implantation, or by annealing in a C-rich environment, such as CO2, CH4, or by PIII, for example. Once the carbon is introduced, it can be diffused by thermal annealing.

[0018] The second semiconductor layer is also made of SiC and is grown on the first semiconductor layer after the at least one C-rich region has been formed. That is, the second semiconductor layer is grown on the first semiconductor layer that already includes the at least one C-rich region. In particular, the second semiconductor layer is grown so as to partially or completely cover the at least one C-rich region. The main extension plane of the second semiconductor layer may be parallel to the main extension plane of the first semiconductor layer.

[0019] The second semiconductor layer may be epitaxially grown on the first semiconductor layer. For example, the second semiconductor layer may be grown directly on the first semiconductor layer, i.e., adjacent to the first semiconductor layer, particularly the at least one C-rich region. The growth technique may be similar to that used for the first semiconductor layer.

[0020] After growth, the second semiconductor layer may have a thickness of at least 2 μm or at least 5 μm. Additionally or alternatively, the thickness of the second semiconductor layer may be up to 30 μm or up to 20 μm. The second semiconductor layer may be grown, for example, as a continuous layer without interruptions. It may extend across the entire lateral extent of the first semiconductor layer, where the lateral direction is a direction parallel to the main extension plane of the first semiconductor layer.

[0021] During growth, the second semiconductor layer may be doped, for example n-doped, with a doping concentration, for example, the same as that specified for the first semiconductor layer.

[0022] According to a further embodiment, a C-rich region is formed on an exposed side of the first semiconductor layer, i.e., the C-rich region is formed adjacent to a top surface of the first semiconductor layer through which carbon is introduced and onto which the second semiconductor layer is subsequently grown.

[0023] According to a further embodiment, the C-rich region is formed such that after growing the second semiconductor layer, the C-rich region is located between the second semiconductor layer and the remaining portion of the first semiconductor layer that was not C-rich. In other words, the C-rich region is formed so as not to extend through the entire thickness of the first semiconductor layer. For example, the depth (thickness) of the C-rich region is at most 10%, at most 5%, or at most 1% of the thickness of the first semiconductor layer.

[0024] According to a further embodiment, carbon is introduced into the first semiconductor layer using plasma ion immersion implantation, or PIII for short. PIII is a particularly gentle implantation method that produces very shallow implants, i.e., implants with small depths (thicknesses). The use of PIII can be detected by SIMS in the final semiconductor body due to the unique implantation geometry produced by PIII and the presence of extraneous species derived from the precursors used.

[0025] According to a further embodiment, the method comprises the further step of implanting a first type dopant into a semiconductor layer sequence comprising a first semiconductor layer and a second semiconductor layer. That is, the first type dopant is implanted after growing the second semiconductor layer. The semiconductor layer sequence into which the first type dopant is implanted may comprise one or more additional semiconductor layers in addition to the first semiconductor layer and the second semiconductor layer. For example, at least one further semiconductor layer is grown before growing the first semiconductor layer and / or after growing the second semiconductor layer.

[0026] For example, the implantation of the first-type dopant is performed after the growth of the semiconductor layer sequence is completed, i.e., after all growth steps for producing the semiconductor body have been performed. For example, the first-type dopant is implanted into the semiconductor layer sequence through a side of the semiconductor layer sequence that is closer to the second semiconductor layer than the first semiconductor layer. For example, the first-type dopant is implanted to a depth such that it does not reach the C-rich region and / or the first semiconductor layer. For example, the first-type dopant is implanted into the second semiconductor layer. The first-type dopant may be a p-type dopant, such as boron. For example, a p-well is formed in the step of implanting the first-type dopant.

[0027] According to further embodiments, the first type dopant is activated at a temperature of at least 1000° C. or at least 1500° C. Additionally or alternatively, the temperature for activating the first type dopant may be up to 1800° C. or up to 1700° C.

[0028] Heating the semiconductor layer sequence to such temperatures also releases carbon at interstitial sites in the C-rich regions, which then recombine with carbon vacancies created during the implantation of the first type of dopant and / or existing carbon vacancies.

[0029] Additionally or alternatively, the semiconductor layer sequence may be heated to the aforementioned temperatures independently of the implantation of the first type dopant. For example, the semiconductor layer sequence may be heated to these temperatures before the implantation of the first type dopant, or even if no dopant implantation is performed at all. This heating has the same effect of releasing carbon from interstitial sites and eventually combining with carbon vacancies.

[0030] According to a further embodiment, the implantation is performed with an energy of C ions in the range of 0.5 keV to 100 keV, for example 1 keV to 50 keV, which allows to keep the damage caused by the implantation low.

[0031] According to a further embodiment, the minimum and / or average concentration of C atoms or C ions in interstitial sites is at least 10 in the C-rich region. 14 cm -3 or at least 10 16 cm -3 or at least 10 17 cm -3 or at least 10 18 cm -3 Additionally or alternatively, the maximum concentration of C atoms or C ions in interstitial sites is up to 10 in the C-rich region. 21 cm -3 In particular, a C-rich region can be defined as a region where this minimum concentration exists anywhere inside the region, or as a region with this average concentration.

[0032] According to a further embodiment, at least one buffer region of the second semiconductor layer is adjacent to the C-rich region and is doped with a second-type dopant, such as an n-type dopant. In particular, the second-type dopant has a different, i.e., opposite, conductivity type than the first-type dopant.

[0033] According to further embodiments, the minimum and / or average concentration of the second type dopant in at least one buffer region of the second semiconductor layer is greater than the maximum and / or average concentration of the second type dopant in the first semiconductor layer. For example, the minimum and / or average concentration of the second type dopant in the buffer region is at least 10 times, or at least 100 times, or at least 1000 times greater than the maximum and / or average concentration of the second type dopant in the first semiconductor layer. The minimum and / or average concentration of the second type dopant in the buffer region may, for example, be at least 10 16 cm -3 or at least 10 17 cm -3 Additionally or alternatively, the maximum and / or average concentration of the second type dopant in the buffer region is at most 10 19 cm-3 or up to 10 18 cm -3 Also, in this case, the buffer region may be defined by the region where the above condition of minimum doping concentration is met, or where the condition of average concentration is met.

[0034] The buffer region may be a buffer layer that extends, for example, continuously and without interruption, across the entire lateral extension range of the second semiconductor layer.

[0035] The C-rich region can introduce strains into the crystal lattice, and the buffer region can compensate for these strains, for example, improving the growth conditions for the rest of the second semiconductor layer.

[0036] According to a further embodiment, a plurality of C-rich regions spaced apart from one another in the laterally spaced direction are formed in the first semiconductor layer. The plurality of C-rich regions are formed, for example, by C ion implantation, during the step of introducing carbon into the first semiconductor layer. The C-rich regions of the first semiconductor layer may all be disposed at the same height relative to the main extension plane of the first semiconductor layer. That is, a plane parallel to the main extension plane of the first semiconductor layer intersects each of the C-rich regions in the first semiconductor layer.

[0037] For example, each of the C-rich regions has a lateral extension of at most 2 μm, or at most 1 μm, and / or at least 0.5 μm. The distance between each two adjacent C-rich regions measured laterally is, for example, at most 5 μm, or at most 2 μm, and / or at least 0.5 μm. The C-rich regions may be arranged on grid points of a regular grid. Each C-rich region may be, for example, a rectangular or circular region when viewed in plan from the side of the first semiconductor layer on which the second semiconductor layer is grown. Alternatively, the C-rich regions of the first semiconductor layer may be formed as stripes extending parallel to each other, for example.

[0038] Forming the multiple C-rich regions may be done, for example, by using a mask during a C ion implantation process.

[0039] According to a further embodiment, the method includes introducing carbon into the second semiconductor layer such that at least a portion of the second semiconductor layer becomes at least one C-rich region. All features disclosed in relation to the at least one C-rich region of the first semiconductor layer are also disclosed for the at least one C-rich region of the second semiconductor layer. For example, the C-rich region in the second semiconductor layer may be formed using the same method, e.g., PIII, used to form the C-rich region in the first semiconductor layer.

[0040] According to a further embodiment, the method includes growing a third semiconductor layer of SiC on the second semiconductor layer. For example, the third semiconductor layer is epitaxially grown. All features disclosed in relation to the second semiconductor layer are also disclosed for the third semiconductor layer, particularly with regard to doping and thickness.

[0041] According to further embodiments, a plurality of laterally spaced apart C-rich regions are formed in the second semiconductor layer, and features disclosed in relation to the plurality of C-rich regions in the first semiconductor layer are also disclosed for the plurality of C-rich regions in the second semiconductor layer.

[0042] According to a further embodiment, the C-rich regions in the first semiconductor layer and the C-rich regions in the second semiconductor layer are arranged in a staggered configuration. This means, in particular, that the C-rich regions of the first semiconductor layer at most partially overlap with the C-rich regions of the second semiconductor layer in at least one lateral direction. For example, the C-rich regions of the first semiconductor layer do not overlap with the C-rich regions of the second semiconductor layer in at least one lateral direction. The C-rich regions of the first semiconductor layer are arranged at a different height from the C-rich regions of the first semiconductor layer relative to a main extension plane of the first semiconductor layer, and do not overlap with each other in the vertical direction, for example.

[0043] Next, a semiconductor body is described. The semiconductor body may be manufactured by a method according to any one of the embodiments described herein, among other things. Accordingly, all features disclosed in relation to the method are also disclosed for the semiconductor body, and vice versa.

[0044] According to one embodiment, the semiconductor body comprises a first semiconductor layer made of SiC, a second semiconductor layer made of SiC on the first semiconductor layer, and at least one C-rich region in the first semiconductor layer, the C-rich region being adjacent to the second semiconductor layer. In the C-rich region, the minimum and / or average concentration of C atoms or C ions in interstitial sites is at least 10 17 cm -3 The C-rich region has a thickness of at most 100 nm, at most 50 nm, at most 30 nm, and / or at least 10 nm, or at least 15 nm, where the thickness is measured perpendicular to the major extension plane of the first semiconductor layer.

[0045] According to a further embodiment, the C-rich region has its maximum concentration of C atoms or C ions in interstitial sites at the interface with the second semiconductor layer. For example, the vertical concentration profile perpendicular to the main extension plane of the first semiconductor layer is asymmetric with respect to the interface between the first and second semiconductor layers. For example, the distance measured vertically from the interface where the concentration is below 0.01 times the maximum concentration is at least two or at least three orders of magnitude greater in the first semiconductor layer than in the second semiconductor layer. For example, the distance in the first semiconductor layer is at least 5 nm or at least 10 nm and / or at most 30 nm or at most 25 nm. The maximum concentration of C atoms / C ions in interstitial sites in the C-rich region is at least 10 19 cm -3 and / or up to 10 21 cm -3 may be.

[0046] The minimum and / or average concentration of C atoms / C ions in interstitial sites is at least 10 18 cm -3The thickness of the portion of the C-rich region where the minimum and / or average concentration of C atoms / C ions in interstitial sites is at least 10 19 cm -3 The thickness of the portion of the C-rich region where

[0047] According to a further embodiment, the maximum and / or average concentration of carbon vacancies, abbreviated C vacancies, in the second semiconductor layer is at most 10 12 cm -3 or up to 10 11 cm -3 This is especially true for Z 1 / 2 Refers to a void.

[0048] According to a further embodiment, the average mobility of the charge carriers and the second semiconductor layer is at least 100 cm at room temperature. 2 / Vs or at least 120cm 2 / Vs or at least 150cm 2 / Vs.

[0049] The described concentrations and described mobilities of C vacancies in the second semiconductor layer may be similarly valid for the first semiconductor layer. In the case of a third semiconductor layer grown on the second semiconductor layer, these values ​​may additionally or alternatively be valid for the third semiconductor layer.

[0050] Next, the power semiconductor device is described. The power semiconductor device comprises a semiconductor body according to any one of the embodiments described herein. The power semiconductor device further comprises an electrode in electrical contact with the semiconductor body. The electrode may be metal and / or highly doped polysilicon. The power semiconductor device is, for example, a transistor such as a MOSFET or an IGBT, or a thyristor.

[0051] Hereinafter, a method for manufacturing a semiconductor body, a semiconductor body, and a power semiconductor device will be described in more detail based on exemplary embodiments with reference to the drawings. The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale. To the extent that elements or components correspond to each other in terms of their function in different figures, their description will not be repeated for each of the following figures. For clarity, elements may not be labeled with corresponding reference numerals in all figures. [Brief explanation of the drawings]

[0052] [Figure 1] 3A-3C illustrate different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and an exemplary embodiment of a power semiconductor device. [Figure 2] 3A-3C illustrate different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and an exemplary embodiment of a power semiconductor device. [Figure 3] 3A-3C illustrate different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and an exemplary embodiment of a power semiconductor device. [Figure 4] 3A-3C illustrate different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and an exemplary embodiment of a power semiconductor device. [Figure 5] 3A-3C illustrate different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and an exemplary embodiment of a power semiconductor device. [Figure 6] 3A-3C illustrate different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and an exemplary embodiment of a power semiconductor device. [Figure 7]3A-3C illustrate different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and an exemplary embodiment of a power semiconductor device. [Figure 8] 3A-3C illustrate different positions in a first exemplary embodiment of the method, different exemplary embodiments of the semiconductor body, and an exemplary embodiment of a power semiconductor device. [Figure 9] FIG. 1 is a diagram showing a DLTS measurement curve. [Figure 10] FIG. 1 shows the curves of the concentration of C atoms or C ions at interstitial sites in the C-rich region produced by PIII. [Figure 11] FIG. 1 shows the curve of the concentration of C atoms in interstitial sites in the C-rich region created by deep ion implantation. [Figure 12] 5A-5C illustrate different positions in a second exemplary embodiment of the method, as well as exemplary embodiments of a semiconductor body and a power semiconductor device. [Figure 13] 5A-5C illustrate different positions in a second exemplary embodiment of the method, as well as exemplary embodiments of a semiconductor body and a power semiconductor device. [Figure 14] 5A-5C illustrate different positions in a second exemplary embodiment of the method, as well as exemplary embodiments of a semiconductor body and a power semiconductor device. [Figure 15] 10A-10D illustrate different positions and further exemplary embodiments of the semiconductor body in the third exemplary embodiment of the method. [Figure 16] 10A-10D illustrate different positions and further exemplary embodiments of the semiconductor body in the third exemplary embodiment of the method. [Figure 17] 10A-10D illustrate different positions and further exemplary embodiments of the semiconductor body in the third exemplary embodiment of the method. [Figure 18] 10A-10D illustrate different positions and further exemplary embodiments of the semiconductor body in the third exemplary embodiment of the method. [Figure 19] 1 illustrates a further exemplary embodiment of a semiconductor body; DETAILED DESCRIPTION OF THE INVENTION

[0053] 1, a substrate 4, for example an n-doped 4H—SiC substrate 4, is provided. The substrate 4 may be a standard 4° off-axis substrate.

[0054] In the position of Figure 2, a first semiconductor layer made of SiC, e.g., 4H-SiC, is epitaxially grown on a substrate 4. The growth may be performed by chemical vapor deposition, abbreviated CVD, e.g., hot wall chemical vapor deposition, abbreviated HWCVD. For example, the first semiconductor layer 1 is grown to a thickness of about 10 µm. During growth, the first semiconductor layer 1 may be doped with a dopant of a second type, in this case an n-type dopant.

[0055] At the position shown in FIG. 3, the growth process is interrupted and carbon is introduced into the first semiconductor layer 1, thereby forming a portion of the first semiconductor layer 1 into a C-rich region 11. Within the C-rich region 11, C atoms or ions accumulate in interstitial sites. The C-rich region 11 is formed only in a region of the exposed surface of the first semiconductor layer 1, i.e., at a very low depth, so that the C-rich region 11 does not extend through the entire thickness of the first semiconductor layer 1. As an example, this is achieved by implanting C ions using plasma ion immersion implantation (PIII). This implantation technique indeed makes it possible to form very shallow, well-defined implanted regions.

[0056] In FIG. 3, the C-rich region 11 extends continuously over the entire exposed surface of the first semiconductor layer 1 .

[0057] In the position of FIG. 4, a second semiconductor layer 2 is grown on the first semiconductor layer 1, i.e., directly on the C-rich region 11, until the desired thickness of the semiconductor layer sequence is obtained. The second semiconductor layer 2 also consists of SiC, e.g., 4H-SiC. The growth of the second semiconductor layer 2 may be performed using the same method as that used for the first semiconductor layer 1. The second semiconductor layer 2 may also be n-doped during growth.

[0058] 5, an implantation process is performed in which a second type of dopant, i.e., an n-type dopant, is implanted into the second semiconductor layer 2, resulting in the formation of a buffer region 20 adjacent to the C-rich region 11. The buffer region 20 has a higher average doping concentration than the rest of the first semiconductor layer 1 or the second semiconductor layer 2. This buffer region 20 compensates for the carbon-induced strain in the C-rich region 11.

[0059] In contrast to what is shown in FIG. 5, the buffer region 20 can already be created during the growth of the second semiconductor layer 2 .

[0060] 6, a further implantation process is carried out in which a first type of dopant (in this case a p-type dopant) is implanted, whereby a so-called p-well is formed in the second semiconductor layer 2.

[0061] 7, an annealing process is performed. The semiconductor body 10 is heated to a temperature in the range of 1500°C to 1700°C to activate the previously implanted first type dopants. During this, the C atoms or C ions in the interstitial C-rich regions 11 are partially released and fill the carbon vacancies in the semiconductor body 10.

[0062] 8 shows the final power semiconductor device 100 in the form of a MOSFET, which has been fabricated by further implanting the p-well with a second type of dopant to form contact regions, and applying main electrodes 5, 6 and a gate electrode 7 onto the semiconductor body 10.

[0063] In FIG. 9, the signal of Deep-Level Transient Spectroscopy, or DLTS for short, is shown for different semiconductor bodies as a function of temperature. Curve S9_1 shows the case of a semiconductor body made of SiC without any carbon vacancy reduction measures. Curve S9_1 shows the Z 1 / 2 The curve S9_2 shows the case where the semiconductor body has been oxidized. The carbon vacancies have disappeared. The curve S9_3 shows the result obtained when the semiconductor body 10 is produced as described above, i.e., by forming the C-rich region 11 by PIII. The carbon vacancies have also disappeared.

[0064] Figure 10 shows the concentration of interstitial C atoms / ions in the C-rich region 11 created in a SiC layer by using PIII as a function of depth, i.e., distance from the surface of the SiC layer where carbon is implanted. Curve S10_1 shows the concentration of interstitial C atoms / ions before heating to temperatures between 1500°C and 1700°C, and curve S10_2 shows the concentration after this heating. Due to the heating, some of the interstitial C atoms / ions recombine with C vacancies, resulting in a decrease in the concentration of interstitial C atoms / ions. As can be seen, the PIII technique produces a very shallow, rapidly decreasing concentration profile with a maximum concentration at the surface of the SiC layer where carbon enters the SiC layer.

[0065] For comparison, Figure 11 shows the concentration of C atoms / ions at interstitial sites when the C-rich region is formed by deep ion implantation, which uses a much higher ion energy than PIII. In this case, the maximum concentration is inside the SiC layer. This region is thicker and the profile is gentler than in Figure 10.

[0066] 12 shows a position in a second exemplary embodiment of the method, where several laterally spaced apart C-rich regions 11 are formed in the exposed surface of the first semiconductor layer 1. The pattern of the C-rich regions 11 can be obtained, for example, by using a mask on the first semiconductor layer 1 during the carbon implantation. The mask is not shown in FIG. 12.

[0067] In the position of FIG. 13, a second semiconductor layer 2 is then grown again on the first semiconductor layer 1 . Figure 14 shows an exemplary embodiment of a final power semiconductor device 100 manufactured by the method described in relation to Figures 12 and 13. Again, the power semiconductor device 100 is a power MOSFET.

[0068] FIG. 15 shows the same method position as in FIG. 12 in a third exemplary embodiment. In FIG. 16, a second semiconductor layer 2 is grown on a first semiconductor layer 1 .

[0069] 17, carbon is introduced into the second semiconductor layer 2, again by, for example, PIII, so as to form laterally spaced apart C-rich regions 22 within the second semiconductor layer 2. Again, a mask, not shown, may be used to obtain this C-rich region pattern.

[0070] As can be seen in FIG. 17, the C-rich regions 22 of the second semiconductor layer 2 and the C-rich regions 11 of the first semiconductor layer 1 are in a staggered configuration in which the regions 11 do not overlap the regions 22 laterally.

[0071] 18 shows the position where the third semiconductor layer 3 is grown on the second semiconductor layer 2. The third semiconductor layer 3 is also SiC and can be grown in the same manner as the first and second semiconductor layers 2.

[0072] Figure 19 shows a further exemplary embodiment of a semiconductor body 10 similar to the embodiment of Figure 18, except that in this case the region 22 of the second semiconductor layer 2 and the region 11 of the first semiconductor layer 1 are adjacent to each other in the vertical direction.

[0073] The embodiments shown in Figures 1-19 above represent exemplary embodiments. As such, they do not constitute an exhaustive list of all embodiments of the improved methods, semiconductor bodies, and power semiconductor devices. Actual methods, semiconductor bodies, and power semiconductor devices may differ from the illustrated embodiments, for example, with respect to arrangements, elements, and layer thicknesses. [Explanation of symbols]

[0074] Reference sign 1. First semiconductor layer 2. Second semiconductor layer 3 Third semiconductor layer 4 boards 5 Main electrode 6 Main electrode 7. Gate electrode 10 Semiconductor body 11 C-rich region 20 buffer space 21 C-rich region 100 Power Semiconductor Devices S9_1~S9_3 curve S10_1,S10_2 curve.

Claims

1. A method for manufacturing a semiconductor body (10), comprising: - providing a first semiconductor layer (1) made of SiC; - introducing carbon into said first semiconductor layer (1) so that at least a part of said first semiconductor layer (1) becomes at least one C-rich region (11); growing a second semiconductor layer (2) made of SiC on said first semiconductor layer (1) containing said at least one C-rich region (11); A method comprising:

2. The method of claim 1, wherein the C-rich region (11) is formed on the exposed side of the first semiconductor layer (1) such that, after growing the second semiconductor layer (2), the C-rich region (11) is located between the second semiconductor layer (2) and the remaining part of the first semiconductor layer (1) that was not made C-rich.

3. The method of claim 1 or 2, wherein the carbon is introduced into the first semiconductor layer using plasma ion immersion implantation.

4. 10. The method of any one of the preceding claims, further comprising implanting a dopant of a first type into a semiconductor layer sequence, said semiconductor layer sequence comprising said first semiconductor layer (1) and said second semiconductor layer (2).

5. 5. The method of claim 4, further comprising activating said first type dopant at a temperature of at least 1500°C.

6. the implantation is carried out with an energy of C ions in the range from 1 keV to 50 keV, Within said C-rich region (11), the average concentration of C atoms or C ions in interstitial sites is at least 10 １４ cm －３ 6. The method according to claim 3 or any one of claims 4 and 5 dependent thereon, wherein

7. 10. The method according to any one of the preceding claims, wherein at least one buffer region (20) of the second semiconductor layer (2) is adjacent to the C-rich region (11) and is doped with a dopant of a second type, the average concentration of the dopant of the second type in the buffer region (20) being higher than the average concentration of the dopant of the second type in the first semiconductor layer (1).

8. A method according to any one of the preceding claims, wherein a plurality of C-rich regions (11) laterally spaced apart from one another are formed in the first semiconductor layer (1).

9. - introducing carbon into said second semiconductor layer (2) so that at least a part of said second semiconductor layer (2) is at least one C-rich region (21); growing a third semiconductor layer (3) made of SiC on said second semiconductor layer (2); 10. The method of any one of the preceding claims, further comprising:

10. - a plurality of laterally spaced apart C-rich regions (21) are formed in said second semiconductor layer (2), - The method according to claim 9 when dependent on claim 8, wherein the C-rich regions (11) in the first semiconductor layer (1) and the C-rich regions (21) in the second semiconductor layer (2) are arranged in a staggered configuration.

11. A semiconductor body (10) comprising: - a first semiconductor layer (1) made of SiC; - a second semiconductor layer (2) made of SiC on the first semiconductor layer (1); - at least one C-rich region (11) in said first semiconductor layer (1), - said at least one C-rich region (11) is adjacent to said second semiconductor layer (2); In the C-rich region (11), the average concentration of C atoms or C ions in interstitial sites is at least 10 １７ cm －３ and a semiconductor body (10), wherein said C-rich region (11) has a thickness of at most 100 nm;

12. The semiconductor body (10) according to claim 11, wherein the at least one C-rich region (11) has its maximum concentration of C atoms or C ions in interstitial sites at the interface with the second semiconductor layer (2).

13. the average concentration of C vacancies in the second semiconductor layer (2) is at most 10 １２ cm －３ 13. The semiconductor body (10) according to claim 11 or 12, wherein:

14. the average mobility of charge carriers in said second semiconductor layer (2) is at least 100 cm at room temperature; ２ The semiconductor body (10) according to any one of claims 11 to 13, wherein Vs.

15. A power semiconductor device (100), - a semiconductor body (10) according to any one of claims 11 to 14, - electrodes (5, 6, 7) in electrical contact with said semiconductor body (10); A power semiconductor device (100) comprising:

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