Silicon carbide epitaxial wafer and manufacturing method thereof

Abstract

This application relates to the technical field of silicon carbide epitaxial wafers and discloses a silicon carbide epitaxial wafer and a manufacturing method thereof, which includes the following steps: S1. preparing a silicon carbide substrate, and sequentially growing a buffer layer and an epitaxial layer on the silicon carbide substrate under conditions required for epitaxial growth, thereby obtaining a first product; S2. sequentially immersing the first product in a first solution, a second solution, and a third solution for cleaning, and then cleaning it in a fourth solution, thereby obtaining a silicon carbide epitaxial wafer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This disclosure claims priority to Chinese Patent Application No. 202211215338.X, filed on September 30, 2014, entitled "Silicon carbide epitaxial wafer and preparation method therefor," the disclosure of which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates to the technical field of silicon carbide epitaxy, and in particular to silicon carbide epitaxial wafers and methods for their manufacture. [Background technology]

[0003] Silicon carbide epitaxy is a crucial part of the silicon carbide semiconductor industry, and the quality of epitaxy has a significant impact on the performance of semiconductor devices. The minority carrier lifetime is directly related to device performance in the subsequent manufacturing process, such as on-resistance, breakdown field strength, and switching speed. Minority carrier lifetime stands for non-equilibrium minority carrier lifetime, a fundamental parameter of semiconductor materials, and directly reflects material quality and device characteristics. Therefore, how to improve and effectively control the carrier lifetime in silicon carbide wafers has become an important factor in the development of silicon carbide substrates and epitaxial wafer products. Summary of the Invention [Problem to be solved by the invention]

[0004] In order to overcome the technical problem existing in the related art of how to effectively improve minority carrier lifetime in silicon carbide epitaxial materials, the objective of the present disclosure is to provide a silicon carbide epitaxial wafer and a manufacturing method thereof. In the present disclosure, the epitaxial process is combined with a cleaning process, and the minority carrier lifetime is increased by the cooperation of the two processes, thereby improving the quality of the epitaxial wafer. [Means for solving the problem]

[0005] To achieve the above object, a first aspect of the present disclosure provides a method for manufacturing a silicon carbide epitaxial wafer, the method comprising the steps of:

[0006] S1: A silicon carbide substrate is prepared, and a buffer layer and an epitaxial layer are sequentially grown on the silicon carbide substrate under conditions required for epitaxial growth to obtain a first product.

[0007] S2: The first product is immersed and washed sequentially with a first solution, a second solution, and a third solution, and then washed with a fourth solution to obtain a silicon carbide epitaxial wafer. The first solution contains 10% to 98% by weight of sulfuric acid and 10% to 50% by weight of hydrogen peroxide. The second solution contains 5% to 30% by weight of aqueous ammonia and 10% to 50% by weight of hydrogen peroxide. The third solution contains 3% to 40% by weight of hydrochloric acid and 10% to 50% by weight of hydrogen peroxide. The fourth solution contains 1% to 15% by weight of hydrofluoric acid and 5% to 70% by weight of nitric acid.

[0008] A second aspect of the present disclosure provides a silicon carbide epitaxial wafer produced by the production method according to the first aspect. [Effects of the Invention]

[0009] Through the above technical solutions, the present disclosure has the following beneficial effects:

[0010] In the present disclosure, the epitaxial process and the cleaning process are closely combined, and the minority carrier lifetime in the epitaxial wafer can be improved by the cooperation of the two processes. Especially, for medium voltage epitaxial wafers (having a thickness of 8 μm to 20 μm), the improvement of the minority carrier lifetime is significant, and no other external contamination is introduced in the method of the present disclosure.

[0011] Advantages of examples of the present disclosure will be set forth in part in the description that follows, and in part will be obvious from the description or may be learned by practice of examples of the present disclosure.

[0012] The accompanying drawings are intended to provide a further understanding of the present disclosure, constitute a part of this specification, and together with the following detailed description, serve to explain the disclosure but do not constitute a limitation of the disclosure. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 shows a mapping of minority carrier lifetime test results for silicon carbide epitaxial samples produced in Example 1 of the present disclosure. [Figure 2] FIG. 2 shows a mapping of surface defect test results corresponding to the test sample in FIG. 1. [Figure 3] FIG. 10 shows a mapping of minority carrier lifetime test results for another silicon carbide epitaxial sample within the same batch of product produced in Example 1 of the present disclosure. [Figure 4] FIG. 4 shows a mapping of surface defect test results corresponding to the test sample in FIG. 3. DETAILED DESCRIPTION OF THE INVENTION

[0014] The endpoints of ranges and any values ​​disclosed herein are not limited to the exact ranges or values, and these ranges or values ​​should be interpreted as including values ​​close to these ranges or values. In the case of numerical ranges, the endpoints of each range may be combined, and the endpoints of each range may be combined with individual point values, and individual point values ​​may be combined, to obtain one or more new numerical ranges (which should be interpreted as specifically disclosed herein).

[0015] A first aspect of the present disclosure provides a method for manufacturing a silicon carbide epitaxial wafer, the method comprising the steps of:

[0016] S1: A silicon carbide substrate is prepared, and a buffer layer and an epitaxial layer are sequentially grown on the silicon carbide substrate under conditions required for epitaxial growth to obtain a first product.

[0017] S2: The first product is immersed and washed sequentially with a first solution, a second solution, and a third solution, and then washed with a fourth solution to obtain a silicon carbide epitaxial wafer. The first solution contains 10% to 98% by weight of sulfuric acid and 10% to 50% by weight of hydrogen peroxide. The second solution contains 5% to 30% by weight of aqueous ammonia and 10% to 50% by weight of hydrogen peroxide. The third solution contains 3% to 40% by weight of hydrochloric acid and 10% to 50% by weight of hydrogen peroxide. The fourth solution contains 1% to 15% by weight of hydrofluoric acid and 5% to 70% by weight of nitric acid.

[0018] In the present disclosure, there is no specific limitation on the silicon carbide substrate, and any silicon carbide substrate commonly used in the art may be used. For example, the silicon carbide substrate may have a thickness of 300 μm to 400 μm. For example, the silicon carbide substrate may have a thickness of 300 μm, 320 μm, 350 μm, 370 μm, or 400 μm.

[0019] In step S2, metal ions on the surface of the epitaxial wafer are removed by washing with a fourth solution.

[0020] Step S2 further includes: after cleaning with the fourth solution, the hydrofluoric acid on the surface of the epitaxial wafer is removed with dilute hydrochloric acid to obtain a silicon carbide epitaxial wafer, and then the epitaxial wafer is spray-washed with pure water and dried by blowing under a nitrogen atmosphere.

[0021] During the growth process of the buffer layer and the epitaxial layer, the desired flow rates of the carbon source, silicon source and doping source, as well as the necessary growth conditions, are selected according to conventional methods in the art.

[0022] It should be noted that the flow rate unit slm in this disclosure can be understood as liters per minute. The flow rate unit sccm can be understood as standard milliliters per minute. The pressure unit 1 Torr is equal to 1 mmHg.

[0023] In some examples, the conditions required for epitaxial growth include the following: a hydrogen flow rate of 10 slm to 200 slm, a hydrogen pressure of 0.1 Torr to 800 Torr, and a temperature of 1000°C to 2000°C. For example, the hydrogen flow rate is 10 slm, 50 slm, 100 slm, 150 slm, or 200 slm. The hydrogen pressure is 0.1 Torr, 1 Torr, 5 Torr, 10 Torr, 50 Torr, 100 Torr, 150 Torr, 200 Torr, 250 Torr, 300 Torr, 350 Torr, 400 Torr, 450 Torr, 500 Torr, 550 Torr, 600 Torr, 650 Torr, 700 Torr, 750 Torr, or 800 Torr. The temperature is 1000°C, 1100°C, 1200°C, 1300°C, 1400°C, 1500°C, 1600°C, 1700°C, 1800°C, 1900°C, or 2000°C. In some other examples, the conditions required for epitaxial growth include the following: a hydrogen flow rate of 50 slm to 150 slm, a hydrogen pressure of 1 Torr to 600 Torr, and a temperature of 1200°C to 1800°C. In some other examples, the conditions required for epitaxial growth include the following: a hydrogen flow rate of 80 slm to 120 slm, a hydrogen pressure of 200 Torr to 300 Torr, and a temperature of 1400°C to 1600°C.

[0024] According to the present disclosure, the conditions required for epitaxial growth specifically include the following: The epitaxial furnace reaction chamber is evacuated to an internal pressure of less than 0.1 Torr. Hydrogen is introduced as an etching atmosphere, and the hydrogen flow rate is controlled to 10 slm to 200 slm. The pressure and temperature are set to the conditions required for epitaxial growth, with the pressure set to 0.1 Torr to 800 Torr and the temperature set to 1000°C to 2000°C.

[0025] In some examples, the steps for growing the buffer layer include using hydrogen as a carrier gas. To grow the buffer layer, the flow rates of the first carbon source, the first silicon source, and the doping source are adjusted to flow rates required for growing the buffer layer, the temperature is controlled to 1000°C to 2000°C, and the pressure is controlled to 0.1 Torr to 800 Torr. For example, the temperature is 1000°C, 1100°C, 1200°C, 1300°C, 1400°C, 1500°C, 1600°C, 1700°C, 1800°C, 1900°C, or 2000°C. The pressure is 0.1 Torr, 1 Torr, 5 Torr, 10 Torr, 50 Torr, 100 Torr, 150 Torr, 200 Torr, 250 Torr, 300 Torr, 350 Torr, 400 Torr, 450 Torr, 500 Torr, 550 Torr, 600 Torr, 650 Torr, 700 Torr, 750 Torr, or 800 Torr.

[0026] In some examples, in the step of growing a buffer layer, the hydrogen flow rate is 10 slm to 200 slm, and the hydrogen-borne carbon to silicon ratio is 0.1 to 10:1. For example, the hydrogen flow rate is 10 slm, 50 slm, 100 slm, 150 slm, or 200 slm. The hydrogen-borne carbon to silicon ratio is 0.1:1, 0.5:1, 1:1, 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1, 6.5:1, 7:1, 7.5:1, 8:1, 8.5:1, 9:1, 9.5:1, or 10:1, etc.

[0027] In some other examples, in the step of growing the buffer layer, the hydrogen flow rate is 50 slm to 150 slm and the hydrogen-borne carbon to silicon ratio is 1 to 8:1. In some other examples, in the step of growing the buffer layer, the hydrogen flow rate is 80 slm to 120 slm and the hydrogen-borne carbon to silicon ratio is 3 to 6:1.

[0028] In this disclosure, the carbon to silicon ratio refers to the atomic ratio of carbon to silicon carried by the introduced hydrogen.

[0029] According to the present disclosure, during the growth of the buffer layer, the hydrogen flow rate is maintained within the range of 10 slm to 200 slm, and the hydrogen-borne carbon to silicon ratio is controlled within the range of 0.1 to 10:1.

[0030] According to the present disclosure, during the growth process of the buffer layer and the epitaxial layer, hydrogen is steadily introduced as a carrier gas at the original flow rate without being stopped.

[0031] According to the present disclosure, the doping source serves to introduce excess valences, i.e., charge carriers, of electrons or holes into the product, improving the conductivity of the product.

[0032] In some examples, the first carbon source comprises at least one of ethylene and propane.

[0033] In some examples, the flow rate of the first carbon source is between 10 sccm and 500 sccm, such as 12 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 75 sccm, 85 sccm, 95 sccm, 100 sccm, 150 sccm, 180 sccm, 200 sccm, 230 sccm, 275 sccm, 300 sccm, 355 sccm, 395 sccm, 400 sccm, 435 sccm, 455 sccm, 485 sccm, and any value within a range formed by any two of the above values. In some other examples, the flow rate of the first carbon source is between 200 sccm and 400 sccm.

[0034] In some examples, the first silicon source includes at least one of silane and trichlorosilane.

[0035] In some examples, the flow rate of the first silicon source is 10 sccm to 500 sccm, such as 12 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 75 sccm, 85 sccm, 95 sccm, 100 sccm, 150 sccm, 180 sccm, 200 sccm, 230 sccm, 275 sccm, 300 sccm, 355 sccm, 395 sccm, 400 sccm, 435 sccm, 455 sccm, 485 sccm, and any value within a range formed by any two of the above values. In some other examples, the flow rate of the first silicon source is 200 sccm to 400 sccm.

[0036] In some examples, the doping source includes at least one of nitrogen and trimethylaluminum.

[0037] In some examples, the flow rate of the doping source is between 1 sccm and 500 sccm, such as 12 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 75 sccm, 85 sccm, 95 sccm, 100 sccm, 150 sccm, 180 sccm, 200 sccm, 230 sccm, 275 sccm, 300 sccm, 355 sccm, 395 sccm, 400 sccm, 435 sccm, 455 sccm, 485 sccm, and any value within a range formed by any two of the above values. In some other examples, the flow rate of the doping source is between 200 sccm and 400 sccm.

[0038] In some examples, the step of growing an epitaxial layer includes: adjusting the flow rates of the second carbon source and the second silicon source to flow rates required to grow the epitaxial layer, thereby growing the epitaxial layer; During the epitaxial layer growth process, the epitaxial layer is grown to a first thickness at a first growth rate, and then grown to a second thickness at a second growth rate, the first rate being faster than the second rate.

[0039] According to the present disclosure, step S1 is an epitaxial process in which the epitaxial layer is grown in a manner that includes an initial rapid growth followed by a slow growth. When the epitaxial layer grows to approximately 75% to 90% of the epitaxial layer thickness, the growth rate is reduced to allow for the slow growth. Point defects, such as color centers and deep energy level vacancies in silicon carbide, are accommodated by the slow growth to reduce the scattering effect of neutral impurities. Therefore, the conversion between stacking faults (SFs) and basal plane dislocations (BPDs) is slowed, significantly reducing the number of SFs, BPDs, and black spots (microscopic black spot defects that cannot be specifically identified) on the surface of the epitaxial wafer, and thus reducing the recombination of minority carriers on the surface.

[0040] During the epitaxial layer growth process, the second carbon source in some instances includes at least one of ethylene and propane.

[0041] In some examples, the flow rate of the second carbon source is between 50 sccm and 500 sccm, such as 80 sccm, 100 sccm, 150 sccm, 175 sccm, 200 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm, 485 sccm, 495 sccm, and any value within the range formed by any two of the above values. In some other examples, the flow rate of the second carbon source is between 100 sccm and 450 sccm.

[0042] In some examples, the flow rate of the second silicon source is 10 sccm to 1000 sccm, such as 20 sccm, 50 sccm, 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 750 sccm, 850 sccm, 900 sccm, 950 sccm, and any value within the range formed by any two of the above values. In some other examples, the flow rate of the second silicon source is 10 sccm to 900 sccm.

[0043] In some examples, the second silicon source includes at least one of a silane and a trichlorosilane.

[0044] In some examples, the first growth rate is between 10 μm / h and 100 μm / h, such as 12 μm / h, 15 μm / h, 20 μm / h, 25 μm / h, 30 μm / h, 40 μm / h, 50 μm / h, 60 μm / h, 75 μm / h, 85 μm / h, 95 μm / h, and any value within a range formed by any two of the above values. In some other examples, the first growth rate is between 35 μm / h and 85 μm / h.

[0045] In some examples, the second growth rate is between 1 μm / h and 10 μm / h, such as 2 μm / h, 3 μm / h, 5 μm / h, 6 μm / h, 7 μm / h, 8 μm / h, 9 μm / h, 9.5 μm / h, and any value within a range formed by any two of the above values. In some other examples, the second growth rate is between 5 μm / h and 8 μm / h.

[0046] In some examples, the first thickness is 75% to 90% of the thickness of the epitaxial layer, such as 78%, 80%, 82%, 84%, 85%, 88%, and any value within a range formed by any two of the foregoing values. In some other examples, the first thickness is 80% to 85% of the thickness of the epitaxial layer.

[0047] In some examples, the second thickness is 10-25% of the thickness of the epitaxial layer, such as 12%, 15%, 18%, 20%, 22%, 24%, and any value within the range formed by any two of the above values.

[0048] In some preferred examples, the thickness of the epitaxial layer is 8 μm to 20 μm, such as 10 μm, 13 μm, 15 μm, 18 μm, and any value within the range formed by any two of the above values. In some other preferred examples, the thickness of the epitaxial layer is 10 μm to 18 μm.

[0049] In the present disclosure, when the thickness of the epitaxial layer is 8 μm to 20 μm, the first thickness is 6 μm to 18 μm, for example, the first thickness is 7 μm to 14 μm, and further, the first thickness is 8 μm to 10 μm.

[0050] As the thickness of the epitaxial layer decreases, the surface and bulk recombination rates slow, resulting in a significant improvement in minority carrier lifetime. At thicknesses between 8 μm and 20 μm, the increase in minority carrier lifetime is severely limited, making it difficult to achieve significant increases. In this disclosure, the epitaxial and cleaning processes are closely integrated, and the minority carrier lifetime in epitaxial wafers can be improved by the cooperation of these two processes. In particular, the improvement in minority carrier lifetime is significant for medium-voltage epitaxial wafers (thicknesses between 8 μm and 20 μm), and no external contamination is introduced in the disclosed method.

[0051] Specifically, in the growth process of the epitaxial layer, rapid growth (growth rate of 10 μm / h to 100 μm / h, for example, 10 μm / h, 15 μm / h, 20 μm / h, 25 μm / h, 30 μm / h, 35 μm / h, 40 μm / h, 45 μm / h, 50 μm / h, 55 μm / h, 60 μm / h, 65 μm / h, 70 μm / h, 75 μm / h, 80 μm / h, 85 μm / h, 90 μm / h, 95 μm / h, 100 μm / h, and any value within a range formed by any two numerical values) is first performed. After growing about 8 μm to 10 μm, the growth rate is reduced to slow growth (1 μm / h to 10 μm / h, for example, 1 μm / h, 2 μm / h, 5 μm / h, 7 μm / h, 10 μm / h, and any value within a range formed by any two of the above values), and grown to about 1 μm to 2 μm to obtain a 4° off-axis silicon carbide epitaxial wafer substrate.

[0052] Due to the different graphite attachments used in the furnace, the growth rate is calculated by dividing the measured epitaxial thickness value by the growth time. During the experiment, the flow rates of the carbon and silicon sources and their flow rate ratios are initially roughly set, and then a sample wafer is grown to confirm the growth rate before the actual growth. The growth rate of the sample wafer is used as the growth rate in the actual experiment. If the current growth rate is 10 μm / h, the approximate flow rate of the second silicon source is 150 ccm to 250 ccm, such as 150 ccm, 170 ccm, 200 ccm, 220 ccm, 250 ccm, and any value within the range formed by any two of the above values. The flow rate of the second carbon source is 60 ccm to 120 ccm, such as 60 ccm, 80 ccm, 100 ccm, 120 ccm, and any value within the range formed by any two of the above values.

[0053] The first growth rate is controlled by adjusting the flow rate of the second silicon source to a range of 100 ccm to 1000 ccm and the flow rate of the second carbon source to a range of 80 ccm to 500 ccm. To control the second growth rate, the flow rate of the second silicon source is 10 ccm to 80 ccm and the flow rate of the second carbon source is 50 ccm to 100 ccm.

[0054] In some examples, the manufacturing method further comprises the step of: annealing the first product before washing the first product.

[0055] In some examples, the annealing step includes the following steps: stopping the introduction of the reaction gas, introducing hydrogen or a mixture of hydrogen and an inert gas at the growth temperature of the epitaxial layer, subjecting the first product to a high-temperature annealing treatment in a hydrogen-rich atmosphere, incubating for 1 to 2 hours, and then cooling to room temperature together with the furnace.

[0056] In this step, the flow rate of hydrogen is 1 slm to 50 slm, for example, 1 slm, 5 slm, 10 slm, 15 slm, 20 slm, 25 slm, 30 slm, 35 slm, 40 slm, 45 slm, and 50 slm, etc. The inert gas is Ar or He, and the flow rate of the inert gas is 1 slm to 10 slm, for example, 1 slm, 5 slm, and 10 slm, etc.

[0057] In this example, after the epitaxial growth of silicon carbide is completed, the silicon carbide epitaxy is directly incubated without changing the equipment, thereby saving time and production costs, reducing the process complexity, and facilitating industrial promotion.

[0058] In some other examples of the present disclosure, after the epitaxial growth of silicon carbide is completed, the first product may be transferred from the growth furnace to other high-temperature equipment for annealing. The atmosphere and temperature used in the annealing process are the same as those in the above examples and will not be described herein.

[0059] Step S2 is a cleaning process. In the present disclosure, by adjusting the composition of the solution and the cleaning sequence, metal ions on the surface of the epitaxial layer can be effectively removed, which can reduce the trapping effect of metal contamination on minority carriers on the surface of the epitaxial layer, inhibit the recombination of minority carriers on the surface of the silicon carbide wafer, and further improve the minority carrier lifetime in the sample.

[0060] In some examples, the first solution is prepared by mixing 98% by weight concentrated sulfuric acid and 30% by weight hydrogen peroxide in a volume ratio of 1 to 3:1, for example, 98% by weight concentrated sulfuric acid and 30% by weight hydrogen peroxide in a volume ratio of 1:1, 2:1, or 3:1.

[0061] In some examples, the second solution is prepared by mixing 27 wt% aqueous ammonia, 30 wt% hydrogen peroxide, and pure water in a volume ratio of 1:1-3:3-10. For example, 27 wt% aqueous ammonia, 30 wt% hydrogen peroxide, and pure water are mixed in a volume ratio of 1:1:3-10, 1:2:3-10, 1:3:3-10, 1:1-3:3, 1:1-3:5, 1:1-3:7, 1:1-3:9, or 1:1-3:10.

[0062] In some examples, the third solution is prepared by mixing 37% by weight hydrochloric acid, 30% by weight hydrogen peroxide, and pure water in a volume ratio of 1:1-5:5-15. For example, 37% by weight hydrochloric acid, 30% by weight hydrogen peroxide, and pure water are mixed in a volume ratio of 1:1:5-15, 1:2:5-15, 1:3:5-15, 1:4:5-15, 1:5:5-15, 1:1-5:5, 1:1-5:7, 1:1-5:9, 1:1-5:10, 1:1-5:12, 1:1-5:13, or 1:1-5:15.

[0063] In some examples, the fourth solution is prepared by mixing 38 wt% hydrofluoric acid, 55 wt% nitric acid, and pure water in a volume ratio of 1:1-3:3-10. For example, 38 wt% hydrofluoric acid, 55 wt% nitric acid, and pure water are mixed in a volume ratio of 1:1:3-10, 1:2:3-10, 1:3:3-10, 1:1-3:3, 1:1-3:5, 1:1-3:7, 1:1-3:9, or 1:1-3:10.

[0064] In some examples, step S2 further includes the following steps: After cleaning with the fourth solution, the hydrofluoric acid on the surface of the epitaxial wafer is removed with dilute hydrochloric acid, and then the epitaxial wafer is spray-washed with pure water and dried by blowing under a nitrogen atmosphere to obtain a silicon carbide epitaxial wafer.

[0065] In some examples, the dilute hydrochloric acid concentration is between 3% and 15% by weight, such as 3%, 5%, 7%, 10%, 12%, 15%, and any value within the range formed by any two of the above values.

[0066] A second aspect of the present disclosure provides a silicon carbide epitaxial wafer produced by the above-described manufacturing method.

[0067] In some preferred examples, the thickness of the epitaxial layer on the silicon carbide epitaxial wafer is 8 μm to 20 μm, such as 10 μm, 13 μm, 15 μm, 18 μm, or any value within the range formed by any two of the above values. In some other examples, the thickness of the epitaxial layer on the silicon carbide epitaxial wafer is 10 μm to 18 μm.

[0068] In some examples, the silicon carbide epitaxial wafer has a minority carrier lifetime between 100 ns and 320 ns, e.g., 100 ns, 120 ns, 150 ns, 180 ns, 200 ns, 220 ns, 250 ns, 280 ns, 300 ns, 320 ns, etc. In some other examples, the silicon carbide epitaxial wafer has a minority carrier lifetime between 160 ns and 300 ns.

[0069] In the present disclosure, the minority carrier lifetime can be detected by the minority carrier lifetime detection method (GB / T26068-2018).

[0070] In some examples, on the surface of the silicon carbide epitaxial wafer, the total number of defects is 700 or less, the number of particles is 10 or less, the number of pits (depressions) is 200 or less, the number of SF and BPD is 100 or less, the number of black spots is 200 or less, and the content of Fe contamination is less than the order of E9, i.e., the content of Fe ions is 10 9 atom / cm -2 The following is the result.

[0071] In some other examples, on the surface of the silicon carbide epitaxial wafer, the total defect count is 600 or less, the particle count is 8 or less, the pit count is 150 or less, the SF and BPD counts are both 90 or less, the black spot count is 180 or less, and the Fe contamination content is less than the order of E9, i.e., the Fe ion content is 10 9 atom / cm -2 The following is the result.

[0072] In this disclosure, on the surface of a silicon carbide epitaxial wafer, grains represent particulate matter, pits represent depressions, SFs represent stacking faults, BPDs represent basal plane dislocations, and black spots represent microscopic black spot defects that cannot be specifically identified. The above parameters can be detected by the Silicon Carbide Epitaxial Defects Detection Method (GB / T17167-1997).

[0073] The content of Fe contamination indicates the iron ion content, which can be detected by the detection method for metal ion contamination (GB / T39145-2020).

[0074] The method of the present disclosure combines an epitaxial process and a cleaning process, and the cooperation of these two processes significantly improves minority carrier lifetime, especially for medium voltage epitaxial wafers (8 μm to 20 μm).

[0075] During the epitaxial growth stage, epitaxial wafers have more point defects, such as carbon vacancies and hydrogen impurities, during the growth process. This leads to the formation of SFs, which slowly expand to the surface as growth progresses to form BPDs, resulting in more defects on the surface of the grown epitaxial wafer, such as SFs (stacking faults), BPDs (basal plane dislocations), black spots (small black spot defects that cannot be specifically identified), and pits (depressions). The traps formed by these defects on the surface capture excited minority carriers, exacerbating the surface recombination effect. Furthermore, during the substrate processing and cleaning process, a large amount of metal ions are also introduced by processing equipment and chemical solutions, and the surface charges of the metal ions also neutralize minority carriers, resulting in a short minority carrier lifetime in the newly grown epitaxial wafer.

[0076] According to a particularly preferred embodiment of the present disclosure, for example, a method for producing a silicon carbide epitaxial wafer having an epitaxial layer thickness of 8 μm to 20 μm includes the following steps.

[0077] S1: The growth process includes the following steps:

[0078] S11: A silicon carbide substrate (300 μm to 400 μm thick) is placed in the mounting position of an epitaxial furnace (Class 100 environment, i.e., the cleanliness level is 100) and transferred to the epitaxial furnace reaction chamber by a mechanical arm. The reaction chamber is evacuated so that the pressure inside the reaction chamber is less than 0.1 Torr.

[0079] S12: Hydrogen is introduced as the etching atmosphere. The hydrogen flow rate is 10 slm to 200 slm, and the pressure and temperature are set to the conditions required for epitaxial growth. The pressure is set to 0.1 Torr to 800 Torr, and the temperature is set to 1000°C to 2000°C. The flow rates of the carbon source, silicon source, and doping source are adjusted to the flow rates required for buffer layer growth (carbon source: 10 sccm to 500 sccm, silicon source: 10 sccm to 500 sccm, doping source: 1 sccm to 500 sccm). At this point, hydrogen is continuously introduced as a carrier gas at its original flow rate without being stopped, and the carbon-to-silicon ratio (i.e., the atomic ratio of carbon to silicon in the introduced gas) is set to 0.1 to 10:1. All gases are discharged until the temperature and pressure in the reaction chamber of the epitaxial furnace reach the required values.

[0080] S13: Once the temperature (1000°C-2000°C) and pressure (0.1 Torr-800 Torr) in the epitaxial furnace reaction chamber have reached the required level and are stable, gas and doping sources are introduced into the reaction chamber to grow a buffer layer with a thickness of 1 μm-5 μm. After the buffer layer is grown, the flow rates of the carbon and silicon sources are adjusted to the flow rates required to grow the epitaxial layer (carbon source: 50 sccm-500 sccm, and silicon source: 10 sccm-1000 sccm). Rapid growth is performed first (growth rate of 10 μm / h-100 μm / h). Once the epitaxial layer has grown to 75%-90% of its thickness, the growth rate is reduced. Perform slow growth (growth rate of 1 μm / h to 10 μm / h) to grow the epitaxial layer to a thickness of 8 μm to 20 μm to obtain 4° off-axis silicon carbide epitaxial wafers.

[0081] S14: Stop the introduction of reaction gas, keep the temperature unchanged, introduce hydrogen (flow rate 1 slm-50 slm) and inert gas (e.g., Ar or He, flow rate 1 slm-10 slm) into the epitaxial furnace reaction chamber, and anneal the epitaxial wafer at high temperature in a hydrogen-rich atmosphere. The temperature is maintained for 1-2 hours, and then the product is cooled to room temperature together with the furnace and then removed.

[0082] S2: The cleaning process includes the following steps:

[0083] S21: The product from S1 is washed in a tank containing SPM (a mixture of sulfuric acid and hydrogen peroxide, 98% by weight concentrated sulfuric acid and 30% by weight hydrogen peroxide, mixed at a volume ratio of 3:1) and ultrasonically cleaned in an ultrasonic cleaning device. It is then transferred to SC1 (a mixture of 27% by weight ammonia water, 30% by weight hydrogen peroxide, mixed at a volume ratio of 1:1:3, and purified water) for immersion and cleaning. Finally, it is transferred to SC2 (a mixture of 37% by weight hydrochloric acid, 30% by weight hydrogen peroxide, mixed at a volume ratio of 1:1:5, and purified water) for immersion and cleaning. This step is a routine cleaning process that removes particle contaminants (0.1 μm to 1 μm in diameter) from the surface of the product.

[0084] S22: 38 wt% hydrofluoric acid + 55 wt% nitric acid + pure water are mixed in a volume ratio of 1:1:3, and then used to remove metal ions.

[0085] S23: Finally, the hydrofluoric acid is removed by spray cleaning with a chemical solution of 15% by weight diluted hydrochloric acid.

[0086] S24: To obtain a silicon carbide epitaxial wafer product with a high minority carrier lifetime, the product is spray-cleaned with pure water and blow-dried under a nitrogen atmosphere.

[0087] The present disclosure is described below with reference to specific examples. It should be noted that these examples are merely illustrative and do not limit the present disclosure in any way.

[0088] In the following examples and comparative examples, the minority carrier lifetime detection method (GB / T26068-2018) is the microwave photoconductivity decay (μ-PCD) method. Microwave photoconductivity decay is primarily used to monitor carrier recombination in materials. The test system includes a semiconductor laser, a circulator, a microwave generator, a detector, and a flat-panel display. The light source selected for the test is typically a YAG laser pump source, with the emitted pulse wave typically having a wavelength of 349 nm and a duration of 200 ns. After the test sample is excited by the laser, non-equilibrium carriers are generated, which changes the conductivity of the semiconductor material. The infrared light emitted by the detector is reflected by the sample surface and captured as a detection signal by a reflection detector. After passing through the circulator, it is converted into an electrical signal and displayed on a transient oscilloscope in the form of an intuitive voltage curve, reflecting the changing pattern of minority carrier lifetime.

[0089] The silicon carbide epitaxial defect detection method (GB / T17167-1997) is an optical surface analysis technique that can simultaneously measure scattering intensity, shape change, surface reflectance, and phase shift. This detection method combines the fundamental principles of scatterometry, ellipsometry, reflectometry, and optical shape analysis to nondestructively detect residual foreign particles, surface and subsurface defects, shape changes, and film thickness uniformity on silicon wafer surfaces. This method uses a laser as the light source. The laser's coherence and multichannel spatial filtering create a diverging beam with a highly uniform wavefront, which illuminates the sample surface. Different types of defects on the sample surface distort the reflected wavefront. The distorted wavefront is spatially folded, making it suitable for coherent imaging, forming images corresponding to various defects. The reflected beam is received by a light-receiving device (e.g., a CCD), and the results of the sample surface condition analysis can be displayed on a screen after algorithmic processing.

[0090] Detection of metal ion contamination (GB / T 39145-2020): ICP-MS method. Metal elements on a silicon carbide wafer are dissolved in nitric acid to obtain a scanning solution containing the metal ions. The silicon carbide scanning solution sample is sprayed, and the microdroplets are screened and introduced into an inductively coupled plasma at high temperatures of 8,000-10,000 K. The inorganic elements to be measured are sequentially gasified, sprayed, and ionized, resulting in positively charged ions. The positive ions are then screened by a quadrupole rod ion deflection system, and interfering ions are completely eliminated by a quadrupole rod collision reaction cell system. Finally, the ions are scanned by a quadrupole rod mass spectrometer and then introduced into a detector system for qualitative and quantitative analysis. [Example]

[0091] Example 1 Silicon carbide epitaxial wafers were produced by a method involving a combination of epitaxial and cleaning processes. The method was as follows:

[0092] S1: Epitaxial process: The reaction chamber was evacuated to an internal pressure of 0.1 Torr or less. The hydrogen flow rate was 150 slm, the temperature was 1640°C, the carbon to silicon ratio was 0.5, the silicon source trichlorosilane (TCS) flow rate was 50 sccm, and the carbon source ethylene flow rate was 15 sccm. A 1 μm buffer layer was grown. After the buffer layer was grown, the carbon source flow rate was adjusted to 80 sccm, and the silicon source flow rate was adjusted to 180 sccm. The epitaxial layer was grown. Rapid growth was first performed (growth rate of 15 μm / h). After 9 μm growth, the growth rate was reduced. Slow growth was performed (growth rate of 5 μm / h). Approximately 2 μm growth was achieved. At this point, the epitaxial layer was fully grown. The introduction of the reaction gas was stopped, the temperature was kept constant (1640 °C), hydrogen (flow rate of 2 slm) was introduced into the epitaxial furnace reaction chamber, and the epitaxial wafer was annealed at high temperature in a hydrogen-rich atmosphere. The temperature was maintained for 1 hour, and then the product was cooled to room temperature together with the furnace before being removed.

[0093] S2. Cleaning process: The product obtained in step S1 was immersed and cleaned using SPM (98 wt% concentrated sulfuric acid + 30 wt% hydrogen peroxide in a 3:1 volume ratio), SC1 (27 wt% aqueous ammonia + 30 wt% hydrogen peroxide + pure water in a 1:1:3 volume ratio), and SC2 (37 wt% hydrochloric acid + 30 wt% hydrogen peroxide + pure water in a 1:1:5 volume ratio). 38 wt% hydrofluoric acid + 55 wt% nitric acid + pure water were mixed in a 1:1:3 volume ratio and used to remove metal ions. The hydrofluoric acid was then removed with 15 wt% diluted hydrochloric acid. Finally, the product was spray-washed with pure water and dried by blowing under a nitrogen atmosphere to obtain silicon carbide epitaxial wafers.

[0094] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0095] In this and the following examples, as well as the comparative examples, the specific method for data acquisition was as follows: Three silicon carbide epitaxial wafer samples from the same batch were selected and tested individually. The detected data were then averaged to obtain data for the silicon carbide epitaxial wafer. This data is shown in Table 1.

[0096] Figures 1-4 show test results for silicon carbide epitaxial wafers. Figure 1 shows a mapping of minority carrier lifetime test results for a silicon carbide epitaxial sample produced in Example 1 of the present disclosure. Figure 2 shows a mapping of surface defect test results corresponding to the test sample in Figure 1. Figures 3 and 4 show a mapping of minority carrier lifetime test results and a mapping of surface defect test results, respectively, for another silicon carbide epitaxial wafer sample within the same batch of product produced in Example 1 of the present disclosure. From Figures 2 and 4, it can be seen that the special epitaxial growth and cleaning process described in this disclosure resulted in a total defect count of 600 or less, a particle count of 5 or less, a pit count of 200 or less, a SF and BPD count of 50 or less, and a black spot count of 120 or less on the surface of the wafer (silicon carbide epitaxial wafer). It can be seen that BPD, SF, pits, and black spots are clearly controlled in this process. The surface was tested for Fe contamination and the concentration was at E8 level (i.e., Fe ion content was 10 8 atom / cm -2 1 and 3, the minority carrier lifetime is found to be up to 280 ns, which is quite high for the epitaxial thickness range required by medium voltages.

[0097] Example 2 The method of Example 1 was used, except that in step S1, the rapid growth rate was 15 μm / h, the slow growth rate was 1 μm / h, and the rest of the conditions were the same. Silicon carbide epitaxial wafers were obtained.

[0098] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0099] Example 3 The method of Example 1 was used, except that in step S1, the rapid growth rate was 15 μm / h, the slow growth rate was 9 μm / h, and the rest of the conditions were the same. Silicon carbide epitaxial wafers were obtained.

[0100] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0101] Example 4 The method of Example 1 was used, except that in step S1, the rapid growth rate was 15 μm / h, the slow growth rate was 9 μm / h, and the rest of the conditions were the same. Silicon carbide epitaxial wafers were obtained.

[0102] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0103] Example 5 The method of Example 1 was used, except that in step S1, the rapid growth rate was 15 μm / h, the slow growth rate was 9 μm / h, and the rest of the conditions were the same. Silicon carbide epitaxial wafers were obtained.

[0104] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0105] Example 6 The method of Example 1 was used, but in step S1, epitaxial growth was performed at the same growth rate. After growing the buffer layer, the entire epitaxial film was grown at a high rate (15 μm / h), and no slow growth process was included. The remaining conditions were the same. Silicon carbide epitaxial wafers were obtained.

[0106] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0107] Example 7 The method of Example 1 was used, but in step S1, after growing the epitaxial layer, the epitaxial layer was directly introduced into the cleaning process without high-temperature annealing under hydrogen atmosphere, and the other conditions were the same. Silicon carbide epitaxial wafers were obtained.

[0108] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0109] (Comparative Example 1) The method of Example 1 was used, but the cleaning in step S2 was different. The nitric acid + hydrofluoric acid cleaning process was not included, and the remaining conditions were the same. Silicon carbide epitaxial wafers were obtained.

[0110] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0111] (Comparative Example 2) The method of Example 1 was used, but only the epitaxial manufacturing process was used to obtain silicon carbide epitaxial wafers, i.e., only step S1 of Example 1 was included, and the subsequent cleaning process S2 was not performed.

[0112] The data for the silicon carbide epitaxial wafer after the test is shown in Table 1.

[0113] [Table 1]

[0114] The results in Table 1 show that on the surfaces of the silicon carbide epitaxial wafers obtained by combining the epitaxial process and cleaning process in Examples 1 to 7 of the present disclosure, the total number of defects was 700 or less, the number of particles was 10 or less, the number of pits was 200 or less, the number of SFs and BPDs was both 100 or less, the number of black spots was 200 or less, and the content of Fe contamination was on the order of less than E9. By comparison, it can be seen that the minority carrier lifetime in the silicon carbide epitaxial wafers obtained in Examples 1 to 7 of the present disclosure was significantly higher than that in Comparative Examples 1 and 2, and that BPDs, SFs, pits, and black spots were also clearly controlled, at extremely high levels within the range of epitaxial thickness required for medium voltages.

[0115] The cleaning process used in Comparative Example 1 does not include the nitric acid + hydrofluoric acid cleaning process. The minority carrier lifetime in the epitaxial wafer is less than about 100 ns. The number of particles and black spots on the surface of the epitaxial wafer is significantly increased, and Fe contamination is significantly increased by about 1 to 2 orders of magnitude.

[0116] In Comparative Example 2, only the epitaxial process was used. Without cleaning, the minority carrier lifetime in the epitaxial wafer was less than about 100 ns, and the number of pits, SFs, BPDs, and black spots increased significantly, and Fe contamination was also severe.

[0117] From the above, it can be seen that by combining the epitaxial process with a special cleaning process, the present disclosure can significantly improve the minority carrier lifetime in silicon carbide epitaxial wafers, and significantly reduce the total number of surface defects, particles, pits, SFs (stacking faults), BPDs (basal plane dislocations), and black spots (microscopic black spot defects that cannot be specifically identified), as well as the Fe contamination content. By combining and controlling the rapid and slow growth modes of the epitaxial layer, the minority carrier lifetime and the performance of the silicon carbide epitaxial wafers are further improved.

[0118] The above examples are merely some implementations of the present application, and are described in detail, but should not be construed as limiting the scope of the present disclosure.It should be understood that a person skilled in the art may make some modifications and improvements without departing from the concept of the present disclosure, and they are all contemplated within the protection scope of the present disclosure.Therefore, the protection scope of the present disclosure is defined by the appended claims.

Claims

1. 1. A method for producing a silicon carbide epitaxial wafer, comprising: S1: providing a silicon carbide substrate and growing a buffer layer and an epitaxial layer, in sequence, on the silicon carbide substrate under conditions required for epitaxial growth to obtain a first product; S2: immersing and washing the first product sequentially using a first solution, a second solution, and a third solution, and then washing with a fourth solution to obtain a silicon carbide epitaxial wafer, wherein the first solution has a sulfuric acid content of 10% by weight to 98% by weight and a hydrogen peroxide content of 10% by weight to 50% by weight; the second solution has an ammonia water content of 5% by weight to 30% by weight and a hydrogen peroxide content of 10% by weight to 50% by weight; the third solution has a hydrochloric acid content of 3% by weight to 40% by weight and a hydrogen peroxide content of 10% by weight to 50% by weight; and the fourth solution has a hydrofluoric acid content of 1% by weight to 15% by weight and a nitric acid content of 5% by weight to 70% by weight.

2. 10. The method of claim 1, wherein the conditions required for epitaxial growth comprise a hydrogen flow rate in the range of 10 slm to 200 slm, a hydrogen pressure in the range of 0.1 Torr to 800 Torr, and a temperature in the range of 1000°C to 2000°C.

3. 3. The method of claim 1, wherein the step of growing the buffer layer comprises using hydrogen as a carrier gas; adjusting flow rates of a first carbon source, a first silicon source, and a doping source to flow rates required for growing the buffer layer, and controlling the temperature to 1000°C to 2000°C and the pressure to 0.1 Torr to 800 Torr, to grow the buffer layer.

4. 4. The method of claim 3, wherein the hydrogen flow rate is between 10 slm and 200 slm and the hydrogen-carried carbon to silicon ratio is between 0.1 and 10:

1.

5. 5. The method of claim 1, wherein the step of growing the epitaxial layer comprises adjusting flow rates of a second carbon source and a second silicon source to flow rates required for growing the epitaxial layer, and growing the epitaxial layer, wherein during the epitaxial layer growth process, the epitaxial layer is grown to a first thickness at a first growth rate, and then grown to a second thickness at a second growth rate, the first rate being faster than the second rate.

6. The method of claim 5, wherein the first thickness is between 75% and 90% of the thickness of the epitaxial layer.

7. The method according to claim 5 or 6, wherein the second thickness is 10% to 25% of the thickness of the epitaxial layer, and the thickness of the epitaxial layer is 8 μm to 20 μm.

8. 8. The method of claim 1, further comprising annealing the first product before washing the first product.

9. 9. The method of claim 8, wherein the annealing step comprises: stopping the introduction of reactive gases; introducing hydrogen or a mixture of hydrogen and an inert gas at a growth temperature of the epitaxial layer; subjecting the first product to a high-temperature annealing treatment under a hydrogen-rich atmosphere; incubating for 1 to 2 hours; and then cooling down to room temperature together with a furnace.

10. 10. The method of claim 1, wherein the first solution is prepared by mixing 98% by weight of concentrated sulfuric acid and 30% by weight of hydrogen peroxide in a volume ratio of 1-3:

1.

11. 11. The method according to claim 1, wherein the second solution is prepared by mixing 27% by weight of aqueous ammonia, 30% by weight of hydrogen peroxide, and pure water in a volume ratio of 1:1 to 3:3 to 10.

12. 12. The method according to claim 1, wherein the third solution is prepared by mixing 37% by weight of hydrochloric acid, 30% by weight of hydrogen peroxide, and pure water in a volume ratio of 1:1-5:5-15.

13. 13. The method according to claim 1, wherein the fourth solution is prepared by mixing 38% by weight of hydrofluoric acid, 55% by weight of nitric acid, and pure water in a volume ratio of 1:1 to 3:3 to 10.

14. 14. The method according to claim 1, wherein step S2 further comprises removing hydrofluoric acid on the surface of the epitaxial wafer with dilute hydrochloric acid after cleaning with the fourth solution, followed by spray-rinsing with pure water and drying by blowing under a nitrogen atmosphere, to obtain the silicon carbide epitaxial wafer.

15. 15. The method of claim 14, wherein the concentration of the dilute hydrochloric acid is 3% to 15% by weight.

16. 16. A silicon carbide epitaxial wafer produced by the method of any one of claims 1 to 15.

17. 17. The silicon carbide epitaxial wafer of claim 16, wherein the epitaxial layer on the silicon carbide epitaxial wafer has a thickness of 8 μm to 20 μm.

18. 18. The silicon carbide epitaxial wafer according to claim 16, wherein the epitaxial layer on the silicon carbide epitaxial wafer has a thickness of 10 μm to 18 μm.

19. 19. The silicon carbide epitaxial wafer according to any one of claims 16 to 18, wherein the silicon carbide epitaxial wafer has a minority carrier lifetime of 100 ns to 320 ns.

20. 20. The silicon carbide epitaxial wafer according to claim 16, wherein the silicon carbide epitaxial wafer has a minority carrier lifetime of 160 ns to 300 ns.

21. 21. The silicon carbide epitaxial wafer according to claim 16, wherein, on a surface of the silicon carbide epitaxial wafer, the total number of defects is 700 or less, the number of particles is 10 or less, the number of pits is 200 or less, the number of SFs and BPDs is both 100 or less, the number of black spots is 200 or less, and the content of Fe contamination is less than the order of magnitude of E9.

22. 22. The silicon carbide epitaxial wafer according to claim 16, wherein the surface of the silicon carbide epitaxial wafer has a total defect count of 600 or less, a particle count of 8 or less, a pit count of 150 or less, a SF and BPD count of 90 or less, a black spot count of 180 or less, and an Fe contamination content of less than the order of E9.

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