Integration of backside power rail / backside power distribution network with backside local interconnects

Abstract

The semiconductor device includes a backside power rail disposed in a space between N-channel field effect transistors and in a space between at least one P-channel field effect transistor and a P-channel field effect transistor; and a backside local signal line disposed between the backside power rails.

Description

[Technical Field]

[0001] TECHNICAL FIELD The exemplary embodiments described herein relate generally to semiconductor device design and integrated circuit design, and more particularly to the integration of backside power rails (BPR) and backside power distribution networks (BSPDN) with backside local interconnects.

[0002] The examples described herein provide local signal lines for both gate and source / drain (S / D) connections as well as backside source / drain supply voltage (VDD) and source / drain supply voltage (VSS). Summary of the Invention

[0003] In one aspect, a semiconductor device includes a backside power rail disposed in a space between N-channel field effect transistors and at least one P-channel field effect transistor; and a backside local signal line disposed between the backside power rails.

[0004] In another aspect, a method for forming a semiconductor device includes forming transistors on at least a portion of a substrate of a wafer, the transistors having at least one gate and at least one source / drain; forming front side contacts to some of the gates and source / drains; forming a back end of line and carrier wafer; inverting the wafer and removing at least a portion of the substrate; forming back side contacts to some of the gates and source / drains; forming a back side power rail to the back side contacts connected to the source / drains; wherein the back side power rail is formed in a space between N-channel field effect transistors and N-channel field effect transistors and in a space between at least one P-channel field effect transistor and P-channel field effect transistor; and forming a back side local signal line between the back side power rails.

[0005] In another aspect, a semiconductor device comprises two adjacent N-channel transistors; two adjacent P-channel transistors, wherein one N-channel transistor of the two adjacent N-channel transistors is adjacent to one P-channel transistor of the two adjacent P-channel transistors; a backside N-channel power rail for the two adjacent N-channel transistors is disposed between the two adjacent N-channel transistors; a backside P-channel power rail for the two adjacent P-channel transistors is disposed between the two adjacent P-channel transistors; and a backside local signal line for the N-channel transistor and the P-channel transistor is disposed between the adjacent N-channel transistor and the P-channel transistor. [Brief explanation of the drawings]

[0006] The foregoing and other aspects of the exemplary embodiments will become more apparent in the following detailed description when read in conjunction with the accompanying drawing figures.

[0007] [Figure 1]1A-1C illustrate semiconductor devices formed in accordance with examples described herein. [Figure 1-1] 1A-1C are cross-sectional views illustrating semiconductor devices formed in accordance with examples described herein. [Figure 1-2] 1A-1C are cross-sectional views illustrating semiconductor devices formed in accordance with examples described herein. [Figure 1-3] 1A-1C are cross-sectional views illustrating semiconductor devices formed in accordance with examples described herein.

[0008] [Figure 2] FIG. 1 illustrates vertical and horizontal metal pitch.

[0009] [Figure 3] FIG. 10 shows n-track cell height with backside routing (example of INV_X2).

[0010] [Figure 4] FIG. 10 shows n-track cell height with backside routing (NAND2_X1 example).

[0011] [Figure 5A] 1 is a cross-sectional view of a starting wafer for an integrated circuit. [Figure 5B] FIG. 2 is a top view including a cutaway portion of an integrated circuit.

[0012] [Figure 6A] FIG. 1 is a cross-sectional view of an integrated circuit after patterning nanosheets (NS) and forming shallow trench isolation (STI). [Figure 6B] FIG. 2 is a top view including a cutaway portion of an integrated circuit.

[0013] [Figure 7A] 1 is a cross-sectional view of an integrated circuit after forming a gate. [Figure 7B] 1 is a cross-sectional view of an integrated circuit after forming a gate. [Figure 7C]1 is a cross-sectional view of an integrated circuit after forming a gate. [Figure 7D] 7A, 7B, and 7C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 7A, 7B, and 7C to the top views.

[0014] [Figure 8A] 1 is a cross-sectional view of an integrated circuit after removing SiGe (eg, SiGe60), forming spacers, and forming bottom dielectric isolation (BDI). [Figure 8B] 1 is a cross-sectional view of an integrated circuit after removing SiGe (eg, SiGe60), forming spacers, and forming bottom dielectric isolation (BDI). [Figure 8C] 1 is a cross-sectional view of an integrated circuit after removing SiGe (eg, SiGe60), forming spacers, and forming bottom dielectric isolation (BDI). [Figure 8D] 8A, 8B, and 8C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 8A, 8B, and 8C to the top views.

[0015] [Figure 9A] Cross-sectional view of an integrated circuit after patterning nanosheets (NSs), forming inner spacers, forming source / drain epitaxy, depositing interlayer insulators, and chemical mechanical polishing (CMP). [Figure 9B] Cross-sectional view of an integrated circuit after patterning nanosheets (NSs), forming inner spacers, forming source / drain epitaxy, depositing interlayer insulators, and chemical mechanical polishing (CMP). [Figure 9C] Cross-sectional view of an integrated circuit after patterning nanosheets (NSs), forming inner spacers, forming source / drain epitaxy, depositing interlayer insulators, and chemical mechanical polishing (CMP). [Figure 9D] 9A, 9B, and 9C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 9A, 9B, and 9C to the top views.

[0016] [Figure 10A] 1 is a cross-sectional view of an integrated circuit after forming a gate cut, removing the gate, releasing the SiGe, and forming a high-k metal gate (HKMG). [Figure 10B] 1 is a cross-sectional view of an integrated circuit after forming a gate cut, removing the gate, releasing the SiGe, and forming a high-k metal gate (HKMG). [Figure 10C] 1 is a cross-sectional view of an integrated circuit after forming a gate cut, removing the gate, releasing the SiGe, and forming a high-k metal gate (HKMG). [Figure 10D] 10A, 10B, and 10C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 10A, 10B, and 10C to the top views.

[0017] [Figure 11A] 1 is a cross-sectional view of an integrated circuit after forming middle-of-line (MOL) contacts, forming back-end-of-line (BEOL), and bonding a carrier wafer. [Figure 11B] 1 is a cross-sectional view of an integrated circuit after forming middle-of-line (MOL) contacts, forming back-end-of-line (BEOL), and bonding a carrier wafer. [Figure 11C] 1 is a cross-sectional view of an integrated circuit after forming middle-of-line (MOL) contacts, forming back-end-of-line (BEOL), and bonding a carrier wafer. [Figure 11D] 11A, 11B, and 11C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 11A, 11B, and 11C to the top views.

[0018] [Figure 12A] 1 is a cross-sectional view of the integrated circuit after flipping the wafer, removing the substrate, and stopping on the etch stop layer. [Figure 12B]1 is a cross-sectional view of the integrated circuit after flipping the wafer, removing the substrate, and stopping on the etch stop layer. [Figure 12C] 1 is a cross-sectional view of the integrated circuit after flipping the wafer, removing the substrate, and stopping on the etch stop layer. [Figure 12D] 12A, 12B, and 12C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 12A, 12B, and 12C to the top views.

[0019] [Figure 13A] FIG. 1 is a cross-sectional view of the integrated circuit after removal of the etch stop layer and removal of the remaining Si. [Figure 13B] FIG. 1 is a cross-sectional view of the integrated circuit after removal of the etch stop layer and removal of the remaining Si. [Figure 13C] FIG. 1 is a cross-sectional view of the integrated circuit after removal of the etch stop layer and removal of the remaining Si. [Figure 13D] 13A, 13B, and 13C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 13A, 13B, and 13C to the top views.

[0020] [Figure 14A] 1 is a cross-sectional view of an integrated circuit after backside interlayer dielectric (ILD) filling and planarization. [Figure 14B] 1 is a cross-sectional view of an integrated circuit after backside interlayer dielectric (ILD) filling and planarization. [Figure 14C] 1 is a cross-sectional view of an integrated circuit after backside interlayer dielectric (ILD) filling and planarization. [Figure 14D] 14A, 14B, and 14C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 14A, 14B, and 14C to the top views.

[0021] [Figure 15A] 1 is a cross-sectional view of an integrated circuit after forming a backside contact. [Figure 15B]1 is a cross-sectional view of an integrated circuit after forming a backside contact. [Figure 15C] 1 is a cross-sectional view of an integrated circuit after forming a backside contact. [Figure 15D] 15A, 15B, and 15C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 15A, 15B, and 15C to the top views.

[0022] [Figure 16A] 1 is a cross-sectional view of an integrated circuit after forming a backside power rail and local signal lines. [Figure 16B] 1 is a cross-sectional view of an integrated circuit after forming backside power rails and local signal lines. [Figure 16C] 1 is a cross-sectional view of an integrated circuit after forming backside power rails and local signal lines. [Figure 16D] 16A, 16B, and 16C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 16A, 16B, and 16C to the top views.

[0023] [Figure 17A] 1 is a cross-sectional view of an integrated circuit after forming a backside power distribution network (BSPDN). [Figure 17B] 1 is a cross-sectional view of an integrated circuit after forming a backside power distribution network (BSPDN). [Figure 17C] 1 is a cross-sectional view of an integrated circuit after forming a backside power distribution network (BSPDN). [Figure 17D] 17A, 17B, and 17C are top views of an integrated circuit, including cut lines (Y, X1, and X2, respectively) relating the cross-sectional views shown in FIGS. 17A, 17B, and 17C to the top views.

[0024] [Figure 18A] 1 is a cross-sectional view of an integrated circuit. [Figure 18B] 1 is a cross-sectional view of an integrated circuit. [Figure 18C] 18A and 18B are cross-sectional views of the integrated circuit, where FIG. 18C shows cross section X3. [Figure 18D] 18A, 18B, and 18C are top views of an integrated circuit, including cut lines (Y, X1, and X3, respectively) relating the cross-sectional views shown in FIGS. 18A, 18B, and 18C to the top views.

[0025] [Figure 19] 1 is a flow diagram for manufacturing a device according to examples described herein. DETAILED DESCRIPTION OF THE INVENTION

[0026] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described in this detailed description are example embodiments provided to enable any person skilled in the art to make or use the invention and do not limit the scope of the invention, which is defined by the claims.

[0027] This document describes the integration of backside power rails (BPR) and backside power distribution networks (BSPDN) with backside local interconnects. The structure described herein has local signal lines for both gate and source / drain (S / D) connections as well as backside source / drain supply voltages (VDD and VSS). In current structures, the backside power rails (BPR) and backside power distribution networks (BSPDN) do not coexist with the local interconnects.

[0028] Based on the examples described herein, a method for forming a semiconductor device includes forming transistors having gates and source / drains (S / Ds), forming front side contacts to some of the gates and S / Ds (source / drains), forming a back end of line and carrier wafer, inverting the wafer and removing the substrate, forming back side contacts to some of the gates and S / Ds, forming back side power rails to the back side contacts connected to the S / Ds in N2N or P2P spaces, and forming back side local signal lines to the back side contacts between the back side power rails or in N2P spaces.

[0029] Based on the examples described herein, a semiconductor device comprises: two adjacent N-channel transistors; two adjacent P-channel transistors, where one N-channel transistor of the two adjacent N-channel transistors is adjacent to one P-channel transistor of the two adjacent P-channel transistors; where a backside N-channel power rail for the two adjacent N-channel transistors is disposed between the two adjacent N-channel transistors; a backside P-channel power rail for the two adjacent P-channel transistors is disposed between the two adjacent P-channel transistors; and a backside local signal line for the N-channel transistor and the P-channel transistor is disposed between the adjacent N-channel transistor and the P-channel transistor.

[0030] 1-1-13, described herein is a semiconductor device 100 including backside power rails (106, 108, 110) disposed in an N2N space (102) and a P2P space (104). The semiconductor device 100 includes backside local signal lines (112, 114) disposed between the backside power rails (106, 108, 110). The backside power rails (106, 108, 110) of the semiconductor device 100 connect to the S / D epitaxy through backside contacts. The backside local signal lines (112, 114, 116) of the semiconductor device 100 connect to the source / drain epitaxy or gate (124) through backside contacts (126). The semiconductor device 100 has a standard cell architecture with horizontally extending local signal lines (112, 114, 116, 117) on the backside and a first frontside metal that extends vertically. Also shown in Figure 1 are transistor 113, N2P space (105), N-channel field effect transistor regions or spaces (504, 506, 512, 514), and P-channel field effect transistor regions or spaces (508, 510).

[0031] As the cell height is reduced while maintaining the same number of metal layer 0 (M0) signal tracks, the M0 pitch is reduced, i.e., from 28 to 24 to 18 to 16. A tighter M0 pitch has narrower metal and smaller vias, which have higher resistance. Since circuit output nodes are connected through these higher resistance metals and vias, circuit delay is affected. The structures described herein relate to standard cell architectures that utilize backside metal to alleviate this high resistance bottleneck.

[0032] FIG. 2 illustrates a high-performance cell architecture with backside metal. In particular, FIG. 2 illustrates a vertical metal pitch (202) of a given dimension (e.g., in nm) and a horizontal metal pitch (204) of a given dimension (e.g., in nm). Vertical metal pitch 202 includes at least signal line 206. Horizontal metal pitch 204 includes at least source / drain supply voltage 208, signal line 210, signal line 212, signal line 214, and source / drain supply voltage 216. As an example, for the configuration illustrated in FIG. 2, in which metal layer 220 is connected to metal layer 222 using via 221, and metal layer 222 is connected to source / drain 226 using via 224, M0P is a given dimension (e.g., in nm) and M1P is a given dimension (e.g., in nm). If the resistance between metal layer 220 and metal layer 222 is a given value M (e.g., in Ω), and the resistance between metal layer 222 and source / drain 226 is a given value N (e.g., in Ω), where via 224 has a size that is aXb for values ​​a and b, then the resistance will be high and performance will be limited.

[0033] FIG. 3 illustrates a high-performance cell architecture with backside metal. In particular, FIG. 3 illustrates an n-track cell height (example INV_X2) with backside routing. Vertical signal tracks (302, 304, 306, 308, 310) are shown on the front side 301, along with output Y 312 along vertical signal track 306. Wafer 300 includes p-channel 314 and n-channel 316. Backside 303 of wafer 300 includes horizontal power and signal tracks (322, 324, 326, 328, 330) that are used, for example, to add backside wires to the backside power distribution network. Source / drain supply voltages (332, 334) are also shown. FIG. 3 further illustrates a configuration in which output Y 312 is coupled to source / drain 342 using via 340. In this case, larger via 340 provides lower resistance and improved performance. If the size of via 340 is sxt for values ​​s and t, then the resistance is given by a value (eg, in ohms).

[0034] FIG. 4 illustrates an n-track cell height (example NAND2_X1) with backside routing. Vertical signal tracks (402, 404, 406, 408, 410) on front side 401 are shown, with output Y 412 along vertical signal track 410. Wafer 400 includes p-channel 414 and n-channel 416. Signal line 420 and via 440 are along signal track 408, and signal line 418 and via 442 are along track 404. Backside 403 of wafer 400 includes horizontal power and signal tracks (422, 424, 426, 428, 430) used, for example, to add backside wires to the backside power distribution network. Signal line 436 is along track 422. Source / drain supply voltages (432, 434) are also shown. FIG. 4 further illustrates a configuration in which output Y 412 is coupled to source / drain 444 using via 442. In this case, larger via 442 results in lower resistance and improved performance. If the size of via 442 is ixj for values ​​i and j, the resistance is given by a value (eg, in ohms).

[0035] 5-17 illustrate an exemplary process flow for forming a semiconductor device or integrated circuit according to examples described herein.

[0036] 5A shows a starting wafer 500 for an integrated circuit, specifically a Y-cut 501. The SiGe 30 layer 502, also known as an etch stop layer 502, may be (e.g., alternatively) a BOX SiO2 layer if it is unable to stop substrate removal. The Y-cut 501 includes a hard mask 520, a silicon layer 522, SiGe 30 layers (502, 526, 528, 530) within the silicon layer 522, and a SiGe 55 layer (524) within the silicon layer 522. Layer 524 may be a SiGe 60 layer.

[0037] Figure 5B shows a top view of an integrated circuit including cut lines for Y cut 501, X1 cut 503, and X2 cut 505. Figure 5B also shows N-channel field effect transistor regions (504, 506, 512, 514), P-channel field effect transistor regions (508, 510), and gate (516). In Figure 5B, Y is a cut line that relates the top view of Figure 5B to the cross-sectional view of Figure 5A. In Figure 5B, Y indicates a cut line for the cross section.

[0038] FIG. 6A shows a Y cut 501 of an integrated circuit after nanosheet (NS) patterning and shallow trench isolation (STI) formation, and FIG. 6B shows a top view of the integrated circuit, including cut lines for cuts Y 501, X1 503, and X2 505 of the integrated circuit. Nanosheet patterning involves removing hard mask 520 and forming etched portions 602 in silicon layer 522, SiGe30 layers (526, 528, 530), and SiGe55 layer 524. Shallow trench isolation 604 is formed in silicon layer 522 below etched portions 602 and above SiGe30 layer 502. In FIG. 6B, Y is a cut line that relates the top view of FIG. 6B to the cross-sectional view of FIG. 6A. In FIG. 6B, Y indicates a cut line for the cross section.

[0039] FIG. 7A shows a cross-section of the integrated circuit at Y cut 501 after gate formation. FIG. 7B shows a cross-section of the integrated circuit at X1 cut 503 after gate formation. FIG. 7C shows a cross-section of the integrated circuit at X2 cut 505 after gate formation. In Y cut 501, gate 516 is formed in and over etch 602 and in contact with shallow trench isolation layer 604. A mask layer 702 is formed over gate 516. FIG. 7B shows, in X1 cut 503, gate (516) is formed over shallow trench isolation layer 604 and mask layer 702 is formed over gate (516). FIG. 7C shows, in X2 cut 505, gate (516) is formed over silicon layer 522 and mask layer 702 is formed over gate (516). Figure 7D shows a top view of an integrated circuit including cut lines Y 501, X1 503, and X2 505 shown in Figures 7A, 7B, and 7C, respectively. In Figure 7D, Y, X1, and X2 are cut lines that relate the top view of Figure 7D to the cross-sectional views of Figures 7A, 7B, and 7C. In Figure 7D, Y, X1, and X2 indicate cut lines for the cross sections.

[0040] 8A, 8B, and 8C show cross-sectional views (Y501, X1 503, and X2 505, respectively) of an integrated circuit after removing the SiGe55 or SiGe60 layer 524, forming spacers, and forming bottom dielectric isolation (BDI) 802. In the Y cut 501, the bottom dielectric isolation 802 is formed in place of the removed SiGe60 layer 524. In the X1 cut 503, spacers 804 are formed along the sides of the gate (516) and mask layer 702. In the X2 cut 503, the bottom dielectric isolation 802 is formed in place of the removed SiGe55 or SiGe60 layer 524, and spacers are formed along the sides of the gate (516) and mask layer 702. FIG. 8D shows the cuts (Y501, X1 503, and X2 505, respectively) shown in FIGS. 8A, 8B, and 8C. In Figure 8D, Y, X1 and X2 are section lines that relate the top view of Figure 8D to the cross-sectional views of Figures 8A, 8B and 8C. In Figure 8D, Y, X1 and X2 indicate the section lines for the cross sections.

[0041] Figure 9A shows the Y cut 501 after removing the mask layer 702 (shown as 902) and performing chemical mechanical polishing. Figure 9B shows the X1 cut 503 after depositing an interlayer insulator 904, which is deposited along the sides of the spacers 804 and above the shallow trench isolation 604, and after chemical mechanical polishing. Figure 9C shows the X2 cut 505 after forming source / drain epitaxy 906 in the interlayer insulator 904 above the bottom dielectric isolation 802 and on the sides of the spacers 804, and in the interlayer insulator 904 above the bottom dielectric isolation 802 and on the sides of the spacers 804. FIG. 9C further illustrates that inner spacers 908 have been formed below the spacers 804 and the gate (516), between the source / drain epitaxy 906 above the lower dielectric isolation 802, between portions of the silicon layer 522, and along the sides of portions of the SiGe 30 layers (526, 528, 530). Operations performed in the context of FIG. 9C may also include chemical-mechanical polishing. FIG. 9D illustrates the cuts (Y 501, X1 503, and X2 505, respectively) shown in FIGS. 9A, 9B, and 9C. In FIG. 9D, Y, X1, and X2 are cut lines that relate the top view of FIG. 9D to the cross-sectional views of FIGS. 9A, 9B, and 9C. In FIG. 9D, Y, X1, and X2 indicate cut lines for the cross sections.

[0042] 10A, 10B, and 10C each show a cross-sectional view of an integrated circuit after forming a gate cut, removing the gate, releasing (removing) the SiGe, and forming a high-k metal gate. In particular, FIG. 10A shows a gate cut 1002 formed at the Y cut 501 and over the shallow trench isolation 604. FIG. 10A also shows that a high-k metal gate 124 is formed between the gate cut 1002 and over at least a portion of the shallow trench isolation 604 and silicon layer 522, as well as in the area where the SiGe 30 layers (526, 528, 530) were released. FIG. 10B shows that the high-k metal gate 124 at the X1 cut 503 is formed in the area where the gate (516) was removed. Figure 10C shows that at X2 cut 505, gate 516 has been removed and high-k metal gate 124 has been formed in the region where SiGe 30 layers (526, 528, 530) have been released between silicon layers 522, between inner spacers 908, between spacers 804, and above bottom dielectric isolation 802. Figure 10D shows the cuts (Y501, X1 503, and X2 505, respectively) shown in Figures 10A, 10B, and 10C. Figure 10D shows that gate cut 1002 has been formed between N-channel field effect transistor regions 504 and 506, P-channel field effect transistor regions 508 and 510, and N-channel field effect transistor regions 512 and 514. In Figure 10D, Y, X1 and X2 are section lines that relate the top view of Figure 10D to the cross-sectional views of Figures 10A, 10B and 10C. In Figure 10D, Y, X1 and X2 indicate the section lines for the cross sections.

[0043] 11A, 11B, and 11C show cross-sectional views of the integrated circuit after forming the MOL contacts, forming the BEOL, and bonding the carrier wafer, respectively.

[0044] 11A shows that in the Y cut 501, a layer of insulator 1102 has been formed over the high-k metal gate 124 and the gate cut 1002. A middle-of-line gate contact 1104 has been formed within the insulator 1102 to join the high-k metal gate 124 to a metal layer in the back-of-line interlayer dielectric layer 1108 after formation. Additionally, in the Y cut 501, additional BEOL layers 1110 have been formed above the back-of-line interlayer dielectric 1108, and a carrier wafer 1112 has been disposed above the additional BEOL layers 1110.

[0045] 11B shows that at the X1 cut 503, an insulating layer 1102 is formed over the interlayer insulator 904, the high-k metal gates 124, and the spacers 804. A middle-of-line gate contact 1104 connects one of the high-k metal gates 124 and the corresponding spacer 804 to a via 1114 within the back-end-of-line interlayer insulator 1108, which is bonded to a metal layer 1116 bonded to an additional back-end-of-line layer 1110 over which the carrier wafer 1112 is positioned. As shown in FIG. 11B, at the X1 cut 503, there are multiple metal layers 1116 bonded to the additional back-end-of-line layer 1110.

[0046] 11C shows that at the X2 cut 505, an insulating layer 1102 is formed over the source / drain epitaxy 906, the high-k metal gate 124, and the corresponding spacers 804. A middle-of-line source / drain contact 1106 connects the source / drain epitaxy (906) to a via 1114 in a back-of-line interlayer insulator 1108 above the insulating layer 1102, which in turn connects to a metal layer 1116 connected to an additional back-of-line layer 1110. At the X2 cut 505, multiple metal layers 1116 are formed in the back-of-line interlayer insulator 1108, and these metal layers 1116 are bonded to the additional back-of-line layer 1110. At the X2 cut 505, a carrier wafer 1112 is positioned over the additional back-of-line layer 1110.

[0047] 11D shows the cuts (Y501, X1 503, and X2 505, respectively) shown in FIGS. 11A, 11B, and 11C. FIG. 11D shows that a middle-of-line source / drain contact 1106 is formed in N-channel field effect transistor region 504, a middle-of-line source / drain contact 1106 is formed in N-channel field effect transistor region 506, a middle-of-line gate contact 1104 is formed between N-channel field effect transistor region 506 and P-channel field effect transistor region 508 and with gate 516, a middle-of-line source / drain contact 1106 is formed in P-channel field effect transistor region 508, and a middle-of-line gate contact 1104 is formed between N-channel field effect transistor region 506 and P-channel field effect transistor region 508. 11D shows that a brine source / drain contact 1106 is formed in the P-channel field effect transistor region 510, two middle-of-line gate contacts (1104) are formed between the P-channel field effect transistor region 510 and the N-channel field effect transistor region 512 and on the gate (516), a middle-of-line source / drain contact 1106 is formed in the N-channel field effect transistor region 512, and a middle-of-line source / drain contact 1106 is formed in the N-channel field effect transistor region 514. In Figure 11D, Y, X1, and X2 are cut lines that relate the top view of Figure 11D to the cross-sectional views of Figures 11A, 11B, and 11C. In Figure 11D, Y, X1, and X2 indicate cut lines for the cross sections.

[0048] Figures 12A, 12B, and 12C each show a cross-sectional view of an integrated circuit after flipping the wafer, removing the substrate, and stopping on the etch stop layer. Figure 12A shows, at Y cut 501, that after the wafer has been flipped (1202), the carrier wafer 1112 is on the bottom and the etch stop layer 502 is on the top. Stopping on the etch stop layer 502 to remove a portion of the substrate 522 is shown as 1208 in Y cut 501. Figure 12B shows, at X1 cut 503, that after the wafer has been flipped (1204), the carrier wafer 1112 is on the bottom and the etch stop layer 502 is on the top. Stopping on the etch stop layer 502 to remove a portion of the substrate 522 is shown as 1208 in X1 cut 503. FIG. 12C shows the X2 cut 505 after the wafer has been flipped (1206) so that the carrier wafer 1112 is on the bottom and the etch stop layer 502 is on top. The removal of a portion of the substrate 522 by stopping at the etch stop layer 502 is indicated as 1208 in the X2 cut 505. FIG. 12D shows the views of the cuts shown in FIGS. 12A, 12B, and 12C (Y 501, X1 503, and X2 505, respectively). In FIG. 12D, Y, X1, and X2 are cut lines that relate the top view of FIG. 12D to the cross-sectional views of FIGS. 12A, 12B, and 12C. In FIG. 12D, Y, X1, and X2 indicate cut lines for the cross-sections.

[0049] FIGS. 13A, 13B, and 13C each show a cross-sectional view of an integrated circuit after removal of the etch stop layer and subsequent removal of the remaining Si. FIG. 13A shows that the silicon of silicon layer 522 between shallow trench isolations 604 and above bottom dielectric isolation 802 at Y cut 501 has been removed (shown as 1302). At Y cut 501, etch stop layer 502 has also been removed (shown as 1304). FIG. 13B shows that the silicon of silicon layer 522 above shallow trench isolation 604 has been removed at X1 cut 503 (shown as 1302). Etch stop layer 502 is also shown as being removed at X1 cut 503 (shown as 1304). FIG. 13C shows that the silicon layer 522 above bottom dielectric isolation 802 has been removed at X2 cut 505 (shown as 1302). The etch stop layer 502 is also shown removed at X2 cut 505 (shown as 1304). Figure 13D shows the cuts shown in Figures 13A, 13B, and 13C (Y 501, X1 503, and X2 505, respectively). In Figure 13D, Y, X1, and X2 are cut lines that relate the top view of Figure 13D to the cross-sectional views of Figures 13A, 13B, and 13C. In Figure 13D, Y, X1, and X2 indicate cut lines for the cross sections.

[0050] Figures 14A, 14B, and 14C each show an integrated circuit cut after backside interlayer dielectric filling and planarization. Figure 14A shows that at Y cut 501, backside interlayer dielectric 1402 has been filled between shallow trench isolation 604 adjacent to bottom dielectric isolation 802 where silicon 522 was removed (1302). Figure 14C shows at X2 cut 505, backside interlayer dielectric 1402 has been formed where silicon 522 was removed (1302) adjacent to bottom dielectric isolation 802. Figure 14D shows the cuts shown in Figures 14A, 14B, and 14C (Y501, X1 503, and X2 505, respectively). In Figure 14D, Y, X1, and X2 are section lines that relate the top view of Figure 14D to the cross-sectional views of Figures 14A, 14B, and 14C. In Figure 14D, Y, X1, and X2 indicate the section lines for the cross sections.

[0051] Figures 15A, 15B, and 15C each show a cross-sectional view of the integrated circuit after backside contact formation. Figure 15A shows that at the Y cut 501, the backside-to-gate contact 126 is formed within the shallow trench isolation 604 between the backside interlayer insulator 1402 to contact the high-k metal gate 124. Figure 15B shows that at the X1 cut 503, the backside-to-gate contact (126) is formed within the shallow trench isolation 604 to contact the high-k metal gate 124 and spacers 804. Figure 15C shows that the backside-to-source / drain contact (1504) is formed within the backside interlayer insulator 1402 and bottom dielectric isolation 802 to contact the source / drain (906). Figure 15D illustrates the cuts (Y 501, X1 503, and X2 505, respectively) shown in Figures 15A, 15B, and 15C. Figure 15D shows that backside source / drain contacts (1504) are formed within the N-channel field effect transistor regions (504, 506, 512, 514), and that a backside gate contact (126) is formed between the N-channel field effect transistor region 506 and the P-channel field effect transistor region 508 on the gate (516). In Figure 15D, Y, X1, and X2 are cut lines that relate the top view of Figure 15D to the cross-sectional views of Figures 15A, 15B, and 15C. In Figure 15D, Y, X1, and X2 indicate cut lines for the cross-sections.

[0052] 16A, 16B, and 16C each show cuts of an integrated circuit after forming backside power rails and local signal lines. FIG. 16A shows that in the Y cut 501, an additional backside interlayer insulator 1602 is formed above the shallow trench isolation 604 and backside contact 126. The backside power rails (106, 108, 110) and local signal lines (112, 114) are formed within the additional backside interlayer insulator 1602. The backside power rails (106, 108, 110) and local signal line 114 are coupled to the shallow trench isolation 604, and the local signal line 112 is coupled to the backside contact 126. The backside power rail is formed at least partially above the backside interlayer insulator (1402).

[0053] Figure 16B shows that at the X1 cut 503, an additional backside interlayer insulator 1602 is formed above the shallow trench isolation 604 and backside contact (126). The local signal line 116 is formed within the additional backside interlayer insulator 1602 and is coupled to the backside contact (125) and shallow trench isolation 604. Figure 16C shows that at the X2 cut 505, an additional backside interlayer insulator 1602 is formed above the backside-to-source / drain contact (1504) and backside interlayer insulator 1402. Figure 16D shows the cuts shown in Figures 16A, 16B, and 16C (Y501, X1 503, and X2 505, respectively). Figure 16D shows the N2N space (102), the P2P space (104), and the N2P space (105). Power rails (106, 108, 110) are in the N2N space (102) and the P2P space 104. Local signal lines (112, 114, 116) are in the N2P space (105). See also FIG. 1. In FIG. 16D, Y, X1, and X2 are cut lines that relate the top view of FIG. 16D to the cross-sectional views of FIGS. 16A, 16B, and 16C. In FIG. 16D, Y, X1, and X2 indicate cut lines for the cross sections.

[0054] 17A, 17B, and 17C each show a cross-sectional view of the integrated circuit after forming a backside power distribution network. FIG. 17A shows that an additional backside interlayer insulator 1702 has been formed above the backside interlayer insulator 1602, the power rails (106, 108, 110), and the local signal lines (112, 114) at the Y-cut 501. Vias (1706) are formed within the additional backside interlayer insulator 1702 to couple the power rails (106, 110) to the formed backside power distribution network (1704). As shown, the backside power distribution network 1704 is formed such that it is partially coupled to the additional backside interlayer insulator 1702.

[0055] FIG. 17B shows that at X1 cut 503, an additional backside interlayer insulator 1702 is formed above the backside interlayer insulator 1602 and the local signal line 116, and a backside power distribution network 1704 is formed adjacent to the additional backside interlayer insulator 1702. FIG. 17C shows that at X2 cut 505, the backside interlayer insulator 1702 is formed above the backside interlayer insulator 1602, and a backside power distribution network 1704 is formed adjacent to the backside interlayer insulator 1702. FIG. 17D shows the cuts shown in FIGS. 17A, 17B, and 17C (Y501, X1 503, and X2 505, respectively). In FIG. 17D, Y, X1, and X2 are cut lines that relate the top view of FIG. 17D to the cross-sectional views of FIGS. 17A, 17B, and 17C. In FIG. 17D, Y, X1 and X2 indicate cutting lines for the cross section.

[0056] Figures 18A, 18B, and 18C each show a cut of the integrated circuit, with Figure 18C showing cut X3 507. Figure 18D shows the cuts shown in Figures 18A, 18B, and 18C (Y501, X1 503, and X3 507, respectively). Figure 18D also shows INV_X2 1802 and NAND2_X1 1804 at cut X3 507. In Figure 18D, Y, X1, and X3 are cut lines that relate the top view of Figure 18D to the cross-sectional views of Figures 18A, 18B, and 18C. In Figure 18D, Y, X1, and X3 indicate cut lines for the cross sections.

[0057] 19 is a flow diagram for fabricating a device according to examples described herein. At 1910, the method includes forming a transistor (113) having at least one gate (124) and at least one source / drain (906) on at least a portion of a substrate (522) of a wafer (500). At 1920, the method includes forming front-side contacts (1104, 1106) to some of the gates (124) and source / drains (906). At 1930, the method includes forming a back-end of line (1108, 1110) and a carrier wafer (1112). At 1940, the method includes inverting the wafer (500) and removing at least a portion of the substrate (522). At 1950, the method includes forming back-side contacts (126, 1504) to some of the gates (124) and source / drains (906). At 1960, the method includes forming backside power rails (106, 108, 110) to backside contacts (1504) connected to the source / drains (906). At 1970, the method includes forming the backside power rails (106, 108, 110) in the spaces (102) between N-channel field effect transistors and in the spaces (104) between at least one P-channel field effect transistor. At 1980, the method includes forming backside local signal lines (112, 114) between the backside power rails (106, 108, 110).

[0058] Referring now to all figures, in one exemplary embodiment, a semiconductor device includes backside power rails disposed in spaces between N-channel field effect transistors and at least one P-channel field effect transistor, and a backside local signal line disposed between the backside power rails.

[0059] A backside power rail may be connected to the source / drain epitaxy through a backside contact. A backside local signal line may be connected to the source / drain epitaxy or the gate through a backside contact. The semiconductor device may include a cell architecture with a backside local signal line extending horizontally on the backside and a frontside metal extending vertically. The semiconductor device may include at least one pair of adjacent N-channel transistors. The backside power rail may include at least one backside N-channel power rail for the at least one pair of adjacent N-channel transistors, the at least one backside N-channel power rail being disposed between the at least one pair of adjacent N-channel transistors. The semiconductor device may include two adjacent P-channel transistors, at least one N-channel transistor of the at least one pair of adjacent N-channel transistors being adjacent to one P-channel transistor of the two adjacent P-channel transistors. The semiconductor device may include at least one backside P-channel power rail for two adjacent P-channel transistors, the at least one backside P-channel power rail being disposed between the two adjacent P-channel transistors. The semiconductor device can include a backside local signal line for the N-channel transistors and the P-channel transistors, the backside local signal line being disposed between at least one of the N-channel transistors and at least one of the P-channel transistors.

[0060] In one embodiment, a method for forming a semiconductor device includes forming transistors having at least one gate and at least one source / drain on at least a portion of a substrate of a wafer; forming front side contacts to some of the gates and source / drains; forming a back end of line and carrier wafer; inverting the wafer and removing at least a portion of the substrate; forming back side contacts to some of the gates and source / drains; forming a back side power rail to the back side contacts connected to the source / drains; where the back side power rail is formed in a space between N-channel field effect transistor to N-channel field effect transistor and in a space between at least one P-channel field effect transistor to P-channel field effect transistor; and forming a back side local signal line between the back side power rails.

[0061] The method may include forming a backside local signal line connecting to at least one source / drain or gate through at least one backside contact. The method may include forming a cell architecture having a backside local signal line extending horizontally on the backside and a frontside metal extending vertically. The method may include forming a backside signal line in a space from an N-channel field effect transistor to a P-channel field effect transistor. The method may include forming at least one pair of adjacent N-channel transistors, where the backside power rail includes at least one backside N-channel power rail for the at least one pair of adjacent N-channel transistors, and the at least one backside N-channel power rail is disposed between the at least one pair of adjacent N-channel transistors; and forming two adjacent P-channel transistors, where at least one N-channel transistor of the at least one pair of adjacent N-channel transistors is adjacent to one P-channel transistor of two adjacent P-channel transistors. The backside power rails can include at least one backside P-channel power rail for two adjacent P-channel transistors, the at least one backside P-channel power rail being disposed between the two adjacent P-channel transistors, and the backside local signal lines are for the N-channel transistors and the P-channel transistors, the backside local signal line being disposed between at least one of the N-channel transistors and at least one of the P-channel transistors.

[0062] In another embodiment, a semiconductor device comprises two adjacent N-channel transistors; two adjacent P-channel transistors, where one N-channel transistor of the two adjacent N-channel transistors is adjacent to one P-channel transistor of the two adjacent P-channel transistors; a backside N-channel power rail for the two adjacent N-channel transistors is disposed between the two adjacent N-channel transistors, a backside P-channel power rail for the two adjacent P-channel transistors is disposed between the two adjacent P-channel transistors, and a backside local signal line for the N-channel transistor and the P-channel transistor is disposed between the adjacent N-channel transistor and the P-channel transistor.

[0063] The semiconductor device may further comprise at least one backside contact connecting to at least one source / drain or at least one gate. A backside N-channel power rail may be connected to at least one source / drain using at least one backside contact. A backside local signal line may be connected to at least one source / drain or at least one gate using at least one backside contact. The semiconductor device may further comprise a cell architecture having a backside local signal line extending horizontally on the backside and a frontside metal extending vertically.

[0064] References to "computer," "processor," and the like should be understood to encompass computers having a variety of architectures, such as single- or multi-processor architectures, and sequential or parallel architectures, as well as special-purpose circuitry, such as field-programmable gate arrays (FPGAs), application specific circuits (ASICs), signal processing devices, and other processing circuitry. References to computer programs, instructions, code, and the like should be understood to encompass software for a programmable processor, or firmware, such as the programmable contents of a hardware device, whether, for example, instructions to a processor or configuration settings for a fixed-function device, gate array, programmable logic device, or the like.

[0065] The memories described herein may be implemented using any suitable data storage technology, such as semiconductor-based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, non-transitory memory, transient memory, fixed memory and removable memory, etc. The memories may comprise databases for storing data.

[0066] As used herein, a circuit may refer to: (a) a hardware circuit implementation, e.g., an implementation in analog and / or digital circuitry, and (b) a combination of circuitry and software (and / or firmware), such as (where applicable): (i) a combination of a processor, or (ii) a portion of a processor / software including a digital signal processor, software, and memory that work together to cause a device to perform various functions, and (c) a circuit, e.g., a microprocessor or portion of a microprocessor that requires software or firmware for operation even when the software or firmware is not physically present. As another example, as used herein, a circuit will also include implementations of just a processor (or processors), or a processor and its (or their) accompanying software and / or firmware portions. A circuit will also include, for example, a baseband integrated circuit or an application processor integrated circuit for a mobile phone, or a similar integrated circuit in a server, cellular network device, or another network device, if applicable to the particular element.

[0067] A list of abbreviations, which may be appended to each other or to other characters, for example, using a dash or hyphen ("-"). A Circuit (inverter) input pin (e.g., Figure 4) ASIC Application Specific Integrated Circuit B The second input pin in the circuit (e.g., Figure 4) BDI bottom dielectric isolation BEOL Back End of Line BOX buried oxide BPR Backside Power Rail BSPDN Backside Power Supply / Distribution Network CA Source / Drain Contacts Contact to CB gate CMP chemical mechanical planarization / polishing epi epitaxy FPGA Field Programmable Gate Array HKMG high-k metal gate HM Hard Mask ILD Interlayer Insulator INV_X2 Inverter X2 circuit M0 Metal layer 0 M0P M0 pitch M1 Metal layer 1 M1P M1 pitch MOL Middle of the Line NN channel NAND Negative logical AND NAND2_X1 NAND2 X1 logic circuit N2N N-channel field effect transistor to N-channel field effect transistor spacing N2P N-channel field effect transistor to P-channel field effect transistor spacing Backside contact to nCA source / drain Backside contact to nCB gate NFET N-channel field effect transistor NS nanosheet n tracks n tracks PP channel P2P P-channel field effect transistor to P-channel field effect transistor spacing PC Gate PFET P-channel field effect transistor Si Silicon SiGe Silicon Germanium (e.g. SiGe30, SiGe55, SiGe60) SiO2 Silicon dioxide STI Shallow Trench Isolation S / D Source / Drain V0 Via 0 VA or Va Via to Source / Drain Contact VDD The source / drain supply voltage, or its supply line, which is usually a positive voltage. VSS The source / drain supply voltage or its supply line, which is usually 0V or ground.

[0068] In the foregoing description, numerous specific details have been set forth, such as particular structures, components, materials, dimensions, process steps, and techniques, to provide a thorough understanding of the exemplary embodiments disclosed herein. However, those skilled in the art will understand that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or process steps may be omitted or not described to avoid obscuring the presented embodiments.

[0069] The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the form disclosed. Many modifications and variations will become apparent to those skilled in the art without departing from the scope of the invention. The embodiments have been chosen and described to best explain the principles and practical applications of the invention and to enable others skilled in the art to understand the invention in terms of various embodiments with various modifications suited to the particular uses contemplated.

Claims

1. a backside power rail disposed in a space between an N-channel field effect transistor and in a space between at least one P-channel field effect transistor; and a backside local signal line disposed between the backside power rails A semiconductor device comprising:

2. 10. The semiconductor device of claim 1, wherein the backside power rail connects to the source / drain epitaxy through a backside contact.

3. 2. The semiconductor device of claim 1, wherein the backside local signal line connects to the source / drain epitaxy or the gate through a backside contact.

4. The semiconductor device of claim 1 further comprising a cell architecture having the backside local signal lines extending horizontally on the backside and frontside metal extending vertically.

5. The semiconductor device of claim 1 , further comprising at least one pair of adjacent N-channel transistors.

6. 6. The semiconductor device of claim 5, wherein the backside power rail comprises at least one backside N-channel power rail for the at least one pair of adjacent N-channel transistors, the at least one backside N-channel power rail being disposed between the at least one pair of adjacent N-channel transistors.

7. 6. The semiconductor device of claim 5, further comprising two adjacent P-channel transistors, wherein at least one N-channel transistor of the at least one pair of adjacent N-channel transistors is adjacent to one P-channel transistor of the two adjacent P-channel transistors.

8. 8. The semiconductor device of claim 7, further comprising at least one backside P-channel power rail for the two adjacent P-channel transistors, the at least one backside P-channel power rail being disposed between the two adjacent P-channel transistors.

9. 8. The semiconductor device of claim 7, further comprising a backside local signal line for the N-channel transistors and the P-channel transistors, the backside local signal line being disposed between at least one of the N-channel transistors and at least one of the P-channel transistors.

10. forming a transistor having at least one gate and at least one source / drain on at least a portion of a substrate of the wafer; forming front side contacts to some of the gates and source / drains; forming a back end of line and a carrier wafer; inverting the wafer and removing at least a portion of the substrate; forming backside contacts to some of the gates and source / drains; forming a backside power rail to the backside contact connected to the source / drain; wherein the backside power rail is formed in a space between N-channel field effect transistors and in a space between at least one P-channel field effect transistor; and forming a backside local signal line between the backside power rails; 1. A method for forming a semiconductor device, comprising:

11. The method of claim 10 , further comprising forming the backside local signal line connecting to at least one source / drain or gate through at least one backside contact.

12. 11. The method of claim 10, further comprising forming a cell architecture with the backside local signal lines extending horizontally on the backside and frontside metal extending vertically.

13. 11. The method of claim 10, further comprising forming the backside signal line in a space from an N-channel field effect transistor to a P-channel field effect transistor.

14. forming at least one pair of adjacent N-channel transistors, wherein the backside power rail includes at least one backside N-channel power rail for the at least one pair of adjacent N-channel transistors, the at least one backside N-channel power rail being disposed between the at least one pair of adjacent N-channel transistors; forming two adjacent P-channel transistors, wherein at least one N-channel transistor of the at least one pair of adjacent N-channel transistors is adjacent to one P-channel transistor of the two adjacent P-channel transistors; The method of claim 10 further comprising:

15. 15. The method of claim 14, wherein the backside power rails include at least one backside P-channel power rail for the two adjacent P-channel transistors, the at least one backside P-channel power rail being disposed between the two adjacent P-channel transistors, and the backside local signal line is for the N-channel transistor and the P-channel transistor, the backside local signal line being disposed between at least one of the N-channel transistors and at least one of the P-channel transistors.

16. two adjacent N-channel transistors; two adjacent P-channel transistors, wherein one N-channel transistor of the two adjacent N-channel transistors is adjacent to one P-channel transistor of the two adjacent P-channel transistors; Equipped with a backside N-channel power rail for the two adjacent N-channel transistors is disposed between the two adjacent N-channel transistors, a backside P-channel power rail for the two adjacent P-channel transistors is disposed between the two adjacent P-channel transistors, and a backside local signal line for the N-channel transistor and the P-channel transistor is disposed between the adjacent N-channel transistor and the P-channel transistor.

17. 17. The semiconductor device of claim 16, further comprising at least one backside contact connecting to at least one source / drain or at least one gate.

18. 20. The semiconductor device of claim 17, wherein the backside N-channel power rail is connected to the at least one source / drain using the at least one backside contact.

19. 20. The semiconductor device of claim 17, wherein the backside local signal line is connected to the at least one source / drain or the at least one gate using the at least one backside contact.

20. 17. The semiconductor device of claim 16, further comprising a cell architecture having the backside local signal lines extending horizontally on the backside and frontside metal extending vertically.

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