Selective deposition of thin films with improved stability

Abstract

A method of processing a substrate is disclosed that includes depositing a layer in a processing chamber in a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a portion of the layer deposited in the sidewall region has a lower hardness than a portion of the layer deposited in the field region and a lower hardness than a portion of the layer deposited in the fill region.

Description

[Technical Field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure generally relate to substrate manufacturing techniques, for example, for use in thin film processing. [Background technology]

[0002] The inventors observed cracking of the silicon oxide (SiO) layer in a 25 μm SiO die-to-die gap-fill process flow after grinding and chemical mechanical polishing (CMP). The inventors investigated the stress generation mechanism of the SiO cracking problem due to thermal (thermal expansion coefficient or CTE mismatch) and mechanical (grinding and CMP forces).

[0003] Thus, the inventors have provided an improved method of processing substrates to deposit thin films with improved stability that can be used to reduce or eliminate inter-die gap fill layer cracking after mechanical processing. Summary of the Invention

[0004] Provided herein are methods for processing a substrate, and structures formed by such methods. In an embodiment, the method of processing a substrate includes depositing a layer in a processing chamber in a field region, a sidewall region, and a fill region of a feature of the substrate, wherein the hardness of the portion of the layer deposited in the sidewall region is lower than the hardness of the portion of the layer deposited in the field region and is lower than the hardness of the portion of the layer deposited in the fill region.

[0005] In an embodiment, a method of processing a substrate includes depositing a layer in a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a portion of the layer deposited in the sidewall region has a hardness that is lower than a hardness of a portion of the layer deposited in the field region and lower than a hardness of a portion of the layer deposited in the fill region; and reducing a thickness of at least a portion of the substrate via chemical mechanical planarization to form a processed substrate, wherein the portion of the layer in the sidewall region of the processed substrate is crack-free.

[0006] In an embodiment, a substrate includes a field region, a sidewall region, and a layer deposited in a fill region of a feature of the substrate, wherein the hardness of the portion of the layer deposited in the sidewall region is less than the hardness of the portion of the layer deposited in the field region and less than the hardness of the portion of the layer deposited in the fill region.

[0007] In an embodiment, a non-transitory computer-readable medium storing instructions that, when executed, cause a method to be performed that includes depositing a layer in a processing chamber in a field region, a sidewall region, and a fill region of a feature of a substrate, wherein a hardness of a portion of the layer deposited in the sidewall region is lower than a hardness of a portion of the layer deposited in the field region and lower than a hardness of a portion of the layer deposited in the fill region.

[0008] Other and further embodiments of the present disclosure are described below.

[0009] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, can be understood by reference to the exemplary embodiments of the present disclosure that are illustrated in the accompanying drawings. However, the accompanying drawings depict only typical embodiments of the present disclosure and therefore should not be considered limiting in scope, as the present disclosure may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram of a substrate according to at least some embodiments of the present disclosure. [Figure 2] FIG. 1 is a schematic diagram of a processing chamber in accordance with at least some embodiments of the present disclosure. [Figure 3] 1 is a flowchart of a method according to at least some embodiments of the present disclosure. [Figure 4] 1 is a flowchart of a method according to at least some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] For ease of understanding, where possible, the same reference numbers have been used to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0012] The methods provided herein can be used, for example, in die-to-die gap fill processes to reduce or eliminate cracking in the fill layer during subsequent planarization processes (e.g., grinding and / or CMP, etc.).

[0013] In embodiments, a process for depositing a filler material, in embodiments an undoped and / or doped silicon oxide glass material, for a die to be bonded to an underlying wafer. The mechanical and thermal properties of the glass gap filler material are controlled by deposition conditions so that it remains crack-free through subsequent integration processes, which may include mechanical stresses, e.g., from grinding and / or CMP, and thermal stresses, e.g., from annealing and / or subsequent deposition. The thickness of the bonded die can be approximately less than 1 micrometer to 5,000 micrometers. The spacing between the bonded die can be approximately 5 micrometers to 5 centimeters.

[0014] The glass hardness and Young's modulus are controlled to be locally lowest on the die sidewalls to prevent cracking of the deposited filler material, e.g., glass gap filler material, during subsequent mechanical processing. The inventors have discovered that a relatively soft filler material on the die sidewalls reduces internal stresses induced from external mechanical shear and loading forces during mechanical processing.

[0015] In some embodiments, a method for processing a substrate includes controlling a deposition process to deposit a fill layer in a trench such that the material deposited in a sidewall region adjacent to the trench sidewall is softer than the material deposited elsewhere in the trench and on the substrate. The method can be performed on a substrate in which the trench is defined as the region between adjacent sidewalls. The deposited material can be a fill material deposited on the substrate and in the trench, for example, on the top surface of the substrate, the trench sidewalls, and the bottom of the trench, and can be, for example, one or more of silicon, silicon oxide, silicon nitride, or silicon carbon nitride. In embodiments, the fill material further includes a dopant.

[0016] The method according to the present disclosure selectively adjusts the modulus of a film deposited on the sidewalls of a trench to relieve stress on the layer during subsequent mechanical processes, such as in a planarization process (e.g., grinding, and / or CMP, etc.). The method according to the present disclosure adjusts (e.g., lowers) the Young's modulus of the deposited film on the interior sidewalls of a trench structure by controlling the chemical vapor deposition (CVD) process used to deposit the film.

[0017] The inventors have observed that alternative approaches focused on optimizing grinding and polishing processes are likely to slow material removal rates, which is undesirable and reduces throughput and increases costs. The method according to the present disclosure advantageously has little or no impact on the cost of ownership to the planarization process. Additionally, the method according to the present disclosure is more effective in mitigating mechanical film damage and for gap filling between dies in 3D packaging, among other applications.

[0018] In an embodiment, a method of processing a substrate includes depositing a layer in a processing chamber in a field region, a sidewall region, and a fill region of a feature of the substrate, wherein the hardness of the portion of the layer deposited in the sidewall region is lower than the hardness of the portion of the layer deposited in the field region and lower than the hardness of the portion of the layer deposited in the fill region. In an embodiment, the layer is silicon, silicon oxide, silicon nitride, or silicon nitride carbon. In an embodiment, the layer further comprises phosphorus, boron, fluorine, aluminum, nitrogen, or a combination thereof.

[0019] In an embodiment, the portion of the layer deposited in the sidewall region has a Young's modulus that is at least about 10% lower than the Young's modulus of the portion of the layer deposited in the field region and the portion of the layer deposited in the fill region. In an embodiment, the layer is deposited by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD).

[0020] In embodiments, the layer is deposited using a chemical precursor including tetraethylorthosilicate, octamethylcyclotetrasiloxane, silane, or a combination thereof. In embodiments, the flow rate of the chemical precursor into the processing chamber is about 0.1 to 5 grams per minute.

[0021] In embodiments, the layer is deposited utilizing a dopant chemical precursor comprising phosphorus, boron, fluorine, aluminum, or a combination thereof, which is delivered into the process chamber at a flow rate of about 0.1 to 2 grams per minute.

[0022] In embodiments, the method further includes diluting the chemical precursor with a carrier gas comprising Ar, He, H, or a combination thereof. In embodiments, the carrier gas is delivered into the process chamber at a flow rate of about 1-100 slm. In embodiments, the layer is deposited utilizing an oxygen precursor of diatomic oxygen, ozone, nitrous oxide, or a combination thereof, where the oxygen precursor is delivered into the process chamber at a flow rate of about 1-50 slm.

[0023] In an embodiment, the plasma enhanced chemical vapor deposition includes a dual frequency RF bias including a low frequency RF signal having a frequency between about 200 kHz and 600 kHz and a high frequency RF signal having a frequency between about 2 MHz and 100 MHz.

[0024] In embodiments, the power of the low frequency RF signal and the power of the high frequency RF signal are each independently between about 50 Watts and about 5000 Watts. In embodiments, the ratio of the power of the low frequency RF signal to the power of the high frequency RF signal is greater than 1. In embodiments, one of the high frequency RF signal or the low frequency RF signal is applied to a showerhead configured to flow gas into the processing chamber, and the other is applied to a substrate support configured to support a substrate during processing.

[0025] In an embodiment, the spacing between the showerhead of the processing chamber and the substrate support is between about 50 mils and 1500 mils. In an embodiment, the temperature of the substrate is between about 50° C. and about 500° C. In an embodiment, the pressure in the processing chamber is between about 0.1 Torr and about 10 Torr.

[0026] 1 is a schematic diagram of a packaging structure 100 in accordance with at least some embodiments of the present disclosure. While described herein in the context of packaging applications, embodiments of the present disclosure may be advantageously used in other thin film manufacturing applications where material is deposited into trenches and then subjected to grinding and / or polishing, which may result in cracking. While described herein using a packaging structure for illustrative purposes, the inventive methods disclosed herein may be used in other applications where features, such as trenches, are filled on a substrate.

[0027] Packaging structure 100 generally includes substrate 102, which includes a plurality of fields 122, such as trenches 108 disposed between an upper surface of substrate 102 and adjacent sidewalls 124 and 126. Trench 108 can have dimensions suitable for a particular application, such as a width 110 of about 80 micrometers and a depth 112 of about 20-30 micrometers. The bottom of the trench forms bottom region 128.

[0028] In some embodiments, an optional barrier and / or liner layer 106 may be conformally disposed over the substrate 102, for example, across the top or field 122 of the silicon layer, along the sidewalls 124 and 126, and along the bottom region 128 of the trench 108. In some embodiments, the barrier and / or liner layer 106 may be a silicon nitride layer.

[0029] A fill layer 104 is disposed over the substrate 102 (e.g., over the field 122, sidewalls 124 and 126, and bottom region 128), and, if present, over the barrier and / or liner layer 106. The fill layer 104 can be silicon, silicon oxide, silicon nitride, silicon nitride carbon, or a combination thereof. In some embodiments, the fill layer consists of or consists essentially of one of silicon, silicon oxide, silicon nitride, or silicon nitride carbon. Fill layer 104 includes a field region 116 disposed generally over a field 122 of substrate 102 (e.g., an upper surface of a feature disposed within substrate 102), a sidewall region 118 disposed along and adjacent sidewalls 124 and 126 of trench 108 and / or barrier and / or liner layer 106, if present, and a fill region 120 disposed within trench 108 (e.g., over a bottom region 128 of trench 108 and between sidewall regions 118) and generally filling trench 108. Fill layer 104 is typically deposited to a thickness such that the upper surface of fill layer 104 is disposed over field 122, i.e., the upper surface of substrate 102 and barrier and / or liner layer 106, if present. In some embodiments, depending on the structure and critical dimensions of trench 108 (e.g., the width of trench 108), sidewall region 118 can have a width or thickness (e.g., measured inward from the wall of trench 108 to the opposite side of sidewall region 118) of about 5 nanometers to about 50 micrometers.

[0030] In processes currently known in the art, the harnesses for all the various layers are essentially identical. In processes according to the present disclosure, the field region 116 and the fill region 120 have a first hardness (e.g., expressed by the Young's modulus of the film) that is greater than a second hardness of the sidewall region 118. In some embodiments, the first hardness or Young's modulus is a typical nominal value for the as-deposited film. The second hardness is less than the first hardness. In some embodiments, the Young's modulus of the sidewall region 118 is about 10-15% lower (e.g., taking an average reading) than the Young's modulus of the field region 116 and the fill region 120. In embodiments, the portion of the layer deposited in the sidewall region has a Young's modulus that is at least about 10% lower than the Young's modulus of the portion of the layer deposited in the field region and the portion of the layer deposited in the fill region.

[0031] For example, if fill layer 104 is a silicon oxide layer, the Young's modulus of field region 116 and fill region 120 may be approximately 85 GPa, and the Young's modulus of sidewall region 118 may be approximately 75 GPa. Other values ​​may be obtained using a silicon oxide layer or if fill layer 104 is fabricated from a different material, as described above. For example, in some embodiments, the Young's modulus of a silicon oxide layer may vary between approximately 59 and 85 GPa. In some embodiments, the Young's modulus of a silicon nitride layer may vary between approximately 200 and 280 GPa. In some embodiments, the Young's modulus of a silicon layer may vary between approximately 67 and 80 GPa.

[0032] The method according to the present disclosure tailors (e.g., lowers) the Young's modulus of the deposited film (e.g., fill layer 104) on the inner sidewalls of the trench structure by controlling the CVD process used to deposit the film. For example, the inventors have discovered that control of process parameters of the CVD process can be used to control the hardness of the deposited film. For example, control of the high-to-low frequency RF ratio, control of chamber pressure, control of gas and precursor flow rates, and / or control of the substrate-to-showerhead spacing can be used, alone or in combination of two or more, to control the hardness of the deposited film along the sidewall regions relative to other regions of the fill layer.

[0033] In embodiments, a number of mixed RF frequencies, including high frequencies between about 2-100 MHz and low frequencies between about 200-600 kHz, can be used to create the plasma for deposition. In some embodiments, multiple high frequencies between 2-100 MHz and / or multiple low frequencies between 200-600 kHz may be used.

[0034] In an embodiment, the high frequency RF power and the low frequency RF power are each independently controlled. In an embodiment, the power of each RF frequency is supplied continuously or pulsed for each RF frequency during deposition. In an embodiment, the power of the low frequency RF and the high frequency RF power is in the range of about 50 to 5000 W.

[0035] In embodiments, using PECVD, the hardness and modulus of the deposited silicon oxide fill material on the die sidewall can be reduced by increasing the ratio of low frequency RF power to high frequency RF power to about 1 or more, or about 1.2 or more, or about 1.5 or more, or about 2 or more, where each of the low RF power and high RF power is between about 50 and 5000 watts.

[0036] In an embodiment, the gap fill material is deposited using a plasma enhanced chemical vapor deposition chamber (PECVD) with a capacitively coupled plasma (CCP) hardware configuration.

[0037] In embodiments, the layer is deposited by plasma enhanced chemical vapor deposition (PECVD) or by chemical vapor deposition (CVD). In embodiments, the chemical vapor deposition utilizes chemical precursors including tetraethyl orthosilicate (TEOS), octamethylcyclotetrasiloxane (OMCTS), and / or SiH at a flow rate of about 0.1-5 grams / min. In embodiments, an oxygen precursor, which may include O, O, and / or NO, is utilized at a flow rate of about 1-50 slm.

[0038] In an embodiment, a method of processing a substrate includes depositing a layer in a processing chamber in a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a portion of the layer deposited in the sidewall region has a lower hardness than a portion of the layer deposited in the field region and a lower hardness than a portion of the layer deposited in the fill region.

[0039] In embodiments, the layer comprises silicon. In embodiments, the layer is silicon, silicon oxide, silicon nitride, or silicon carbon nitride. In embodiments, the layer further comprises a dopant. In embodiments, the dopant comprises phosphorus, boron, fluorine, or a combination thereof. In embodiments, the dopant is present in an amount sufficient to modify the hardness of the layer such that a portion of the layer deposited in the sidewall region has a lower hardness than the portion of the layer deposited in the field region and a lower hardness than the portion of the layer deposited in the fill region.

[0040] In embodiments, chemical vapor deposition utilizes a chemical precursor that includes a dopant. In embodiments, the dopant includes one or more elements from Groups 1-2 and / or 11-15 of the Periodic Table of the Elements. In embodiments, the dopant includes phosphorus, boron, aluminum, gallium, indium, silver, arsenic, antimony, bismuth, germanium, gold, platinum, cadmium, or a combination thereof.

[0041] In embodiments, the chemical precursor may include phosphorus as a dopant and may include at least one of triethylphosphate (TEPO), phosphoryl chloride (e.g., phosphorus oxychloride, POCl), phosphine (PH), or tertiary butyl phosphine (TBP), etc. In embodiments, the chemical precursor may include boron as a dopant and may include at least one of triethylborane (TEB), diborane (BH), boric acid (HBO), etc. In embodiments, the chemical precursor may include aluminum as a dopant and may include at least one of trimethylaluminum (TMA), triethylaluminum (TEA), ammonia, nitrogen, etc. In embodiments, the chemical precursor may include gallium as a dopant and may include at least one of trimethylgallium (TMG), triethylgallium (TEG), gallium arsenide, gallium phosphide, gallium nitride, indium gallium nitride, aluminum gallium nitride, etc. In embodiments, the chemical precursor may include both silver and phosphorus as dopants and may include a silver phosphine precursor.

[0042] In embodiments, the dopant is provided at a flow rate of about 0.1-2 grams / min and may be diluted with a carrier gas such as Ar, He, H2, etc., with the diluent provided at a flow rate of about 1-100 slm.

[0043] In embodiments, the dopant concentration is present in the precursor in an amount sufficient to produce a final layer having a dopant concentration of about 1-30 atomic %, or about 1-10 atomic %, or about 3-7 atomic %.

[0044] In embodiments, the layers are deposited as composite layers. For example, a first deposit including a doped liner may be deposited, followed by an undoped deposit to complete the gap fill. Deposition of any number of such layers in any order is contemplated.

[0045] 2 is a schematic diagram of a substrate processing chamber 200 that can be used to process substrates in accordance with embodiments described herein, although the processes described herein can be performed in other substrate processing chambers as well.

[0046] The processing chamber 200 is coupled to a gas panel 230 and a controller 210. The processing chamber 200 generally includes a top 224, a side 201, and a bottom wall 222 that define an interior processing volume 226. A substrate support 250 is provided in the interior processing volume 226 of the processing chamber 200. The substrate support 250 is supported by a stem 260 and may generally be fabricated from aluminum, ceramic, and other suitable materials. The substrate support 250 may be moved vertically within the processing chamber 200 using a displacement mechanism to control the distance 223 between the substrate 291 and the showerhead 220.

[0047] In embodiments, a substrate support 250 for a substrate 290 (e.g., a wafer) and a showerhead 220 for gas / precursor distribution are utilized as an anode / cathode for RF delivery and plasma generation. In embodiments, a spacing 296 between the substrate 290 and the showerhead 220 during plasma deposition can be between about 50 mils and 1500 mils.

[0048] The substrate support 250 may include an embedded heater element 270 suitable for controlling the temperature of a substrate 290 supported on a surface 292 of the substrate support 250. The substrate support 250 may be resistively heated by applying an electric current from a power source 206 to the heater element 270. The heater element 270 may be fabricated from a nickel-chromium wire encapsulated in a nickel-iron-chromium alloy (e.g., INCOLOY®) sheath tube. The electric current provided by the power source 206 is adjusted by the controller 210 to control the heat generated by the heater element 270, thereby maintaining the substrate 290 and the substrate support 250 at a substantially constant temperature during film deposition.

[0049] A temperature sensor 272, such as a thermocouple, may be embedded in or otherwise operably coupled to the substrate support 250 to measure the temperature of the substrate support 250. The measured temperature is used by the controller 210 to control the power supplied to the heater element 270, thereby maintaining the substrate at a desired temperature.

[0050] In embodiments, the temperature of substrate 290 is between about 50°C and 500°C, or between about 200°C and 350°C, during deposition. In embodiments, substrate support 250 is configured for wafer chucking to keep the wafer flat and in close contact with heater 270 during deposition, and heater 270 has precise temperature control capability, i.e., ±1°C, during the entire deposition process to enable precise control and uniformity of deposited film properties across the wafer. In embodiments, the pressure within inner processing volume 226 is between about 0.1 and 10 Torr during deposition.

[0051] A vacuum pump 202 is coupled to a port formed in the bottom of the processing chamber 200. The vacuum pump 202 and a controller 204 are used to maintain a desired gas pressure within the processing chamber 200. The vacuum pump 202 also evacuates post-processing gases and process by-products from the processing chamber 200.

[0052] The substrate processing chamber 200 may further include additional equipment for controlling the chamber pressure, such as valves (e.g., throttle valves and isolation valves) positioned between the processing chamber 200 and the vacuum pump 202 to control the chamber pressure.

[0053] A showerhead 220 having a plurality of apertures 228 is disposed at the top of the processing chamber 200 above the substrate support 250. The apertures 228 of the showerhead 220 are utilized to introduce process gases into the processing chamber 200. The apertures 228 can have various sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for different process requirements. The showerhead 220 is connected to a gas panel 230 that enables various gases to be supplied to the interior processing volume 226 during the deposition process.

[0054] The gas panel 230 may also be used to control and supply various chemical vapor deposition precursors and / or reagents, which may be in gaseous or vaporized liquid form, that are delivered to the process chamber 200 in the presence of a carrier gas. The carrier gas is typically an inert gas such as nitrogen, or a noble gas such as argon or helium. Alternatively, liquid precursors may be vaporized from ampoules by thermal and / or vacuum-assisted vaporization processes.

[0055] The showerhead 220 and the substrate support 250 can form a pair of spaced-apart electrodes within the internal processing volume 226. One or more RF power sources 240 and 241 supply bias potentials to the showerhead 220, the substrate support, or a combination thereof through corresponding matching networks 238 and 239 to facilitate chemical vapor deposition between the showerhead 220 and the substrate support 250. The RF power sources 240 and the matching network 238 can be coupled to the showerhead 220, the substrate support 250, or both the showerhead 220 and the substrate support 250. In one embodiment, the RF power sources 240 and 241 include a low-frequency RF power source and a high-frequency RF power source. Each RF power source can supply power between about 50 watts and about 5,000 watts.

[0056] The controller 210 includes a central processing unit (CPU) 212, memory 216, and support circuits 214, which are utilized to control process sequences and regulate gas flow from the gas panel 230. The CPU 212 can be any form of general-purpose computer processor that can be used in an industrial environment. Software routines can be stored in the memory 216, such as random access memory, read-only memory, a floppy or hard disk drive, or other form of digital storage. The support circuits 214 are conventionally coupled to the CPU 212 and can include cache, clock circuits, input / output systems, power supplies, etc. Bidirectional communication between the controller 210 and the various components of the substrate processing chamber 232 is handled via a number of signal cables collectively referred to as a signal bus 218, some of which are shown in FIG. 2.

[0057] In an embodiment, the spacing 296 between the showerhead 220 of the processing chamber 200 and the substrate support 250 is less than the comparative spacing between the showerhead of the processing chamber and the substrate support that is sufficient to deposit the comparative layer in the field region, sidewall region, and fill region of the substrate feature under otherwise essentially identical conditions, except that the hardness of the portion of the comparative layer deposited in the sidewall region, the hardness of the portion of the comparative layer deposited in the field region, and the hardness of the portion of the comparative layer deposited in the fill region are essentially equal.

[0058] In an embodiment, the spacing 296 between the showerhead of the processing chamber 200 and the substrate support 250 is greater than the spacing between the showerhead of the processing chamber and the substrate support sufficient to deposit the comparative layer in the field region, sidewall region, and fill region of the substrate feature under otherwise essentially identical conditions, except that the hardness of the portion of the comparative layer deposited in the sidewall region, the hardness of the portion of the comparative layer deposited in the field region, and the hardness of the portion of the comparative layer deposited in the fill region are essentially equal.

[0059] In an embodiment, the spacing between the showerhead of the processing chamber and the substrate support is between about 1 cm and about 20 cm.

[0060] In embodiments, the CVD process can be performed in a processing chamber with a showerhead dual frequency RF bias that flows gases into the processing chamber during processing. The dual frequency RF bias can include a low frequency (LF) RF signal and a high frequency (HF) RF signal.

[0061] Other chamber configurations are possible, for example, where both HF and LF power are applied to a substrate support that supports the substrate during processing, or where one of the HF or LF power is applied to a showerhead and the other is coupled to the substrate support. In some embodiments, the low frequency can be between about 200 kHz and 600 kHz. In some embodiments, the high frequency can be between about 2 MHz and 100 MHz.

[0062] The inventors have discovered that depositing fill layer 104 using a CVD process in which the applied HF power is greater than the applied LF power results in a film with a nominal hardness or Young's modulus. However, reducing the HF to approach or below the LF is effective in depositing a softer film on the sidewalls.

[0063] In an embodiment, the power of the high frequency RF signal is about 50% to about 105% of the power of the low frequency RF signal.

[0064] In embodiments, both high frequency RF signals and low frequency RF signals are applied to a showerhead configured to flow gases into the processing chamber or to a substrate support configured to support a substrate during processing.

[0065] In embodiments, one of a high frequency RF signal or a low frequency RF signal is applied to a showerhead configured to flow gases into the processing chamber, and the other is applied to a substrate support configured to support a substrate during processing. For example, in one embodiment, a high frequency RF signal is applied to a showerhead configured to flow gases into the processing chamber, and a low frequency RF signal is applied to a substrate support configured to support a substrate during processing. In one embodiment, a low frequency RF signal is applied to a showerhead configured to flow gases into the processing chamber, and a high frequency RF signal is applied to a substrate support configured to support a substrate during processing.

[0066] For example, the inventors have discovered that higher precursor flow rates (such as TEOS) and / or lower O or N O flow rates tend to result in the deposition of softer films. In embodiments, the chemical precursors are mixed with a diluent. Suitable diluents include argon, helium, neon, nitrogen, and the like.

[0067] In an embodiment, the flow rate of the chemical precursor is greater than a flow rate of the same chemical precursor that is sufficient to deposit a comparative layer in the field region, sidewall region, and fill region of a feature of a substrate under otherwise essentially identical conditions, except that the hardness of the portion of the comparative layer deposited in the sidewall region, the hardness of the portion of the comparative layer deposited in the field region, and the hardness of the portion of the comparative layer deposited in the fill region are essentially equal.

[0068] In an embodiment, the flow rate of oxygen, nitrous oxide, or a combination thereof is less than a flow rate of oxygen, nitrous oxide, or a combination thereof that is sufficient to deposit a comparative layer in the field region, sidewall region, and fill region of a feature of a substrate, except that under otherwise essentially identical conditions, the hardness of the portion of the comparative layer deposited in the sidewall region, the hardness of the portion of the comparative layer deposited in the field region, and the hardness of the portion of the comparative layer deposited in the fill region are essentially equal.

[0069] In an embodiment, the flow rate of oxygen, nitrous oxide, or a combination thereof is less than a flow rate of oxygen, nitrous oxide, or a combination thereof that is sufficient to deposit a comparative layer in the field region, sidewall region, and fill region of a feature of a substrate, except that under otherwise essentially identical conditions, the hardness of the portion of the comparative layer deposited in the sidewall region, the hardness of the portion of the comparative layer deposited in the field region, and the hardness of the portion of the comparative layer deposited in the fill region are essentially equal.

[0070] In an embodiment, the deposition pressure in the processing chamber is greater than the deposition pressure of the processing chamber sufficient to deposit the comparative layer in the field region, sidewall region, and fill region of the feature of the substrate, except that under otherwise essentially identical conditions, the hardness of the portion of the comparative layer deposited in the sidewall region, the hardness of the portion of the comparative layer deposited in the field region, and the hardness of the portion of the comparative layer deposited in the fill region are essentially equal.

[0071] In an embodiment, the deposition pressure in the processing chamber is less than a deposition pressure in the processing chamber that is sufficient to deposit the comparative layer in the field region, sidewall region, and fill region of the feature of the substrate, except that under otherwise essentially identical conditions, the hardness of the portion of the comparative layer deposited in the sidewall region, the hardness of the portion of the comparative layer deposited in the field region, and the hardness of the portion of the comparative layer deposited in the fill region are essentially equal.

[0072] Figure 3 is a flow diagram of an example process 300. In some embodiments, block 302 of Figure 3 may be performed by a device.

[0073] 3, process 300 can include depositing a layer in a processing chamber in a field region, a sidewall region, and a fill region of a feature of a substrate, where the hardness of the portion of the layer deposited in the sidewall region is lower than the hardness of the portion of the layer deposited in the field region and lower than the hardness of the portion of the layer deposited in the fill region (block 302). Although FIG. 3 shows example blocks of process 300, in some implementations, process 300 can include additional blocks.

[0074] Figure 4 is a flow diagram of an example process 400. In some embodiments, one or more blocks of Figure 4 may be performed by a device.

[0075] As shown in Figure 4, process 400 can include depositing a layer in a field region, a sidewall region, and a fill region of a feature of a substrate, where the hardness of the portion of the layer deposited in the sidewall region is lower than the hardness of the portion of the layer deposited in the field region and lower than the hardness of the portion of the layer deposited in the fill region (block 402). As further shown in Figure 4, process 400 includes reducing a thickness of at least a portion of the substrate via chemical mechanical planarization to form a processed substrate, where the portion of the layer in the sidewall region of the processed substrate is crack-free (block 404). While Figure 4 shows example blocks of process 400, in some implementations, process 400 can include additional blocks.

[0076] Embodiments include the following. E01. Depositing a layer in a processing chamber in a field region, a sidewall region, and a fill region of a feature on a substrate, wherein the hardness of the portion of the layer deposited in the sidewall region is lower than the hardness of the portion of the layer deposited in the field region and lower than the hardness of the portion of the layer deposited in the fill region. A method for processing a substrate, comprising: E02. The method of embodiment E01, wherein the layer is silicon, silicon oxide, silicon nitride, or silicon carbon nitride. E03. The method of embodiment E01 or E02, wherein the layer further comprises phosphorus, boron, fluorine, aluminum, nitrogen, or a combination thereof. E04. The method of any of embodiments E01-E03, wherein the portion of the layer deposited in the sidewall region has a Young's modulus that is at least about 10% lower than the Young's modulus of the portion of the layer deposited in the field region and the portion of the layer deposited in the fill region. E05. The method of any one of embodiments E01-E04, wherein the layer is deposited by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD). E06. The method of any one of embodiments E01-E05, wherein the layer is deposited utilizing a chemical precursor comprising tetraethylorthosilicate, octamethylcyclotetrasiloxane, a silane, or a combination thereof. E07. The method of any one of embodiments E01-E06, wherein the flow rate of the chemical precursor into the processing chamber is about 0.1-5 grams / minute. E08. The method of any one of embodiments E01-E07, wherein the layer is deposited utilizing a dopant chemical precursor comprising phosphorus, boron, fluorine, aluminum, or a combination thereof. E09. The method of any one of embodiments E01-E08, wherein the dopant chemical precursor is delivered into the processing chamber at a flow rate of about 0.1-2 grams / minute. E10. The method of any one of embodiments E01-E09, further comprising diluting the chemical precursor with a carrier gas comprising Ar, He, H2, or a combination thereof. E11. The method of any one of embodiments E01-E10, wherein the carrier gas is supplied into the processing chamber at a flow rate of about 1-100 slm. E12. The method of any one of embodiments E01-E11, wherein the layer is deposited utilizing an oxygen precursor of diatomic oxygen, ozone, nitrous oxide, or a combination thereof, supplied into the processing chamber at a flow rate of about 1-50 slm. E13. The method of any of embodiments E01-E12, wherein the plasma enhanced chemical vapor deposition comprises a dual frequency RF bias comprising a low frequency RF signal having a frequency between about 200 kHz and 600 kHz and a high frequency RF signal having a frequency between about 2 MHz and 100 MHz. E14. The method of any of embodiments E01-E13, wherein the power of the low frequency RF signal and the power of the high frequency RF signal are each individually between about 50 Watts and about 5000 Watts. E15. The method of any one of embodiments E01-E14, wherein the ratio of the power of the low frequency RF signal to the power of the high frequency RF signal is greater than one. E16. The method of any one of embodiments E01-E15, wherein one of a high frequency RF signal or a low frequency RF signal is applied to a showerhead configured to flow gas into the processing chamber, and the other is applied to a substrate support configured to support a substrate during processing. E17. The method of any one of embodiments E01-E16, wherein the spacing between the showerhead of the processing chamber and the substrate support is between about 50 mils and 1500 mils. E18. The method of any one of embodiments E01-E17, wherein the temperature of the substrate is from about 50°C to about 500°C. E19. The method of any one of embodiments E01-E18, wherein the pressure in the processing chamber is between about 0.1 Torr and about 10 Torr. E20. Depositing a layer in a field region, a sidewall region, and a fill region of a feature of a substrate, wherein the hardness of the portion of the layer deposited in the sidewall region is lower than the hardness of the portion of the layer deposited in the field region and lower than the hardness of the portion of the layer deposited in the fill region; reducing a thickness of at least a portion of the substrate via chemical mechanical planarization to form a processed substrate, wherein portions of the layer in a sidewall region of the processed substrate are free of cracks; A method for treating a substrate according to any one of embodiments E01 to E19, comprising:

[0077] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.

Claims

1. Depositing a layer in a processing chamber in a field region, a sidewall region, and a fill region of a feature on a substrate, wherein a portion of the layer deposited in the sidewall region has a lower hardness than a portion of the layer deposited in the field region and a lower hardness than a portion of the layer deposited in the fill region. A method for processing a substrate, comprising:

2. The method of claim 1 , wherein the layer is silicon, silicon oxide, silicon nitride, or silicon carbon nitride.

3. The method of claim 1 , wherein the layer comprises a dopant comprising phosphorus, boron, fluorine, aluminum, nitrogen, or a combination thereof.

4. 2. The method of claim 1, wherein the portion of the layer deposited in the sidewall region has a Young's modulus that is at least about 10% lower than the Young's modulus of the portion of the layer deposited in the field region and the portion of the layer deposited in the fill region.

5. The method according to any of claims 1 to 4, wherein the layer is deposited by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD).

6. The method of claim 5 , wherein the layer is deposited utilizing a chemical precursor comprising tetraethylorthosilicate, octamethylcyclotetrasiloxane, a silane, or a combination thereof.

7. The method of claim 6, wherein the flow rate of the chemical precursor into the processing chamber is about 0.1 to 5 grams per minute.

8. The method of claim 6 , wherein the layer is deposited utilizing a dopant chemical precursor comprising phosphorus, boron, fluorine, aluminum, or a combination thereof.

9. 9. The method of claim 8, wherein the dopant chemical precursor is delivered into the processing chamber at a flow rate of about 0.1 to 2 grams per minute.

10. Ar, He, H 2 7. The method of claim 6, further comprising diluting the chemical precursor with a carrier gas comprising:

11. 7. The method of claim 6, wherein the layer is deposited utilizing an oxygen precursor of diatomic oxygen, ozone, nitrous oxide, or a combination thereof, the oxygen precursor being delivered into the processing chamber at a flow rate of about 1 to 50 slm.

12. 6. The method of claim 5, wherein the plasma enhanced chemical vapor deposition comprises a dual frequency RF bias comprising a low frequency RF signal having a frequency between about 200 kHz and 600 kHz and a high frequency RF signal having a frequency between about 2 MHz and 100 MHz.

13. 13. The method of claim 12, wherein the power of the low frequency RF signal and the power of the high frequency RF signal are each individually between about 50 watts and about 5000 watts.

14. The method of claim 12 , wherein a ratio of the power of the low frequency RF signal to the power of the high frequency RF signal is greater than one.

15. 13. The method of claim 12, wherein one of the high frequency RF signal or the low frequency RF signal is applied to a showerhead configured to flow gas into the processing chamber, and the other is applied to a substrate support configured to support the substrate during the processing.

16. 16. The method of claim 15, wherein the spacing between the showerhead of the processing chamber and the substrate support is between about 50 mils and 1500 mils.

17. 10. The method of claim 1, wherein the temperature of the substrate is between about 50° C. and about 500° C. and the pressure in the processing chamber is between about 0.1 Torr and about 10 Torr.

18. 5. The method of claim 1, further comprising reducing a thickness of at least a portion of the substrate via chemical mechanical planarization to form a processed substrate, wherein the portion of the layer in the sidewall region of the processed substrate is free of cracks.

19. 1. A substrate comprising: a layer deposited in a field region, a sidewall region, and a fill region of a feature of the substrate, the layer comprising silicon, silicon oxide, silicon nitride, or silicon carbon nitride; a substrate, wherein the hardness of the portion of the layer deposited in the sidewall region is less than the hardness of the portion of the layer deposited in the field region and less than the hardness of the portion of the layer deposited in the fill region.

20. A non-transitory computer readable medium having stored thereon instructions which, when executed, cause the method of any of claims 1 to 4 to be performed.

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