Hydrogen reduction in silicon nitride passivation layers by passivation sublayer formation and treatment

Abstract

A method for growing a passivation film having less than 10 atomic % hydrogen on a substrate includes providing the substrate in a processing station of a substrate processing system, where a resultant passivation film having less than 10 atomic % hydrogen is formed on the substrate by performing the steps of depositing a passivation film sub-layer on the substrate, the passivation film sub-layer being disposed on a semiconductor device layer or directly on a previously deposited passivation film sub-layer, and after deposition of the passivation film sub-layer, subjecting the passivation film sub-layer to a post-plasma treatment with at least one of nitrogen and argon to reduce the hydrogen content in the passivation film sub-layer.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application is a PCT International patent application and claims the benefit of U.S. Provisional Patent Application No. 63 / 412,717, filed October 3, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to the formation of passivation layers, and more particularly to the reduction of hydrogen in silicon nitride passivation layers. [Background technology]

[0003] The description of the background art provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in the background art section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0004] Substrate processing systems can be used to etch, deposit, and / or otherwise process substrates, such as semiconductor wafers. As an example, in a substrate processing system, a substrate may be placed on an electrostatic chuck (ESC). Multiple device layers may be formed on the substrate. After the device layers are formed, a passivation layer of silicon nitride (SiN) may be formed on the device layers using a plasma-enhanced chemical vapor deposition (PECVD) process. Summary of the Invention

[0005] A method for growing a passivation film having less than 10 atomic % hydrogen on a substrate is disclosed, the method comprising providing the substrate in a processing station of a substrate processing system and forming a resultant passivation film having less than 10 atomic % hydrogen on the substrate by performing the steps of depositing a passivation film sub-layer on the substrate, the passivation film sub-layer being disposed on a semiconductor device layer or directly on a previously deposited passivation film sub-layer, and after deposition of the passivation film sub-layer, subjecting the passivation film sub-layer to a post-plasma treatment with at least one of nitrogen and argon to reduce the hydrogen content in the passivation film sub-layer.

[0006] In other features, the method includes the substrate including a stack of layers including a semiconductor device layer and another semiconductor device layer, the stack including at least one III-V type semiconductor material, and the step of depositing the passivation film sub-layer includes depositing the passivation film sub-layer on the stack of layers.

[0007] In other features, the top layer of the stack of layers comprises at least one III-V semiconductor material. In other features, the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content in the passivation film sub-layer to 10.0 atomic % or less.

[0008] In other features, the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content in the passivation film sub-layer to less than 10.0 atomic %. In other features, the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content in the passivation film sub-layer to less than 7.5 atomic %.

[0009] In other features, depositing the passivation film sub-layer includes depositing the passivation film sub-layer to a thickness of less than 200 Å. In other features, depositing the passivation film sub-layer includes depositing the passivation film sub-layer to a thickness of less than 100 Å. In other features, depositing the passivation film sub-layer includes depositing the passivation film sub-layer to a thickness of less than 50 Å. In other features, depositing the passivation film sub-layer includes depositing the passivation film sub-layer to a thickness of 20 to 40 Å.

[0010] In other features, the method further includes introducing at least one of nitrogen and argon for more than 30 seconds. In other features, the method further includes introducing at least one of nitrogen and argon for 60 seconds or less. In other features, the method further includes forming a plurality of passivation film sub-layers on the substrate in the processing station.

[0011] In other features, the method further includes forming passivation film sub-layers on the substrate in the processing stations, each of the passivation film sub-layers being formed in one of the processing stations such that all of the passivation film sub-layers are not formed in the same processing station.

[0012] In another aspect, a semiconductor device is disclosed that includes a substrate, a stack of semiconductor device layers disposed on the substrate, and a plurality of passivation film sub-layers disposed on the stack of semiconductor device layers, wherein the passivation film sub-layers have a combined hydrogen content level of 10.0 atomic % or less.

[0013] In other features, the stack of semiconductor device layers comprises at least one III-V semiconductor material. In other features, a top layer of the stack of semiconductor device layers comprises at least one III-V semiconductor material.

[0014] In another feature, the passivation film sub-layers are stacked as a single passivation layer. In another feature, the single passivation layer has a WER of 6 to 10 Å / m. In another feature, each of the passivation film sub-layers is an ammonia-free silicon nitride layer. In another feature, each of the passivation film sub-layers has a hydrogen content level of 10.0 atomic % or less.

[0015] In other features, each of the passivation film sub-layers has a hydrogen content level of less than 10.0 atomic percent.In other features, each of the passivation film sub-layers has a hydrogen content level of less than 7.5 atomic percent.

[0016] In other features, the thickness of each of the passivation film sublayers is less than 200 Å. In other features, the thickness of each of the passivation film sublayers is less than 100 Å. In other features, the thickness of each of the passivation film sublayers is less than 50 Å. In other features, the thickness of each of the passivation film sublayers is between 20 and 40 Å.

[0017] A method for passivating a semiconductor device in a substrate processing system is disclosed. The method includes providing a substrate including a semiconductor device in a processing station of the substrate processing system and repeatedly performing a passivation process to form a passivation film sub-layer on the semiconductor device. The passivation process includes depositing a current passivation film sub-layer on a semiconductor device layer of the semiconductor device or on one of previously deposited passivation film sub-layers, and performing a post-plasma treatment on the current passivation film sub-layer with at least one of nitrogen and argon to reduce hydrogen content in the current passivation film sub-layer.

[0018] In other features, the semiconductor device includes a stack of layers including a semiconductor device layer and another semiconductor device layer, the stack including at least one III-V type semiconductor material, and a passivation film sub-layer deposited on the stack of layers, in other features, a top layer of the stack of layers including at least one III-V type semiconductor material.

[0019] In other features, the passivation film sub-layers are stacked to provide a resulting single passivation layer. In other features, a post-plasma treatment of the current passivation film sub-layer is performed to reduce the hydrogen content in the current passivation film sub-layer to 10.0 atomic % or less.

[0020] In other features, the post-plasma treatment of the present passivation film sub-layer is performed to reduce a hydrogen content in the present passivation film sub-layer to less than 10.0 atomic %. In other features, the post-plasma treatment of the present passivation film sub-layer is performed to reduce a hydrogen content in the present passivation film sub-layer to less than 7.5 atomic %.

[0021] In other features, the current passivation film sub-layer is deposited to have a thickness of less than 200 Å. In other features, the current passivation film sub-layer is deposited to have a thickness of less than 100 Å. In other features, the current passivation film sub-layer is deposited to have a thickness of less than 50 Å. In other features, the current passivation film sub-layer is deposited to have a thickness of 20-40 Å.

[0022] In other features, the method further comprises introducing at least one of nitrogen and argon for more than 30 seconds, hi other features, the method further comprises introducing at least one of nitrogen and argon for 60 seconds or less.

[0023] In other features, the method further includes forming the passivation film sub-layer in the processing station. In other features, the method further includes forming the passivation film sub-layer in a plurality of processing stations, each of the passivation film sub-layers being formed in one of the processing stations such that all of the passivation film sub-layers are not formed in the same processing station.

[0024] In another feature, a semiconductor device is provided, comprising: a base layer; a stack of semiconductor device layers disposed on the base layer; and passivation film sub-layers disposed on the stack of semiconductor device layers, wherein at least one of i) the passivation film sub-layers have a hydrogen content level of less than or equal to 10.0 atomic % in total; and ii) each of the passivation film sub-layers has a hydrogen content level of less than or equal to 10.0 atomic %.

[0025] In other features, the stack of semiconductor device layers comprises at least one III-V semiconductor material. In other features, a top layer of the stack of semiconductor device layers comprises at least one III-V semiconductor material.

[0026] In other features, the passivation film sub-layers are stacked as a single passivation layer. In other features, the single passivation layer has a WER of 6 to 10 Å / m. In other features, each of the passivation film sub-layers is an ammonia-free silicon nitride layer.

[0027] In other features, the hydrogen content level of each of the passivation film sub-layers is equal to or less than 10.0 atomic percent. In other features, the hydrogen content level of each of the passivation film sub-layers is less than 10.0 atomic percent. In other features, each of the passivation film sub-layers has a hydrogen content level of less than 7.5 atomic percent.

[0028] In other features, the thickness of each of the passivation film sublayers is less than 200 Å. In other features, the thickness of each of the passivation film sublayers is less than 100 Å. In other features, the thickness of each of the passivation film sublayers is less than 50 Å. In other features, the thickness of each of the passivation film sublayers is between 20 and 40 Å.

[0029] Further areas of applicability of the present disclosure will become apparent from the detailed description, claims, and drawings. The detailed description and specific examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. [Brief explanation of the drawings]

[0030] The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0031] [Figure 1] FIG. 1 illustrates a functional block diagram of an example substrate processing system for performing passivation methods according to embodiments of the present disclosure.

[0032] [Figure 2] FIG. 2 is a top cross-sectional view of the processing chamber of FIG. 1 including multiple processing stations utilized to deposit passivation film sub-layers and perform post-plasma treatments in accordance with an embodiment of the present disclosure.

[0033] [Figure 3] FIG. 3 is a cross-sectional side view of a semiconductor device layer including a semiconductor device layer and a resulting passivation layer formed by depositing and processing each of a plurality of passivation film sub-layers in accordance with the present disclosure.

[0034] [Figure 4] FIG. 4 illustrates a passivation method for forming the resulting passivation layer of FIG.

[0035] [Figure 5]FIG. 5 is a functional block diagram of another example substrate processing system for implementing passivation methods according to embodiments of the present disclosure.

[0036] In the drawings, reference numerals may be reused to identify similar and / or identical elements. DETAILED DESCRIPTION OF THE INVENTION

[0037] Devices such as radio frequency (RF) power devices, micro light-emitting diodes, and wide-bandgap power devices contain nitride materials known as "III-V" semiconductor materials. III-V semiconductor materials have a wurtzite structure and include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and corresponding alloys. III-V semiconductor-based devices offer improved optical and electrical properties compared to conventional silicon and silicon carbide (SiC)-based devices. Process integration of III-V semiconductor-based devices typically requires the deposition of a relatively thin passivation layer that is in direct contact with the III-V semiconductor-based device. For example, the passivation layer may be 20 to 300 nanometers (nm) thick, depending on the purpose of the passivation and the device structure. An increase in thickness (e.g., greater than 300 nm) can cause degradation of the device's electrical properties, such as a reduction in breakdown voltage. The purpose of a passivation layer is not only to provide protection from chemical-based degradation but also to eliminate potential charge trapping sources by introducing silicon (Si) or nickel (Ni) into the surface of III-V semiconductor-based devices. This creates stringent requirements for the processing and physical properties of the passivation layer, such as hydrogen content, deposition temperature, type of reactant species, and conformality. To meet some of these requirements, atomic layer deposition (ALD) may be employed to form the passivation layer. However, ALD is a slow process, resulting in reduced throughput and increased costs.

[0038] In applications requiring a passivation film layer, the molecular hydrogen content of the passivation film layer is reduced to prevent hydrogen atoms from moving around and adversely affecting the components and operation of the semiconductor device, potentially causing failure of the semiconductor device. Therefore, in certain applications, it is desirable to have a passivation film layer with a very low hydrogen concentration.

[0039] Examples described herein include the formation of a resulting passivation film layer with a low hydrogen concentration (e.g., less than 10 atomic % hydrogen). While certain processes may be able to reduce the hydrogen concentration to 20 atomic %, it is difficult to consistently produce a passivation film layer with less than 12 atomic % hydrogen. The atomic % hydrogen represents the total number of hydrogen (H) atoms in the passivation layer divided by the total number of atoms in the passivation layer. In some examples, an iterative process is performed to form multiple thin passivation film sublayers. Each thin passivation film sublayer is then post-plasma treated to remove the hydrogen content. In some examples, an NH3-free silicon nitride deposition process is used to form the passivation film sublayers, followed by a post-treatment with nitrogen and / or argon. The post-treatment with nitrogen and / or argon removes hydrogen from the passivation film sublayers. Additionally, forming multiple thin passivation film sublayers instead of depositing a single thick passivation film improves the effectiveness of the post-plasma treatment and further minimizes the overall hydrogen content.

[0040] 1 illustrates an example of a substrate processing system (or tool) 100 that includes a system controller 101 that performs a passivation method, forms different passivation film sub-layers, and performs post-plasma treatments of the passivation film sub-layers, as described in more detail below. In FIG. 1, the substrate processing system 100 includes a processing chamber 102 having multiple processing stations 104; although two processing stations are shown, the processing chamber 102 may have four processing stations, as shown in FIG. 2.

[0041] In one embodiment, each of the processing stations 104 may be used to complete a resulting passivation layer on each substrate, including depositing multiple passivation film sub-layers on the respective substrate. Each substrate may include multiple semiconductor devices on which passivation film sub-layers are formed. A post-plasma treatment is performed on each of the passivation film sub-layers. As an example, 20 passivation film sub-layers may be deposited on a substrate in a processing station, with each passivation film sub-layer being post-plasma treated before the deposition of the next passivation film sub-layer and / or completion of the formation of the resulting passivation layer. This is also referred to as a discontinuous operating mode for film formation.

[0042] In another embodiment, each of the processing stations 104 deposits one or more passivation film sublayers of the resulting passivation layer on each of a plurality of substrates. Each substrate may include multiple semiconductor devices on which a passivation film sublayer is formed. In this exemplary embodiment, each substrate moves from processing station to processing station as a passivation film sublayer is formed. In one embodiment, a single passivation film sublayer is formed in a first processing station, and then the corresponding substrate moves to the next processing station, where the next passivation film sublayer is formed. This continues until all passivation film sublayers are formed on that substrate. Each substrate moves between adjacent processing stations after depositing a passivation film sublayer and performing a post-plasma treatment on that passivation film sublayer. This is also referred to as a continuous operation mode of film formation.

[0043] As an example, 20 passivation film sublayers of the resulting passivation layer may be formed on each of four substrates, with five passivation film sublayers formed in each of four processing stations for each of the four substrates. A post-plasma treatment is performed on each of the passivation film sublayers. The post-plasma treatment for each passivation film sublayer is performed in the processing station in which that passivation film sublayer is deposited. The continuous operation mode improves the uniformity of the passivation film sublayers and the resulting passivation layer between substrates.

[0044] Each of the processing stations 104 includes a respective substrate support (e.g., substrate support 106), such as an electrostatic chuck, and a showerhead (e.g., showerhead 108). The substrate support includes a respective lift pin actuator assembly (e.g., lift pin actuator assembly 110). The lift pin actuator assembly includes lift pins (e.g., lift pins 112) that operate to raise and lower a substrate (e.g., substrate 114) between the substrate support and a substrate transport paddle 111.

[0045] Each of the processing stations 104 includes an upper electrode and a lower electrode. The showerhead may be implemented as the upper electrode or may include the upper electrode. The substrate support may be implemented as the lower electrode or may include the lower electrode. The upper and lower electrodes may be implemented as radio frequency (RF) electrodes, bias electrodes, clamping electrodes, and / or heating electrodes. For example, the upper electrode may be implemented as a showerhead that introduces and distributes gases within the processing station. The showerhead may include a stem 116 with an end connected to the top surface of the processing chamber 102. The showerhead is generally cylindrical and extends radially outward from the opposite end of the stem 116 at a location spaced from the top surface of the processing chamber. The substrate-facing surface of the showerhead includes holes through which process or purge gases flow. Alternatively, the showerhead may include a conductive plate, and gases may be introduced in other ways.

[0046] The RF generation system 120 generates and outputs RF voltages to the upper and lower electrodes. In each of the processing stations, one of the upper and lower electrodes may be DC grounded, AC grounded, or at a floating potential. For example, the RF generation system 120 may be controlled by a system controller 101 and may include one or more RF generators 122 (e.g., capacitively coupled plasma RF power generators, bias power generators, and / or other RF power generators) that generate RF voltages and supply them to the upper and / or lower electrodes via one or more matching and distribution networks 124. The system controller 101 sets and adjusts the frequencies of the RF signals output from the RF generators 123, 125. The frequencies may be adjusted to adjust the power distribution within and across the substrate support. The system controller 101 is connected to and / or includes a memory 126, which may store passivation instructions 130 for implementing the passivation methods disclosed herein.

[0047] As an example, a first RF generator 123, a second RF generator 125, a first RF matching network 127, and a second RF matching network 129 are shown. The first RF generator 123 and the first RF matching network 127 may provide RF voltages or may simply connect the showerhead to a ground reference. The second RF generator 125 and the second RF matching network 129, which may each be referred to as a power source or collectively, provide RF / bias voltages to the substrate support. In one embodiment, the first RF generator 123 and the first RF matching network 127 provide power to ionize the gas and drive the plasma. In another embodiment, the second RF generator 125 and the second RF matching network 129 provide power to ionize the gas and drive the plasma. One of the RF generators 123, 125 may be a high-power RF generator, generating, for example, 6-10 kilowatts (kW) or more of power.

[0048] The gas delivery system 131 includes one or more gas sources 132-1, 132-2, ..., and 132-N (collectively, gas sources 132), where N is an integer greater than 0. The gas source 132 supplies one or more precursors and their gas mixtures. The gas source 132 may also supply an etching gas, a carrier gas, and / or a purge gas. Silane and nitrogen may be supplied from the gas source 132 to the processing chamber 102 during the formation of the passivation film sub-layer. Nitrogen and / or argon may be supplied from one or more of the gas sources 132 to the processing chamber 102 during post-plasma treatment of the passivation film sub-layer. Vaporized precursors may also be used. The gas source 132 is connected to a manifold 140 by valves 134-1, 134-2, ..., and 134-N (collectively valves 134) and mass flow controllers 136-1, 136-2, ..., and 136-N (collectively mass flow controllers 136). The output of the manifold 140 is provided to the processing chamber 102. For example, the output of the manifold 140 is provided to a showerhead.

[0049] Valves 156 and pumps 158 may be used to evacuate reactants from the processing chamber 102. The system controller 101 may control the components of the substrate processing system 100, including controlling the supplied RF power levels, the pressure and flow rates of supplied gases, RF matching, etc. The system controller 101 controls the states of the valves 156 and pumps 158. A robot 164 may be used to deliver substrates into and remove substrates from the processing station 104. For example, the robot 164 may transport substrates between the substrate support 106 and a load lock 166. The robot 164 may be controlled by the system controller 101. The system controller 101 may control the operation of the load lock 166. Valves, gas and / or coolant pumps, power supplies, RF generators, etc. may be referred to as actuators.

[0050] The substrate processing system 100 further includes a power supply 170 capable of providing power to the system controller 101, the lift pin actuator assembly 110, and a motor 172. The motor 172 rotates a spindle 174. The power supply 170 is controllable by the system controller 101. The system controller 101 is capable of controlling the supply of power from the power supply 170 to the motor 172 and / or the RF generation system 120.

[0051] The lift pin actuator assembly 110 raises and lowers the lift pins 112. The lift pin actuator assembly 110 may include electric and / or pneumatic actuators for adjusting the position of the lift pins 112. A motor 172 rotates a spindle 174, which is connected to a hub 176. The hub 176 is connected to a hub portion of the substrate transport paddle 111. The hub portion may be held by the hub 176 using various techniques. In one embodiment, the hub portion is clamped to and therefore held by the hub 176. In another embodiment, the hub portion is inserted into and supported (or held) by the hub 176. The substrate transport paddle 111 may extend laterally and / or horizontally from the hub 176. The top and / or bottom planes of the substrate transport paddle 111 may be parallel to the top and / or bottom planes of the substrate support 106.

[0052] In operation, the substrate transport paddle 111 rotates to position the substrate 114 above the substrate support 106. The lift pins 112 raise to move the substrate 114 away from the substrate transport paddle 111, which rotates and moves to a stowed position. The lift pins 112 then lower to place the substrate 114 on the substrate support 106. One or more processing operations (e.g., etching, deposition, or cleaning operations) are then performed on the substrate 114. The lift pins 112 then raise to lift the substrate off the substrate support 106, and the substrate transport paddle 111 rotates to position itself between the substrate support 106 and the substrate 114. The lift pins 112 then lower to place the substrate 114 back on the substrate transport paddle 111. This process may be repeated, and the substrate may be moved between processing stations in this manner. Each processing station may perform a different set of processing operations.

[0053] The lift pins 112 may also be used to allow the substrate 114 to be loaded and unloaded from the processing chamber 102 using a robot arm of the robot 164. The upper ends of the lift pins 112 may be flush with or below the upper surface of the substrate support 106 when stowed. During substrate delivery, retrieval, and / or transfer, the lift pins are raised relative to the upper surface of the substrate support 106 to elevate the substrate 114 and provide clearance between the substrate 114 and the substrate support 106. The clearance between the substrate 114 and the substrate support 106 (i) allows for insertion or removal of an end effector of the robot arm and (ii) allows for movement of a substrate transfer paddle between the substrate 114 and the substrate support 106.

[0054] 2 illustrates a processing chamber 102 that includes a processing station 104. The processing station 104 is utilized to deposit a passivation film sub-layer and perform post-plasma treatment of the passivation film sub-layer. The processing chamber 102 is shown with the substrate transfer paddle 111 in a stowed position, but may be rotated above the substrate support 106 and deployed.

[0055] The substrate transport paddle 111 is carried by and extends from a hub 176. In a stowed state, the substrate transport paddle 111 is positioned between the processing stations 104. When deployed, the substrate transport paddle 111 is positioned at a location between the stowed positions. Rotation of the hub 176 causes the substrate transport paddle 111 to rotate clockwise or counterclockwise from the current processing station to the stowed position and then from the stowed position to the next processing station.

[0056] By way of example, substrate transport paddle 111 is shown including support pins. One support pin of substrate transport paddle 111 is designated 210 and 212. Another support pin of substrate transport paddle 111 may be configured similarly to support pins 210, 212. Support pin 210 is located radially inward from support pin 212. For each of substrate transport paddles 202, support pin 210 is located along the substrate transport paddle between hub 176 and support pin 212.

[0057] FIG. 3 shows a substrate 300 including a base layer 302, a semiconductor device layer 304, and a resulting passivation layer 306. The resulting passivation layer 306 includes a stack of passivation film sub-layers 308, each of which has been post-plasma treated. The passivation film sub-layers 308 may be referred to as a post-plasma treated passivation layer. The semiconductor device layer 304 may include semiconductor devices, such as one or more micro light emitting diodes (LEDs), one or more wide bandgap power devices, one or more memory devices, or other known semiconductor devices. The semiconductor devices are represented by dashed boxes 310 and may each be included in some or all of the semiconductor device layer 304. In some examples, the semiconductor device layer 304 includes multiple semiconductor devices. The semiconductor device layer 304 may include, for example, metal layers, dielectric layers, intermediate bonding layers, P-type, I-type, and / or N-type doped layers, etc. The semiconductor device layer 304 may include III-V semiconductor materials such as GaN, AlN, InN, and / or other nitride materials and / or corresponding alloys. The semiconductor device layer 304 may include semiconductor devices that require the formation of a passivation layer having a low atomic percent hydrogen thereon. The bottom layer of the passivation film sub-layer 308 may be in contact with one or more of the semiconductor devices 310 or may be separated from the semiconductor devices by one or more other layers.

[0058] The passivation film sublayers 308 may each be formed from SiN and / or ultraviolet (UV) light-transmitting SiN (UV-SiN). In an embodiment, the passivation film sublayers 308 are formed without the use of ammonia (NH), referred to as an NH3-free process. In an embodiment, silane (SiH4) and nitrogen are introduced to form each of the passivation film sublayers 308. This is done to provide an NH3-free silicon nitride film sublayer. As an example, when the passivation film sublayers 308 are formed by introducing SiH4 and NH3, the resulting passivation film sublayer may have a hydrogen content of 20 to 30 atomic %. The introduction of NH3 increases the hydrogen content level of the passivation layer. In some examples, by using an NH3-free process, the hydrogen content may be reduced to 11 to 15 atomic %. Each of the passivation film sublayers 308 has a set thickness and / or a thickness within a set range, for example, a thickness T P is shown in Figure 3. The passivation film sub-layers 308 may have the same thickness or may have different thicknesses. In one embodiment, the passivation film sub-layers 308 have the same thickness. Exemplary thicknesses and ranges for the method of Figure 4 are disclosed below.

[0059] 4 illustrates a method of forming the resulting passivation layer 306 of FIG. 3 and may be performed using the substrate processing system 100 of FIG. 1 or the substrate processing system 500 of FIG. 5. The following operations are described with respect to a single processing station operating in a discontinuous mode of operation, although the operations may be modified for a continuous mode of operation. The following operations are primarily described with respect to the substrate processing system of FIG. 1, but are also applicable to the substrate processing system of FIG. 5. By way of example, the operations may be performed by the system controller 101 executing the passivation layer instructions 130.

[0060] The method may start at 400. At 402, if a substrate is not already present in the processing station, a substrate (or semiconductor wafer) may be introduced into the processing station and placed on a substrate support. The substrate may include a base layer and one or more semiconductor device layers, such as base layer 302 and semiconductor device layer 304, which include semiconductor devices 310.

[0061] In 403, the system controller 101 may adjust the temperature within the processing station and / or the substrate support to adjust the temperature of the substrate within a predetermined range. By way of example, the temperature of the substrate may be adjusted to 400-450°C. In an embodiment, the temperature of the substrate is adjusted to 425°C. FIG. 5 shows an example including a temperature control system 514 that may be used to adjust the above temperatures. A similar temperature control system may be implemented for each processing station in the example of FIG. 1.

[0062] The following operations 404 and 406 are performed at least once to grow a film with a low hydrogen concentration. In some embodiments, operations 404 and 406 are performed iteratively until a desired resulting layer thickness is met or a predetermined number of sublayers are formed. Each iteration may be referred to as a passivation sublayer cycle. During each cycle, a SiN and / or UV-SiN passivation film sublayer with minimal hydrogen content is formed. By way of example, more than 20 cycles may be performed to form more than 20 passivation film sublayers. In one embodiment, 20-40 passivation film sublayers are formed.

[0063] At 404, a deposition step is performed, which includes introducing SiH4 and nitrogen into the processing station to deposit a passivation film sub-layer on the top surface(s) of the stack of semiconductor device layers or on the top surface of the last-deposited passivation film sub-layer. The deposition step is a PECVD process in some examples. In some embodiments, the deposition step may utilize a dual radio frequency (RF) process, which includes providing dual frequencies, such as 13.56 MHz and 400 kHz. Other radio frequencies are also usable. The dual frequency can be used to adjust the film stress of the passivation layer to a target level. The passivation layer may require a slight compressive stress for better adhesion to the semiconductor device layers. The use of dual frequencies provides a larger process space for adjusting the film stress. However, the deposition step may utilize a single radio frequency in some examples.

[0064] In some examples, the passivation film sub-layer is formed using an NH3-free silicon nitride PECVD deposition process. In one embodiment, operation 404 occurs for 1-2 seconds. In another embodiment, the PECVD time is 1 second. In another embodiment, the PECVD time is less than 1 second and greater than 0.5 seconds. The passivation film sub-layer is thin, e.g., less than 200 Å thick. In one embodiment, the passivation film sub-layer is less than 100 Å thick. In another embodiment, the thickness is less than 50 Å thick. In another embodiment, the thickness is 20-30 Å thick. The thickness of the passivation film sub-layer depends in part on the duration of the deposition process / step; longer deposition times can result in thicker sub-layers. Generally, thinner passivation film sub-layers can be more effectively treated with a subsequent post-plasma treatment to remove H atoms.

[0065] At 406, the passivation film sub-layer is post-plasma treated with at least one of nitrogen and argon. During the post-plasma treatment, nitrogen and / or argon are introduced into the chamber 102. The nitrogen and / or argon may be injected into the processing chamber at a rate ranging from 8,000 to 13,000 standard cubic centimeters per minute (sccm), and the pressure in the processing chamber may be between 4 and 8.5 torr (T). In one embodiment, nitrogen is introduced without argon. In another embodiment, argon is introduced without nitrogen. In yet another embodiment, both nitrogen and argon are introduced. The post-plasma treatment allows for the release of hydrogen content in the film sub-layer, thereby reducing the hydrogen concentration level of the film. The post-plasma treatment reduces hydrogen by breaking silicon-hydrogen (SiH) bonds and releasing hydrogen from the film. In some embodiments, the post-plasma treatment includes exposing the passivation film sub-layer to nitrogen and / or argon. By way of example, the duration of the exposure may be 10 to 60 seconds. In one embodiment, the duration of exposure is at least 30 seconds. In another embodiment, the duration of exposure is 60 seconds or less. In another embodiment, the duration of exposure is 40 seconds or less. In another embodiment, the duration of exposure is 60 seconds. The effectiveness of post-plasma treatment in removing hydrogen may be highest when the duration is 30-60 seconds. The effectiveness of hydrogen removal may decrease after 40 seconds of exposure. Effectiveness refers to the amount and rate of hydrogen removal. In some examples, the amount of hydrogen removal decreases from 40-60 seconds compared to the effectiveness of hydrogen removal from 10-40 seconds. In some examples, after 60 seconds, the effectiveness of hydrogen removal decreases significantly, and the post-plasma treatment becomes negligible.

[0066] In one embodiment, the post-plasma treatment is carried out for a length of time to reduce the atomic hydrogen % to less than 10 atomic %. In another embodiment, the post-plasma treatment is carried out for a length of time to reduce the atomic hydrogen % to between 7 and 10 atomic %. In another embodiment, the post-plasma treatment is carried out for a length of time to reduce the atomic hydrogen % to between 7 and 8 atomic %. In another embodiment, the atomic hydrogen % is less than 7.5%.

[0067] In one embodiment, RF power is not supplied during the post-plasma treatment. In another embodiment, RF power is supplied. The post-plasma treatment may be a dual frequency process and may include supplying RF power at the same or a different frequency than the frequency introduced during the deposition process used to form the passivation film sub-layer being treated.

[0068] At 408, the system controller determines whether to form another passivation film sub-layer. If so, operations 404 and 406 may be performed again; if not, the method may end at 410.

[0069] Repeating the deposition-plasma treatment cycle—operations 404 and 406—reduces the H content in the resulting passivation layer film. By way of example, the H content in the film may be reduced from up to 20 atomic % to less than 8 atomic %, e.g., 7.3 atomic %. Quantitative analysis of the hydrogen content to determine the atomic % may be obtained, for example, using hydrogen forward scattering spectroscopy (HFSS). This may be performed after deposition of a predetermined number of passivation film sub-layers and / or after formation of the resulting passivation layer.

[0070] HFSS is an ion scattering technique used to quantitatively determine the vertical distribution of hydrogen in thin films. During the HFSS process, He 2+Ions strike the sample surface at a glancing angle, knocking hydrogen atoms from the sample, which can then be analyzed using a solid-state detector. The ability to measure the composition and vertical distribution of hydrogen content within a thin film can be used to understand the physical and / or electrical properties of the thin film. The higher the hydrogen concentration level, the greater the impact on the physical and / or electrical properties of the thin film. Other techniques, such as Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDS), and X-ray photoelectron spectroscopy (XPS), cannot detect hydrogen concentration levels, while secondary ion mass spectroscopy (SIMS) can measure hydrogen. However, quantifying hydrogen with SIMS can be difficult, so a standard is required. HFSS provides a non-destructive method for measuring hydrogen content. Using HFSS, entire wafers can be analyzed. Both conductors and insulators can be analyzed. HFSS has a depth resolution of 300 Å.

[0071] As a comparative example using HFSS, an NH3-free SiN passivation layer formed using a dual-RF PECVD process at a temperature of 400°C without a post-plasma treatment can have a hydrogen content of 17 atomic %. An NH3-free SiN passivation layer formed using a dual-RF PECVD process at a temperature of 425°C without a post-plasma treatment can have a hydrogen content of 11 atomic %. An NH3-free SiN passivation layer formed using a dual-RF PECVD process at a temperature of 425°C with a post-plasma treatment can have a hydrogen content of 8 atomic %. Until utilizing the processes disclosed above, it was challenging to grow a SiN passivation layer with less than 10 atomic % hydrogen.

[0072] Another technique that can be used to indirectly estimate hydrogen content is, for example, measuring the wet etch rate (WER) of the resulting passivation layer. The lower the hydrogen content (or atomic % of hydrogen), the slower the WER. In some embodiments, the resulting passivation layer grown using the above process has a low WER, such as 6.2-6.4 angstroms per minute (Å / m), when immersed in 100:1 diluted hydrofluoric acid (dHF) for 5 minutes (e.g., using dual RF power at 425°C and nitrogen for the post-plasma treatment). There is an inverse correlation between WER and the duration of the post-plasma treatment. There is minimal change in WER as the duration of the post-plasma treatment increases from 40-60 seconds. This indicates that post-plasma treatments longer than 60 seconds have little effect.

[0073] As another comparative example, an NH3-free SiN passivation layer formed using a dual-RF PECVD process without a post-plasma treatment may have a WER of 17 angstroms per minute (Å / m). An NH3-free SiN passivation layer formed using a dual-RF PECVD process and post-plasma treatment without RF power may have a WER of 12-18 Å / m. An NH3-free SiN passivation layer formed using a dual-RF PECVD process with a dual-RF post-plasma treatment including the introduction of argon (Ar) may have a WER of 10-15 Å / m. An NH3-free SiN passivation layer formed using a dual-RF PECVD process with a dual-RF post-plasma treatment including the introduction of nitrogen (N) may have a WER of 6-10 Å / m. The WER decreases as the thickness of the passivation film sublayer decreases. A low WER indicates a low level of hydrogen content.

[0074] 5 shows an exemplary substrate processing system 500 including a substrate support 501, shown as an electrostatic chuck. In the illustrated example, the substrate support 501 includes a body 502. The body 502 may be formed of different materials and / or different ceramic compositions. The body 502 may include, for example, an aluminum alloy, aluminum nitride (AlN), aluminum oxide (AlO), and / or aluminum oxynitride (AlON).

[0075] The substrate processing system 500 includes a processing chamber 504. A substrate support 501 is enclosed within the processing chamber 504. The processing chamber 504 also encloses other components, such as an upper electrode 505, and contains an RF plasma. During operation, a substrate 507 is placed on the substrate support 501 and electrostatically clamped to the substrate support 501. For example, the upper electrode 505 may include a showerhead 509 for introducing and distributing gases. The showerhead 509 may include a stem 511 with one end connected to the top surface of the processing chamber 504. The showerhead 509 is generally cylindrical and extends radially outward from the opposite end of the stem 511 at a location spaced from the top surface of the processing chamber 504. The substrate-facing surface of the showerhead 509 includes holes through which process or purge gases can flow. Alternatively, the upper electrode 505 may include a conductive plate, and gases may be introduced in another manner. In an embodiment, the substrate support 501 may include one or more gas channels 512 for flowing a backside gas to the backside of the substrate 507 .

[0076] The substrate support 501 may include one or more coolant channels 510 that receive coolant from a pump 513. A temperature controller 514 may control the operation of the pump 513 to control the flow and temperature of coolant into and out of the coolant channels 510. The pump 513 may circulate coolant between a reservoir 515 and the coolant channels 510. Although a single pump 513 is shown, two or more pumps may be included. A valve assembly 517 is disposed between the pump 513 and the coolant channels 510 and may be controlled by the temperature controller 514. Supply and return lines may be connected (i) between the one or more pumps and the coolant channels 510, and / or (ii) between the valve assembly 517 and the coolant channels 510.

[0077] The RF generation system 520 generates and outputs RF voltages to the upper electrode 505 and one or more lower electrodes 519 within the substrate support 501. One of the upper electrode 505 and the substrate support 501 may be DC grounded, AC grounded, or at floating potential. For example, the RF generation system 520 may include one or more RF generators 522 (e.g., capacitively coupled plasma RF power generators, bias RF power generators, and / or other RF power generators) that generate RF voltages, which are supplied to the upper electrode 505 and / or the substrate support 501 by one or more matching and distribution networks 524. Electrodes that receive the RF signals, RF voltages, and / or RF power are referred to as RF electrodes. Exemplary components include a plasma RF generator 523, a bias RF generator 525, a plasma RF matching network 527, and a bias RF matching network 529. The plasma RF generator 523 may be a high-power RF generator that generates, for example, 6 to 10 kilowatts (kW) or more of power. The bias RF matching network supplies power to the RF electrodes, such as RF electrode 519 .

[0078] The gas delivery system 530 includes one or more gas sources 532-1, 532-2, ..., and 532-N (collectively, gas source 532), where N is an integer greater than 0. The gas source 532 supplies one or more precursors and their gas mixtures. The gas source 532 may supply silane, nitrogen, and / or argon for forming the passivation film sublayer and post-plasma treatment as described above. The gas source 532 may also supply etching gases, carrier gases, and / or purge gases. Vaporized precursors may also be used. The gas sources 532 are connected to a manifold 540 by valves 534-1, 534-2, ..., and 534-N (collectively, valves 534) and mass flow controllers 536-1, 536-2, ..., and 536-N (collectively, mass flow controllers 536). The output of the manifold 540 is supplied to the processing chamber 504. For example, the output of manifold 540 is fed to showerhead 509 .

[0079] Although the temperature controller 514 is shown separate from the system controller 560, it may be implemented as part of the system controller 560. The substrate support 501 may include multiple temperature control zones, each of which includes a temperature sensor and a set of microchannels. The temperature controller 514 may monitor the temperature indicated by the temperature sensors and adjust the flow rate and / or temperature of a coolant circulating through one or more sets of microchannels to regulate the temperature to a target temperature.

[0080] The substrate processing system 500 may also include a power supply 544 that supplies power, including a high voltage, to the clamping electrode 531 to electrostatically clamp the substrate 507 to the substrate support 501. The clamping electrode receives power to electrostatically clamp the substrate 507 to the substrate support 501 and may receive an RF signal, an RF voltage, and / or RF power. The power supply 544 may be controlled by a system controller 560.

[0081] The substrate processing system 500 may further include a backside vacuum controller 552. The backside vacuum controller 552 may receive gas from the manifold 540 and supply gas to the channel 512 and / or pump 558, thereby improving the transfer of thermal energy between the substrate support 501 and the substrate 507. A backside gas may also be supplied to purge the peripheral edge of the substrate and improve vacuum tracking of the substrate location. The channel 512 may be supplied by one or more injection ports. In one embodiment, multiple injection ports are included to improve cooling. By way of example, the backside gas may include helium.

[0082] The temperature controller 514 can control the operation of the pump 513, and / or other coolant circulation pumps, and / or valve assembly 517 based on parameters detected from a temperature sensor 543 in the processing chamber 504. The backside vacuum controller 552 controls the flow rate of a backside gas (e.g., helium) into the channels 512 for cooling the substrate 507 by controlling the flow from one or more of the gas sources 532 into the channels 512. The backside vacuum controller 552 controls the pressure and flow rate of the gas supplied to the channels 512 based on parameters detected from the temperature sensor 543. In one embodiment, the temperature controller 514 and the backside vacuum controller 552 are implemented as an integrated single controller.

[0083] The temperature sensors 543 may include resistive temperature devices, thermocouples, digital temperature sensors, and / or other suitable temperature sensors. One or more of the temperature sensors 543 may be disposed within and used to detect the temperature of the substrate support 501. During the deposition process, the substrate 507 may be heated in the presence of a high-power plasma. The flow of gas through the channels 512 may reduce the temperature of the substrate 507.

[0084] Valves 556 and pumps 558 may be used to evacuate reactants from the processing chamber 504. A system controller 560 may control components of the substrate processing system 500, including controlling the supplied RF power levels, the pressure and flow rates of supplied gases, RF matching, etc. The system controller 560 controls the states of the valves 556 and pumps 558. The system controller 560 may be configured similarly to and / or operate similarly to the system controller 101 of FIG. 1 , or vice versa. A robot 564 may be used to deliver substrates onto and retrieve substrates from the substrate support 501. For example, the robot 564 may transfer substrates between the substrate support 501 and a load lock 566. The robot 564 may be controlled by the system controller 560. The system controller 560 may control the operation of the load lock 566.

[0085] Valves, gas pumps, power supplies, RF generators, etc., referred to herein may be referred to as actuators. Coolant channels, gas channels, etc., referred to herein may be referred to as temperature adjustment elements. Other temperature control elements, such as heating elements, may also be included within the substrate support. In the illustrated example, electrodes 519, 531 are located in the top layer of the substrate support 501. Coolant channel 510 is located in another layer or layers.

[0086] The foregoing description is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the present disclosure can be embodied in a variety of forms. Accordingly, while the present disclosure includes specific examples, the true scope of the present disclosure should not be so limited, as other modifications will become apparent upon review of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be performed in a different order (or simultaneously) without altering the principles of the present disclosure. Furthermore, although each embodiment is described above as having specific features, any one or more of those features described with respect to any embodiment of the present disclosure can be implemented in and / or combined with the features of any other embodiment, even if that combination is not explicitly stated. In other words, the described embodiments are not mutually exclusive, and substituting one or more embodiments for one another remains within the scope of the present disclosure.

[0087] Spatial and functional relationships between elements (e.g., between modules, circuit elements, semiconductor layers, etc.) are described using various terms, such as "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "on," "above," "below," and "disposed." When a relationship between a first element and a second element is described in the above disclosure, unless explicitly stated as "direct" or "directly," the relationship may be a direct relationship in which there are no intervening elements between the first and second elements, but it may also be an indirect relationship in which one or more intervening elements (spatially or functionally) exist between the first and second elements. As an example, a first layer disposed on a second layer indicates that the first layer is above the second layer and covers a portion of the second layer. The first layer may be in direct contact with the second layer or may be separated from the second layer by one or more intervening (or intermediate) layers. As used herein, the phrase at least one of A, B, and C should be interpreted to mean the logical (A OR B OR C), using a non-exclusive logical OR, and not to mean "at least one of A, at least one of B, and at least one of C."

[0088] In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling the operation of the system before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as a "controller" and may control various components or subparts of one or more systems. Depending on the processing requirements and / or type of system, the controller may be programmed to control any of the processes disclosed herein, such as supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and motion settings, wafer transfer in and out of the tool, and wafer transfer in and out of other transfer tools and / or load locks connected or interfaced to the particular system.

[0089] Broadly, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0090] The controller, in some embodiments, may be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or may be all or part of a fab host computer system, thereby enabling remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, examine trends or performance indicators from multiple fabrication operations, modify parameters of a current process, set processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings. These parameters and / or settings are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, which specifies parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as noted above, the controller may be distributed, such as by having one or more separate controllers networked together and cooperating toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes is one or more integrated circuits on the chamber that communicate with one or more remotely located (e.g., at the platform level or as part of a remote computer) integrated circuits that combine to control the process on the chamber.

[0091] Exemplary systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system related to or usable for the fabrication and / or manufacturing of semiconductor wafers.

[0092] As described above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports of wafers within a semiconductor fabrication factory.

Claims

1. 1. A method for growing a passivation film having less than 10 atomic % hydrogen on a substrate, the method comprising: providing the substrate in a processing station of a substrate processing system; forming a resultant passivation film having less than 10 atomic % hydrogen on the substrate by performing the steps of: Including, The steps include: depositing a passivation film sub-layer on the substrate, the passivation film sub-layer being disposed on a semiconductor device layer or directly on a previously deposited passivation film sub-layer; after depositing the passivation film sub-layer, subjecting the passivation film sub-layer to a post-plasma treatment using at least one of nitrogen and argon to reduce hydrogen content in the passivation film sub-layer; A method comprising:

2. 10. The method of claim 1, the substrate includes a stack of layers including the semiconductor device layer and other semiconductor device layers, the stack including at least one III-V type semiconductor material; The method, wherein the step of depositing the passivation film sub-layer includes depositing the passivation film sub-layer on the stack of layers.

3. 3. The method of claim 2, A method wherein a top layer of the stack of layers comprises the at least one III-V semiconductor material.

4. 10. The method of claim 1, The method, wherein the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content in the passivation film sub-layer to 10.0 atomic % or less.

5. 10. The method of claim 1, The method, wherein the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content in the passivation film sub-layer to less than 10.0 atomic %.

6. 10. The method of claim 1, The method, wherein the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content in the passivation film sub-layer to less than 7.5 atomic %.

7. 10. The method of claim 1, The method, wherein the step of depositing the passivation film sub-layer includes depositing the passivation film sub-layer to have a thickness of less than 200 Å.

8. 10. The method of claim 1, The method, wherein the step of depositing the passivation film sub-layer includes depositing the passivation film sub-layer to have a thickness of less than 100 Å.

9. 10. The method of claim 1, The method, wherein the step of depositing the passivation film sub-layer includes depositing the passivation film sub-layer to have a thickness of less than 50 Å.

10. 10. The method of claim 1, The method, wherein the step of depositing the passivation film sub-layer includes depositing the passivation film sub-layer to have a thickness of 20 to 40 Å.

11. 10. The method of claim 1, The method further comprising introducing said at least one of nitrogen and argon for more than 30 seconds.

12. 10. The method of claim 1, The method further comprising introducing said at least one of nitrogen and argon for a period of 60 seconds or less.

13. 10. The method of claim 1, The method further includes forming a plurality of passivation film sub-layers on the substrate in the processing station.

14. 10. The method of claim 1, The method further includes forming a plurality of passivation film sub-layers on the substrate in a plurality of processing stations, each of the plurality of passivation film sub-layers being formed in one of the plurality of processing stations such that all of the plurality of passivation film sub-layers are not formed in the same processing station.

15. A semiconductor device comprising: The base layer and a stack of semiconductor device layers disposed on the substrate layer; a plurality of passivation film sub-layers disposed on the stack of semiconductor device layers; Equipped with A semiconductor device, wherein the plurality of passivation film sub-layers have a combined hydrogen content level of 10.0 atomic % or less.

16. 16. The semiconductor device of claim 15, A semiconductor device, wherein the stack of semiconductor device layers comprises at least one III-V semiconductor material.

17. 16. The semiconductor device of claim 15, A semiconductor device, wherein a top layer of said stack of semiconductor device layers comprises at least one III-V semiconductor material.

18. 16. The semiconductor device of claim 15, A semiconductor device, wherein the plurality of passivation film sub-layers are stacked as a single passivation layer.

19. 20. The semiconductor device of claim 18, A semiconductor device, wherein the WER of the single passivation layer is 6 to 10 Å / m.

20. 16. The semiconductor device of claim 15, 1. A semiconductor device, wherein each of the plurality of passivation film sub-layers is an ammonia-free silicon nitride layer.

21. 16. The semiconductor device of claim 15, The hydrogen content level of each of the plurality of passivation film sub-layers is less than or equal to 10.0 atomic percent.

22. 16. The semiconductor device of claim 15, The hydrogen content level of each of the plurality of passivation film sub-layers is less than 10.0 atomic percent.

23. 16. The semiconductor device of claim 15, 10. A semiconductor device, wherein each of the plurality of passivation film sub-layers has a hydrogen content level of less than 7.5 atomic percent.

24. 16. The semiconductor device of claim 15, A semiconductor device, wherein each of the plurality of passivation film sub-layers has a thickness of less than 200 Å.

25. 16. The semiconductor device of claim 15, A semiconductor device, wherein each of the plurality of passivation film sub-layers has a thickness of less than 100 Å.

26. 16. The semiconductor device of claim 15, A semiconductor device, wherein each of the plurality of passivation film sub-layers has a thickness of less than 50 Å.

27. 16. The semiconductor device of claim 15, A semiconductor device, wherein each of the plurality of passivation film sub-layers has a thickness of 20 to 40 Å.

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