Display panel and display device

Abstract

The display panel, its manufacturing method, and display device include a base (10), an array circuit layer (20), a pixel definition layer (30), a first capacitor (Cst1), and a plurality of sub-pixel units (PX), the array circuit layer (20) includes a plurality of driving transistors (DT), the sub-pixel units (PX) include a first electrode (40), the first capacitor (Cst1) includes a first electrode plate (110) and a second electrode plate (120), the pixel definition layer (30) covers the first electrode plate (110), the second electrode plate (120) is located on a side of the pixel definition layer (30) away from the base (10), the orthogonal projection of the first electrode plate (110) on the base (10) and the orthogonal projection of the second electrode plate (120) on the base (10) at least partially overlap, and the first electrode plate (110) is connected to the gate electrode of the driving transistor (DT).

Description

[Technical Field]

[0001] This application claims priority from a Chinese patent application bearing application number 202310938917.5, filed with the China Patent Office on July 26, 2023, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD Embodiments of the present application relate to the field of display technology, for example, to a display panel, a manufacturing method thereof, and a display device. [Background technology]

[0003] Flat panel display devices based on technologies such as organic light emitting diodes (OLEDs) and light emitting diodes (LEDs) have advantages such as high image quality, low power consumption, thin body, and wide range of applications. As a result, they are widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers, and have become the mainstream display device.

[0004] However, the display effect of OLED display products in the related art still has room for improvement. Summary of the Invention [Problem to be solved by the invention]

[0005] The embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device. [Means for solving the problem]

[0006] The present embodiment is With the base, an array circuitry layer overlying the base and including a plurality of drive transistors; a plurality of sub-pixel units, each sub-pixel unit including a pixel definition layer and a first electrode, the sub-pixel units being located on a side of the array circuit layer away from the base; a first electrode plate provided in the same layer as the first electrode and covered with the pixel definition layer, and a second electrode plate located on a side of the pixel definition layer away from the base, wherein an orthogonal projection of the first electrode plate on the base and an orthogonal projection of the second electrode plate on the base at least partially overlap each other, and the first electrode plate comprises a first capacitor connected to a gate electrode of the driving transistor; A display panel is provided.

[0007] The present embodiment is With the base, an array circuitry layer overlying the base and including a plurality of drive transistors; a pixel definition layer located on a side of the array circuit layer away from the base, the pixel definition layer including a pixel definition portion and an opening area surrounded and closed by the pixel definition portion, and a plurality of sub-pixel units including first electrodes exposed from the opening area; a first capacitor comprising a first plate and a second plate whose orthogonal projections on the base at least partially overlap, the first plate being connected to the gate electrode of the drive transistor; a separator located on one side of the base and at least partially surrounding the opening area, the orthogonal projection of the first electrode plate on the base at least partially overlapping with the orthogonal projection of the first electrode plate on the base, and at least a portion of the separator serving as the second electrode plate; A display panel is further provided.

[0008] The present embodiment is To provide a base and forming an array circuit layer over the base, the array circuit layer comprising a plurality of drive transistors; forming a first electrode plate connected to the gate electrode of the driving transistor and a first electrode in the sub-pixel unit on a side of the array circuit layer away from the base; forming a pixel defining layer covering the first plate on a side of the first electrode away from the base; forming a second plate on a side of the pixel definition layer away from the base, wherein an orthogonal projection of the first plate on the base and an orthogonal projection of the second plate on the base at least partially overlap, and the first plate and the second plate constitute two plates of a first capacitor. A method for fabricating a display panel is also provided.

[0009] An embodiment of the present application further provides a display device including the display panel according to any embodiment of the present application. [Effects of the Invention]

[0010] The display panel, manufacturing method thereof, and display device according to the embodiments of the present application use a first capacitor to store the gate electrode voltage of the driving transistor. For example, the first electrode plate may be disposed in the same layer as the first electrode, and the second electrode plate may be disposed on a side of the pixel definition layer that is spaced apart from the base, and the first and second electrodes may be insulated by the pixel definition layer. Using the pixel definition layer as a capacitor dielectric layer between the first and second electrodes is advantageous in increasing the capacitance of the first capacitor, improving the stability of the gate electrode voltage of the driving transistor, and improving the display effect of the display panel.

[0011] As can be seen from the above, the technical solution of the present application forms a first capacitor and uses the first capacitor as a storage capacitor in the pixel circuit, which is advantageous for increasing the capacitance value of the storage capacitor, avoiding the constraints on the capacitance value of the storage capacitor due to high pixel density unit (Pixels Per Inch, PPI) design, improving the stability of the gate electrode voltage of the driving transistor, and improving the display effect of the display panel. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a plan view of a display panel according to an embodiment of the present invention. [Figure 2] 2 is a cross-sectional view obtained by cutting the display panel shown in FIG. 1 along cutting line BB'. FIG. [Figure 3]FIG. 2 is a structural schematic diagram of a pixel circuit according to an embodiment of the present application. [Figure 4] 2 is another cross-sectional view obtained by cutting the display panel shown in FIG. 1 along cutting line BB'. FIG. [Figure 5] 2 is an enlarged view of an M region in the display panel shown in FIG. [Figure 6] FIG. 10 is a structural schematic diagram of another pixel circuit according to an embodiment of the present application. [Figure 7] 1 is a schematic diagram illustrating a flow of a method for manufacturing a display panel according to an embodiment of the present application. [Figure 8] 3A to 3C are structural schematic diagrams of a display panel formed in some steps of a method for manufacturing a display panel according to an embodiment of the present application. [Figure 9] 5A to 5C are structural schematic diagrams of a display panel formed in another step of the method for manufacturing a display panel according to an embodiment of the present application. [Figure 10] 5A to 5C are structural schematic diagrams of a display panel formed in another step of the method for manufacturing a display panel according to an embodiment of the present application. [Figure 11] 5A to 5C are structural schematic diagrams of a display panel formed in another step of the method for manufacturing a display panel according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0013] The terms "first," "second," and the like in the present specification, claims, and drawings need not be used to describe a particular order or sequence, but are merely used to distinguish between similar objects. Such used data may be interchanged where appropriate, so that it should be understood that the embodiments of the present invention described herein may be practiced in orders other than those illustrated or described herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, and may include, for example, other processes, methods, systems, products, or devices of a sequence of steps or units not explicitly recited, or other steps or units inherent in such processes, methods, systems, products, or devices, other than the process, method, system, product, or device of a sequence of steps or units shown in the embodiments of the present invention.

[0014] In a display panel with a high pixel density (Pixels Per Inch, PPI), the area of ​​a single sub-pixel is limited, making it difficult to increase the size of the storage capacitor in the pixel circuit, which affects the stability of the gate electrode voltage of the driving transistor in the pixel circuit. This causes display abnormalities such as flicker and bright spots on a black screen on the display panel, limiting the improvement of the display effect.

[0015] An embodiment of the present application provides a display panel. FIG. 1 is a plan view of the display panel according to the embodiment of the present application, FIG. 2 is a cross-sectional view of the display panel shown in FIG. 1 taken along section line BB', and FIG. 3 is a structural schematic diagram of a pixel circuit according to the embodiment of the present application. Referring to FIGS. 1 to 3, the display panel includes a base 10, an array circuit layer 20, a pixel definition layer 30, a first capacitor Cst1, and a plurality of subpixel units PX. The embodiment of the present application forms the first capacitor without adding any additional film layers and corresponding mask plates to the display panel. The first capacitor serves as a storage capacitor in the pixel circuit, thereby increasing the capacitance of the storage capacitor, avoiding the constraints on the capacitance of the storage capacitor due to high PPI design, improving the stability of the gate electrode voltage of the driving transistor, and improving the display effect of the display panel.

[0016] The array circuit layer 20 is disposed on the base 10 and includes a plurality of pixel circuits, each of which includes a drive transistor DT. The pixel definition layer 30 and the sub-pixel unit PX are disposed on a side of the array circuit layer 20 away from the base 10, and the sub-pixel unit PX includes a first electrode 40. The first capacitor Cst1 includes a first electrode plate 110 and a second electrode plate 120, the first electrode plate 110 being disposed in the same layer as the first electrode 40, the pixel definition layer 30 covering the first electrode plate 110, and the second electrode plate 120 being disposed on a side of the pixel definition layer 30 away from the base 10, the orthogonal projection of the first electrode plate 110 on the base 10 at least partially overlapping with the orthogonal projection of the second electrode plate 120 on the base 10, and the first electrode plate 110 being connected to the gate electrode 220 of the drive transistor DT.

[0017] The base 10 can provide protection, support, etc. for the display panel. The base 10 may be a flexible base, and the material of the flexible base may be polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), etc., or a mixture of a plurality of the above materials. The base 10 may also be a hard base made of a material such as glass.

[0018] The display panel has a display area AA and a non-display area NAA. The display area AA is provided with a plurality of sub-pixel units PX, which are located in an area defined by a pixel definition layer 30. The sub-pixel units PX have first electrodes 40, and a pixel circuit is electrically connected to the first electrodes 40 of the corresponding sub-pixel units PX to drive the corresponding sub-pixel units PX to emit light. Exemplarily, the sub-pixel units PX include a light-emitting element D0, which may be an organic light-emitting diode (OLED) or a micro-light-emitting diode (Micro-LED), and the first electrode 40 is an electrode, such as an anode, of the light-emitting element D0. The driving transistor DT and the light-emitting element D0 are connected between a first power line ELVDD and a second power line ELVSS. The driving transistor DT generates a driving current based on its gate electrode voltage to drive the light-emitting element D0 to emit light, so that the display panel can display.

[0019] An overlapping region exists between the orthogonal projection of the first plate 110 on the base 10 and the orthogonal projection of the second plate 120 on the base 10, and the pixel definition layer 30 covers the first plate 110, while the second plate 120 is located on the side of the pixel definition layer 30 that is away from the base 10. As a result, the first plate 110 and the second plate 120 are insulated by the pixel definition layer 30, and the first plate 110 and the second plate 120 form a first capacitor Cst1, the first plate 110 of which is connected to the gate electrode 220 of the driving transistor DT. As a result, the first capacitor Cst1 serves as a storage capacitor of the pixel circuit, and can store the gate electrode voltage of the driving transistor DT through the first capacitor Cst1.

[0020] In the technical solution of the embodiments of the present application, the first capacitor Cst1 is used as a storage capacitor to store the gate electrode voltage of the drive transistor DT, the first plate 110 is located in the same layer as the first electrode 40, and the second plate 120 is located on the side of the pixel defining layer 30 that is away from the base 10. The first plate 110 and the second plate 120 are insulated from each other by the pixel defining layer 30. Because the material of the pixel defining layer 30 has a high dielectric constant and is usually thin, using the pixel defining layer 30 as a capacitor dielectric layer between the first plate 110 and the second plate 120 is advantageous for increasing the capacitance of the first capacitor Cst1, improving the stability of the gate electrode voltage of the drive transistor DT, and enhancing the display effect of the display panel.

[0021] As can be seen from the above, the technical solution of the embodiment of the present application forms the first capacitor without adding an extra film layer and a corresponding mask plate to the display panel, and the first capacitor can be used as a storage capacitor in the pixel circuit, which is advantageous for increasing the capacitance of the storage capacitor, avoiding the constraints on the capacitance of the storage capacitor due to high PPI design, and increasing the capacitance of the storage capacitor improves the stability of the gate electrode voltage of the driving transistor and improves the display effect of the display panel.

[0022] There are various types of specific installation methods for the first capacitor Cst1, and several of these will be described below as examples.

[0023] 1 to 3 , in one embodiment, the sub-pixel unit PX further includes a second electrode 60 located on a side of the pixel definition layer 30 away from the base 10, where the second electrode 60 and the second electrode 120 comprise different materials. The second electrode 60 may be the cathode of the light-emitting element D0. The second electrode 60 and the second electrode 120 are both located on a side of the pixel definition layer 30 away from the base 10, and the second electrode 120 and the second electrode 60 may both comprise a conductive material, and the light transmittance of the second electrode 60 is greater than that of the second electrode 120. Preferably, the second electrode 120 and the second electrode 60 are provided on different layers, that is, they may be located on different layers. The second electrode 120 and the second electrode 60 are both located on the side of the pixel definition layer 30 that is away from the base 10, but the second electrode 120 and the second electrode 60 are formed in different film layer manufacturing processes. For example, the second electrode 120 may be first formed on the side of the pixel definition layer 30 that is away from the base 10, and then the second electrode 60 may be formed on the side of the pixel definition layer 30 that is away from the base 10. By making the second electrode 120 and the second electrode 60 comprise different materials and / or positioning the second electrode 120 and the second electrode 60 in different layers, the second electrode 120 and the second electrode 60 are formed as different structures rather than an integrated structure, and the space on the side of the pixel definition layer 30 that is away from the base 10 is used to respectively install the second electrode 120 and the second electrode 60, thereby achieving the above-mentioned effects and avoiding an increase in the thickness of the display panel.

[0024] Preferably, the pixel defining layer 30 includes a pixel defining portion 310 and an opening area 320 enclosed by the pixel defining portion 310, exposing the first electrode 40. The pixel defining portion 310 covers the first electrode 110, and the second electrode 120 is located on a side of the pixel defining portion 310 that is away from the base 10. The pixel defining portion 310 separates the first electrode 110 from the second electrode 120, thereby insulating the first electrode 110 from the second electrode 120. The display panel further includes a light-emitting layer 50, which is disposed in the opening area 320 and is located on a side of the first electrode 40 that is away from the base 10. The second electrode 60 is located on the side of the light-emitting layer 50 that is farther from the base 10. A power supply voltage is input to the second electrode 60, and the second electrode plate 120 is in contact with the second electrode 60 so that the power supply voltage can be input. The power supply voltage may be a fixed voltage or a variable voltage. For example, the power supply voltage may be kept constant within the same display period, and may be different between different display periods.

[0025] The pixel defining portion 310 is made of an insulating material with a high dielectric constant and a thin thickness. Using the pixel defining portion 310 as a capacitor dielectric layer between the first plate 110 and the second plate 120 is advantageous for increasing the capacitance of the first capacitor Cst1, improving the stability of the gate electrode voltage of the driving transistor DT, and improving the display effect of the display panel. The second electrode 60 is partially located on a side of the light emitting layer 50 that is spaced apart from the base 10, and partially located on a side of the pixel defining portion 310 that is spaced apart from the base 10, and the second plate 120 and the second electrode 60 are in contact with each other to achieve electrical connection. The second electrode 60 serves as the cathode of the light emitting element D0 and is connected to the second power line ELVSS. The second power line ELVSS inputs a power supply voltage, i.e., the second power line ELVSS transmits the power supply voltage to the second electrode 60, thereby inputting the power supply voltage to both the second electrode 60 and the second electrode 120. By making the second plate 120 contact the second electrode 60 so that the power supply voltage is input, the potential of the second plate 120 is fixed within the same display period, and the first capacitor Cst1 stores the gate electrode voltage of the driving transistor DT. As a result, there is no need to provide a fixed voltage to the second plate 120 alone, and the power supply voltage can be used as the fixed voltage that needs to be input to the second plate 120. This is advantageous in reducing the number of signal terminals and signal lines for transmitting voltage signals in the display panel and simplifying the structure of the display panel.

[0026] FIG. 4 is another cross-sectional view of the display panel shown in FIG. 1 taken along the cutting line BB'. Referring to FIGS. 3 and 4, in another embodiment, the display panel includes a base 10, an array circuit layer 20, a pixel definition layer 30, a first capacitor Cst1, an isolation portion 70, and a plurality of sub-pixel units PX. The array circuit layer 20 is located on the base 10 and includes a plurality of pixel circuits, each of which includes a driving transistor DT. The sub-pixel units PX include a first electrode 40, and the pixel definition layer 30 and the first electrode 40 are located on a side of the array circuit layer 20 away from the base 10. The pixel definition layer 30 includes a pixel definition portion 310 and an opening area 320 enclosed by the pixel definition portion 310, exposing the first electrode 40. The first capacitor Cst1 includes a first electrode plate 110 and a second electrode plate 120, and the orthogonal projection of the first electrode plate 110 on the base 10 at least partially overlaps with the orthogonal projection of the second electrode plate 120 on the base 10, and the first electrode plate 110 is connected to the gate electrode 220 of the drive transistor DT. The isolation portion 70 is located on the base 10, and the orthogonal projection of the isolation portion 70 on the base 10 at least partially overlaps with the orthogonal projection of the first electrode plate 110 on the base 10, and at least a portion of the isolation portion 70 also serves as the second electrode plate 120.

[0027] The isolation portion 70 includes a conductive material, for example, a metal material. The isolation portion 70 may be provided on a side of the pixel definition layer 30 that is away from the base 10, for example, the isolation portion 70 is provided to at least partially surround the opening area 320. Preferably, the first electrode plate 110 is provided in the same layer as the first electrode 40, the pixel definition layer 30 covers the first electrode plate 110, and the isolation portion 70 is located on a side of the pixel definition layer 30 that is away from the base 10, so that the first electrode plate 110 and the isolation portion 70 are insulated by the pixel definition layer 30. The sub-pixel unit PX may include a first electrode 40, a light-emitting layer 50, and a second electrode 60, and the isolation portion 70 is located between adjacent sub-pixel units PX to isolate the adjacent sub-pixel units PX. Since the first electrode plate 110 and the isolation portion 70 are insulated by the pixel definition layer 30, and the orthogonal projection of the isolation portion 70 on the base 10 overlaps with the orthogonal projection of the first electrode plate 110 on the base 10, the isolation portion 70 can be used as the second electrode plate 120, thereby forming a first capacitor Cst1 using the first electrode plate 110 and the isolation portion 70, and the first capacitor Cst1 can be used as a storage capacitor. In order to achieve the above-mentioned effect, the existing isolation portion 70 in the display panel can be used as the second electrode plate 120, eliminating the need to install an additional second electrode plate 120, which is advantageous in simplifying the manufacturing process of the display panel.

[0028] Preferably, the potential of the second plate 120 is fixed within the same display period by inputting a power supply voltage to the isolation part 70, which also serves as the second plate 120. Thus, the gate electrode voltage of the driving transistor DT is stored by the first capacitor Cst1. In this way, there is no need to provide a fixed voltage to the second plate 120 alone, and the power supply voltage can be used as the fixed voltage that needs to be input to the second plate 120. This is advantageous in reducing the number of signal terminals and signal lines for transmitting voltage signals in the display panel and simplifying the structure of the display panel.

[0029] Preferably, the isolation portion 70 is located on a side of the pixel defining portion 310 that is away from the base 10, and the pixel defining portion 310 covers the first electrode plate 110 to insulate the first electrode plate 110 from the isolation portion 70. The first electrode 40, the light-emitting layer 50, and the second electrode 60 located in the same opening area 320 belong to the same sub-pixel unit PX, and the light-emitting layer 50 of the sub-pixel unit PX has gaps on the side surfaces of the isolation portion 70, i.e., the light-emitting layers 50 of multiple sub-pixel units PX are separated by the side surfaces of the isolation portion 70, and the light-emitting layers 50 of adjacent sub-pixel units PX are isolated by the isolation portion 70, and the second electrode 60 is overlapped and connected to the isolation portion 70.

[0030] As can be seen from the above, in the technical solution of the embodiment of the present application, the first plate 110 is connected to the gate electrode of the drive transistor DT, the first plate 110 and the first electrode 40 are disposed on the same layer, the first plate 110 is one plate of the first capacitor Cst1, the isolation portion 70 is the other plate of the first capacitor Cst1, and the pixel definition portion 310 is a capacitor dielectric layer between the two plates. In order to achieve the above-mentioned effects, the isolation portion 70 also serves as the second plate 120, and the second electrode 60 is connected to the adjacent isolation portion 70 in an overlapping manner. By inputting a power supply voltage to the isolation portion 70, the first capacitor Cst1 can store the gate electrode voltage of the drive transistor DT, so there is no need to separately provide a fixed voltage to the isolation portion 70. The power supply voltage can be used as a fixed voltage that needs to be input to the second electrode 120, which is advantageous in reducing the number of signal terminals and signal lines for transmitting voltage signals in the display panel and simplifying the structure of the display panel. On the other hand, by inputting the power supply voltage to both the second electrode 60 and the isolation portion 70 and reducing the overall resistance of the second electrode 60 and the isolation portion 70, the impact of the voltage drop of the power supply voltage at the second electrode 60 on the magnitude of the power supply voltage is mitigated, the difference in the magnitude of the power supply voltage input to different areas of the display panel is reduced, and a sudden change in the power supply voltage is prevented from affecting the amount of charge stored in the first capacitor Cst1, which contributes to ensuring the stability of the gate electrode voltage of the drive transistor DT.

[0031] 4, the isolation unit 70 preferably includes a first sub-isolation unit 710, a second sub-isolation unit 720, and a third sub-isolation unit 730 that are sequentially stacked on a side of the pixel definition unit 310 that is farther from the base 10. Any one or at least two adjacent ones of the first sub-isolation unit 710, the second sub-isolation unit 720, and the third sub-isolation unit 730 is a conductive isolation unit, and an orthogonal projection of the conductive isolation unit on the base 10 and an orthogonal projection of the first electrode plate 110 on the base 10 at least partially overlap each other, and at least a portion of the conductive isolation unit doubles as the second electrode plate 120 to receive a power supply voltage.

[0032] Any one of the first sub-isolation portion 710, the second sub-isolation portion 720, and the third sub-isolation portion 730 may be a conductive isolation portion, or the first sub-isolation portion 710 and the second sub-isolation portion 720 may be conductive isolation portions, or the second sub-isolation portion 720 and the third sub-isolation portion 730 may be conductive isolation portions, or all of the first sub-isolation portion 710, the second sub-isolation portion 720, and the third sub-isolation portion 730 may be conductive isolation portions. The conductive isolation portions are made of a conductive material (e.g., a metal material), and at least some of the conductive isolation portions double as the second electrode plate 120 to input power voltage. This eliminates the need for an additional second electrode plate 120 to achieve the above-mentioned effects, and allows the conductive isolation portions to double as the second electrode plate 120, which is advantageous in simplifying the manufacturing process of the display panel.

[0033] Preferably, along the direction perpendicular to the base 10, the cross sections of the first sub-isolation section 710 and the third sub-isolation section 730 are rectangular, the cross section of the second sub-isolation section 720 is rectangular or trapezoidal, and if the cross section of the second sub-isolation section 720 is trapezoidal, the lower base of the trapezoid is adjacent to the first sub-isolation section 710, the upper base of the trapezoid is adjacent to the third sub-isolation section 720, the orthogonal projection of the third sub-isolation section 730 on the base 10 covers the orthogonal projection of the first sub-isolation section 710 on the base 10, and the orthogonal projection of the third sub-isolation section 730 on the base 10 covers the orthogonal projection of the second sub-isolation section 720 on the base 10.

[0034] For example, the length of the third sub-isolation portion 730 may be greater than or equal to the length of the first sub-isolation portion 710, and greater than or equal to the length of the second sub-isolation portion 720. The length of the second sub-isolation portion 720 may be the length of the side closer to the first sub-isolation portion 710 or the third sub-isolation portion 730. The length of each sub-isolation portion is the size of the edge of each sub-isolation portion parallel to the first direction Y. The first direction Y is parallel to the surface of the base 10 closer to the isolation portion 70. In this way, the orthogonal projection of the third sub-isolation portion 730 on the base 10 covers the orthogonal projection of the first sub-isolation portion 710 on the base 10, and the orthogonal projection of the third sub-isolation portion 730 on the base 10 covers the orthogonal projection of the second sub-isolation portion 720 on the base 10. That is, along the first direction Y, the length of the first sub-isolation portion 710 is equal to the length of the first sub-isolation portion 710. the opposite edges of the second sub-isolation portion 720 can be shrunk inward relative to both opposite edges of the third sub-isolation portion 730, and the opposite edges of the second sub-isolation portion 720 can be shrunk inward relative to both opposite edges of the third sub-isolation portion 730, so that when forming the second electrode 60, the second electrodes 60 of adjacent sub-pixel units PX can be separated by the first sub-isolation portion 710 in the isolation portion 70, the second electrode 60 can be formed between adjacent isolation portions 70, and the second electrode 60 can be overlap-connected to the first sub-isolation portion 710, or the second electrode 60 can be overlap-connected to both the first sub-isolation portion 710 and the second sub-isolation portion 720. When the first sub-isolation portion 710 is a conductive isolation portion, or when the first sub-isolation portion 710 and the second sub-isolation portion 720 are both conductive isolation portions, a power supply voltage is input to the conductive isolation portion via the second electrode 60.

[0035] 4 , the pixel defining portion 310 includes an inorganic insulating layer material. Preferably, the pixel defining portion 310 includes at least one of a silicon oxide layer and a silicon nitride layer. For example, the pixel defining portion 310 may be made of a silicon oxide material, i.e., the pixel defining portion 310 is a silicon oxide layer, or the pixel defining portion 310 may be made of a silicon nitride material, i.e., the pixel defining portion 310 is a silicon nitride layer, or the pixel defining portion 310 may include at least one silicon oxide layer and at least one silicon nitride layer stacked together. Fabricating and forming the pixel defining portion 310 using an inorganic insulating layer material such as silicon oxide and / or silicon nitride is advantageous in increasing the dielectric constant of the pixel defining portion 310 and thereby increasing the capacitance value of the first capacitor Cst1.

[0036] Preferably, the total thickness of the pixel defining portion 310 is in the range of 100 nm to 1000 nm, and for example, the total thickness of the pixel defining portion 310 may be 500 nm. In this way, the thickness of the pixel defining portion 310 can be reduced, and the capacitance value of the first capacitor Cst1 can be further increased.

[0037] Fig. 5 is an enlarged view of area M in the display panel shown in Fig. 1, in which only some of the film layers of the display panel are shown. Referring to Figs. 4 and 5, preferably, the first plate 110 and the first electrode 40 are insulated, and the first plate 110 is located between adjacent first electrodes 40. By using the area between the adjacent first electrodes 40 to provide the first plate 110, not only can the above-mentioned effects be achieved but also the space utilization rate of the display panel can be improved.

[0038] Preferably, in one embodiment, the first plate 110 is disposed to surround the first electrode 40, and the first plate 110 can form a ring-shaped structure that surrounds the periphery of the first electrode 40. The second plate 120 is disposed to surround the opening area 320 of the pixel definition layer 30, and the overlapping area of ​​the orthogonal projection of the first plate 110 on the base 10 and the orthogonal projection of the second plate 120 on the base 10 surrounds the opening area 320. This can further improve the space utilization of the display panel. At the same time, the areas of the first plate 110 and the second plate 120 are increased, thereby increasing the vertical overlapping area of ​​the first plate 110 and the second plate 120. This increases the capacitance of the first capacitor Cst1, further improving the stability of the gate electrode voltage of the driving transistor DT, and contributing to improving the display effect.

[0039] 3 to 5, preferably, the first electrode 110 of the first capacitor Cst1 connected to the same pixel circuit is arranged to surround the first electrode 40 of the subpixel unit PX driven by the pixel circuit. For example, the subpixel unit PX includes a subpixel unit having a first color light-emitting layer 501, a subpixel unit having a second color light-emitting layer 502, and a subpixel unit having a third color light-emitting layer 503, and the first color, the second color, and the third color are different, for example, the first color is red, the second color is green, and the third color is blue. The first electrode 110 of the first capacitor Cst1 connected to each pixel circuit is arranged to surround the first electrode 40 of the subpixel unit PX driven by the pixel circuit, which facilitates the connection between the first electrode 110 and the driving transistor DT in the corresponding pixel circuit and simplifies the manufacturing process of the display panel.

[0040] 2 and 3, the display panel further includes a connection electrode 250 provided in the same layer as the source electrode 230 or the drain electrode 240 of the driving transistor DT, the connection electrode 250 is electrically connected to the gate electrode 220 and the first electrode plate 110 of the driving transistor DT, respectively, the first electrode plate 110 is connected to the gate electrode 220 of the driving transistor DT by the connection electrode 250, and the orthogonal projection of the connection electrode 250 on the base 10 overlaps with the orthogonal projection of the gate electrode 220 of the driving transistor DT on the base 10.

[0041] For example, the transistor shown in FIG. 3 may be a drive transistor DT, in which the orthogonal projection of the first plate 110 on the base 10 overlaps with the orthogonal projection of the second plate 120 on the base 10, the connection electrode 250 is electrically connected to the gate electrode 220 of the drive transistor DT and the first plate 110, respectively, and the orthogonal projection of the connection electrode 250 on the base 10 overlaps with the orthogonal projection of the gate electrode 220 of the drive transistor DT on the base 10. Therefore, the first capacitor Cst1 may be equivalently a capacitor formed by the gate electrode 220 of the drive transistor DT and the second plate 120, and a fixed voltage is input to the second plate 120 to store the gate electrode voltage of the drive transistor DT in the first capacitor Cst1. This corresponds to increasing the vertical overlap area between the gate electrode 220 of the drive transistor DT and the second plate 120, which is advantageous for increasing the capacitance value of the first capacitor Cst1.

[0042] 2 shows a case where the connection electrode 250 is directly electrically connected to the first electrode plate 110. Referring to FIGS. 3 and 4, in another embodiment, the display panel further includes a connection part 260, which is connected between the first electrode plate 110 and the connection electrode 250, and which is located in the metal layer between the first electrode plate 110 and the connection electrode 250, electrically connecting the first electrode plate 110 and the connection electrode 250.

[0043] 3 and 4, the array circuit layer 20 has a plurality of metal layers, with an insulating layer provided between two adjacent metal layers, the plurality of metal layers having a first metal layer M1 and a second metal layer M2, the gate electrode 220 of the driving transistor DT being located on the first metal layer M1, the array circuit layer 20 further having a third electrode plate 130 located on the second metal layer M2, the orthogonal projection of the third electrode plate 130 on the base 10 and the orthogonal projection of the gate electrode 220 of the driving transistor DT on the base 10 at least partially overlapping, and the third electrode plate 130 and the gate electrode 220 of the driving transistor DT constituting two electrodes of the second capacitor Cst2.

[0044] For example, the third plate 130 may be electrically connected to a first power line ELVDD, which transmits a power supply voltage to the third plate 130 as a fixed voltage. The third plate 130 and the gate electrode 220 of the driving transistor DT may form a second capacitor Cst2, which stores the gate electrode voltage of the driving transistor DT. The first power line ELVDD receives the first power supply voltage, and the second power line ELVSS receives the second power supply voltage. That is, the second plate 120 contacts the second electrode 60 to receive the second power supply voltage. The first and second power supply voltages may be different, e.g., the first power supply voltage may be a positive number, and the second power supply voltage may be a negative number or zero. In order to achieve the above-mentioned effects, the technical solution of the embodiments of the present application uses the first capacitor Cst1 and the second capacitor Cst2 jointly as the storage capacitor of the pixel circuit. In this way, the total capacitance of the storage capacitor of the pixel circuit is the sum of the capacitances of the first capacitor Cst1 and the second capacitor Cst2. Even in a high PPI design, the capacitance of the storage capacitor can be increased to further improve the stability of the gate electrode voltage of the driving transistor DT, and further improve the display effect of the display panel.

[0045] Continuing to refer to FIG. 4, the array circuit layer 20 further includes an active layer 210, a third metal layer M3, and a fourth metal layer M4, and the active layer 210, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are sequentially stacked on one side of the base 10, and the source electrode 230 and the drain electrode 240 of the driving transistor DT and the connection electrode 250 may all be provided in the third metal layer M3, and the connection portion 260 may be provided in the fourth metal layer M4. Preferably, the display panel further includes a first sealing layer 810, a second sealing layer 820, and a third sealing layer 830, wherein the first sealing layer 810 is formed on the side of the second electrode 60 and the isolation portion 70 away from the base 10 and covers the second electrode 60 and at least a portion of the isolation portion 70, the second sealing layer 820 is formed on the side of the first sealing layer 810 and the isolation portion 70 away from the base 10 and covers the first sealing layer 810 and the isolation portion 70, and the third sealing layer 830 is formed on the side of the second sealing layer 820 away from the base 10 and covers the second sealing layer 820.

[0046] 6 is a structural schematic diagram of another pixel circuit according to an embodiment of the present application. Referring to FIG. 6, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor DT, and further includes a first capacitor Cst1 and a second capacitor Cst2 as in any of the above embodiments. Exemplarily, the operation stages of the pixel circuit include an initialization stage, a data writing stage, and a light-emitting stage. In the initialization stage, the third transistor T3 and the fourth transistor T4 are controlled to be turned on in response to a first scan signal S1, and the third transistor T3 transmits an initialization voltage input via an initialization signal line Vref to the gate electrode of the driving transistor DT to initialize the gate electrode voltage of the driving transistor DT. The driving transistor DT is controlled to be turned on, and the fourth transistor T4 transmits an initialization voltage input via an initialization signal line Vref to the anode of the light-emitting element D0 to initialize the anode voltage of the light-emitting element D0. In the data write phase, the first transistor T1 and the second transistor T2 are turned on in response to the second scan signal S2, allowing the data voltage input through the data line Data to be sequentially transmitted to the gate electrode of the driving transistor DT via the first transistor T1, the driving transistor DT, and the second transistor T2, and the gate electrode voltage of the driving transistor DT is related to both the data voltage and the threshold voltage of the driving transistor DT, thereby achieving threshold voltage compensation while writing the data voltage to the driving transistor DT, and the first capacitor Cst1 and the second capacitor Cst2 store the gate electrode voltage of the driving transistor DT. In the light emitting phase, the fifth transistor T5 and the sixth transistor T6 are turned on in response to the light emitting control signal EM, and the first transistor T1 to the fourth transistor T4 are all turned off, thereby forming a conductive path between the first power line ELVDD and the second power line ELVSS, and the driving transistor DT generates a driving current according to the voltage stored in the first capacitor Cst1 and the second capacitor Cst2 to drive the light emitting element D0 to emit light.

[0047] In the technical solution of the embodiments of the present application, the first capacitor Cst1 and the second capacitor Cst2 jointly serve as the storage capacitor of the pixel circuit, thereby increasing the capacitance of the storage capacitor and avoiding the constraints on the capacitance of the storage capacitor due to high PPI design, thereby improving the stability of the gate electrode voltage of the driving transistor DT and contributing to improving the display effect of the display panel.

[0048] The present invention also provides a method for manufacturing a display panel according to any of the above embodiments. Figure 7 is a flow diagram of the method for manufacturing a display panel according to the present invention. Referring to Figure 7, the method specifically includes the following steps:

[0049] In S110, a base is provided.

[0050] In S120, an array circuit layer including a plurality of driving transistors is formed on the base.

[0051] In S130, a first electrode plate connected to the gate electrode of the driving transistor and a first electrode in the sub-pixel unit are formed on the side of the array circuit layer away from the base.

[0052] 8 to 11 are structural schematic diagrams of a display panel formed in steps of a method for fabricating a display panel according to an embodiment of the present disclosure. Referring to Fig. 8, a base 10 is provided, and an array circuit layer 20 is formed on the base 10, on which a plurality of pixel circuits are formed, and a driving transistor DT is provided in the pixel circuit. Exemplarily, the array circuit layer 20 includes an active layer 210, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, and the gate electrode 220 of the driving transistor DT is located on the first metal layer M1, and the source electrode 230 and the drain electrode 240 of the driving transistor DT are located on the third metal layer M3.

[0053] After forming the array circuit layer 20, a first electrode 40 and a first electrode plate 110 are formed on the side of the array circuit layer 20 away from the base 10. For example, the first electrode 40 and the first electrode plate 110 may be provided on the side of the fourth metal layer M4 away from the base 10, and the first electrode plate 110 may be connected to the gate electrode 220 of the driving transistor by a connection portion 260 in the fourth metal layer M4 and a connection electrode 250 in the third metal layer M3.

[0054] In S140, a pixel defining layer is formed covering the first plate and a side of the first electrode away from the base.

[0055] In S150, a second electrode plate is formed on a side of the pixel definition layer away from the base, such that the orthogonal projection of the first electrode plate on the base and the orthogonal projection of the second electrode plate on the base at least partially overlap, and the first electrode plate and the second electrode plate constitute two electrodes of a first capacitor.

[0056] 9, a pixel defining layer 30 is formed on a side of the first electrode 40 and the first electrode plate 110 that is separated from the base 10. Referring to Fig. 10, a second electrode plate 120 is formed on a side of the pixel defining layer 30 that is separated from the base 10, so that an orthogonal projection of the first electrode plate 110 on the base 10 and an orthogonal projection of the second electrode plate 120 on the base 10 at least partially overlap each other, and the first electrode plate 110 and the second electrode plate 120 constitute two electrodes of a first capacitor Cst1.

[0057] The technical solution of the embodiment of the present application forms the first capacitor without adding an extra film layer and corresponding mask plate to the display panel, and the first capacitor can be used as a storage capacitor in the pixel circuit, which is advantageous for increasing the capacitance value of the storage capacitor and avoiding the constraints on the capacitance value of the storage capacitor due to high PPI design. Increasing the capacitance value of the storage capacitor improves the stability of the gate electrode voltage of the driving transistor and improves the display effect of the display panel.

[0058] Referring to FIG. 10 , preferably, step S150 specifically includes forming an isolation portion 70 on the side of the pixel definition layer 30 away from the base 10 such that the orthogonal projection on the base 10 and the orthogonal projection of the first electrode plate 110 on the base 10 at least partially overlap, and at least a portion of the isolation portion 70 doubles as the second electrode plate 120.

[0059] Preferably, after step S150, the method further includes forming the opening area 320 in the pixel definition layer 30, so that the pixel definition layer 30 is composed of the pixel definition portion 310 and the opening area 320 enclosed by the pixel definition portion 310, and the pixel definition portion 310 covers the first electrode plate 110. For example, after forming the isolation portion 70, the opening area 320 of the pixel definition layer 30 may be formed between the regions enclosed by the isolation portion 70, so that the isolation portion 70 surrounds the opening area 320. In another embodiment, the opening area 320 of the pixel definition layer 30 may be formed first, and then step S150 may be performed. For example, the isolation portion 70 may be formed so that it is located on the side of the pixel definition portion 310 that is away from the base 10 and surrounds the opening area 320.

[0060] 11 , the method further includes S160 as follows: in the opening area 320, the light-emitting layer 50 of each sub-pixel unit PX is formed on a side of the first electrode 40 that is away from the base 10, and the light-emitting layer 50 of adjacent sub-pixel units PX is isolated by an isolation portion 70; and the second electrode 60 is formed on a side of the light-emitting layer 50 that is away from the base 10, and the second electrode 60 of adjacent sub-pixel units PX is isolated by the isolation portion 70; the first electrode 40, the light-emitting layer 50, and the second electrode 60 of the same sub-pixel unit PX are located in the same opening area 320, and the light-emitting layer 50 and the second electrode 60 of different sub-pixel units PX are isolated by the isolation portion 70; thus, it is easy to control each sub-pixel unit PX individually, and there is no need to use an additional mask to isolate different sub-pixel units PX during the manufacturing process of the display panel, which is advantageous to reducing the manufacturing cost of the display panel. Referring to Figure 4, after forming the second electrode 60, a first sealing layer 810 may be formed on the side of the second electrode 60 and the isolation portion 70 that is away from the base 10, so as to cover the second electrode 60 and at least a portion of the isolation portion 70; then, a second sealing layer 820 may be formed on the side of the first sealing layer 810 and the isolation portion 70 that is away from the base 10, so as to cover the first sealing layer 810 and the isolation portion 70; and a third sealing layer 830 may be formed on the side of the second sealing layer 820 that is away from the base 10, so as to cover the second sealing layer 820.This completes the sealing process of the display panel, and the display panel shown in Figure 4 is obtained.

[0061] The embodiments of the present application further provide a display device including the display panel of any of the above embodiments, and thus have the functional structure and effects corresponding to the display panel, which will not be described again here. The display device may be a mobile phone, or any electronic product with a display function, including but not limited to, a television, a laptop, a desktop display, a tablet, a digital camera, a smart bracelet, smart glasses, an in-vehicle display, a medical device, an industrial control device, a touch interactive terminal, etc., and the embodiments of the present application are not particularly limited thereto.

Claims

1. With the base, an array circuitry layer overlying the base and including a plurality of drive transistors; a plurality of sub-pixel units, each sub-pixel unit including a pixel definition layer and a first electrode, the sub-pixel units being located on a side of the array circuit layer away from the base; a first electrode plate provided in the same layer as the first electrode and covered with the pixel definition layer, and a second electrode plate located on a side of the pixel definition layer away from the base, wherein an orthogonal projection of the first electrode plate on the base and an orthogonal projection of the second electrode plate on the base at least partially overlap each other, and the first electrode plate comprises a first capacitor connected to a gate electrode of the driving transistor; Display panel.

2. The sub-pixel unit comprises: a second electrode located on a side of the pixel defining layer away from the base, the second plate and the second electrode comprising different materials; The display panel according to claim 1 .

3. The second electrode plate and the second electrode are provided on different layers.

3. The display panel according to claim 1 or 2.

4. the pixel definition layer further includes an isolation portion located on a side away from the base, the isolation portion having an orthogonal projection on the base that at least partially overlaps with an orthogonal projection of the first electrode plate on the base, and at least a portion of the isolation portion also serving as the second electrode plate; The display panel according to claim 1 .

5. the subpixel unit further includes a light-emitting layer having a gap on a side surface of the isolation portion, the light-emitting layer being stacked on a side of the first electrode that is separated from the base, and a second electrode being connected to and overlapping the isolation portion; The display panel according to claim 4 .

6. the isolation portion includes a first sub-isolation portion, a second sub-isolation portion, and a third sub-isolation portion that are sequentially stacked on a side of the pixel definition layer that is farther from the base, any one or at least two adjacent ones of the first sub-isolation portion, the second sub-isolation portion, and the third sub-isolation portion is a conductive isolation portion, an orthogonal projection of the conductive isolation portion on the base and an orthogonal projection of the first electrode plate on the base at least partially overlap each other, and at least a part of the conductive isolation portion is also used as the second electrode plate so that a power supply voltage is input. The display panel according to claim 4 .

7. a cross section of the second sub-isolation section along a direction perpendicular to the base is rectangular or trapezoidal, and when the cross section of the second sub-isolation section is trapezoidal, a lower base of the trapezoid is adjacent to the first sub-isolation section, an upper base of the trapezoid is adjacent to the third sub-isolation section, and an orthogonal projection of the third sub-isolation section on the base covers an orthogonal projection of the first sub-isolation section on the base and also covers an orthogonal projection of the second sub-isolation section on the base; The display panel according to claim 6 .

8. the pixel definition layer includes a pixel definition portion and an opening area that is enclosed by the pixel definition portion and exposes the first electrode; the pixel definition part covers the first electrode plate, the second electrode plate is located on a side of the pixel definition part that is separated from the base, and the pixel definition part separates the first electrode plate from the second electrode plate to insulate the first electrode plate from the second electrode plate. The display panel according to claim 1 .

9. the pixel definition portion includes at least one of a silicon oxide layer and a silicon nitride layer; The display panel according to claim 8 .

10. a thickness range of the pixel defining portion along a direction perpendicular to the base is 100 nm to 1000 nm; The display panel according to claim 8 .

11. The sub-pixel unit comprises: a light-emitting layer provided in the opening area and positioned on a side of the first electrode that is separated from the base; a second electrode located on a side of the light-emitting layer away from the base, configured to receive a power supply voltage, and in contact with the second electrode plate; The display panel according to claim 8 .

12. the first plate and the first electrode are insulated, and the first plate is located between adjacent first electrodes; the first plate is provided to surround the first electrode, the second plate is disposed to surround the opening area of ​​the pixel definition layer, and an overlapping region between the orthogonal projection of the first plate on the base and the orthogonal projection of the second plate on the base surrounds the opening area; The display panel according to claim 8 .

13. a connection electrode provided in the same layer as a source electrode or a drain electrode of the driving transistor, the connection electrode being electrically connected to the gate electrode of the driving transistor and the first electrode plate, respectively, and an orthogonal projection of the connection electrode on the base and an orthogonal projection of the gate electrode of the driving transistor on the base at least partially overlap each other; The display panel according to claim 1 .

14. the array circuit layer further comprises a plurality of metal layers and a third electrode plate; an insulating layer is provided between two adjacent metal layers, the plurality of metal layers include a first metal layer and a second metal layer, and a gate electrode of the driving transistor is located in the first metal layer; the third plate is located on the second metal layer, and an orthogonal projection of the third plate on the base and an orthogonal projection of the gate electrode of the drive transistor on the base at least partially overlap, and the third plate and the gate electrode of the drive transistor constitute two plates of a second capacitor. The display panel according to claim 1 .

15. With the base, an array circuitry layer overlying the base and including a plurality of drive transistors; a pixel definition layer located on a side of the array circuit layer away from the base, the pixel definition layer including a pixel definition portion and an opening area surrounded and closed by the pixel definition portion, and a plurality of sub-pixel units including first electrodes exposed from the opening area; a first capacitor comprising a first plate and a second plate whose orthogonal projections on the base at least partially overlap, the first plate being connected to the gate electrode of the drive transistor; a separator located on one side of the base and at least partially surrounding the opening area, the orthogonal projection of the first electrode plate on the base at least partially overlapping with the orthogonal projection of the first electrode plate on the base, and at least a portion of the separator serving as the second electrode plate; Display panel.

16. the first electrode plate is provided in the same layer as the first electrode, the pixel definition layer covers the first electrode plate, the isolation portion is located on a side of the pixel definition portion that is separated from the base, and the isolation portion that also serves as the second electrode plate is configured to receive a power supply voltage. The display panel according to claim 15.

17. the subpixel unit further includes a light-emitting layer having a gap on a side surface of the isolation portion, the light-emitting layer being stacked on a side of the first electrode that is separated from the base, and a second electrode being connected to and overlapping the isolation portion; The display panel according to claim 15.

18. the isolation portion includes a first sub-isolation portion, a second sub-isolation portion, and a third sub-isolation portion that are sequentially stacked on a side of the pixel definition layer that is farther from the base, any one or at least two adjacent ones of the first sub-isolation portion, the second sub-isolation portion, and the third sub-isolation portion are conductive isolation portions, an orthogonal projection of the conductive isolation portion on the base and an orthogonal projection of the first electrode plate on the base at least partially overlap each other, and at least a part of the conductive isolation portion is configured to receive a power supply voltage and is used as the second electrode plate; a length of the third sub-isolation portion along a direction perpendicular to the base is greater than or equal to a length of the first sub-isolation portion; a cross section of the second sub-isolation portion is rectangular or trapezoidal; if the cross section of the second sub-isolation portion is trapezoidal, a lower base of the trapezoid is adjacent to the first sub-isolation portion, and an upper base of the trapezoid is adjacent to the third sub-isolation portion; The display panel according to claim 15.

19. the array circuit layer further comprises a plurality of metal layers and a third electrode plate; an insulating layer is provided between two adjacent metal layers, the plurality of metal layers include a first metal layer and a second metal layer, and a gate electrode of the driving transistor is located in the first metal layer; the third plate is located on the second metal layer, and an orthogonal projection of the third plate on the base and an orthogonal projection of the gate electrode of the drive transistor on the base at least partially overlap, and the third plate and the gate electrode of the drive transistor constitute two plates of a second capacitor. The display panel according to claim 15.

20. To provide a base and forming an array circuit layer over the base, the array circuit layer comprising a plurality of drive transistors; forming a first electrode plate connected to a gate electrode of the driving transistor and a first electrode in a sub-pixel unit on a side of the array circuit layer away from the base; forming a pixel defining layer covering the first plate on a side of the first electrode away from the base; forming a second plate on a side of the pixel definition layer away from the base, wherein an orthogonal projection of the first plate on the base and an orthogonal projection of the second plate on the base at least partially overlap, and the first plate and the second plate constitute two plates of a first capacitor. How to make a display panel.

21. The display panel according to any one of claims 1 to 14, or the display panel according to any one of claims 15 to 19, Display device.

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