Circuit board and semiconductor package including the same

Abstract

The circuit board of the embodiment includes an insulating layer, a connecting member embedded in the insulating layer, and an electrode portion embedded in the insulating layer and vertically overlapping the connecting member, the connecting member including an electrode pattern disposed on the connecting member, and the electrode pattern being electrically floating with respect to the electrode portion.

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor package, and more particularly to a semiconductor package in which the bonding strength between an insulating substrate and a connecting member is improved. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for arranging more semiconductor elements on a semiconductor package substrate with limited size have been proposed and researched. However, since a typical semiconductor package is based on mounting one semiconductor element, there is a limit to achieving the desired performance.

[0003] Recently, semiconductor packages have been developed that use multiple substrates to arrange multiple semiconductor devices. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. As a result, the semiconductor packages have the advantages of efficiently using the mounting area of ​​the semiconductor devices and transmitting high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Due to these advantages, the above-mentioned semiconductor packages are widely used in mobile devices and the like.

[0005] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, high-performance servers, etc. are becoming more highly integrated, with the number of semiconductor elements and / or the size of each semiconductor element increasing, or the functional parts of the semiconductor element being divided, expanding the concept to semiconductor chiplets.

[0006] This has made intercommunication between semiconductor devices and / or semiconductor chiplets important, leading to a trend toward placing an interposer between a substrate of a semiconductor package and a semiconductor device.

[0007] The interposer functions as a redistribution layer that gradually increases the width or area of ​​the circuit pattern from the semiconductor device to the semiconductor package in order to facilitate intercommunication between the semiconductor device and / or semiconductor chiplet, or to interconnect the semiconductor device and the semiconductor package substrate, thereby facilitating electrical signals between the semiconductor device and the semiconductor package substrate, which has a circuit pattern that is relatively larger than the circuit pattern of the semiconductor device.

[0008] Meanwhile, a package substrate and / or an interposer used in a semiconductor package includes a connecting member for connecting with semiconductor devices and / or semiconductor chiplets. The connecting member functions to horizontally connect a plurality of semiconductor devices and / or semiconductor chiplets. Therefore, the connecting member is embedded in the package substrate and / or the interposer.

[0009] In this case, the connecting member may be either an inorganic bridge or an organic bridge. The electrodes of the connecting member may have a smaller width and / or spacing than the electrodes of the package substrate and / or interposer. For example, the connecting member may include high-density electrodes. Therefore, the surface roughness of the electrodes of the connecting member may be relatively small. That is, the greater the surface roughness of the electrodes, the more difficult it is to reduce the line width or spacing of the electrodes. Therefore, when the connecting member is embedded in the package substrate and / or interposer, the adhesion between the connecting member and the package substrate and / or interposer may be reduced. This may result in the problem of the connecting member peeling off from the package substrate and / or interposer. Summary of the Invention [Problem to be solved by the invention]

[0010] The embodiment provides a semiconductor package with a new structure.

[0011] Also, an embodiment provides a semiconductor package including a substrate and a connecting member embedded in the substrate.

[0012] Additionally, embodiments provide semiconductor packages with improved mechanical and electrical reliability.

[0013] Furthermore, the embodiment provides a semiconductor package that can improve the adhesion between the substrate and the connecting member.

[0014] Furthermore, the embodiments provide a semiconductor package that can prevent the substrate and / or the connecting member from warping significantly in a specific direction.

[0015] The technical problems to be solved by the proposed embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the embodiments pertain from the following description. [Means for solving the problem]

[0016] The circuit board of the embodiment includes an insulating layer, a connecting member embedded in the insulating layer, and an electrode portion embedded in the insulating layer and vertically overlapping the connecting member, the connecting member including an electrode pattern disposed on the connecting member, and the electrode pattern being electrically floating with respect to the electrode portion.

[0017] In addition, the connecting member includes first and second connecting electrodes spaced apart horizontally from the electrode pattern, the electrode portion includes a first electrode portion vertically overlapping the first connecting electrode and a second electrode portion vertically overlapping the second connecting electrode, and the electrode pattern is electrically floating with the first electrode portion, the second electrode portion, the first connecting electrode, and the second connecting electrode.

[0018] The insulating layer includes a first insulating layer having a cavity and a second insulating layer disposed on the first insulating layer and filling at least a portion of the cavity, the connecting member is disposed within the cavity, the first electrode portion includes a first through electrode that penetrates at least a portion of the second insulating layer and vertically overlaps with the first connecting electrode, and a second through electrode that penetrates at least a portion of the second insulating layer and vertically overlaps with the first connecting electrode, and the electrode pattern does not vertically overlap with the first and second through electrodes.

[0019] Further, the first electrode portion includes a first wiring electrode arranged on the first through electrode and a second wiring electrode arranged on the second through electrode, and the electrode pattern does not overlap the first and second wiring electrodes in the vertical direction.

[0020] The electrode pattern is disposed on the same plane as the first and second connecting electrodes on the upper surface of the connecting member.

[0021] The surface roughness of the electrode pattern is greater than the surface roughness of at least one of the first and second connecting electrodes.

[0022] The first and second connecting electrodes may each be provided in a plurality of pieces, and the planar area of ​​a single electrode pattern may be greater than the planar area of ​​a single electrode of the plurality of first and second connecting electrodes.

[0023] The first and second connecting electrodes have the same edge shape on the top surface, and the electrode pattern has a different edge shape from the first and second connecting electrodes.

[0024] The circuit board also includes a dummy through electrode arranged on the electrode pattern and overlapping horizontally with at least a portion of the first and second through electrodes, and a dummy wiring electrode arranged on the dummy through electrode and overlapping horizontally with the first and second wiring electrodes.

[0025] The circuit board further includes a protective layer disposed on the insulating layer, a first protruding electrode that penetrates at least a portion of the protective layer and vertically overlaps the first wiring electrode, a second protruding electrode that penetrates at least a portion of the protective layer and vertically overlaps the second wiring electrode, and a dummy protruding electrode that penetrates at least a portion of the protective layer and vertically overlaps the dummy wiring electrode.

[0026] Meanwhile, a semiconductor package according to an embodiment includes the circuit board and a semiconductor element disposed on the circuit board, the semiconductor element including first and second semiconductor elements spaced apart along a horizontal direction on the circuit board, and the electrode pattern vertically overlaps the spaced apart area between the first and second semiconductor elements.

[0027] The first semiconductor element includes a first terminal that overlaps the first connecting electrode in a vertical direction, and the second semiconductor element includes a second terminal that overlaps the second connecting electrode in a vertical direction.

[0028] Furthermore, at least a portion of the electrode pattern does not vertically overlap the first and second semiconductor elements.

[0029] In addition, the electrode patterns are electrically floating with respect to the first and second terminals of the first and second semiconductor elements.

[0030] In addition, the lower surfaces of the first and second through electrodes are positioned lower than the upper surface of the connection member, and the electrode pattern is disposed on the upper surface of the connection member to overlap the first and second through electrodes in the horizontal direction.

[0031] In addition, the first and second connecting electrodes are each provided in plurality, and the plurality of first and second connecting electrodes are spaced apart from each other with dummy regions sandwiched between them on the connecting member, and the electrode pattern is disposed in the dummy regions of the connecting member.

[0032] The horizontal width of the dummy region satisfies the range of 160 μm to 310 μm.

[0033] Furthermore, among the plurality of first terminals, the first terminal arranged closest to the edge of one surface of the first semiconductor element is spaced apart from the edge of one surface of the first semiconductor element by a distance of 40 μm to 80 μm, and among the plurality of second terminals, the second terminal arranged closest to the edge of one surface of the second semiconductor element is spaced apart from the edge of one surface of the second semiconductor element by a distance of 40 μm to 80 μm.

[0034] The first semiconductor element and the second semiconductor element include sides that are horizontally opposed to each other, and the horizontal distance between the opposed sides satisfies the range of 80 μm to 150 μm.

[0035] Furthermore, the horizontal distance between the first terminals and second terminals arranged closest to each other among the plurality of first terminals and the plurality of second terminals satisfies the range of 160 μm to 310 μm.

[0036] The semiconductor package further includes a third semiconductor element disposed on the circuit board and vertically overlapping at least a portion of the connecting member, and the electrode pattern includes a first dummy electrode pattern vertically overlapping the separation area between the first and second semiconductor elements, and a second dummy electrode pattern disposed in an area vertically overlapping the separation area between the first or second semiconductor element and the third semiconductor element. [Effects of the Invention]

[0037] The semiconductor package according to the embodiment may include an insulating layer and a connecting member embedded in the insulating layer. The connecting member may include first and second connecting electrodes. The semiconductor package may also include a first electrode portion and a second electrode portion disposed in the insulating layer. The first electrode portion may vertically overlap the first connecting electrode of the connecting member. The second electrode portion may vertically overlap the second connecting electrode of the connecting member. The electrode portion may further include a third electrode portion disposed between the first and second electrode portions or between the first and second connecting electrodes. The third electrode portion may be electrically floating with respect to the connecting member and may be in physical contact with the connecting member. The third electrode portion may be disposed in a region of the upper surface of the connecting member where the connecting electrode is not disposed. The third electrode portion may improve adhesion between the insulating layer and the connecting member.

[0038] As a result, the embodiment can increase the adhesion between the insulating layer and the connecting member, thereby solving the problem of the connecting member peeling off from the insulating layer.

[0039] In addition, the embodiment may improve the rigidity of the connecting member and / or the semiconductor package by using the third electrode portion, thereby improving the mechanical reliability of the semiconductor package. As a result, the embodiment may solve the problem of the connecting member and / or the semiconductor package being significantly warped in a specific direction. As a result, the embodiment may enable the semiconductor package to operate stably. Furthermore, the embodiment may enable the electronic product and / or server to which the semiconductor package is applied to operate smoothly.

[0040] In addition, the surface roughness of the third electrode portion may be greater than the surface roughness of the connecting electrode provided on the connecting member. Thus, in this embodiment, the connecting electrode has a surface roughness smaller than the surface roughness of the third electrode portion, thereby minimizing signal transmission loss, which increases in proportion to the surface roughness, and thereby improving the signal transmission characteristics of the semiconductor package. In addition, in this embodiment, the surface roughness of the dummy electrode may be increased, thereby further improving adhesion between the insulating layer and the connecting member without affecting the signal transmission characteristics.

[0041] Meanwhile, in one embodiment, the dummy electrode may include only a dummy electrode pattern disposed on the connecting member. In another embodiment, the dummy electrode may include, in addition to the dummy electrode pattern, a dummy through electrode that penetrates from the upper surface of the first insulating layer to a partial region. In yet another embodiment, the third electrode portion may include, in addition to the dummy electrode pattern, a dummy through electrode and a dummy protruding electrode. When the third electrode portion includes the dummy through electrode and the dummy protruding electrode, the adhesion between the connecting member and the insulating layer and the rigidity of the semiconductor package can be further improved. [Brief explanation of the drawings]

[0042] [Figure 1a] FIG. 1a is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 1b] FIG. 1b is a cross-sectional view showing a semiconductor package according to the second embodiment. [Figure 1c] FIG. 1c is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 1e] FIG. 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the circuit board according to the first embodiment. [Figure 3] FIG. 3 is a plan view of the circuit board of FIG. 2 as seen from above. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor package including the circuit board of FIG. [Figure 5] FIG. 5 is an enlarged view of a region of FIG. [Figure 6] 6 is a plan view of the connecting member embedded in the circuit board of FIG. 2 as viewed from above. [Figure 7] FIG. 7 is a plan view including dummy electrodes arranged on the connecting member according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing the surface roughness of the connecting electrode and the dummy electrode of FIG. [Figure 9] FIG. 9 is a plan view including a dummy electrode disposed on a connecting member according to the second embodiment. [Figure 10] FIG. 10 is a plan view including a dummy electrode disposed on a connecting member according to the third embodiment. [Figure 11] FIG. 11 is a plan view including a dummy electrode arranged on a connecting member according to the fourth embodiment. [Figure 12] FIG. 12 is a diagram showing a detailed layer structure of a connecting member according to an embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a detailed layer structure of the protruding electrodes included in the circuit board of FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a circuit board according to the second embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing a circuit board according to the third embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a circuit board according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0043] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, identical or similar components will be designated by the same reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "unit" used in the following description are used interchangeably to facilitate the preparation of the specification and do not have any distinguishing meaning or function. Furthermore, in describing the embodiments disclosed herein, if a detailed description of related known technology is deemed to interfere with the gist of the embodiments disclosed herein, such a detailed description will be omitted. Furthermore, the accompanying drawings are provided to facilitate understanding of the embodiments disclosed herein, and the technical concepts disclosed herein should not be construed as limiting the scope of the present invention, but should be understood to include all modifications, equivalents, and alternatives within the scope of the present invention.

[0044] Although terms including ordinal numbers such as first, second, etc. are used to describe various components, the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0045] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the component may be directly "coupled" or "connected" to the other component, and that there may be other components between them. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components between them.

[0046] The singular expression includes the plural expression unless the context clearly dictates otherwise.

[0047] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof stated in the specification, but is understood not to preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0048] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0049] <Electronic Devices> Before describing the embodiments, a brief description will be given of an electronic device to which the semiconductor package of the embodiments is applied. The electronic device includes a main board (not shown). The main board is physically and / or electrically connected to various components. For example, the main board is connected to the semiconductor package of the embodiments. Various semiconductor elements are mounted in the semiconductor package.

[0050] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) semiconductor chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chipset including a specific combination of the above.

[0051] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and other memory chips.

[0052] On the other hand, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited to these.

[0053] Furthermore, the electronic device may be a smartphone, a PDA (personal digital assistant), a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device is not limited to these, and may of course be any other electronic device that processes data.

[0054] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0055] And, in one embodiment, the circuit board may be the first circuit board described below.

[0056] Alternatively, in another embodiment, the circuit board may be the second circuit board described below.

[0057] FIG. 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, FIG. 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, and FIG. 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0058] Referring to FIG. 1 a, the semiconductor package of the first embodiment may include a first circuit board 1100 , a second circuit board 1200 and a semiconductor device 1300 .

[0059] The first circuit board 1100 may refer to a package circuit board.

[0060] For example, the first circuit board 1100 may provide a space to which at least one external circuit board is coupled. The external circuit board may refer to the second circuit board 1200 coupled on the first circuit board 1100. Alternatively, the external circuit board may refer to a main board included in an electronic device coupled to the lower part of the first circuit board 1100.

[0061] Although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor element is mounted.

[0062] The first circuit board 1100 can include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

[0063] A second circuit board 1200 is disposed on the first circuit board 1100 .

[0064] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is mounted. The second circuit board 1200 is connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320, and electrically connect the first and second semiconductor devices 1310 and 1320 to the first circuit board 1100. That is, the second circuit board 1200 may function as a horizontal connection between multiple semiconductor devices and a vertical connection between the semiconductor devices and a package substrate.

[0065] 1a illustrates two semiconductor elements 1310 and 1320 disposed on the second circuit board 1200, but is not limited thereto. For example, one semiconductor element may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor elements may be disposed on the second circuit board 1200.

[0066] The second circuit board 1200 is disposed between at least one semiconductor device 1300 and the first circuit board 1100 .

[0067] In one embodiment, the second circuit board 1200 may be an active interposer that functions as a semiconductor device. When the second circuit board 1200 functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first circuit board 1100 and may function as multiple logic chips. Having the function of a logic chip may mean having the functions of both active and passive devices. Unlike passive devices, active devices do not have linear current-voltage characteristics, whereas an active interposer may have the function of an active device. Furthermore, the active interposer may function as a logic chip and also transmit signals between the second logic chip disposed thereon and the first circuit board 1100.

[0068] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may function as a signal relay between the semiconductor device 1300 and the first circuit board 1100 and may function as a passive element such as a resistor, capacitor, or inductor. For example, the number of terminals on the semiconductor device 1300 is gradually increasing due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 1300 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first circuit board 1100 is connected to the main board of an electronic device. Therefore, in order to ensure that the electrodes provided on the first circuit board 1100 have the width and spacing required to be connected to the semiconductor device 1300 and the main board, respectively, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complex. Therefore, in the first embodiment, the second circuit board 1200 can be disposed on the first circuit board 1100 and the semiconductor device 1300. The second circuit board 1200 can include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 1300.

[0069] The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0070] On the other hand, the semiconductor package of the first embodiment can include a connecting portion.

[0071] For example, the semiconductor package may include a first connection portion 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 may couple the first circuit board 1100 to the second circuit board 1200 and electrically connect them together.

[0072] For example, the semiconductor package may include a second connection portion 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection portion 1420 may couple the semiconductor device 1300 onto the second circuit board 1200 and electrically connect them together.

[0073] The semiconductor package may include a third connection portion 1430 disposed on the lower surface of the first circuit board 1100. The third connection portion 1430 may couple the first circuit board 1100 to the main board and electrically connect them together.

[0074] In this case, the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 can electrically connect the multiple components using at least one bonding method of wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as the electrically connected part, not the solder or wire.

[0075] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The direct inter-metal bonding method may refer to directly bonding multiple components by applying heat and pressure between the multiple components to cause recrystallization without using a material such as solder, wire, or conductive adhesive. The direct inter-metal bonding method may refer to a bonding method using the second connecting portion 1420. In this case, the second connecting portion 1420 may refer to a metal layer formed between the multiple components by recrystallization.

[0076] Specifically, the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 may be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 by applying heat and pressure to the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430.

[0077] In this case, in at least one of the first circuit board 1100 and the second circuit board 1200, the electrodes on which the first connection part 1410, the second connection part 1420, and the third connection part 1430 are disposed may be provided with a protrusion that protrudes outward away from the insulating layer of the circuit board. The protrusion may protrude outward from the first circuit board 1100 or the second circuit board 1200.

[0078] The protrusion may be a bump, a post, or a pillar. Preferably, the protrusion may refer to an electrode of the second circuit board 1200 on which a second connection portion 1420 for coupling with the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, short circuits may occur between the second connection portions 1420, which are respectively connected to the terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in an embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion 1420. Accordingly, in an embodiment, a protrusion may be included in the electrode of the second circuit board 1200 on which the second connection portion 1420 is disposed to ensure consistency, diffusion strength, and a diffusion prevention force that prevents an intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the circuit board.

[0079] The semiconductor package may also include a connecting member 1210. The connecting member may be referred to as a bridge circuit board. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may function to electrically connect a plurality of semiconductor devices horizontally to each other. Exemplarily, since a semiconductor device generally requires a large area, the connecting member 1210 may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width of the circuit pattern, etc., a buffering function for the circuit pattern for electrical connection is required. The buffering function may mean that the redistribution layer has an intermediate size between the width of the circuit pattern of the semiconductor package and the width of the circuit pattern of the semiconductor device, and the buffering function may be included.

[0080] In one embodiment, the connecting member 1210 may be an inorganic bridge. For example, the inorganic bridge may include a silicon bridge. That is, the connecting member 1210 may include a silicon circuit substrate and a redistribution layer disposed on the silicon circuit substrate.

[0081] In another embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 may include an organic circuit board that includes an organic material instead of a silicon circuit board. The connecting member 1210 may be embedded within the second circuit board 1200.

[0082] For this purpose, the second circuit board 1200 may include a cavity, and the connecting member 1210 may be disposed in the cavity of the second circuit board 1200. The connecting member 1210 may horizontally connect between multiple semiconductor elements disposed on the second circuit board 1200.

[0083] 1b, the semiconductor package of the second embodiment may include a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the second embodiment may have a structure in which the first circuit board 1100 is omitted compared to the semiconductor package of the first embodiment.

[0084] That is, the second circuit board 1200 of the second embodiment can function as an interposer and also as a package circuit board.

[0085] The first connection portion 1410 disposed on the bottom surface of the second circuit board 1200 can couple the second circuit board 1200 to a main board of an electronic device.

[0086] Referring to FIG. 1c, the semiconductor package of the third embodiment may include a first circuit board 1100 and a semiconductor device 1300.

[0087] In this case, the semiconductor package of the third embodiment may have a structure in which the second circuit board 1200 is omitted compared to the semiconductor package of the first embodiment.

[0088] That is, the first circuit board 1100 of the third embodiment can function as a package circuit board and also as a connection between the semiconductor devices 1300 and the main board. To this end, the first circuit board 1100 can include a connecting member 1110 for connecting between the plurality of semiconductor devices. The connecting member 1110 can be an inorganic bridge or an organic bridge for connecting between the plurality of semiconductor devices.

[0089] Referring to FIG. 1d, the semiconductor package of the fourth embodiment may further include a third semiconductor element 1330 compared to the semiconductor package of the third embodiment.

[0090] For this purpose, a fourth connection portion 1440 is disposed on the lower surface of the first circuit board 1100.

[0091] The third semiconductor element 1330 is disposed on the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0092] In this case, the third semiconductor device 1330 may have a structure in which it is disposed on the lower surface of the second circuit board 1200 in the semiconductor package of FIG. 1b.

[0093] 1e, the semiconductor package of the sixth embodiment may include a first circuit board 1100. First and second semiconductor devices 1310 and 1320 are disposed on the first circuit board 1100. To this end, a first connection part 1410 is disposed between the first circuit board 1100 and the first and second semiconductor devices 1310 and 1320.

[0094] A connecting member 1110 may be embedded in the first circuit board 1110. The connecting member 1110 may connect the first and second semiconductor elements 1310 and 1320 horizontally.

[0095] The first circuit board 1100 may also include a conductive coupling part 1450. The conductive coupling part 1450 may further protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive coupling part 1450 may be referred to as a bump or alternatively as a post. The conductive coupling part 1450 may be disposed in a protruding structure on an electrode disposed on the top side of the first circuit board 1100.

[0096] The third semiconductor element 1330 is disposed on the conductive coupling part 1450. At this time, the third semiconductor element 1330 is connected to the first circuit board 1100 via the conductive coupling part 1450. In addition, a second connection part 1420 is disposed between the first and second semiconductor elements 1310 and 1320 and the third semiconductor element 1330.

[0097] Thus, the third semiconductor element 1330 is electrically connected to the first and second semiconductor elements 1310 and 1320 via the second connection part 1420 .

[0098] That is, the third semiconductor device 1330 is connected to the first circuit board 1100 through the conductive coupling part 1450 , and is also connected to the first and second semiconductor devices 1310 and 1320 through the second connection part 1420 .

[0099] At this time, the third semiconductor element 1330 is supplied with a power signal and / or power through the conductive coupling part 1450. In addition, the third semiconductor element 1330 can exchange communication signals with the first and second semiconductor elements 1310 and 1320 through the second connection part 1420.

[0100] The semiconductor package of the fifth embodiment supplies a power signal and / or power to the third semiconductor element 1330 via the conductive coupling portion 1450, thereby enabling the provision of sufficient power for driving the third semiconductor element 1330 and smooth control of the power supply operation.

[0101] As a result, the embodiment may improve the driving characteristics of the third semiconductor device 1330. That is, the embodiment may solve the problem of insufficient power provided to the third semiconductor device 1330. Furthermore, the embodiment may provide at least one of the power signal, power, and communication signal of the third semiconductor device 1330 via different paths via the conductive coupling part 1450 and the second connection part 1420. As a result, the embodiment may solve the problem of loss of the communication signal due to the power signal. For example, the embodiment may minimize mutual interference between the power signal and the communication signal.

[0102] Meanwhile, in the fifth embodiment, the third semiconductor device 1330 may be disposed on the first circuit board 1100 in a package-on-package (POP) structure, in which a plurality of package circuit boards are stacked. For example, the third semiconductor device 1330 may be a memory package including a memory chip. The memory package is coupled to the conductive coupling part 1450. In this case, the memory package may not be connected to the first and second semiconductor devices 1310 and 1320.

[0103] The circuit board of the embodiment will be described below. The circuit board described below may be either the first circuit board 1100 or the second circuit board 1200 of the semiconductor package.

[0104] 2 is a cross-sectional view showing a circuit board according to a first embodiment, FIG. 3 is a plan view of the circuit board of FIG. 2 seen from above, FIG. 4 is a cross-sectional view of a semiconductor package including the circuit board of FIG. 2, FIG. 5 is an enlarged view of an area of ​​FIG. 4, FIG. 6 is a plan view of a connecting member embedded in the circuit board of FIG. 2 seen from above, FIG. 7 is a plan view including dummy electrodes arranged on the connecting member according to the first embodiment, FIG. 8 is a cross-sectional view showing the surface roughness of the connecting electrodes and dummy electrodes of FIG. 7, and FIG. 9 is a cross-sectional view of a dummy electrode arranged on the connecting member according to a second embodiment. 10 is a plan view including a dummy electrode arranged on a connecting member according to a third embodiment, FIG. 11 is a plan view including a dummy electrode arranged on a connecting member according to a fourth embodiment, FIG. 12 is a drawing showing a detailed layer structure of a connecting member according to one embodiment, FIG. 13 is a cross-sectional view showing a detailed layer structure of a protruding electrode included in the circuit board of FIG. 2, FIG. 14 is a cross-sectional view showing a circuit board according to a second embodiment, FIG. 15 is a cross-sectional view showing a circuit board according to a third embodiment, and FIG. 16 is a cross-sectional view showing a circuit board according to a fourth embodiment.

[0105] Hereinafter, the semiconductor package according to the embodiment will be specifically described with reference to FIGS.

[0106] 2, the circuit board according to the first embodiment may include an insulating part 110, an electrode part, and a connecting member 200. The insulating part 110 may include an insulating layer 111, a first protective layer 112, and a second protective layer 113.

[0107] The insulating layer 111 may have a layer structure of at least one layer. Preferably, the insulating layer 111 may have a build-up structure in which multiple layers are stacked in the vertical direction. The insulating layer 111 may have a multiple-layer structure. The layer structure may be divided by the electrode portion. For example, the electrode portion may include a wiring electrode EP1 and a through electrode EP2. The wiring electrode EP1 and the through electrode EP2 may have different widths. The layer structure may be divided by the difference in width between the wiring electrode EP1 and the through electrode EP2. The wiring electrode EP1 may have a width larger than that of the through electrode EP2. Thus, the wiring electrode EP1 and the through electrode EP2 can be divided by the electrode portion. The wiring electrode EP1 may refer to a pad and / or trace of the electrode portion. The through electrode EP2 may refer to a via electrode connected to a connecting electrode. The through electrode EP2 may be disposed between multiple wiring electrodes EP1 disposed on different layers. With the above-described layer structure, the circuit board of the embodiment can efficiently electrically connect at least one semiconductor device and / or a second circuit board to a main board.

[0108] Furthermore, when the multiple layers of the insulating layer 111 contain the same insulating material, the interfaces between the multiple layers may not be distinguishable. In this case, the stacked structure can be distinguished by the wiring electrodes EP1 and the through electrodes EP2 of the electrode portion.

[0109] The insulating layer 111 may be rigid or flexible. For example, the insulating layer 111 may include glass or plastic. For example, the insulating layer 111 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer 111 may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), etc. For example, the insulating layer 111 may include sapphire. For example, the first insulating layer 111 may include an optically isotropic film. For example, the insulating layer 111 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 111 may be made of a material containing an inorganic filler and an insulating resin, and may have a structure in which inorganic filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0110] The insulating layer 111 may have a structure in which a plurality of different insulating materials are stacked, and an exemplary arrangement structure will be described in more detail below.

[0111] In one embodiment, the insulating layer 111 may include a first insulating layer corresponding to a core layer including a reinforcing member. Here, the core layer may refer to an insulating layer including a reinforcing member and having a vertical thickness exceeding 30 μm. The insulating layer may also include an upper build-up insulating layer disposed on the core layer and a lower build-up insulating layer disposed below the core layer. In one embodiment, the upper build-up insulating layer and / or the lower build-up insulating layer may not include a reinforcing member. In this case, the circuit board may be a core board. The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

[0112] The term "reinforcing member" may refer to glass fiber material extending horizontally in the insulating layer and may have a different meaning from inorganic fillers spaced apart from each other. That is, the reinforcing member of the core layer may have a different length or width in the horizontal direction from the fillers of the upper and / or lower build-up insulating layers. Furthermore, the reinforcing member of the core layer may have a structure extending long in one direction, while the fillers of the upper and / or lower build-up insulating layers are distributed and arranged with any size, so the reinforcing member of the core layer and the fillers of the upper and / or lower build-up insulating layers may be distinguished from each other. For example, the glass fiber may extend to have a surface length greater than the width of the core layer. Here, "having a surface length greater than the width of the core layer" may mean that the glass fiber may be arranged in a curved shape in the horizontal direction. Furthermore, even if the upper and / or lower build-up insulating layers contain fillers, the effect of preventing problems such as warping is less significant than that of the glass fiber of the core layer, so the reinforcing member will be described separately from the fillers of the upper and / or lower build-up insulating layers.

[0113] In another embodiment, the insulating layer 111 may be a coreless circuit board that does not include a core layer. For example, the insulating layer 111 may include an organic material that does not include a reinforcing member, which allows for excellent processability, slimming of the circuit board, and miniaturization of the electrode portion of the circuit board. For example, the insulating layer 111 may be made of ABF (Ajinomoto Build-up Film), a product sold by Ajinomoto Co., Inc., and may include FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. For example, the insulating layer 111 may have a structure in which multiple build-up insulating layers made of ABF are stacked vertically. If the insulating layer 111 is made only of ABF without a reinforcing member, the rigidity of the circuit board may be reduced. Therefore, the insulating layer 111 may be made of ABF (Ajinomoto Build-up Film), and at least one of the multiple build-up insulating layers that make up the insulating layer 111 of the circuit board may include a reinforcing member. For example, the insulating layer 111 may include a first insulating layer made of a first ABF including a resin and a filler. Alternatively, the insulating layer 111 may include a second insulating layer made of a second ABF including a resin, a filler, and a reinforcing member. In this case, the reinforcing member included in the second ABF may include, but is not limited to, a GCP (Glass Core Primer) material.

[0114] The insulating layer 111 layer that does not include a reinforcing member may have a thickness in the range of 10 μm to 40 μm. Preferably, the insulating layer 111 layer that does not include a reinforcing member may satisfy a thickness in the range of 15 μm to 35 μm. More preferably, the insulating layer 111 layer that does not include a reinforcing member may satisfy a thickness in the range of 18 μm to 32 μm. If the insulating layer 111 layer that does not include a reinforcing member has a thickness of less than 10 μm, the rigidity of the circuit board may be reduced. If the insulating layer 111 layer that does not include a reinforcing member has a thickness of less than 10 μm, the electrodes of the circuit board may not be reliably protected, which may reduce electrical reliability. If the insulating layer 111 layer that does not include a reinforcing member has a thickness of more than 40 μm, the overall thickness of the circuit board increases, which in turn increases the thickness of the semiconductor package. If the insulating layer 111 layer that does not include a reinforcing member has a thickness of more than 40 μm, it becomes difficult to miniaturize the electrodes of the circuit board.

[0115] The thickness may correspond to the distance in the vertical direction of the circuit board between wiring electrodes EP1 arranged on different layers. That is, the thickness may refer to the length from the top surface to the bottom surface of the circuit board or from the bottom surface to the top surface, and may refer to the vertical length of the circuit board. Here, the top surface may refer to the highest position in the vertical direction of each component, and the bottom surface may refer to the lowest position in the vertical direction of each component. These positions may be referred to as opposite positions.

[0116] The insulating portion 110 may include a first protective layer 112 and a second protective layer 113. The first protective layer 112 and the second protective layer 113 of the circuit board may be resist layers. For example, the first protective layer 112 of the circuit board may be a first resist layer arranged on the uppermost side of the circuit board. Also, the second protective layer 113 of the circuit board may be a second resist layer arranged on the lowermost side of the circuit board.

[0117] In one embodiment, the first protective layer 112 and the second protective layer 113 of the circuit board may contain the same insulating material as the insulating layer 111. In this case, it may be difficult to distinguish the interfaces between the insulating layer 111 and the first protective layer 112 and second protective layer 113. In this case, the interfaces between the insulating layer 111, the first protective layer 112, and the second protective layer 113 may be distinguished using the wiring electrodes EP1 and the through electrodes EP2 of the electrode parts arranged on the insulating layer 111, the first protective layer 112, and the second protective layer 113.

[0118] The circuit board may include an electrode portion, which may include a first electrode portion 130, a second electrode portion 135, a third electrode portion 140, and a fourth electrode portion 150 disposed within the insulating layer 100.

[0119] The first electrode portion 130 , the second electrode portion 135 , and the third electrode portion 140 may refer to electrodes that are vertically stacked with the connecting member 200 within the insulating layer 100 .

[0120] The fourth electrode unit 150 may refer to an electrode that does not vertically overlap the connecting member 200 within the insulating layer 100 .

[0121] The first electrode unit 130 and the second electrode unit 135 may refer to electrodes electrically connected to the connection member 200 .

[0122] For example, the connecting member 200 may include a connecting electrode 210. The connecting electrode 210 may include a first connecting electrode 210A and a second connecting electrode 210B spaced apart from the first connecting electrode 210A.

[0123] The first electrode unit 130 may be an electrode that vertically overlaps the first connecting electrode 210A of the connecting member 200. For example, the first electrode unit 130 may be an electrode that is electrically connected to the first connecting electrode 210A of the connecting member 200.

[0124] The second electrode portion 135 may be an electrode that vertically overlaps the second linking electrode 210B of the linking member 200. For example, the second electrode 210B may be an electrode that is electrically connected to the second linking electrode 210B of the linking member 200.

[0125] In one embodiment, the third electrode unit 140 may be disposed between the first electrode unit 130 and the second electrode unit 135. In another embodiment, the third electrode unit 140 may be disposed between the first connecting electrode 210A and the second connecting electrode 210B of the connecting member 200.

[0126] The third electrode unit 140 is electrically floating with respect to the connecting member 200. For example, the third electrode unit 140 may be a dummy electrode. For example, the third electrode unit 140 may be a dummy electrode disposed between the connecting member 200 and the semiconductor element and electrically floating with respect to the connecting member 200 and the semiconductor element. The third electrode unit 140 is disposed between the first electrode unit 130 and the second electrode unit 135 or between the first connecting electrode 210A and the second connecting electrode 210B of the connecting member 200, and may function to improve adhesion between the insulating layer 100 and the connecting member 200. Here, in one embodiment, the third electrode unit 140 may be a component of an electrode unit of a circuit board that is separate from the connecting electrode of the connecting member 200. In this case, in the embodiment, during the manufacturing process of the circuit board, after performing a process of embedding the connecting member 200 in the insulating layer 111, a process of forming the third electrode unit 140 may be performed so that the third electrode unit 140 overlaps horizontally with the first and second linking electrodes 210A, 210B of the connecting member 200 and is electrically floating with respect to the first and second linking electrodes 210A, 210B. In another embodiment, the third electrode unit 140 may be a component of the connecting member 200. In this case, the connecting member 200 may be provided with the third electrode unit 140 disposed between the first and second linking electrodes 210A, 210B.

[0127] The connecting member 200 may function to horizontally connect terminals of multiple semiconductor devices. That is, the multiple semiconductor devices may be arranged horizontally spaced apart on a circuit board. The multiple semiconductor devices may exchange signals with each other. Therefore, the terminals provided on the multiple semiconductor devices may include terminals that are connected to each other. As the number of functions provided by the multiple semiconductor devices increases, the number of terminals provided on the multiple semiconductor devices is also increasing. Accordingly, the number of terminals to be connected to each other among the terminals provided on the multiple semiconductor devices is also increasing. Furthermore, as semiconductor packages and / or semiconductor devices become smaller, the size of the terminals provided on the multiple semiconductor devices is becoming smaller. Therefore, it is difficult to connect the terminals of the multiple semiconductor devices within a limited space using only electrodes provided on a circuit board. Furthermore, the size of the electrodes provided on the circuit board is significantly different from the size of the terminals provided on the semiconductor devices. Therefore, if these terminals are connected only using electrodes provided on the circuit board, signal transmission loss may increase, resulting in degraded signal transmission characteristics. A connecting member 200 is embedded in the circuit board, and the connecting member 200 can electrically connect between terminals of the plurality of semiconductor elements that should be connected to each other.

[0128] The connecting member 200 includes a connecting electrode 210, which may include first and second connecting electrodes 210A and 210B. The first connecting electrode 210A and the second connecting electrode 210B may be spaced apart horizontally on the connecting member 200, taking into consideration the positions of terminals provided on the first and second semiconductor elements disposed on the circuit board and the horizontal separation distance between the first and second semiconductor elements. The top surface of the connecting member 200 may include a first region where the first connecting electrode 210A is disposed, a second region where the second connecting electrode 210B is disposed, and a third region between the first and second regions where no connecting electrode is disposed.

[0129] The connecting electrodes 210 included in the connecting member 200 may have a high density, and therefore may have a relatively low surface roughness. Therefore, since the connecting electrodes 210 of the connecting member 200 have a relatively low surface roughness and the connecting electrodes 210 are not disposed in certain regions on the upper surface of the connecting member 200, the adhesion between the insulating layer 100 and the connecting member 200 may be reduced. This may result in the connecting member 200 peeling off from the insulating layer 100. Furthermore, various thermal stresses may occur during the manufacturing process and / or in the usage environment of the semiconductor package, which may cause cracks in the connecting member 200, peeling off of the connecting member 200, or significant warping of the connecting member 200 in a specific direction.

[0130] Therefore, the embodiment may include a third electrode unit 140 disposed on the connecting member 200. The third electrode unit 140 may be an electrode formed in a separate process from the connecting electrode 210 of the connecting member 200. However, the present invention is not limited thereto, and the third electrode unit 140 may be formed together with the connecting electrode 210 in the process of manufacturing the connecting member 200. In this case, the process of embedding the connecting member 200 in the insulating layer 100 may be performed in a state in which the third electrode unit 140 is disposed on the connecting member 200 together with the connecting electrode 210.

[0131] The third electrode portion 140 is electrically floating with respect to the connecting member 200 and is physically coupled to the connecting member 200 .

[0132] As a result, the third electrode unit 140 may function to improve adhesion between the connecting member 200 and the insulating layer 100. As a result, the embodiment may use the third electrode unit 140 to solve a mechanical reliability problem, such as peeling of the connecting member 200 from the insulating layer 100. Furthermore, the third electrode unit 140 may function to increase the rigidity of the connecting member 200 and / or the circuit board. For example, the third electrode unit 140 is coupled to the connecting member 200, thereby preventing the connecting member 200 and / or the circuit board from warping significantly in a particular direction. As a result, the embodiment may enable stable operation of multiple semiconductor devices arranged on the circuit board. Furthermore, the embodiment may enable smooth operation of electronic products and / or servers to which the semiconductor package is applied.

[0133] Meanwhile, the fourth electrode unit 150 may not overlap the connecting member 200 vertically and may overlap the first electrode unit 130 and the second electrode unit 135 horizontally.

[0134] The fourth electrode unit 150 may be an electrode connected to a semiconductor element. For example, the fourth electrode unit 150 may be connected to the semiconductor elements connected to the first electrode unit 130 and the second electrode unit 135, respectively.

[0135] The electrode unit of the embodiment may include a protruding electrode. For example, the electrode unit may include a first protruding electrode 160A disposed on the first electrode unit 130. The electrode unit may also include a second protruding electrode 160B disposed on the second electrode unit 135. The electrode unit may also include a third protruding electrode 180 disposed on the fourth electrode unit 150.

[0136] The first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 can penetrate from the upper surface of the insulating layer 100 to a partial region.

[0137] In addition, the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may protrude above the upper surface of the insulating layer 100.

[0138] The first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 can improve the bonding between the semiconductor elements and the circuit board.

[0139] The first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may be referred to as bumps. The first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may also be referred to as posts. The first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may also be referred to as pillars. Preferably, the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may refer to electrodes on which conductive connection members for coupling with a semiconductor device are disposed. That is, as the pitch of terminals of a semiconductor device becomes finer, short circuits may occur between multiple conductive connection members respectively connected to multiple terminals of the semiconductor device by a conductive adhesive such as solder. Therefore, in this embodiment, thermal compression bonding may be performed to reduce the volume of the conductive connection members. Therefore, the embodiment may include a first protruding electrode 160A, a second protruding electrode 160B, and a third protruding electrode 180 to ensure the degree of matching, the diffusion force, and the diffusion prevention force that prevents the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protruding portion from diffusing into the circuit board.

[0140] 3 and 4, a first semiconductor element 310 and a second semiconductor element 320 are mounted on a circuit board. The first semiconductor element 310 may include a plurality of first terminals 315. The second semiconductor element 320 may include a plurality of second terminals 325.

[0141] The first semiconductor element 310 and the second semiconductor element 320 are electrically connected to the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 provided on the circuit board. To this end, a conductive adhesive member 300 may be provided between the first terminal 315 of the first semiconductor element 310 and the second terminal 325 of the second semiconductor element 320 and the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180.

[0142] Also, a molding member 330 may be provided on the circuit board. The molding member 330 is disposed on the circuit board, thereby molding the first semiconductor element 310 and the second semiconductor element 320.

[0143] The first protruding electrode 160A may refer to a bonding electrode electrically connected to the first terminal 315 of the first semiconductor device 310. The second protruding electrode 160B may refer to a bonding electrode electrically connected to the second terminal 325 of the second semiconductor device 320.

[0144] The first protruding electrode 160A and the second protruding electrode 160B may be spaced apart from each other in the horizontal direction. For example, the first protruding electrode 160A and the second protruding electrode 160B may be spaced apart by a predetermined horizontal distance based on the positions of the first terminal 315 of the first semiconductor element 310 and the second terminal 325 of the second semiconductor element 320 and the separation distance between the first semiconductor element 310 and the second semiconductor element 320.

[0145] Meanwhile, the third protruding electrodes 180 may include a first group of third protruding electrodes 180A and a second group of third protruding electrodes 180B. The first group of third protruding electrodes 180A may be arranged adjacent to the first protruding electrodes 160A. For example, the first group of third protruding electrodes 180A may be arranged on one side of the first protruding electrodes 160A. The first group of third protruding electrodes 180A may overlap the first semiconductor element 310 in the vertical direction. The first group of third protruding electrodes 180A is connected to the first terminal 315 of the first semiconductor element 310. The second group of third protruding electrodes 180B may be arranged adjacent to the second protruding electrodes 160B. For example, the second group of third protruding electrodes 180B may be arranged on the other side of the second protruding electrodes 160B. The second group of third protruding electrodes 180B may overlap the second semiconductor element 320 in the vertical direction. The second group of third protruding electrodes 180B is connected to the second terminal 325 of the second semiconductor element 320 .

[0146] The first protruding electrodes 160A and the second protruding electrodes 160B may each be provided in plural and spaced apart from each other in the horizontal direction, and the third protruding electrodes 180 may also be provided in plural and spaced apart from each other in the horizontal direction.

[0147] 5, a plurality of first terminals 315 may be provided on one surface of the first semiconductor device 310. The first terminals 315 may be spaced apart by a first distance W1 from an edge of the one surface of the first semiconductor device 310. For example, among the plurality of first terminals provided on the first semiconductor device 310, a first terminal disposed closest to the edge of the one surface of the first semiconductor device 310 may be spaced apart by the first distance W1 from the edge of the first semiconductor device 310.

[0148] A plurality of second terminals 325 may be provided on one surface of the second semiconductor element 320. The second terminals 325 may be spaced apart by a second distance W2 from an edge of the one surface of the second semiconductor element 320. For example, among the plurality of second terminals provided on the second semiconductor element 320, the second terminal arranged closest to the edge of the one surface of the second semiconductor element 320 may be spaced apart by the second distance W2 from the edge of the second semiconductor element 320.

[0149] In this case, the first distance W1 and the second distance W2 can each satisfy the range of 40 μm to 80 μm. Preferably, the first distance W1 and the second distance W2 can each satisfy the range of 45 μm to 75 μm. More preferably, the first distance W1 and the second distance W2 can each satisfy the range of 50 μm to 70 μm.

[0150] If the first distance W1 and the second distance W2 are each less than 40 μm, the mechanical and / or electrical reliability of the first terminal 315 and / or the second terminal 325 may be reduced. For example, if the first distance W1 and the second distance W2 are each less than 40 μm, the electrodes located closest to the edges may be subjected to an impact during a sawing process during the manufacturing process of the first semiconductor element 310 and / or the second semiconductor element 320. This impact may cause cracks or peeling of the electrodes. Furthermore, if the first distance W1 and the second distance W2 are each more than 80 μm, a dummy area where the first terminal and / or the second terminal is not located increases by a corresponding amount. Furthermore, if the dummy area increases, the size of the first semiconductor element 310 and / or the second semiconductor element 320 increases, which in turn increases the size of the semiconductor package, making it difficult to miniaturize electronic products, servers, etc.

[0151] The first semiconductor element 310 and the second semiconductor element 320 may be disposed on the circuit board separated by a third distance W3. The third distance W3 may be in the range of 80 μm to 150 μm. Preferably, the third distance W3 may be in the range of 85 μm to 140 μm. More preferably, the third distance W3 may be in the range of 90 μm to 120 μm.

[0152] If the third distance W3 is less than 80 μm, the separation distance between the first semiconductor element 310 and the second semiconductor element 320 becomes too small, which may reduce the processability of mounting the first semiconductor element 310 and the second semiconductor element 320 on a circuit board. For example, if the third distance W3 is less than 80 μm, the first semiconductor element 310 may come into contact with the second semiconductor element 320 during the process of mounting the second semiconductor element 320 after mounting the first semiconductor element 310, or there may not be enough space to mount the second semiconductor element 320, which may result in insufficient mounting of the first semiconductor element 310 and / or the second semiconductor element 320. Furthermore, if the third distance W3 is less than 80 μm, the separation distance becomes too small, which may result in a short circuit, where electrodes of the first terminal 315 of the first semiconductor element 310 and the second terminal 325 of the second semiconductor element 320 that should not be connected to each other are connected to each other.

[0153] Furthermore, if the third distance W3 exceeds 150 μm, the separation distance between the first semiconductor element 310 and the second semiconductor element 320 becomes excessively large, which increases the signal transmission distance between them. As the signal transmission distance increases, signal transmission loss also increases in proportion to the increase in signal transmission distance. This may result in a deterioration in communication characteristics. Furthermore, if the third distance W3 exceeds 150 μm, the size of the semiconductor package increases.

[0154] Therefore, the first terminal 315 and the second terminal 325, which are arranged closest to each other in the first semiconductor device 310 and the second semiconductor device 320, may be spaced apart by a fourth distance W4. The fourth distance W4 is determined by the sum of the first distance W1, the second distance W2, and the third distance W3.

[0155] For example, the fourth distance W4 may be in the range of 160 μm to 310 μm. If the fourth distance W4 is less than 160 μm or exceeds 310 μm, any one of the first distance W1, the second distance W2, and the third distance W3 may not be within the range, which may result in the above-described problems.

[0156] Referring to FIG. 6, the connecting member 200 may include a first connecting electrode 210A connected to the first terminal 315 of the first semiconductor element 310 and a second connecting electrode 210B connected to the second terminal 325 of the second semiconductor element 320.

[0157] The first connecting electrode 210A of the connecting member 200 may vertically overlap the first terminal 315 of the first semiconductor element 310. In addition, the second connecting electrode 210B of the connecting member 200 may vertically overlap the second terminal 325 of the second semiconductor element 320.

[0158] In this case, the electrodes of the first terminal 315 and the second terminal 325 that are arranged closest to each other may be spaced apart by a fourth distance W4.

[0159] Therefore, the first connecting electrode 210A and the second connecting electrode 210B provided on the connecting member 200 may also be spaced apart by the fourth distance W4. For example, the upper surface of the connecting member 200 may have an area where no connecting electrodes 210 are arranged, corresponding to the fourth distance W4.

[0160] 7, in this embodiment, a process of forming the third electrode unit 140 on the connecting member 200 may be performed in a state where the connecting member 200 is disposed on the insulating layer 111. The third electrode unit 140 may be provided in a region between the first connecting electrode 210A and the second connecting electrode 210B provided on the connecting member 200. The third electrode unit 140 may be in physical contact with the connecting member 200 and is electrically floating.

[0161] Meanwhile, the first connecting electrode 210A of the connecting member 200 may include a plurality of connecting electrodes, and the second connecting electrode 210B of the connecting member 200 may include a plurality of connecting electrodes.

[0162] In this case, the planar area of ​​the third electrode unit 140 may be larger than the planar area of ​​a single electrode of the first linking electrode 210A and the planar area of ​​a single electrode of the second linking electrode 210B. Preferably, a single third electrode unit 140 may be provided, and the planar area of ​​the third electrode unit 140 may be larger than the planar area of ​​a single electrode of the first linking electrode 210A and the planar area of ​​a single electrode of the second linking electrode 210B. For example, a plurality of third electrode units 140 may be provided, and in this case, the planar area of ​​a single electrode of the third electrode unit 140 may be larger than the planar area of ​​a single electrode of the first linking electrode 210A and the planar area of ​​a single electrode of the second linking electrode 210B.

[0163] Accordingly, in the embodiment, the planar area of ​​the single electrode of the third electrode unit 140 is larger than the planar area of ​​the single electrode of the first connecting electrode 210A and the planar area of ​​the single electrode of the second connecting electrode 210B, thereby further improving the adhesion between the connecting member 200 and the insulating layer 111 due to the third electrode unit 140, thereby solving the problem of the connecting member 200 peeling off from the insulating layer 100. Furthermore, the embodiment maximizes the effect of improving the rigidity of the connecting member 200 and / or the circuit board due to the third electrode unit 140, thereby solving the problem of the connecting member 200, the circuit board, and / or the semiconductor package warping significantly in a specific direction.

[0164] 8, the connecting electrode 210 of the connecting member 200 and the third electrode unit 140 may have different surface roughnesses. The connecting electrode 210 of the connecting member 200 may have a relatively small surface roughness value to minimize signal transmission loss due to the skin effect. In contrast, the third electrode unit 140 is a dummy electrode that is not an electrode through which a signal is transmitted. Therefore, the third electrode unit 140 may have a surface roughness value greater than that of the connecting electrode 210 of the connecting member 200.

[0165] As a result, the embodiment can relatively increase the surface roughness value of the third electrode portion 140, thereby further improving the adhesion between the insulating layer 100 and the third electrode portion 140, and ultimately further improving the adhesion between the connecting member 200 physically bonded to the third electrode portion 140 and the insulating layer 100.

[0166] 9, the planar shape of the third electrode unit 140 may have various shapes. For example, although the planar shape of the third electrode unit 140 in the previous embodiment is illustrated as being rectangular, the planar shape is not limited thereto. For example, the planar shape of the third electrode unit 140 may be circular or elliptical. The planar shape of the third electrode unit 140 may also be modified to be triangular, polygonal, or the like.

[0167] 10 , the third electrode unit 140 may include a plurality of dummy electrode patterns. For example, although the third electrode unit 140 in the previous embodiment is provided as a single electrode between the first connecting electrode 210A and the second connecting electrode 210B of the connecting member 200, this is not limiting. For example, the third electrode unit 140 may include a plurality of dummy electrode patterns spaced apart from each other in the region between the first connecting electrode 210A and the second connecting electrode 210B of the connecting member 200. In this case, if the third electrode unit 140 includes a plurality of dummy electrode patterns, the contact area between the insulating layer 100 and the third electrode unit 140 may be further increased, thereby further improving the adhesion between the insulating layer 110 and the connecting member 200.

[0168] Meanwhile, although the first semiconductor device 310 and the second semiconductor device 320 are illustrated as being disposed on a circuit board in the previous embodiment, the present invention is not limited thereto.

[0169] For example, the semiconductor package may include a first semiconductor device 310 and a second semiconductor device 320 spaced apart in a first horizontal direction, and may include a third semiconductor device spaced apart from the first semiconductor device 310 and the second semiconductor device 320 in a second horizontal direction different from the first horizontal direction.

[0170] As shown in FIG. 11, the connecting electrode 210 of the connecting member 200 may include a first connecting electrode 210A that vertically overlaps the terminal of the first semiconductor element 310, a second connecting electrode 210B that vertically overlaps the second semiconductor element 320, and a third connecting electrode 210C that vertically overlaps the third semiconductor element.

[0171] The third electrode unit 140 may also include a first dummy electrode 140A provided between the first linking electrode 210A and the second linking electrode 210B on the connecting member 200, and a second dummy electrode 140B provided between the first linking electrode 210A, the second linking electrode 210B, and the third linking electrode 210C.

[0172] The detailed layer structure of the connecting member 200 will be described as follows. The connecting member 200 may be an inorganic bridge. For example, the inorganic bridge may be a silicon bridge. Therefore, the connecting member 200 may include an insulating member containing a silicon material and a connecting electrode disposed on the insulating member. In another embodiment, the connecting member 200 may be an organic bridge. For example, the organic bridge may include an organic insulating layer. For example, the connecting member 200 may include multiple organic insulating layers.

[0173] Specifically, according to the embodiment of FIG. 12, the connecting member 200 may include a first insulating layer 201, a second insulating layer 202 and a third insulating layer 203.

[0174] The first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 may contain different insulating materials, but are not limited to this example. For example, the first insulating layer 201 may contain an organic material. The first insulating layer 201 may contain a different material from the second insulating layer 202, but is not limited to this example.

[0175] The first insulating layer 201 may have properties that enable the formation of the electrode layer 206 of the connecting member 200, which includes a fine electrode pattern. For example, the first insulating layer 201 may include an insulating material that is easy to process and has elasticity. For example, the first insulating layer 201 of the connecting member 200 may include polyimide (PI). Conventional connecting members have used inorganic bridges, such as silicon bridges. Silicon has a thermal expansion coefficient that is significantly different from that of the insulating layer 111, which can easily cause cracks to occur due to thermal stress. In another embodiment, the first insulating layer 201 of the connecting member 200 may include an organic material that has a thermal expansion coefficient similar to that of the insulating layer 111. As a result, the embodiment can minimize stress applied to the connecting member 200. Furthermore, the embodiment can solve problems such as cracks occurring in the connecting member 200 or peeling off of the connecting member 200 from the circuit board. As a result, the embodiment can improve the mechanical and electrical reliability of the semiconductor package.

[0176] Furthermore, in the embodiment, if the first insulating layer 201 of the connecting member 200 includes polyimide, the cost of the connecting member 200 can be reduced compared to a silicon bridge.

[0177] Furthermore, the connecting member 200 may be provided with via electrodes having a small width. The alignment between the via electrodes provided on different layers significantly affects the operational characteristics of the connecting member 200, the operational characteristics of the semiconductor package, and the operational characteristics of electronic products, servers, etc. to which the semiconductor package is applied. In this case, polyimide may have a transparent property. As a result, the embodiment can improve the alignment between the via electrodes arranged on different layers. As a result, the operational characteristics of the connecting member 200, the operational characteristics of the semiconductor package, and the operational characteristics of electronic products, servers, etc. to which the semiconductor package is applied can be further improved.

[0178] The first insulating layer 201 may refer to an insulating layer disposed inside the connecting member 200. The overall characteristics of the connecting member 200 are determined by the characteristics of the first insulating layer 201. The first insulating layer 201 may have a thermal expansion coefficient similar to that of the insulating layer of the circuit board and may also have elasticity. As a result, the first insulating layer 201 of the connecting member 200 may flow together with the circuit board when the circuit board is thermally deformed. As a result, the embodiment may solve the problem of cracks in the connecting member 200 that may occur due to thermal deformation of the circuit board.

[0179] In addition, in the embodiment, the first insulating layer 201 of the connecting member 200 includes polyimide (PI), which allows for easy adjustment of the thickness of the connecting member 200. As a result, the embodiment can minimize the difference between the depth of the cavity C, which is a space for accommodating the connecting member 200 formed on the circuit board, and the thickness of the connecting member 200. As a result, the embodiment can minimize the difference in height between the first electrode unit 130 and the fourth electrode unit 150 and / or the difference in height between the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180. As a result, the embodiment can stably bond a semiconductor device onto the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180.

[0180] The connecting member 200 may include a second insulating layer 202 disposed on the first insulating layer 201. The second insulating layer 202 may include, but is not limited to, a different insulating material from the first insulating layer 201. For example, the second insulating layer 202 may include polyimide, which is the same insulating material as the first insulating layer 201. For example, the first insulating layer 201 may include the same insulating material as the insulating material of the second insulating layer 202 described below, instead of polyimide.

[0181] The second insulating layer 202 may include a photosensitive material. For example, the second insulating layer 202 may include a PID. For example, the second insulating layer 202 may be a PID in which the photosensitive material is a resin layer and a filler is dispersed in the resin layer.

[0182] In another embodiment, the second insulating layer 202 may include the same insulating material as the insulating layer 111. For example, the second insulating layer 202 may include ABF, which is the same insulating material as the insulating layer 111. Alternatively, the second insulating layer 202 may be disposed on both sides of the first insulating layer 201.

[0183] The connecting member 200 may also include a third insulating layer 203 disposed on the second insulating layer 202. The third insulating layer 203 may be a protective layer. For example, the third insulating layer 203 may be a solder resist layer.

[0184] At this time, the side of the connection member 200 may have a step. For example, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 of the connection member 200 may have a step.

[0185] For example, the horizontal width of the first insulating layer 201 of the connecting member 200 may be different from the horizontal width of the second insulating layer 202 and the horizontal width of the third insulating layer 203. Preferably, the horizontal width of the first insulating layer 201 of the connecting member 200 may be greater than the horizontal width of the second insulating layer 202 and the horizontal width of the third insulating layer 203.

[0186] That is, among the insulating layers of the connecting member 200, the first insulating layer 201 may have the highest elasticity and / or rigidity compared to the second insulating layer 202 and the third insulating layer 203. Therefore, in this embodiment, the first insulating layer 201 of the connecting member 200 is configured to have the largest width, so that an impact applied to the connecting member 200 is absorbed by the first insulating layer 201, and thus, the impact is not transmitted to the second insulating layer 202 and / or the third insulating layer 203.

[0187] In addition, the horizontal width of the second insulating layer 202 of the connecting member 200 may be different from the horizontal width of the third insulating layer 203. The horizontal width of the second insulating layer 202 may be greater than the horizontal width of the third insulating layer 203. In this case, the third insulating layer 203 is a solder resist, and therefore may easily crack due to external impact. In addition, the manufacturing process of the connecting member 200 may include a sawing process. The sawing process includes a process of individually separating the connecting members. In this case, if an impact is applied to the third insulating layer 203 during the sawing process, cracks may occur in the third insulating layer 203. Therefore, in this embodiment, the width of the third insulating layer 203 is made smaller than the widths of the first insulating layer 201 and the second insulating layer 202, so that the third insulating layer 203 can be protected from impact.

[0188] Specifically, the horizontal distance from the side edge of the first insulating layer 201 to the side edge of the third insulating layer 203 of the connecting member 200 may be in the range of 50 μm to 70 μm. If the horizontal distance from the side edge of the first insulating layer 201 to the side edge of the third insulating layer 203 of the connecting member 200 is less than 50 μm, the third insulating layer 203 may be subjected to an impact during the sawing process, which may cause cracks in the third insulating layer 203. If the horizontal distance from the side edge of the first insulating layer 201 to the side edge of the third insulating layer 203 of the connecting member 200 exceeds 70 μm, the circuit layers included in the connecting member 200 may not be stably protected, or the area of ​​the connecting member 200 where no circuit layers are disposed may increase, resulting in a decrease in circuit integration density.

[0189] As a result, the side surfaces of the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 of the connecting member 200 may have steps. As a result, the steps on the side surfaces of the connecting member 200 may come into contact with the insulating layers of the circuit board, thereby increasing the contact area.

[0190] Meanwhile, the connecting member 200 may be provided with a circuit pattern 204. The circuit pattern 204 may include a connecting electrode 210 disposed on the top side of the connecting member 200.

[0191] In this case, the top surface of the connecting electrode 210 of the connecting member 200 may be located lower than the top surface of the third insulating layer 203 of the connecting member 200. For example, the connecting electrode 210 of the connecting member 200 may include only a pad portion. When the connecting electrode 210 of the connecting member 200 includes only a pad portion, the third electrode unit 140 does not horizontally overlap the connecting electrode 210. In another embodiment, the connecting electrode 210 of the connecting member 200 may further include a bump portion disposed on the pad portion. As a result, the connecting electrode 210 of the connecting member 200 may protrude from the top surface of the connecting member 200. In this case, the third electrode unit 140 is provided on the connecting member 200. For example, the third electrode unit 140 may be provided in a region of the top surface of the third insulating layer 203 of the connecting member 200 that does not vertically overlap the connecting electrode 210. In addition, when the connecting electrode 210 of the connecting member 200 includes a bump portion, the third electrode portion 140 may overlap the connecting electrode 210 of the connecting member 200 horizontally.

[0192] Referring to FIG. 12, each of the first protruding electrode 160A, the second protruding electrode 160B, and the second and third protruding electrodes 180 may include a plurality of metal layers.

[0193] For example, each of the first protruding electrode 160A and the second protruding electrode 160B may include a first metal layer 160-1 disposed on the first electrode unit 130 and the second electrode unit 135, respectively. Also, each of the first protruding electrode 160A and the second protruding electrode 160B may include a second metal layer 160-2 disposed on the first metal layer 160-1. In this case, the first metal layer 160-1 and the second metal layer 160-2 may include different metal materials.

[0194] Preferably, the first metal layer 160-1 may include nickel. The second metal layer 160-2 may include copper. The first metal layer 160-1 may improve the bonding strength between the second metal layer 160-2 and the first electrode unit 130 or the second electrode unit 135. For example, if the second metal layer 160-2 is disposed directly on the first electrode unit 130 or the second electrode unit 135, oxidation of the first electrode unit 130 or the second electrode unit 135 may occur, which may weaken the bonding strength between them. Therefore, the first metal layer 160-1 may function to prevent oxidation of the first electrode unit 130 or the second electrode unit 135 and improve the bonding strength between them. In addition, the first metal layer 160-1 may prevent the first protruding electrode 160A and the second protruding electrode 160B from peeling off from the first electrode unit 130 or the second electrode unit 135 due to contraction and expansion of the first protective layer 112 caused by thermal stress.

[0195] Specifically, when the first metal layer 160-1 contains nickel, it can improve adhesion between the first electrode unit 130 or the second electrode unit 135 and the second metal layer 160-2. Furthermore, when electrical connection is later made with the first electrode unit 130 or the second electrode unit 135 using a material such as solder, the solder diffuses into the first electrode unit 130 or the second electrode unit 135 to form an inter-metallic compound, which can cause problems with poor mechanical and electrical reliability. In particular, when the second metal layer 160-2 is made of copper, the problem of the formation of an inter-metallic compound is exacerbated. However, when nickel is disposed, it is possible to prevent the diffusion of solder and the formation of an inter-metallic compound, thereby improving the electrical and mechanical reliability of the semiconductor package.

[0196] In this case, the first electrode unit 130 and the second electrode unit 135 may include a clevis 130C. For example, the top surfaces of the first electrode unit 130 and the second electrode unit 135 may include a clevis 130C that vertically overlaps the first protruding electrode 160A and the second protruding electrode 160B and is recessed toward the bottom surface of the first electrode unit 130 or the second electrode unit 135. The clevis 130C is filled with the first metal layer 160-1. This increases the contact area between the first electrode unit 130 or the second electrode unit 135 and the first protruding electrode 160A or the second protruding electrode 160B, thereby further improving the bonding force.

[0197] The third protruding electrode 180 may also include a first metal layer 180-1 and a second metal layer 180-2. The first metal layer 180-1 of the third protruding electrode 180 is disposed on the fourth electrode unit 150. The second metal layer 180-2 of the third protruding electrode 180 is disposed on the first metal layer 180-1. A clevis 150C may be formed on the upper surface of the fourth electrode unit 150, and the first metal layer 180-1 of the third protruding electrode 180 may be disposed to fill the clevis 150C of the fourth electrode unit 150.

[0198] 14, the third electrode unit 140 may include a dummy through electrode 145 that horizontally overlaps the first electrode unit 130 and the second electrode unit 135. The dummy through electrode 145 can improve the rigidity of the circuit board and prevent the circuit board from warping significantly in a specific direction.

[0199] 15, the circuit board may further include a dummy protruding electrode 170 disposed on the dummy through electrode 145. The dummy protruding electrode 170 is provided between the first protruding electrode 160A and the second protruding electrode 160B. The dummy protruding electrode 170 improves the rigidity of the circuit board and transfers heat generated from the connecting member 200 to the end of the circuit board. The dummy protruding electrode 170 may also function as an identification unit that identifies the bonding positions of multiple semiconductor elements on the circuit board. For example, in the embodiment, the bonding positions of the first and second semiconductor elements can be easily identified based on the dummy protruding electrode 170 having a relatively large size, thereby enabling the first and second semiconductor elements to be stably bonded to the circuit board at accurate positions.

[0200] The dummy protruding electrode 170 is provided between the first protruding electrode 160A and the second protruding electrode 160B. For example, the dummy protruding electrode 170 may be provided in a region corresponding to the separation distance between the first semiconductor element 310 and the second semiconductor element 320. Therefore, at least a portion of the dummy protruding electrode 170 does not vertically overlap the first semiconductor element 310 and the second semiconductor element 320.

[0201] Also, the dummy protruding electrode 170 may be provided in a single piece or in a plurality of pieces.

[0202] However, the planar area of ​​a single electrode of the dummy protruding electrode 170 may be larger than the planar area of ​​each of the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180. Accordingly, in the embodiment, the planar area of ​​the dummy protruding electrode 170 is maximized, thereby improving the rigidity of the semiconductor package. Furthermore, the dummy protruding electrode 170 may contact the molding member 330. The molding member 330 has a stronger adhesive strength with a metal material than with an insulating material. Therefore, in the embodiment, the planar area of ​​the dummy protruding electrode 170 is maximized to increase the contact area with the molding member 330, thereby further improving the adhesive strength between them. Furthermore, in the embodiment, the planar area of ​​the dummy protruding electrode 170 is maximized to further improve the heat dissipation characteristics of the heat generated from the first semiconductor element 310, the second semiconductor element 320, and the connecting member 200.

[0203] 16, the connecting member 200 is disposed in a cavity formed in the first insulating part 110. At this time, the cavity is formed in at least a portion of the layer of the first insulating part 110.

[0204] The circuit board 100 may further include an adhesive member 190 disposed on the bottom surface of the cavity. The adhesive member 190 may allow the connecting member 200 to be firmly fixed to the cavity. The adhesive member 190 may have a width different from that of the connecting member 200. Furthermore, the adhesive member 190 may have a width different from that of the cavity.

[0205] For example, the adhesive member 190 may be wider than the connecting member 200. This can prevent the connecting member 200 from peeling off due to various shocks applied in the operating environment of the semiconductor package. For example, the adhesive member 190 may have a width greater than that of the connecting member 200 in order to improve the bonding strength with the connecting member 200.

[0206] Furthermore, the adhesive member 190 may have a width smaller than the width of the cavity. For example, the adhesive member 190 may not contact the sidewall of the cavity. Therefore, the embodiment may prevent the adhesive member 190 from contacting the inner wall of the cavity due to expansion of the adhesive member 190 caused by damage. As a result, the embodiment may minimize stress caused by the expansion of the adhesive member 190.

[0207] The semiconductor package according to the embodiment may include an insulating layer and a connecting member embedded in the insulating layer. The connecting member may include first and second connecting electrodes. The semiconductor package may also include a first electrode portion and a second electrode portion disposed in the insulating layer. The first electrode portion may vertically overlap the first connecting electrode of the connecting member. The second electrode portion may vertically overlap the second connecting electrode of the connecting member. The electrode portion may further include a third electrode portion disposed between the first and second electrode portions or between the first and second connecting electrodes. The third electrode portion may be electrically floating with respect to the connecting member and may be in physical contact with the connecting member. The third electrode portion may be disposed in a region of the upper surface of the connecting member where no connecting electrode is provided. The third electrode portion may improve adhesion between the insulating layer and the connecting member.

[0208] As a result, the embodiment can increase the adhesive strength between the insulating layer and the connecting member, thereby solving the problem of the connecting member peeling off from the insulating layer.

[0209] In addition, the embodiment may improve the rigidity of the connecting member and / or the semiconductor package by using the third electrode portion, thereby improving the mechanical reliability of the semiconductor package. As a result, the embodiment may solve the problem of the connecting member and / or the semiconductor package being significantly warped in a specific direction. As a result, the embodiment may enable the semiconductor package to operate stably. Furthermore, the embodiment may enable the electronic product and / or server to which the semiconductor package is applied to operate smoothly.

[0210] In addition, the surface roughness of the third electrode portion may be greater than the surface roughness of the connecting electrode provided on the connecting member. Thus, in this embodiment, the connecting electrode has a surface roughness value smaller than the surface roughness of the third electrode portion, thereby minimizing signal transmission loss, which increases in proportion to the surface roughness value, and thereby improving the signal transmission characteristics of the semiconductor package. In addition, in this embodiment, the surface roughness of the dummy electrode is increased, thereby further improving the adhesion between the insulating layer and the connecting member without affecting the signal transmission characteristics.

[0211] Meanwhile, in one embodiment, the dummy electrode may include only a dummy electrode pattern disposed on the connecting member. In another embodiment, the dummy electrode may include a dummy through electrode that penetrates from the upper surface of the first insulating layer to a partial region, together with the dummy electrode pattern. In yet another embodiment, the third electrode unit may include a dummy through electrode and a dummy protruding electrode, together with the dummy electrode pattern. When the third electrode unit includes a dummy through electrode and a dummy protruding electrode, the adhesion between the connecting member and the insulating layer can be further improved, and the rigidity of the semiconductor package can be further improved.

[0212] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stabilize functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, or electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, a circuit board having the above-described inventive features can maintain stable functions in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0213] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0214] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

[0215] The above description has focused on the embodiments, but these are merely illustrative and do not limit the present invention. A person skilled in the art to which the present invention pertains may make various modifications and applications not exemplified above within the scope of the essential characteristics of the present embodiments. For example, each component specifically presented in the embodiments may be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the present invention as defined by the appended claims.

Claims

1. an insulating layer; a connecting member embedded in the insulating layer; an electrode portion embedded in the insulating layer and overlapping the connecting member in a vertical direction; the connecting member includes an electrode pattern disposed on the connecting member; The electrode pattern is electrically floating relative to the electrode portion.

2. the connecting member includes first and second connecting electrodes spaced apart from the electrode pattern in a horizontal direction; the electrode portion includes a first electrode portion vertically overlapping the first connecting electrode and a second electrode portion vertically overlapping the second connecting electrode; The circuit board of claim 1 , wherein the electrode pattern is electrically floating with respect to the first electrode portion, the second electrode portion, the first connecting electrode, and the second connecting electrode.

3. The insulating layer includes a first insulating layer having a cavity; a second insulating layer disposed on the first insulating layer and filling at least a portion of the cavity; the connecting member is disposed within the cavity; the first electrode portion includes a first through electrode that penetrates at least a partial region of the second insulating layer and overlaps the first linking electrode in a vertical direction, and a second through electrode that penetrates at least a partial region of the second insulating layer and overlaps the first linking electrode in a vertical direction, The circuit board according to claim 2 , wherein the electrode pattern does not overlap the first and second through electrodes in a vertical direction.

4. the first electrode portion includes a first wiring electrode disposed on the first through-hole electrode and a second wiring electrode disposed on the second through-hole electrode; The circuit board according to claim 3 , wherein the electrode pattern does not overlap the first and second wiring electrodes in the vertical direction.

5. The circuit board according to claim 2 , wherein the electrode pattern is disposed on the same plane as the first and second connecting electrodes on the upper surface of the connecting member.

6. The circuit board according to claim 2 , wherein the surface roughness of the electrode pattern is greater than the surface roughness of at least one of the first and second connecting electrodes.

7. The first and second connecting electrodes are each provided in plural numbers, The circuit board according to claim 7 , wherein a plane area of ​​the single electrode pattern is larger than a plane area of ​​each of the first and second plurality of connecting electrodes.

8. The first and second connecting electrodes have the same edge shape on their top surfaces, The circuit board according to claim 2 , wherein the shape of the edge of the upper surface of the electrode pattern is different from the shape of the edges of the first and second connecting electrodes.

9. The circuit board according to claim 4, further comprising a dummy through electrode arranged on the electrode pattern and overlapping horizontally with at least a portion of the first and second through electrodes, and a dummy wiring electrode arranged on the dummy through electrode and overlapping horizontally with the first and second wiring electrodes.

10. a protective layer disposed on the insulating layer; a first protruding electrode that penetrates at least a partial region of the protective layer and overlaps the first wiring electrode in a vertical direction; a second protruding electrode that penetrates at least a partial region of the protective layer and overlaps the second wiring electrode in a vertical direction; The circuit board according to claim 9 , further comprising a dummy protruding electrode that penetrates at least a partial region of the protective layer and overlaps the dummy wiring electrode in a vertical direction.

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