Array substrate and display device

Abstract

The present invention provides an array substrate and a display device. The array substrate includes a base substrate having a main surface, a transistor positioned on the main surface of the base substrate, the transistor including an active layer and a first electrode connected to the active layer, a first insulating layer positioned between the base substrate and the active layer, a second insulating layer positioned between the active layer and the first electrode, a pixel electrode connected to the first electrode, and a common electrode insulated from the pixel electrode, the pixel electrode and the common electrode being configured to form an electric field, and the first electrode contacting a surface of the active layer opposite the base substrate and a side surface of the active layer. The array substrate and display device contribute to increasing the contact area between the first electrode and the side surface of the active layer and contribute to increasing the capacitance of a storage capacitor formed by the first electrode and another electrode, thereby solving the problem of a reduction in the capacitance of the storage capacitor due to a reduction in pixel area, resulting in an unstable pixel voltage.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] For all purposes, this application claims priority to Chinese patent application no. 202211387912.X, filed on November 8, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] At least one embodiment of the present disclosure relates to an array substrate and a display device. [Background technology]

[0003] Currently, the widely used display devices include thin film transistor-liquid crystal displays (TFT-LCDs), and more and more displays are being developed with high resolution and high image quality to provide users with a better user experience. Summary of the Invention [Means for solving the problem]

[0004] At least one embodiment of the present disclosure relates to an array substrate and a display device that increases the capacitance of a storage capacitor by setting a compensation capacitor.

[0005] At least one embodiment of the present disclosure provides an array substrate including a base substrate having a main surface, a transistor positioned on the main surface of the base substrate, the transistor including an active layer and a first electrode connected to the active layer, a first insulating layer positioned between the base substrate and the active layer, a second insulating layer positioned between the active layer and the first electrode, a pixel electrode connected to the first electrode, and a common electrode insulated from the pixel electrode and from each other, wherein the pixel electrode and the common electrode are configured to form an electric field, and the first electrode contacts a surface of the active layer opposite the base substrate and a side surface of the active layer.

[0006] For example, the array substrate further includes a first via hole, the first electrode is connected to the active layer through the first via hole, and the first via hole includes a first through hole penetrating the second insulating layer and a first groove in the first insulating layer.

[0007] For example, the maximum size of the first trench in a plane parallel to the main surface is smaller than the minimum size of the first via hole in a plane parallel to the main surface.

[0008] For example, the maximum size of the first groove in a plane perpendicular to the main surface is smaller than the maximum size of the first through hole in a plane perpendicular to the main surface.

[0009] For example, the pixel electrode extends into the first via hole and contacts the first electrode at the first via hole.

[0010] For example, the pixel electrode and the first electrode are conformal in the first via hole, and the maximum size of the contact portion between the pixel electrode and the first electrode in a direction perpendicular to the main surface is greater than or equal to the maximum size of the first via hole in a direction perpendicular to the main surface.

[0011] For example, the array substrate further includes a third insulating layer located on the first electrode, and the common electrode is located on the third insulating layer.

[0012] For example, the pixel electrode and the common electrode are conformal in the first via hole.

[0013] For example, the first insulating layer includes a first insulating portion and a second insulating portion, the first groove is located in the first insulating portion, and the thickness of the first insulating portion is greater than the thickness of the second insulating portion.

[0014] For example, the thickness of the first insulating portion is more than twice the thickness of the second insulating portion.

[0015] For example, the array substrate further includes a light-shielding layer positioned between the active layer and the base substrate, wherein the orthogonal projection of the active layer on the base substrate is within the orthogonal projection of the light-shielding layer on the base substrate, and the first electrode and the light-shielding layer form a compensation capacitor.

[0016] For example, the light-shielding layer is disposed in a floating state or is electrically connected to the common electrode.

[0017] For example, the thickness of the first insulating layer is 50 nm to 300 nm.

[0018] For example, the pixel electrode and the common electrode form a main storage capacitor, and the capacitance ratio between the compensation capacitor and the main storage capacitor is 0.2 or more.

[0019] For example, the capacitance ratio between the compensation capacitor and the main storage capacitor is 0.8 or less.

[0020] For example, the capacitance ratio between the compensation capacitor and the main storage capacitor is greater than or equal to 0.25 and less than or equal to 0.6.

[0021] For example, at least one of the first electrode and the pixel electrode together with the common electrode forms a first storage capacitor, and the first storage capacitor includes a first capacitor in a plane parallel to the main surface and a second capacitor in a direction perpendicular to the main surface.

[0022] For example, the pixel electrode and the common electrode form a main storage capacitor, and the capacitance ratio between the second capacitor and the main storage capacitor is 0.02 or more.

[0023] For example, the capacitance ratio between the second capacitor and the main storage capacitor is 0.2 or less.

[0024] For example, the capacitance ratio between the second capacitor and the main storage capacitor is greater than or equal to 0.06 and less than or equal to 0.08.

[0025] For example, the array substrate further includes a third insulating layer positioned on the first electrode and a fourth insulating layer, the common electrode is positioned on the third insulating layer, and the fourth insulating layer is positioned between the pixel electrode and the common electrode.

[0026] For example, the array substrate further includes a second via hole, the pixel electrode is connected to the first electrode through the second via hole, the second via hole includes a second via hole that penetrates the third insulating layer or penetrates the fourth insulating layer and the third insulating layer, and a second groove provided in the second insulating layer, and the pixel electrode contacts the surface of the first electrode opposite the base substrate and a side of the first electrode.

[0027] For example, the maximum size of the second groove in a plane parallel to the main surface is smaller than the minimum size of the second through hole in a plane parallel to the main surface.

[0028] For example, the maximum size of the second groove in the direction perpendicular to the main surface is smaller than the maximum size of the second through hole in the direction perpendicular to the main surface.

[0029] For example, the common electrode is located between the first electrode and the pixel electrode, the common electrode and the first electrode form a first storage capacitor, and the common electrode and the pixel electrode form another first storage capacitor.

[0030] For example, the array substrate further includes a third insulating layer positioned on the first electrode, a fourth insulating layer positioned between the pixel electrode and the common electrode, and a second via hole, wherein the pixel electrode is connected to the first electrode through the second via hole, and the second via hole includes a second through hole that penetrates the third insulating layer or penetrates the third insulating layer and the fourth insulating layer, and a second groove positioned in the fourth insulating layer.

[0031] For example, the pixel electrode contacts the surface of the first electrode opposite to the base substrate and a side surface of the first electrode.

[0032] For example, the array substrate further includes a first via hole, the first electrode is connected to the active layer through the first via hole, the pixel electrode contacts the surface of the first electrode opposite the base substrate, and the orthogonal projection of the first via hole on the base substrate overlaps with the orthogonal projection of the second via hole on the base substrate.

[0033] For example, the first via hole includes a first through hole penetrating the second insulating layer and a first trench in the first insulating layer.

[0034] For example, the array substrate further includes a data line, the transistor further includes a second electrode, the second electrode is connected to the active layer, the data line is connected to the second electrode, and the orthogonal projection of the pixel electrode on the base substrate overlaps with the orthogonal projection of the data line on the base substrate.

[0035] For example, the width of the overlapping portion between the pixel electrode and the data line is less than 3 microns.

[0036] For example, the array substrate further includes a data line, the transistor further includes a second electrode, the second electrode is connected to the active layer, the data line is connected to the second electrode, one of the pixel electrode and the common electrode that is away from the base substrate has a slit, and the orthogonal projection of the common electrode on the base substrate overlaps with the orthogonal projection of the data line on the base substrate.

[0037] For example, the width of the overlapping portion between the common electrode and the data line is less than 3 microns.

[0038] For example, the angle between the data line and the slit is 1 to 20 degrees.

[0039] For example, the shape of the first via hole includes at least one of a circle, a rectangle, or a rectangle with truncated corners.

[0040] For example, the array substrate further includes a first protective structure, the orthogonal projection of the first protective structure on the base substrate overlaps with the orthogonal projection of the first via hole on the base substrate, a portion of the first protective structure fills a first recess in the first via hole of the array substrate, and a portion of the first protective structure protrudes from the first recess.

[0041] For example, the array substrate further includes a second protective structure, the orthogonal projection of the second protective structure on the base substrate overlaps with the orthogonal projection of the second via hole on the base substrate, a portion of the second protective structure fills a second recess in the second via hole of the array substrate, and a portion of the second protective structure protrudes from the second recess.

[0042] For example, the array substrate further includes a data line, the transistor further includes a second electrode, the second electrode is connected to the active layer, the data line is connected to the second electrode, the pixel electrode is located between the common electrode and the base substrate, and the common electrode has a slit.

[0043] For example, on the same side of the slit, the distance between the pixel electrode and the slit includes at least two unequal distances.

[0044] For example, the array substrate further includes an electrode lead connected to the common electrode, and an orthogonal projection of the electrode lead on the base substrate overlaps with an orthogonal projection of the data line on the base substrate.

[0045] For example, the data line includes a plurality of inclined portions, a bent portion is provided between adjacent inclined portions, the extending direction of the inclined portions is the same as the extending direction of the slit, the first via hole has a corner cut portion, and the extending direction of the edge of the corner cut portion of the first via hole is the same as the extending direction of the bent portion.

[0046] For example, the distance between the edge of the corner cut portion of the first via hole and the bent portion is not less than 1 micron and not more than 5 microns.

[0047] For example, the pixel electrode has a first portion and a second portion with different extension directions, the extension direction of the first portion is the same as the extension direction of the slit, and the edge of the first portion is parallel to the edge of the slit and parallel to the edge of the data line.

[0048] For example, the edge of the second portion is not parallel to the edge of the slit, and the edge of the second portion is parallel to the data line.

[0049] For example, the minimum distance between the edge of the second portion and the edge of the slit is less than 1 micron.

[0050] An embodiment of the present disclosure provides an array substrate including a base substrate having a main surface, a transistor positioned on the main surface of the base substrate, the transistor including an active layer and a first electrode connected to the active layer, a first insulating layer positioned between the base substrate and the active layer, a second insulating layer positioned between the active layer and the first electrode, and a pixel electrode connected to the first electrode, wherein the pixel electrode contacts a surface of the first electrode opposite the base substrate and a side surface of the first electrode.

[0051] An embodiment of the present disclosure further provides a display device including any of the above array substrates.

[0052] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure. [Brief explanation of the drawings]

[0053] [Figure 1A] FIG. 1A is a cross-sectional view of a display panel. [Figure 1B] FIG. 1B is a plan view of the display panel. [Figure 2] FIG. 2 is a plan view of an array substrate provided according to one embodiment of the present disclosure. [Figure 3] FIG. 3 is a cross-sectional view taken along the line A1-A2 in FIG. [Figure 4A] FIG. 4A is a single layer view of the array substrate shown in FIG. [Figure 4B] FIG. 4B is a single layer view of the array substrate shown in FIG. [Figure 4C] FIG. 4C is a single layer view of the array substrate shown in FIG. [Figure 4D] FIG. 4D is a single layer view of the array substrate shown in FIG. [Figure 4E] FIG. 4E is a single layer view of the array substrate shown in FIG. [Figure 4F] FIG. 4F is a single layer view of the array substrate shown in FIG. [Figure 4G] FIG. 4G is a single layer view of the array substrate shown in FIG. [Figure 4H] FIG. 4H is a single layer view of the array substrate shown in FIG. [Figure 5] FIG. 5 is a schematic diagram of a first capacitor of a first storage capacitor formed by a common electrode and a first electrode on an array substrate provided by an embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic diagram of a second capacitor of the first storage capacitor formed by the common electrode and the first electrode on the array substrate provided by one embodiment of the present disclosure. [Figure 7]FIG. 7 is a schematic diagram of an equivalent circuit of an array substrate provided by one embodiment of the present disclosure. [Figure 8] FIG. 8 is a simplified schematic diagram of an array substrate provided according to one embodiment of the present disclosure. [Figure 9] FIG. 9 is a schematic diagram of a common electrode of an array substrate provided by one embodiment of the present disclosure. [Figure 10] FIG. 10 is a cross-sectional view of an array substrate provided according to one embodiment of the present disclosure. [Figure 11] FIG. 11 is an equivalent circuit diagram of the array substrate shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view of an array substrate provided according to one embodiment of the present disclosure. [Figure 13] FIG. 13 is an equivalent circuit diagram of the array substrate shown in FIG. [Figure 14] FIG. 14 is a plan view of an array substrate provided according to one embodiment of the present disclosure. [Figure 15] FIG. 15 is a cross-sectional view taken along the line A3-A4 in FIG. [Figure 16A] FIG. 16A is a plan view of an array substrate provided according to one embodiment of the present disclosure. [Figure 16B] FIG. 16B is a plan view of an array substrate provided according to one embodiment of the present disclosure. [Figure 17] FIG. 17 is a cross-sectional view taken along line A5-A6 in FIG. 16A. [Figure 18] FIG. 18 is a plan view of an array substrate provided according to one embodiment of the present disclosure. [Figure 19] FIG. 19 is a plan view of an array substrate provided according to one embodiment of the present disclosure. [Figure 20] FIG. 20 is a cross-sectional view of an array substrate provided according to one embodiment of the present disclosure. [Figure 21] FIG. 21 is a plan view of an array substrate provided according to one embodiment of the present disclosure. [Figure 22] FIG. 22 is a cross-sectional view of an array substrate provided according to one embodiment of the present disclosure. [Figure 23] FIG. 23 is a cross-sectional view of an array substrate provided according to one embodiment of the present disclosure. [Figure 24] FIG. 24 is a cross-sectional view of an array substrate provided according to one embodiment of the present disclosure. [Figure 25] FIG. 25 is a cross-sectional view of another array substrate provided according to an embodiment of the present disclosure. [Figure 26] FIG. 26 is a plan view of an array substrate provided according to an embodiment of the present disclosure. [Figure 27] FIG. 27 is a plan view of an array substrate provided according to an embodiment of the present disclosure. [Figure 28] FIG. 28 is a cross-sectional view of an array substrate provided according to an embodiment of the present disclosure. [Figure 29] FIG. 29 is a cross-sectional view of an array substrate provided according to an embodiment of the present disclosure. [Figure 30] FIG. 30 is a cross-sectional view of an array substrate provided according to an embodiment of the present disclosure. [Figure 31] FIG. 31 is a cross-sectional view of an array substrate provided according to an embodiment of the present disclosure. [Figure 32] FIG. 32 is a cross-sectional view of an array substrate provided according to an embodiment of the present disclosure. [Figure 33] FIG. 33 is a plan view of an array substrate provided by an embodiment of the present disclosure. [Figure 34] FIG. 34 is a plan view of an array substrate provided by an embodiment of the present disclosure. [Figure 35] FIG. 35 is a flowchart of the fabrication of an array substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0054] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure.

[0055] Unless otherwise specified, technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. As used in this disclosure, the words "first," "second," and similar words do not denote any order, quantity, or importance, but are used only to distinguish between different components. Similarly, similar words such as "comprise" or "contain" mean that the element or thing before the word includes the elements or things listed thereafter and their equivalents, without excluding other elements or things. Words such as "connect" or "coupled" are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. Terms such as "top," "bottom," "left," and "right" are used to express only relative positions, and if the absolute position of the described object changes, the relative positions may also change accordingly.

[0056] 1A is a cross-sectional view of a display panel. As shown in FIG. 1A, the display panel includes an array substrate 100 and an opposing substrate 200, which are arranged facing each other and bonded together by a frame sealant 400 to form a liquid crystal cell LC. The liquid crystal cell LC includes a liquid crystal layer 300 including a plurality of liquid crystal molecules 301. Pixel electrodes and a common electrode may be disposed within the array substrate 100 to form a planar electric field that rotates the liquid crystal molecules 301.

[0057] FIG. 1B is a plan view of a display panel. FIG. 1B shows that the display panel includes a plurality of sub-pixels SP. The method of configuring the sub-pixels SP is not limited to FIG. 1B and can be determined as needed. FIG. 1B shows a display region R1 and a peripheral region R2. A plurality of sub-pixels SP are positioned in the display region R1. In FIG. 1B, the peripheral region R2 surrounds the display region R1 as an example. The peripheral region R2 is positioned on at least one side of the display region R1.

[0058] In the drawings of the embodiments of the present disclosure, the X direction, Y direction, and Z direction are three different directions. The X direction and Y direction are parallel to the main surface of the array substrate 100 or the counter substrate 200, and the Z direction is perpendicular to the X direction and the Y direction. For example, the Z direction is the thickness direction of the array substrate 100 or the counter substrate 200. The Z direction may be the direction in which the array substrate 100 faces the counter substrate 200. For example, the X direction and the Y direction intersect. In the embodiments of the present disclosure, an example will be described in which the Y direction is perpendicular to the X direction.

[0059] As the scanning frequency of displays continues to increase, in display panels, the pixel electrodes and common electrodes overlap to form storage capacitors, and the non-overlapping portions of the pixel electrodes and common electrodes form electric fields that control the rotation of liquid crystal molecules, controlling the display panel to display colorful images and videos.

[0060] As pixel density (Pixels Per Inch, PPI) continues to increase, the pixel area continues to decrease. In high-resolution displays with high PPI, the reduction in pixel area reduces the capacitance of the storage capacitor, resulting in unstable pixel voltages and affecting display quality.

[0061] The embodiments of the present disclosure provide an array substrate and a display device including the array substrate, which solves the problem of unstable pixel voltage affecting display quality, and arranges a compensation capacitor to increase the capacitance of a storage capacitor, thereby improving display quality.

[0062] FIG. 2 is a plan view of an array substrate provided by an embodiment of the present disclosure. FIG. 3 is a cross-sectional view taken along line A1-A2 in FIG. 2. FIGS. 4A to 4H are single-layer views of the array substrate shown in FIG. 2. FIG. 5 is a schematic diagram of a first capacitor of a first storage capacitor formed by a common electrode and a first electrode in an array substrate provided by an embodiment of the present disclosure. FIG. 6 is a schematic diagram of a second capacitor of a first storage capacitor formed by a common electrode and a first electrode in an array substrate provided by an embodiment of the present disclosure. FIG. 7 is a schematic diagram of an equivalent circuit of an array substrate provided by an embodiment of the present disclosure. FIG. 8 is a simplified schematic diagram of an array substrate provided by an embodiment of the present disclosure.

[0063] As shown in Figures 2 and 3, an embodiment of the present disclosure provides an array substrate including a base substrate 101, a transistor TR, a first insulating layer BF, a second insulating layer 122, and a pixel electrode PE. As shown in Figure 3, the base substrate 101 includes a main surface MS. As shown in Figures 2 and 3, the transistor TR is located on the main surface MS of the base substrate 101 and includes an active layer AT and a first electrode E1 connected to the active layer AT. As shown in Figure 3, the first insulating layer BF is located between the base substrate 101 and the active layer AT, and the second insulating layer 122 is located between the active layer AT and the first electrode E1, and the pixel electrode PE is connected to the first electrode E1.

[0064] 3, the first electrode E1 contacts a surface S1 of the active layer AT opposite the base substrate 101 and a side surface S2 of the active layer AT. As shown in FIG. 3, the second insulating layer 122 includes, but is not limited to, a gate insulating layer GI and an interlayer insulating layer ILD. For example, the transistor TR includes, but is not limited to, a thin film transistor (TFT).

[0065] In the array substrate provided by the embodiments of the present disclosure, the first electrode E1 can be in contact with the surface S1 of the active layer AT opposite the base substrate 101 and with the side surface S2 of the active layer AT, contributing to increasing the contact area between the first electrode E1 and the side surface of the active layer AT, increasing the size of the first electrode E1 in the Z direction, contributing to increasing the Z-direction capacitance of a storage capacitor (compensation capacitor) formed by the first electrode E1 and another electrode such as the common electrode CE, and contributing to forming a storage capacitor (compensation capacitor) for compensating the storage capacitor by the first electrode E1 and another electrode such as the light-shielding layer LSL. By designing the compensation capacitor, the array substrate provided by the embodiments of the present disclosure can solve the problem of unstable pixel voltage caused by a reduction in the storage capacitor due to a reduction in pixel area in a high-resolution display with a high PPI.

[0066] 2 and 3, the array substrate further includes a common electrode CE, where the common electrode CE and the pixel electrode PE are insulated from each other and configured to form an electric field between the pixel electrode PE and the common electrode CE, for example, the pixel electrode PE and the common electrode CE can form a planar electric field.

[0067] For example, the common electrode CE may be formed of a transparent conductive material, and the pixel electrode PE may be formed of a transparent conductive material. For example, the transparent conductive material may include, but is not limited to, indium tin oxide (ITO). In the embodiments of the present disclosure, the pixel electrode PE and the common electrode CE are both formed of indium tin oxide.

[0068] 3, 5, and 6, the first electrode E1 and the common electrode CE form a first storage capacitor Cst1, which includes a first capacitor C1 in a plane parallel to the main surface MS and a second capacitor C2 (compensation capacitor) in a direction perpendicular to the main surface MS, where the second capacitor C2 may be called a sidewall capacitor. The first capacitor C1 is a planar capacitor.

[0069] In the embodiments of the present disclosure, a planar capacitor means that each of the two plates of the capacitor is parallel to the major surface MS of the base substrate 101. A sidewall capacitor means that each of the two plates of the capacitor is not parallel to the major surface MS of the base substrate 101.

[0070] As shown in Figures 3, 5 to 7, the compensation capacitor includes a second capacitor C2 in the first storage capacitor Cst1 and a storage capacitor C0, i.e., the compensation capacitor includes the second capacitor C2 and the storage capacitor C0. As shown in Figure 7, the common electrode CE is configured to input a common voltage Vcom. The storage capacitor C0 may also be referred to as a compensation capacitor C0.

[0071] Since the pixel area of ​​a high PPI pixel is small, the area of ​​the storage capacitor of the pixel electrode and the common electrode is greatly reduced (for example, the area is reduced to 1 / 4 or 1 / 8 of the original), and therefore, the capacitance of the storage capacitor can be compensated by arranging a compensation capacitor (the second capacitor C2 and the storage capacitor C0).

[0072] For example, as shown in FIGS. 2, 3, and 4A, the array substrate further includes a light-shielding layer LSL located between the active layer AT and the base substrate 101. The orthogonal projection of the active layer AT on the base substrate 101 is within the orthogonal projection of the light-shielding layer LSL on the base substrate 101, and a storage capacitor C0 (compensation capacitor) is formed by the first electrode E1 and the light-shielding layer LSL, and the storage capacitor C0 may be referred to as a second storage capacitor Cst2. For example, as shown in FIGS. 2 and 3, the orthogonal projection of the first electrode E1 on the base substrate 101 overlaps with the orthogonal projection of the light-shielding layer LSL on the base substrate 101. For example, as shown in FIGS. 2 and 3, the orthogonal projection of the first electrode E1 on the base substrate 101 is within the orthogonal projection of the light-shielding layer LSL on the base substrate 101. For example, the light-shielding layer LSL is disposed in a floating state or is electrically connected to a common electrode. The light-shielding layer LSL functions as a light shield to protect the active layer AT, and also forms a storage capacitor C0 with the first electrode E1 so as to function as a compensation capacitor.

[0073] For example, as shown in Figure 3, to further increase the storage capacitor C0 to enhance the capacitance compensation effect, the thickness of the first insulating portion BF1 is made greater than the thickness of the second insulating portion BF2. For example, the thickness of the first insulating portion BF1 is made 1.5 to 3.5 times the thickness of the second insulating portion BF2. For example, the thickness of the first insulating portion BF1 is made more than twice the thickness of the second insulating portion BF2.

[0074] In the embodiments of the present disclosure, the thickness of an element refers to the size of the element in the Z direction.

[0075] For example, in the array substrate provided by the embodiment of the present disclosure, the first insulating layer BF is over-etched to increase the depth of the first via hole V1 and reduce the thickness of the dielectric layer (second insulating layer BF2) between the first electrode E1 and the light-shielding layer LSL, which makes it easier to increase the capacitance of the compensation capacitor.The array substrate provided by the embodiment of the present disclosure increases the capacitance of the compensation capacitor by reducing the thickness of the dielectric layer of the storage capacitor C0.

[0076] Referring to Figure 3, the array substrate provided by the embodiment of the present disclosure can meet the requirement that the first electrode E1 contacts the side S2 of the active layer AT without contacting the surface S1 of the active layer AT opposite the base substrate 101, and that only the first insulating layer BF is over-etched. That is, as long as the condition of over-etching the first insulating layer BF and reducing the thickness of the dielectric layer (second insulating portion BF2) between the first electrode E1 and the light-shielding layer LSL is met, the capacitance of the storage capacitor C0 formed by the first electrode E1 and the light-shielding layer LSL can be increased.

[0077] 2 and 3, the array substrate further includes a first via hole V1, and the first electrode E1 is connected to the active layer AT through the first via hole V1. The first via hole V1 includes a first through hole Va located in the second insulating layer 122 and a first groove G1 located in a portion of the first insulating layer BF close to the second insulating layer 122. As shown in FIG. 3, the first insulating layer BF is partially etched to form a half hole (groove). By etching a portion of the first insulating layer BF, the thickness of the dielectric layer between the first electrode E1 and the light-shielding layer LSL is reduced, and the size of the first via hole V1 in the Z direction is increased.

[0078] 3, the first insulating layer BF includes a first insulating portion BF1 and a second insulating portion BF2. The first groove G1 penetrates the first insulating portion BF1, and the second insulating portion BF2 is a portion of the first insulating layer BF that is not penetrated.

[0079] For example, as shown in FIG. 3, to increase the storage capacitor, the maximum size of the first groove G1 in a plane parallel to the main surface MS is smaller than the minimum size of the first through hole Va in a plane parallel to the main surface MS.

[0080] For example, as shown in FIG. 3, to increase the storage capacitor, the maximum size of the first groove G1 in a plane perpendicular to the main surface MS is smaller than the maximum size of the first through hole Va in a plane perpendicular to the main surface MS.

[0081] For example, as shown in FIG. 3, in order to increase the storage capacitor, the array substrate further includes a second via hole V2, and the pixel electrode PE is connected to the first electrode E1 through the second via hole V2. The second via hole V2 includes a second through hole Vb that penetrates the third insulating layer PVX1 or penetrates the fourth insulating layer PVX2 and the third insulating layer PVX1, and a second groove G2 located in the second insulating layer 122. The second groove G2 is located in a part of the second insulating layer 122 close to the third insulating layer PVX1, and the pixel electrode PE contacts the surface of the first electrode E1 opposite to the base substrate 101 and the side of the first electrode E1, thereby mitigating the step and reducing the probability of disconnection of the pixel electrode, and increasing the contact area between the pixel electrode PE and the first electrode E1, thereby reducing the contact resistance.

[0082] For example, as shown in FIG. 3, to increase the storage capacitor, the maximum size of the second groove G2 in a plane parallel to the main surface MS is smaller than the minimum size of the second through hole Vb in a plane parallel to the main surface MS.

[0083] For example, as shown in FIG. 3, to increase the storage capacitor, the maximum size of the second groove G2 in a plane perpendicular to the main surface MS is smaller than the maximum size of the second through hole Vb in a plane perpendicular to the main surface MS.

[0084] For example, the maximum size of a through hole refers to the maximum size of a cross section of the through hole, and the cross section may be a cross section at the maximum size of the through hole or a cross section in another direction. For example, the minimum size of a through hole refers to the minimum size of a cross section of the through hole, and the cross section may be a cross section at the minimum size of the through hole or a cross section in another direction. For example, the through hole includes a first through hole Va or a second through hole Vb.

[0085] For example, the maximum size of a groove is the maximum size of a cross section of the groove, and the cross section may be a cross section at the maximum size of the groove or a cross section in another direction. For example, the minimum size of a groove is the minimum size of a cross section of the groove, and the cross section may be a cross section at the minimum size of the groove or a cross section in another direction. For example, the groove includes a first groove G1 or a second groove G2.

[0086] 3, the array substrate includes a third insulating layer PVX1 disposed on the first electrode E1 and a common electrode CE disposed on the third insulating layer PVX1. In the subpixel SP, the common electrode CE and the pixel electrode PE can form a main storage capacitor Cstm.

[0087] 4A is a plan view of the light-shielding layer in the array substrate shown in FIG. 2. FIGS. 2, 3, and 4A show the light-shielding layer LSL. For example, the light-shielding layer LSL is disposed in a floating state or is electrically connected to a common electrode. The light-shielding layer LSL functions as a light shield to protect the active layer AT, and also forms a storage capacitor C0 with the first electrode E1 so as to function as a compensation capacitor.

[0088] For example, the light-shielding layer LSL is made of a conductive material, and the material of the light-shielding layer LSL contains a metal to obtain a light-shielding effect.

[0089] FIG. 3 shows a first recess RC1 in a first via hole V1 and a second recess RC2 in a second via hole V2 of the array substrate.

[0090] FIG. 4B is a plan view of the active layer in the array substrate shown in FIG. 2. For example, as shown in FIGS. 2, 3, and 4B, the active layer AT may be in the shape of a rectangular ring with truncated corners to facilitate the formation of a dual channel. FIGS. 2 and 4B show a first channel CN1 and a second channel CN2, with the transistor TR forming a double-gate structure. As shown in FIGS. 2 and 4B, the active layer AT further includes a connection portion CP connecting the first channel CN1 and the second channel CN2, a first connection region AT1 connected to the first electrode E1, and a second connection region AT2 connected to the second electrode E2. In the active layer AT, the first channel CN1 and the second channel CN2 are made of semiconductor materials, and the connection portion CP, the first connection region AT1, and the second connection region AT2 are all conductors formed by doping the semiconductor. For example, the semiconductor may include, but is not limited to, polysilicon or an oxide semiconductor.

[0091] 4B shows a cutout structure AT0 in the active layer AT. As shown in FIGS. 3 and 4B, the orthogonal projection of the cutout structure AT0 on the base substrate 101 is within the orthogonal projection of the first via hole V1 on the base substrate 101, and the size of the cutout structure AT0 is smaller than the size of the first via hole V1. When the first via hole V1 and the cutout structure AT0 are both circular, the diameter of the cutout structure AT0 is smaller than the diameter of the first via hole V1. The installation position of the cutout structure AT0 is not limited to the position shown in the figure and may be determined as needed.

[0092] As shown in FIGS. 3 and 4B, the orthogonal projection of the cutout structure AT0 on the base substrate 101 is within the orthogonal projection of the light-shielding layer LSL on the base substrate 101.

[0093] 4C is a plan view of the gate electrode and gate line of the array substrate shown in FIG. 2. As shown in FIGS. 2 and 4C, the gate electrode GE includes a first gate electrode GE1 and a second gate electrode GE2, and the first gate electrode GE1 and the second gate electrode GE2 overlap with the first channel CN1 and the second channel CN2, respectively, in a direction perpendicular to the base substrate 101. As shown in FIG. 4C, the gate electrode GE and the gate line GL have an integral structure. As shown in FIG. 4C, the gate electrode GE is a part of the gate line GL.

[0094] Fig. 4D is a plan view of the first via holes and third via holes of the array substrate shown in Fig. 2. Fig. 4E is a plan view of the data lines, first electrodes and second via holes of the array substrate shown in Fig. 2.

[0095] As shown in FIGS. 2, 4D, and 4E, the first electrode E1 is connected to the active layer AT through a first via hole V1. As shown in FIGS. 2, 4B, 4D, and 4E, the first electrode E1 is connected to a first connection region AT1 of the active layer AT through a first via hole V1. As shown in FIGS. 2, 4D, and 4E, the second electrode E2 is connected to the active layer AT through a third via hole V3. As shown in FIGS. 2, 4B, 4D, and 4E, the second electrode E2 is connected to a second connection region AT2 of the active layer AT through a third via hole V3. The array substrate shown in FIG. 2 is described as an example in which the first electrode E1 and the data line DL are located in the same layer, but this is not limiting. In other embodiments, the first electrode E1 may be located in the same layer as the gate line GL, not in the same layer as the data line DL.

[0096] Fig. 4F is a plan view of the common electrode of the array substrate shown in Fig. 2. Fig. 4F shows the common electrode CE, and as shown in Fig. 4F, the common electrode CE has a body portion CEm that forms a storage capacitor (main storage capacitor Cstm) together with the pixel electrode PE.

[0097] As shown in FIGS. 2 and 4F, the common electrode CE has a cutout structure CE0 to facilitate connection between the pixel electrode PE and the first electrode E1.

[0098] FIG. 4G is a plan view of the second via hole V2 of the array substrate shown in FIG.

[0099] Fig. 4H is a plan view of a pixel electrode of the array substrate shown in Fig. 2. As shown in Fig. 2 and Fig. 4H, the pixel electrode PE has a slit SL, and an electric field is formed by the pixel electrode PE and the common electrode CE.

[0100] 2, 3, 4E, 4F, 4G, and 4H, the pixel electrode PE is connected to the first electrode E1 through the second via hole V2 and the cutout structure CE0. As shown in FIGS. 2 and 3, the orthogonal projection of the second via hole V2 on the base substrate 101 is within the orthogonal projection of the cutout structure CE0 on the base substrate 101.

[0101] In the array substrate provided by the embodiment of the present disclosure, the capacitance of the storage capacitor of the sub-pixel can be increased by arranging at least one of the storage capacitor C0 and the second capacitor C2. The main storage capacitor Cstm formed between the common electrode CE and the pixel electrode PE may be called a planar capacitor, which is a capacitor formed by electrodes in a plane parallel to the base substrate.

[0102] As shown in Figures 2, 3 and 8, the capacitance of the main storage capacitor is Cstm=ε PVX2 *W*H / (4πk*THK PVX2 ) is obtained. PVX2 is the dielectric constant of the fourth insulating layer PVX2, W is the width of the pixel electrode PE, i.e., the size of the pixel electrode PE in the X direction, H is the length of the pixel electrode PE, i.e., the size of the pixel electrode PE in the Y direction, and THK PVX2 is the thickness of the fourth insulating layer PVX2, and k is the electrostatic force constant. For example, the capacitance of the main storage capacitor is determined by taking the area of ​​the pixel electrode PE as the opposing area of ​​the two plates of the capacitor.

[0103] As shown in FIGS. 3 and 8, the first via hole V1 is circular and the second capacitor C2 is a cylindrical capacitor.

[0104] As shown in Figures 3 and 8, the capacitance of the storage capacitor C0 is C0=ε BF2 *πR 2 / (4πk*THK BF2 ) and ε BF2 is the dielectric constant of the first insulating layer BF (second insulating portion BF2), R is the radius of the first via hole V1, and THK BF2 is the thickness of the insulating layer between the first electrode E1 and the light-shielding layer LSL, that is, the thickness of the second insulating portion BF2, and k is the electrostatic force constant.

[0105] As shown in FIGS. 3 and 8, the capacitance of the second capacitor C2 is C2=[ε pvx1 *(2πR*(THK ILD+ THK GI+ THK BF1 )] / [4πk*THK PVX1 ] and ε pvx1 is the dielectric constant of the third insulating layer PVX1, R is the radius of the first via hole V1, and THK ILD is the thickness of the interlayer insulating layer ILD, and THK GI is the thickness of the gate insulating layer GI, and THK ILD +THK GI is the thickness of the second insulating layer 122, and THK PVX1 is the thickness of the third insulating layer PVX1 between the first electrode E1 and the common electrode CE, and k is the electrostatic force constant.

[0106] Since the first insulating layer BF includes the first insulating portion BF1 and the second insulating portion BF2, ε BF2 =ε BF1 =ε BF and ε BF2 is the dielectric constant of the second insulating part BF2, and ε BF1 is the dielectric constant of the first insulating part BF1, and ε BF is the dielectric constant of the first insulating layer BF.

[0107] For simplicity, the first insulating layer BF, the second insulating layer 122, the third insulating layer PVX1, and the fourth insulating layer PVX2 are assumed to be made of the same material. If the second insulating layer 122 includes an interlayer insulating layer ILD and a gate insulating layer GI, the interlayer insulating layer ILD and the gate insulating layer GI are made of the same material and each insulating layer has the same dielectric constant. For example, the insulating layer material may be, but is not limited to, silicon nitride.

[0108] For example, when the first via hole V1 is circular, the capacitance ratio between the storage capacitor C0 and the main storage capacitor Cstm is C0 / Cstm=[ε BF2 *πR 2 / (4πk*THK BF2 )] / [ε PVX2 *W*H / (4πk*THK PVX2 )]=[πR 2 *THK PVX2 ] / [W*H*THK BF2 ].

[0109] For example, as shown in FIGS. 3 and 8, when the first via hole V1 is circular, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm in the array substrate is 0.2 or more. For example, the capacitance ratio C0 / Cstm is 0.25 or more. As a further example, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm is 0.48 or more. For example, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm is 0.50 or more. For example, when the first via hole V1 is circular, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm is 0.8 or less.

[0110] In some embodiments, when the first via hole V1 is circular, 0.2≦C0 / Cstm≦0.8. For example, 0.25≦C0 / Cstm≦0.8. For example, 0.48≦C0 / Cstm≦0.8. For example, 0.50≦C0 / Cstm≦0.8. For example, 0.50≦C0 / Cstm≦0.8.

[0111] For example, in some embodiments, R=2.59 μm, THK BF2 = 0.08 μm, W = 1.7 μm, H = 21 μm, and by substituting these values ​​into the equation for C0 / Cstm, the capacitance ratio between the storage capacitor C0 and the main storage capacitor Cstm becomes C0 / Cstm = 0.59. Of course, the values ​​of each variable in the equation are not limited to these.

[0112] For example, when the first via hole V1 is circular, the capacitance ratio between the second capacitor C2 and the main storage capacitor Cstm is C2 / Cstm=[ε pvx1 *(2πR*(THK ILD+ THK GI+ THK BF1 )] / 4πk*THK PVX1 ] / [ε PVX2 *W*H / (4πk*THK PVX2 )]=[2πR*(THK ILD+ THK GI+ THK BF1 )*THK PVX2 )] / (W*H*THK PVX1 )

[0113] 3 and 8, when the first via hole V1 is circular, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is 0.02 or more. As a further example, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is 0.03 or more.

[0114] For example, when the first via hole V1 is circular, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is 0.2 or less. As a further example, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is 0.1 or less.

[0115] For example, when the first via hole V1 is circular, 0.02≦C2 / Cstm≦0.2, and as a further example, 0.03≦C2 / Cstm≦0.1, and as a further example, 0.06≦C2 / Cstm≦0.08.

[0116] In some embodiments, R=2.59 μm, THK BF1 =0.28μm, THK ILD =0.78μm, THK GI =0.11μm, THK PVX2 =0.08μm, W=1.7μm, H=21μm, THK PVX1 = 0.52 μm, and by substituting each value into the equation for C2 / Cstm, the capacitance ratio between the second capacitor C2 and the main storage capacitor Cstm becomes C2 / Cstm = 0.08. Of course, the values ​​of each variable in the equation are not limited to these.

[0117] In the embodiments of the present disclosure, the capacitance of a capacitor may be calculated by the formula C=εS / 4πkd, where ε is a constant, S is the opposing area of ​​the capacitor's plates, d is the distance between the capacitor's plates, and k is an electrostatic force constant. Calculation of the specific capacitance of each capacitor follows the calculation and measurement methods provided in this disclosure.

[0118] FIG. 9 is a schematic diagram of a common electrode of an array substrate provided according to an embodiment of the present disclosure. As shown in FIG. 9, the common electrodes of multiple subpixels SP have an integrated structure. As shown in FIGS. 2, 3, and 9, a slit SL is provided within the pixel electrode PE, and the pixel electrode PE is positioned on the common electrode CE. The common electrode CE has a cutout structure CE0 to facilitate connection between the pixel electrode PE and the first electrode E1. Of course, in other embodiments, the common electrode CE may be positioned on the pixel electrode PE, the slit SL is provided within the common electrode CE, and the cutout structure CE0 may not be provided. In this case, refer to FIG. 16A.

[0119] For example, in the array substrate, the main storage capacitor Cstm is a storage capacitor in a plane parallel to the main surface MS.

[0120] Fig. 10 is a cross-sectional view of an array substrate provided according to an embodiment of the present disclosure. Fig. 11 is an equivalent circuit diagram of the array substrate shown in Fig. 10. As shown in Figs. 10 and 11, the array substrate includes a first storage capacitor Cst1 but does not include a second storage capacitor Cst2. As shown in Fig. 10, compared to the array substrate shown in Fig. 3, the first via hole V1 does not have a first groove G1, and the first electrode E1 is not connected to the side surface S2 of the active layer AT.

[0121] As shown in FIG. 10 , an embodiment of the present disclosure further provides an array substrate including a base substrate 101 having a main surface MS, a transistor TR located on the main surface MS of the base substrate 101 and including an active layer AT and a first electrode E1 connected to the active layer AT, a first insulating layer BF located between the base substrate 101 and the active layer AT, a second insulating layer 122 located between the active layer AT and the first electrode E1, and a pixel electrode PE connected to the first electrode E1 and in contact with the surface of the first electrode E1 opposite the base substrate 101 and the side of the first electrode E1.

[0122] For example, as shown in FIG. 10, the array substrate further includes a third insulating layer PVX1 positioned on the first electrode E1, and a common electrode CE positioned on the third insulating layer PVX1 and insulated from the pixel electrode PE and from each other, wherein the pixel electrode CE and the common electrode are configured to form an electric field, the pixel electrode PE and the common electrode CE are conformal in the first via hole V1, and the pixel electrode PE and the common electrode CE form a main storage capacitor.

[0123] For example, as shown in FIG. 10, the array substrate further includes a fourth insulating layer PVX2 located between the pixel electrode PE and the common electrode CE.

[0124] For example, as shown in FIG. 10, the array substrate further includes a second via hole V2, which includes a second through hole Vb penetrating the fourth insulating layer PVX2 and the third insulating layer PVX1, and a second groove G2 located in the second insulating layer 122, and the second groove G2 is located in a portion of the second insulating layer 122 close to the third insulating layer PVX1, and the pixel electrode PE contacts the surface of the first electrode E1 opposite the base substrate 101 and the side of the first electrode E1.

[0125] For example, as shown in FIG. 10, the maximum size of the second groove G2 in a plane parallel to the main surface MS is smaller than the minimum size of the second through hole Vb in a plane parallel to the main surface MS.

[0126] For example, as shown in FIG. 10, the maximum size of the second groove G2 in a plane perpendicular to the main surface MS is smaller than the maximum size of the second through hole Vb in a plane perpendicular to the main surface MS.

[0127] FIG. 12 is a cross-sectional view of an array substrate provided according to an embodiment of the present disclosure. FIG. 13 is an equivalent circuit diagram of the array substrate shown in FIG. 12. As shown in FIGS. 12 and 13, a compensation capacitor (also referred to as a storage capacitor C0 or a second storage capacitor Cst2) is provided in each subpixel. The pixel electrode PE and the first electrode E1 form an upper electrode of the compensation capacitor, and the light-shielding layer LSL forms a lower electrode. To reduce the thickness of the insulating medium of the compensation capacitor and increase the compensation capacitance, the first insulating layer BF is over-etched and thinned. As shown in FIGS. 2, 12, and 13, the pixel electrode PE and the common electrode CE form a main storage capacitor Cstm, which is a storage capacitor in a plane parallel to the main surface MS.

[0128] 12, the pixel electrode PE is located on the fourth insulating layer PVX2, the common electrode CE is located on the third insulating layer PVX1, the fourth insulating layer PVX2 is located between the pixel electrode PE and the common electrode CE, and the pixel electrode P is located on the common electrode CE, and in this case, a slit SL is provided in the pixel electrode PE. That is, the slit SL is provided in one of the common electrode CE and the pixel electrode PE that is farther from the base substrate 101.

[0129] For example, as shown in FIGS. 12 and 13, in the array substrate, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm can be referred to the above description, and will not be described again here.

[0130] For example, as shown in FIGS. 12 and 13, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm can be determined from the above description, and will not be described again here.

[0131] Fig. 14 is a plan view of an array substrate provided by an embodiment of the present disclosure. Fig. 15 is a cross-sectional view taken along line A3-A4 in Fig. 14. The common electrode CE is omitted in Fig. 14. For example, as shown in Fig. 15, in the array substrate, the common electrode CE is located between the first electrode E1 and the pixel electrode PE, and the common electrode CE and the first electrode E1 form a first storage capacitor Cst1, and the common electrode CE and the pixel electrode PE form another first storage capacitor Cst1.

[0132] 14 and 15, a double-layer sidewall capacitor is formed in the first via hole V1 to increase the storage capacitor. The double-layer sidewall capacitor includes a first storage capacitor Cst1 formed by the common electrode CE and the first electrode E1, and another first storage capacitor Cst1 formed by the common electrode CE and the pixel electrode PE. The pixel electrode PE extends into the first via hole V1, and the first storage capacitor Cst1 is formed by the pixel electrode PE, the common electrode CE, and the fourth insulating layer PVX2 positioned therebetween, thereby increasing the capacitance value of the storage capacitor.

[0133] As shown in FIGS. 14 and 15, the pixel electrode PE is located on the common electrode CE, and the pixel electrode PE is provided with a slit SL.

[0134] As shown in FIGS. 14 and 15, the common electrode CE has a hollow structure CE0 to facilitate connection between the pixel electrode PE and the first electrode E1.

[0135] As shown in FIG. 14, the active layer AT has a rectangular ring shape with truncated corners, and the active layer AT passes through the gate line GL twice to form a double-gate transistor.

[0136] As shown in FIG. 14, the first channel CN1 and the second channel CN2 of the active layer AT are arranged so as to avoid the data line DL.

[0137] As shown in FIGS. 14 and 15, the pixel electrode PE covers the first via hole V1 and the second via hole V2 in the first electrode E1.

[0138] Figure 15 shows two second capacitors C2, which double the compensation effect on the array substrate. The ratio of each second capacitor C2 to the main storage capacitor is consistent with the above description. Therefore, the capacitance of the second capacitor C2 is doubled.

[0139] Figure 16A is a plan view of an array substrate provided by an embodiment of the present disclosure, Figure 16B is a plan view of an array substrate provided by an embodiment of the present disclosure, and Figure 17 is a cross-sectional view taken along line A5-A6 in Figure 16A.

[0140] 16A, the first via hole V1, the second via hole V2, and the third via hole V3 are all rectangular. As shown in FIG. 16A, the channel of the active layer AT (the portion where the active layer AT overlaps with the gate line GL) overlaps with the data line DL.

[0141] In a high PPI display, the size of a single pixel can be reduced to about 7 microns * 21 microns, which reduces the wiring space, making it difficult for the channel of the active layer to bypass the data line. The first via hole V1 and the second via hole V2 can be designed into other shapes, and do not need to be circular, but can be square or other shapes, so that the second capacitor C2 (compensation capacitor) does not necessarily need to be a cylindrical capacitor, but can also be a sidewall capacitor perpendicular to the direction of the planar storage capacitor.

[0142] For example, as shown in Fig. 16A, in the ADS (Advanced Super Dimension Switch) or Fringe Field Switching (FFS) mode, the data line DL needs to be designed to have a curved shape in accordance with the direction of the slit SL in the common electrode CE. The tilt direction of the data line DL is the same as the tilt direction of the slit SL in the common electrode.

[0143] As shown in Figure 16B, the bending direction of the data line DL is parallel to the corner chipping direction D0 of the first via hole V1, and the minimum distance between the bending portion DLa of the data line DL and the corner chipping portion of the first via hole V1 is 3 μm, and the range of this minimum distance is 1 to 5 μm.

[0144] As shown in FIGS. 16A and 17, the common electrode CE has a hollow structure CE0 to facilitate connection between the pixel electrode PE and the first electrode E1.

[0145] 16A to 17, the first electrode E1 is connected to the active layer AT through a first via hole V1, and the pixel electrode PE is connected to the first electrode E1 through a second via hole V2. As shown in Fig. 17, the first via hole V1 is a half hole, and the second via hole V2 is also a half hole.

[0146] As shown in Figure 16A, the first via hole V1 may have a shape other than a circle. The shape of the first via hole V1 may be rectangular. Figure 16A takes the first via hole V1 as an example, which is rectangular with truncated corners.

[0147] The capacitance of the main storage capacitor is the same as when the first via hole V1 is circular. That is, as shown in FIGS. 8, 16A, and 17, the capacitance of the main storage capacitor is Cstm=ε PVX2 *W*H / (4πk*THK PVX2 ) ε PVX2is the dielectric constant of the fourth insulating layer PVX2, W is the width of the pixel electrode PE, i.e., the size of the pixel electrode PE in the X direction, H is the length of the pixel electrode PE, i.e., the size of the pixel electrode PE in the Y direction, and THK PVX2 is the thickness of the fourth insulating layer PVX2, and k is the electrostatic force constant.

[0148] 16A, the first via hole V1 is rectangular, and the second capacitor C2 is a square capacitor. In the embodiment of the present disclosure, the first via hole V1 is a square hole, and the length L of the first via hole V1 is h is 3 μm, and the width W of the first via hole V1 h The size of the first via hole V1 may be determined as needed.

[0149] As shown in FIGS. 16A and 17, the capacitance of the storage capacitor C0 is C0=ε BF2 *L h *W h / (4πk*THK BF2 ) and ε BF2 is the dielectric constant of the first insulating layer BF (second insulating portion BF2), and L h is the length of the first via hole V1, and W h is the width of the first via hole V1, and THK BF2 is the thickness of the insulating layer between the first electrode E1 and the light-shielding layer LSL, i.e., the thickness of the second insulating portion BF2, and k is the electrostatic force constant. h *W h is the area of ​​the rectangular first via hole V1.

[0150] As shown in FIGS. 6, 16A, and 17, the capacitance of the second capacitor (sidewall capacitor) C2 is C2=[ε pvx1 *(2L h +2W h )*(THK ILD+ THK GI+ THK BF1 )] / [4πk*THK PVX1 ] and ε pvx1is the dielectric constant of the third insulating layer PVX1, and L h is the length of the first via hole V1, and W h is the width of the first via hole V1, and THK ILD is the thickness of the interlayer insulating layer ILD, and THK GI is the thickness of the gate insulating layer GI, and THK ILD +THK GI is the thickness of the second insulating layer 122, and THK PVX1 is the thickness of the third insulating layer PVX1 between the first electrode E1 and the common electrode CE, and k is the electrostatic force constant. (2L h +2W h ) is the perimeter of the rectangular first via hole V1.

[0151] Similarly, the first insulating layer BF includes a first insulating portion BF1 and a second insulating portion BF2, so that ε BF2 =ε BF1 =ε BF and ε BF2 is the dielectric constant of the second insulating part BF2, and ε BF1 is the dielectric constant of the first insulating part BF1, and ε BF is the dielectric constant of the first insulating layer BF.

[0152] Similarly, for simplicity of calculation, the first insulating layer BF, the second insulating layer 122, the third insulating layer PVX1, and the fourth insulating layer PVX2 are assumed to be made of the same material. If the second insulating layer 122 includes an interlayer insulating layer ILD and a gate insulating layer GI, the interlayer insulating layer ILD and the gate insulating layer GI are made of the same material and each insulating layer has the same dielectric constant. For example, the insulating layer material may be, but is not limited to, silicon nitride.

[0153] For example, when the first via hole V1 is rectangular, the capacitance ratio between the storage capacitor C0 and the main storage capacitor Cstm is C0 / Cstm=[ε BF2 *L h *W h / (4πk*THK BF2 )] / [ε PVX2 *W*H / (4πk*THK PVX2 )]=[L h*W h *THK PVX2 ] / [W*H*THK BF2 ].

[0154] For example, when the first via is rectangular, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm on the array substrate is 0.2 or more. For example, the capacitance ratio C0 / Cstm is 0.25 or more. As a further example, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm is 0.48 or more. For example, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm is 0.50 or more.

[0155] For example, when the first via hole V1 is rectangular, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm is 0.8 or less.

[0156] In some embodiments, when the first via hole V1 is rectangular, 0.2≦C0 / Cstm≦0.8. For example, 0.25≦C0 / Cstm≦0.8. For example, 0.48≦C0 / Cstm≦0.8. For example, 0.50≦C0 / Cstm≦0.8. For example, 0.50≦C0 / Cstm≦0.8.

[0157] For example, in some embodiments, L h = 3 μm, W h =3μm, THK BF2 = 0.08 μm, W = 1.7 μm, H = 21 μm. Substituting these values ​​into the equation for C0 / Cstm, the capacitance ratio between the storage capacitor C0 and the main storage capacitor Cstm is C0 / Cstm = 0.252. Of course, the values ​​of the variables in the equation are not limited to these.

[0158] For example, the capacitance ratio between the second capacitor C2 and the main storage capacitor Cstm is C2 / Cstm=[ε pvx1 *(2L h +2W h )*(THK ILD+ THKGI+ THK BF1 ) / [4πk*THK PVX1 ] / [ε PVX2 *W*H / (4πk*THK PVX2 )]=[(2L h +2W h )*(THK ILD+ THK GI+ THK BF1 )*THK PVX2 )] / (W*H*THK PVX1 )

[0159] 16A and 17, when the first via hole V1 is rectangular, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is 0.02 or more. As a further example, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is 0.03 or more.

[0160] For example, when the first via hole V1 is rectangular, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is 0.2 or less. As a further example, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is 0.1 or less.

[0161] For example, when the first via hole V1 is rectangular, 0.02≦C2 / Cstm≦0.2, and as a further example, 0.03≦C2 / Cstm≦0.1, and as a further example, 0.06≦C2 / Cstm≦0.08.

[0162] In some embodiments, L h = 3 μm, W h =3μm, THK BF1 =0.28μm, THK ILD =0.78μm, THK GI =0.11μm, THK PVX2 =0.08μm, W=1.7μm, H=21μm, THK PVX1= 0.52 μm, and by substituting each value into the equation for C2 / Cstm, the capacitance ratio between the second capacitor C2 and the main storage capacitor Cstm becomes C2 / Cstm = 0.06. Of course, the values ​​of each variable in the equation are not limited to these.

[0163] Therefore, in the embodiments of the present disclosure, regardless of the shape of the first via hole V1, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm is all within the above range, and the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm is all within the above range.

[0164] In the embodiments of the present disclosure, a capacitor and its capacitance are represented by the same symbol.

[0165] For example, as shown in FIGS. 8 and 16A, the width of the sub-pixel may be 2 to 7 μm, and the length of the sub-pixel may be 15 to 60 μm.

[0166] 18 is a plan view of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 18, the common electrode CE has slits SL, which are not bent, and the pixel electrodes PE are plate-shaped. The shape / direction and spacing of the pixel electrodes PE are as follows: (1) The pixel electrode PE has a notched corner PE0. (2) The edge of the upper half of the pixel electrode PE is parallel to the edge of the slit SL of the common electrode and also parallel to the data line. (3) The edge of the lower half of the pixel electrode PE is not parallel to the edge of the slit SL of the common electrode but is parallel to the data line. (4) The minimum distance between the edge of the lower half of the pixel electrode PE and the edge of the slit SL of the common electrode is less than 1 μm, and the pixel electrode PE of the subpixel in the previous row covers the first via hole V1 (the via hole connecting the first electrode E1 of the transistor TR to the active layer AT) of the subpixel in the next row.

[0167] For example, as shown in FIG. 16A, the data line DL includes a plurality of inclined portions DL1, and a bent portion DL2 is provided between adjacent inclined portions DL1, the extending direction of the inclined portions DL1 is the same as the extending direction of the slit SL, and the first via hole V1 has a corner cut portion, and the extending direction of the edge of the corner cut portion of the first via hole V1 is the same as the extending direction of the bent portion.

[0168] For example, as shown in FIG. 16A, the distance W7 between the edge of the corner cut portion of the first via hole V1 and the bent portion DL2 is not less than 1 micron and not more than 5 microns.

[0169] For example, as shown in FIG. 16A, the pixel electrode PE has a first portion P1 and a second portion P2 which extend in different directions, the extension direction of the first portion P1 is the same as the extension direction of the slit SL, and the edge of the first portion P1 is parallel to the edge of the slit SL and parallel to the edge of the data line DL.

[0170] For example, as shown in FIG. 16A, the edge of the second portion P2 is not parallel to the edge of the slit SL, but is parallel to the data line DL.

[0171] For example, as shown in Figures 16A and 18, the minimum distance W8 between the edge of the second portion P2 and the edge of the slit SL is less than 1 micron. W8 is shown as an oval in Figure 18.

[0172] 19 and 20 are plan and cross-sectional views of an array substrate provided according to an embodiment of the present disclosure.

[0173] For example, as shown in Figures 19 and 20, the array substrate further includes a first via hole V1, the first electrode E1 is connected to the active layer AT through the first via hole V1, the pixel electrode PE contacts the surface of the first electrode E1 opposite the base substrate 101, and the orthogonal projection of the first via hole V1 on the base substrate 101 overlaps with the orthogonal projection of the second via hole V2 on the base substrate 101.

[0174] For example, as shown in FIG. 20, the first via hole V1 includes a first through hole Va penetrating the second insulating layer 122 and a first groove G1 located in the first insulating layer BF, and the first groove G1 is located in a part of the first insulating layer BF close to the second insulating layer 122, which facilitates contact between the first electrode E1 and the side of the active layer AT, increasing the capacitance of the compensation capacitor in the Z direction and increasing the capacitance of the storage capacitor.

[0175] For example, as shown in FIG. 20, the second via hole V2 penetrates the third insulating layer PVX1 and the fourth insulating layer PVX2.

[0176] For example, as shown in FIG. 20, the first electrode E1 and the common electrode CE form a first storage capacitor Cst1.

[0177] For example, as shown in FIG. 20, the array substrate further includes a light-shielding layer LSL positioned between the active layer AT and the base substrate 101, and the orthogonal projection of the active layer AT on the base substrate 101 is within the orthogonal projection of the light-shielding layer LSL on the base substrate 101, and the first electrode E1 and the light-shielding layer LSL form a second storage capacitor Cst2.

[0178] 20, the light-shielding layer LSL is arranged in a floating state. In the embodiment of the present disclosure, the floating state means that no signals are connected.

[0179] For example, as shown in FIG. 20, in the array substrate, the pixel electrode PE extends into the first via hole V1 and contacts the first electrode E1 at the first via hole V1.

[0180] As shown in Figures 19 and 20, when the PPI is high, the double hole needs to be changed to a single hole, in which case the ratio of the two compensation capacitors (storage capacitor C0 and second capacitor C2) and their respective main storage capacitors Cstm remains almost the same as described above.

[0181] As shown in FIGS. 19 and 20, the array substrate is in the ADS mode, and the pixel electrode PE has a slit SL, but the first via hole V1 and the second via hole V2 overlap each other.

[0182] Figure 21 is a plan view of an array substrate provided by an embodiment of the present disclosure, Figure 22 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure, and Figure 23 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure.

[0183] 22 and 23, the array substrate further includes a third insulating layer PVX1 disposed on the first electrode E1 and a common electrode CE disposed on the third insulating layer PVX1 and insulated from the pixel electrode PE. The pixel electrode PE and the common electrode CE are configured to form an electric field. At least one of the first electrode E1 and the pixel electrode PE forms a first storage capacitor Cst1 together with the common electrode CE. The first storage capacitor Cst1 includes a first capacitor C1 in a plane parallel to the main surface MS and a second capacitor C2 in a direction perpendicular to the main surface MS. For example, the capacitance ratio C0 / Cstm between the storage capacitor C0 and the main storage capacitor Cstm can refer to the above description. For example, the capacitance ratio C2 / Cstm between the second capacitor C2 and the main storage capacitor Cstm can refer to the above description.

[0184] For example, as shown in FIGS. 22 and 23, in the array substrate, the main storage capacitor Cstm is a storage capacitor in a plane parallel to the main surface MS.

[0185] For example, the array substrate further includes a light-shielding layer LSL positioned between the active layer AT and the base substrate 101, the orthogonal projection of the active layer AT on the base substrate 101 is within the orthogonal projection of the light-shielding layer LSL on the base substrate 101, and the first electrode E1 and the light-shielding layer LSL form a storage capacitor C0 (second storage capacitor Cst2).

[0186] For example, the light-shielding layer LSL is disposed in a floating state or is electrically connected to the common electrode CE. As shown in Figures 22 and 23, the light-shielding layer LSL is disposed in a floating state. The light-shielding layer LSL is electrically connected to the common electrode CE so as to have the same potential as the common electrode CE.

[0187] For example, as shown in FIGS. 22 and 23, in the array substrate, the pixel electrode PE extends into the first via hole V1 and contacts the first electrode E1 at the first via hole V1.

[0188] For example, as shown in FIG. 23, the pixel electrode PE and the first electrode E1 are conformal in the first via hole V1, and the maximum size h2 of the contact portion between the pixel electrode PE and the first electrode E1 in a direction perpendicular to the main surface MS is greater than or equal to the maximum size h1 of the first via hole V1 in a direction perpendicular to the main surface MS.

[0189] For example, as shown in FIG. 23, the pixel electrode PE and the common electrode CE are conformal in the first via hole V1, and the pixel electrode PE and the common electrode CE form a first storage capacitor Cst1 in the first via hole V1, and the pixel electrode PE and the common electrode CE form a main storage capacitor Cstm.

[0190] Compared with the array substrate shown in FIG. 22, the contact area between the first electrodes E1 and the pixel electrodes PE is further increased in the array substrate 23 shown in FIG.

[0191] Referring to Figures 21 to 23, the array substrate is a wide-viewing-angle multi-domain ADS or FFS or vertical alignment (VA) mode, and one via hole is used to electrically connect the first electrode E1 to the active layer AT, electrically connect the pixel electrode PE to the first electrode E1, and form one or more compensation capacitors.

[0192] Figure 24 is a cross-sectional view of an array substrate provided according to an embodiment of the present disclosure. Figure 25 is a cross-sectional view of another array substrate provided according to an embodiment of the present disclosure.

[0193] In FIG. 24, the first insulating layer BF is not over-etched. For example, as shown in FIG. 24, in the array substrate, the maximum thickness of the first insulating layer BF is in the range of 50 nm to 300 nm, which increases the capacitance of the storage capacitor C0 and provides a compensation effect. By thinning the first insulating layer BF, the thickness of the dielectric layer between the first electrode E1 and the light-shielding layer LSL is reduced, resulting in a larger storage capacitor C0 and a better compensation effect. In the embodiment of the present disclosure, by thinning the dielectric layer between the first electrode E1 and the light-shielding layer LSL, a storage capacitor C0 with a larger capacitance is obtained. A smaller dielectric layer can be achieved by over-etching the first insulating layer BF or by making the first insulating layer BF thinner.

[0194] 25, the first insulating layer BF is not over-etched. For example, as shown in FIG. 25, in the array substrate, the maximum size h3 of the first groove G1 in the direction perpendicular to the base substrate 101 is larger than the maximum size h4 of the part of the first insulating layer BF directly below the first groove G1 in the direction perpendicular to the base substrate 101. Of course, in other embodiments, h3 may be equal to or smaller than h4.

[0195] For example, the over-etching of the first insulating layer BF can be performed simultaneously with the patterning of the active layer. The over-etching of the first insulating layer BF can be performed using a process required for etching the active layer material, such as polysilicon, an oxide semiconductor, or amorphous silicon. The process gas or liquid used to etch the active layer material also etches a portion of the material of the first insulating layer BF. For example, the material of the first insulating layer BF may include silicon oxide or silicon nitride. That is, the over-etching of the first insulating layer BF and the formation of the active layer are performed simultaneously. That is, the first groove G1 is formed during the patterning and etching of the active layer. Of course, the over-etching of the first insulating layer BF is not limited to the above method.

[0196] For example, as shown in Figures 24 and 25, the array substrate further includes a fourth insulating layer PVX2 located between the pixel electrode PE and the common electrode CE. As shown in Figures 24 and 25, the pixel electrode PE is located on the common electrode CE, and the fourth insulating layer PVX2 is provided between the pixel electrode PE and the common electrode CE.

[0197] For example, as shown in Figures 24 and 25, the array substrate further includes a second via hole V2, which includes a second through hole Vb that penetrates the fourth insulating layer PVX2 and the third insulating layer PVX1 and a second groove G2 located in the second insulating layer 122, and the second groove G2 is located in a part of the second insulating layer 122 close to the third insulating layer PVX1, and the pixel electrode PE contacts the surface S1 of the first electrode E1 opposite the base substrate 101 and the side surface S2 of the first electrode E1, thereby increasing the contact area of ​​the side surfaces and increasing the size of the first electrode E1 in the Z direction, contributing to increasing the capacitance of the storage capacitor (compensation capacitor) formed by the first electrode E1 and another electrode such as the common electrode CE in the Z direction.

[0198] 24 and 25, the maximum size W1 of the second groove G2 in a plane parallel to the main surface MS is smaller than the minimum size W2 of the second through hole Vb in a plane parallel to the main surface MS. W1 and W2 are marked in FIG.

[0199] For example, as shown in Fig. 25, the maximum size h5 of the second groove G2 in a plane perpendicular to the main surface MS is smaller than the maximum size h6 of the second through hole Vb in a plane perpendicular to the main surface MS. h5 and h6 are marked in Fig. 24.

[0200] 25, the array substrate further includes a fourth insulating layer PVX2 located between the pixel electrode PE and the common electrode CE, and a second via hole V2. The second via hole V2 includes a second through hole Vb penetrating the third insulating layer PVX1 and the fourth insulating layer PVX2, and a second groove G2 located in the second insulating layer 122. The second groove G2 is located in a portion of the second insulating layer 122 close to the third insulating layer PVX1.

[0201] For example, as shown in FIG. 25, in the array substrate, the pixel electrode PE contacts the surface S1 of the first electrode E1 opposite to the base substrate 101, and the side surface S2 of the first electrode E1.

[0202] For example, the array substrate shown in Figures 24 and 25 is described as an example in which the light-shielding layer LSL is arranged in a floating state, but in other embodiments, the light-shielding layer LSL may be electrically connected to the common electrode CE.

[0203] 26 is a plan view of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 26, the array substrate further includes a data line DL, and the transistor TR further includes a second electrode E2, where the second electrode E2 is connected to the active layer AT and the data line DL is connected to the second electrode E2. The orthogonal projection of the pixel electrode PE on the base substrate 101 overlaps with the orthogonal projection of the data line DL on the base substrate 101. For example, the width W3 of the overlapping portion between the pixel electrode PE and the data line DL is less than 3 microns.

[0204] FIG. 27 is a plan view of an array substrate provided by an embodiment of the present disclosure. In a high-PPI display, the size of one pixel can be reduced to approximately 7 microns x 21 microns, reducing the wiring space. Therefore, the first via hole V1 and the second via hole V2 need to be designed in a square shape to accommodate the electrode shapes and wiring in different display modes. Therefore, the second capacitor C2 (compensation capacitor) does not necessarily need to be a cylindrical capacitor, but can also be a sidewall capacitor perpendicular to the direction of the planar storage capacitor. For example, as shown in FIG. 27, the array substrate is in ADS mode, the first via hole V1 is square, and the second via hole V2 is square. FIG. 27 shows the bottom V21 and top V22 of the second via hole V2, where the top V22 is larger than the bottom V21.

[0205] As shown in Figure 27, the data line DL is bent, and the slit SL in the pixel electrode PE or common electrode CE also has a certain inclination angle (1 to 20 degrees) with respect to the data line, and the edge of the pixel electrode PE and the slit SL in the common electrode CE also partially overlap with the data line, with the overlap width being less than 3 microns. Figure 27 shows the maximum width W3 of the overlapping portion between the pixel electrode PE and the data line, and the maximum width W4 of the overlapping portion between the slit SL and the data line DL. W3 is less than 3 microns, and W4 is less than 3 microns.

[0206] For example, in an embodiment of the present disclosure, the array substrate further includes a common electrode CE, and one of the pixel electrode PE and the common electrode CE, which is farther from the base substrate 101, has a slit SL, and the pixel electrode PE and the common electrode CE are configured to form an electric field. As shown in Fig. 27, the orthogonal projection of the slit SL on the base substrate 101 overlaps with the orthogonal projection of the data line DL on the base substrate 101. For example, the width W4 of the overlapping portion between the slit SL and the data line DL is less than 3 microns, but is not limited to this.

[0207] For example, as shown in FIG. 27, the angle θ1 between the data line DL and the slit SL is 1 to 20 degrees.

[0208] For example, in the embodiments of the present disclosure, the shape of the first via hole V1 may include, but is not limited to, at least one of a circle, a rectangle, and a rectangle with rounded corners, and can be determined as needed.

[0209] 28 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure. For example, as shown in FIG. 28, the array substrate further includes a first protection structure 191, where an orthogonal projection of the first protection structure 191 on the base substrate 101 overlaps with an orthogonal projection of the first via hole V1 on the base substrate 101, a portion of the first protection structure 191 fills the first recess RC1 of the first via hole V1, and a portion of the first protection structure 191 protrudes from the first recess RC1.

[0210] 29 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure. For example, as shown in FIG. 29, the array substrate further includes a second protection structure 192, and the orthogonal projection of the second protection structure 192 on the base substrate 101 overlaps with the orthogonal projection of the second via hole V2 on the base substrate 101. A portion of the second protection structure 192 fills the second recess RC2 of the second via hole V2, and a portion of the second protection structure 192 protrudes from the second recess RC2.

[0211] 30 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure. FIG. 30 shows a first protection structure 191 and a second protection structure 192. The first protection structure 191 and the second protection structure 192 may refer to those shown in FIG. 28 and FIG. 29, respectively. Of course, the first protection structure 191 and the second protection structure 192 may be integrated into one structure.

[0212] For example, the first protective structure 191, the second protective structure 192, or the fused protective structure may be made of metal or organic material and may be integrally formed with an antistatic structure or spacer. The spacer is configured to support the thickness of the liquid crystal cell and may be fabricated on the array substrate or disposed on the opposing substrate.

[0213] FIG. 31 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure. FIG. 32 is a cross-sectional view of an array substrate provided by an embodiment of the present disclosure. As shown in FIGS. 31 and 32, the array substrate includes a connection electrode 180. The common electrode CE is connected to the light-shielding layer LSL via the connection electrode 180. The connection electrode 180 in FIG. 31 may be located in the same layer as the first electrode E1. The connection electrode 180 in FIG. 32 includes a first connection portion 181 and a second connection portion 182. As shown in FIG. 32, the first connection portion 181 may be located in the same layer as the gate line GL, and the second connection portion 182 may be located in the same layer as the first electrode E1.

[0214] 33 and 34 are plan views of an array substrate provided by an embodiment of the present disclosure.

[0215] For example, as shown in Figures 17, 33 and 34, the array substrate further includes a data line DL and a common electrode CE, the transistor TR further includes a second electrode E2, the second electrode E2 is connected to the active layer AT, the data line DL is connected to the second electrode E2, the pixel electrode PE and the common electrode CE are configured to form an electric field, the pixel electrode PE is positioned between the common electrode CE and the base substrate 101, and the common electrode CE has a slit SL.

[0216] For example, as shown in Figures 33 and 34, on the array substrate, the distance between the pixel electrode PE and the slit SL on the same side of the slit SL includes at least two unequal distances. Figures 33 and 34 show a distance W5 and a distance W6, and the distance W5 and the distance W6 are unequal.

[0217] For example, as shown in FIGS. 33 and 34, the array substrate further includes an electrode lead CEL connected to the common electrode CE, and the orthogonal projection of the electrode lead CEL on the base substrate 101 overlaps with the orthogonal projection of the data line DL on the base substrate 101.

[0218] 35 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 35 and the cross-sectional and plan views of an embodiment of the present disclosure, the method for manufacturing an array substrate includes the following steps:

[0219] In step (1), a light-shielding layer LSL is formed. In step (2), a first insulating layer BF is formed. In step (3), a polysilicon semiconductor layer is formed. Step (4): A doping process is performed to adjust the threshold voltage. Step (5) is to perform an N-type ion doping process. In step (6), a gate insulating layer GI is formed. In step (7), a gate electrode and a gate line are formed. Step (8): A P-type ion doping process is carried out. In step (9), an interlayer insulating layer ILD is formed. In step (10), the data line DL, the first electrode E1 and the second electrode E2 of the transistor are formed. Step (11): forming a third insulating layer PVX1. Step (12): forming a common electrode CE. In step (13), a fourth insulating layer PVX2 is formed. In step (14), the pixel electrode PE is formed.

[0220] Of course, the manufacturing method of the array substrate provided by the embodiments of the present disclosure is not limited to the above method. Other suitable methods can be used. The manufacturing method of the array substrate and the order of forming each film layer can be determined according to its structure.

[0221] Table 1 shows the material and thickness of each film layer of the array substrate provided by the embodiment of the present disclosure. Of course, the material and thickness of each film layer of the array substrate are not limited to those shown in the figure.

[0222] [Table 1]

[0223] An embodiment of the present disclosure further provides a display device including any of the above array substrates.

[0224] For example, the display device includes a liquid crystal display device. For example, the display device includes a liquid crystal display or a product including a liquid crystal display. For example, the display device includes any product or component with a display function, such as glasses, televisions, digital cameras, mobile phones, watches, tablet computers, notebook computers, and navigators, which include the above-mentioned display panel.

[0225] (1) Unless otherwise specified, the same symbols have the same meanings in the implementation of this disclosure and the accompanying drawings. (2) The drawings of the embodiments of the present disclosure include only the structures related to the embodiments of the present disclosure, and common designs may be referenced for other structures. (3) For clarity, thicknesses of layers or regions are exaggerated in the figures illustrating the embodiments of the present disclosure. When an element such as a layer, film, region, or substrate is referred to as being located "on" or "under" another element, it may be located "directly" "on" or "under" the other element, or intermediate elements may be present. When an element is referred to as being in contact with another element, there are no intermediate elements between the two elements. (4) Features in the same embodiment and different embodiments of the present disclosure may be combined if there is no contradiction. (5) The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are used only to distinguish different components. The ordinal numbers before the components may be deleted or replaced to arrange them in the order of appearance.

[0226] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto. Those skilled in the art can easily think of modifications or alternatives within the technical scope disclosed in the present disclosure, which should fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be subject to the scope of protection of the claims. [Explanation of symbols]

[0227] 101 Base board MS main surface AT active layer E1 First electrode TR transistor BF First insulating layer 122 Second insulating layer PE pixel electrode CE common electrode

Claims

1. a base substrate including a main surface; a transistor located on the main surface of the base substrate, the transistor including an active layer and a first electrode connected to the active layer; a first insulating layer located between the base substrate and the active layer; a second insulating layer located between the active layer and the first electrode; a pixel electrode connected to the first electrode; a common electrode insulated from the pixel electrodes and configured to form an electric field together with the pixel electrodes; The array substrate, wherein the first electrode contacts a surface of the active layer opposite the base substrate and a side surface of the first electrode.

2. 2. The array substrate of claim 1, further comprising a first via hole, wherein the first electrode is connected to the active layer through the first via hole, and the first via hole comprises a first through hole penetrating the second insulating layer and a first groove in the first insulating layer.

3. 3. The array substrate according to claim 2, wherein a maximum size of said first groove in a plane parallel to said main surface is smaller than a minimum size of said first through hole in a plane parallel to said main surface.

4. 4. The array substrate according to claim 2, wherein a maximum size of said first groove in a direction perpendicular to said main surface is smaller than a maximum size of said first through hole in a direction perpendicular to said main surface.

5. 5. The array substrate according to claim 2, wherein the pixel electrode extends into the first via hole and contacts the first electrode at the first via hole.

6. 6. The array substrate of claim 5, wherein the pixel electrode and the first electrode are conformal in the first via hole, and the maximum size of a contact portion between the pixel electrode and the first electrode in a direction perpendicular to the main surface is equal to or greater than the maximum size of the first via hole in a direction perpendicular to the main surface.

7. 7. The array substrate according to claim 5, further comprising a third insulating layer located on the first electrode, the common electrode being located on the third insulating layer.

8. The array substrate according to claim 7 , wherein the pixel electrode and the common electrode are conformal in the first via hole.

9. 9. The array substrate according to claim 2, wherein the first insulating layer includes a first insulating portion and a second insulating portion, the first groove is located in the first insulating portion, and the thickness of the first insulating portion is greater than the thickness of the second insulating portion.

10. The array substrate according to claim 9 , wherein the thickness of the first insulating portion is more than twice the thickness of the second insulating portion.

11. 11. The array substrate of claim 9, further comprising a light-shielding layer located between the active layer and the base substrate, wherein an orthogonal projection of the active layer on the base substrate is within an orthogonal projection of the light-shielding layer on the base substrate, and the first electrode and the light-shielding layer form a compensation capacitor.

12. The array substrate according to claim 11 , wherein the light-shielding layer is disposed in a floating state or is electrically connected to the common electrode.

13. 11. The array substrate of claim 1, further comprising a light-shielding layer located between the active layer and the base substrate, wherein an orthogonal projection of the active layer on the base substrate is within an orthogonal projection of the light-shielding layer on the base substrate, and the first electrode and the light-shielding layer form a compensation capacitor.

14. The array substrate according to claim 13 , wherein the light-shielding layer is disposed in a floating state or is electrically connected to the common electrode.

15. 15. The array substrate according to claim 13, wherein the thickness of the first insulating portion is 50 nm to 300 nm.

16. 16. The array substrate according to claim 11, wherein the pixel electrode and the common electrode form a main storage capacitor, and a capacitance ratio between the compensation capacitor and the main storage capacitor is 0.2 or more.

17. 17. The array substrate according to claim 16, wherein a capacitance ratio between the compensation capacitor and the main storage capacitor is 0.8 or less.

18. 18. The array substrate according to claim 17, wherein a capacitance ratio between the compensation capacitor and the main storage capacitor is equal to or greater than 0.25 and equal to or less than 0.

6.

19. 16. The array substrate of claim 1, wherein at least one of the first electrode and the pixel electrode forms a first storage capacitor together with the common electrode, and the first storage capacitor includes a first capacitor in a plane parallel to the main surface and a second capacitor in a direction perpendicular to the main surface.

20. 20. The array substrate according to claim 19, wherein the pixel electrode and the common electrode form the main storage capacitor, and a capacitance ratio between the second capacitor and the main storage capacitor is 0.02 or more.

21. 21. The array substrate according to claim 20, wherein a capacitance ratio between the second capacitor and the main storage capacitor is 0.2 or less.

22. 22. The array substrate according to claim 21, wherein a capacitance ratio between the second capacitor and the main storage capacitor is equal to or greater than 0.06 and equal to or less than 0.

08.

23. 23. The array substrate of claim 19, further comprising a third insulating layer positioned on the first electrode and a fourth insulating layer, the common electrode being positioned on the third insulating layer, and the fourth insulating layer being positioned between the pixel electrode and the common electrode.

24. 24. The array substrate of claim 23, further comprising a second via hole, wherein the pixel electrode is connected to the first electrode through the second via hole, the second via hole including a second via hole penetrating the third insulating layer or penetrating the fourth insulating layer and the third insulating layer, and a second groove provided in the second insulating layer, and the pixel electrode contacts a surface of the first electrode opposite to the base substrate and a side surface of the first electrode.

25. 25. The array substrate according to claim 24, wherein the second groove has a maximum size in a plane parallel to the main surface that is smaller than the minimum size of the through hole in a plane parallel to the main surface.

26. 26. The array substrate according to claim 24, wherein the maximum size of the second groove in the direction perpendicular to the main surface is smaller than the maximum size of the through hole in the direction perpendicular to the main surface.

27. 23. The array substrate of claim 19, wherein the common electrode is located between the first electrode and the pixel electrode, the common electrode and the first electrode forming a first storage capacitor, and the common electrode and the pixel electrode forming another first storage capacitor.

28. 28. The array substrate of claim 27, further comprising: a third insulating layer positioned on the first electrode; a fourth insulating layer positioned between the pixel electrode and the common electrode; and a second via hole, wherein the pixel electrode is connected to the first electrode through the second via hole, and the second via hole includes a second via hole that penetrates the third insulating layer or penetrates the third insulating layer and the fourth insulating layer, and a second groove positioned in the fourth insulating layer.

29. 30. The array substrate according to claim 28, wherein the pixel electrode contacts a surface of the first electrode opposite to the base substrate and a side surface of the first electrode.

30. 30. The array substrate of claim 28 or 29, further comprising a first via hole, wherein the first electrode is connected to the active layer through the first via hole, the pixel electrode is in contact with a surface of the first electrode opposite the base substrate, and the orthogonal projection of the first via hole on the base substrate overlaps with the orthogonal projection of the second via hole on the base substrate.

31. 31. The array substrate of claim 30, wherein the first via hole comprises a first through hole penetrating the second insulating layer and a first trench in the first insulating layer.

32. 32. The array substrate of claim 2, further comprising a data line, the transistor further comprising a second electrode, the second electrode being connected to the active layer, the data line being connected to the second electrode, and an orthogonal projection of the pixel electrode on the base substrate overlapping with an orthogonal projection of the data line on the base substrate.

33. 33. The array substrate of claim 32, wherein the width of the overlapping portion between the pixel electrode and the data line is less than 3 microns.

34. 32. The array substrate of claim 2, further comprising a data line, the transistor further comprising a second electrode, the second electrode being connected to the active layer, the data line being connected to the second electrode, a slit being provided in one of the pixel electrode and the common electrode that is remote from the base substrate, and an orthogonal projection of the common electrode on the base substrate overlaps with an orthogonal projection of the data line on the base substrate.

35. 35. The array substrate of claim 34, wherein the width of the overlapping portion between the common electrode and the data line is less than 3 microns.

36. 36. The array substrate according to claim 34, wherein an angle between the data lines and the slits is between 1 degree and 20 degrees.

37. 13. The array substrate according to claim 2, wherein the shape of the first via hole includes at least one of a circle, a rectangle, or a rectangle with truncated corners.

38. 13. The array substrate of claim 2, further comprising a first protective structure, wherein an orthogonal projection of the first protective structure on the base substrate overlaps with an orthogonal projection of the first via hole on the base substrate, a portion of the first protective structure fills a first recess in the first via hole of the array substrate, and a portion of the first protective structure protrudes from the first recess.

39. 32. The array substrate of claim 24, further comprising a second protective structure, wherein an orthogonal projection of the second protective structure on the base substrate overlaps with an orthogonal projection of the second via hole on the base substrate, a portion of the second protective structure fills a second recess in the second via hole of the array substrate, and a portion of the second protective structure protrudes from the second recess.

40. 13. The array substrate according to claim 2, further comprising a data line, the transistor further comprising a second electrode, the second electrode being connected to the active layer, the data line being connected to the second electrode, the pixel electrode being located between the common electrode and the base substrate, and the common electrode being provided with a slit.

41. 41. The array substrate according to claim 40, wherein on the same side of the slit, the distance between the pixel electrode and the slit comprises at least two unequal distances.

42. 42. The array substrate of claim 41, further comprising an electrode lead connected to the common electrode, wherein an orthogonal projection of the electrode lead on the base substrate overlaps an orthogonal projection of the data line on the base substrate.

43. 43. The array substrate of claim 40, wherein the data line includes a plurality of inclined portions, a bent portion is provided between adjacent inclined portions, the extending direction of the inclined portions is the same as the extending direction of the slit, and the first via hole has a corner cut portion, and the extending direction of the edge of the corner cut portion of the first via hole is the same as the extending direction of the bent portion.

44. 44. The array substrate according to claim 43, wherein the distance between the edge of the corner cutout and the bent portion of the first via hole is not less than 1 micron and not more than 5 microns.

45. The array substrate of any one of claims 40 to 44, wherein the pixel electrode has a first portion and a second portion having different extension directions, the extension direction of the first portion is the same as the extension direction of the slit, and the edge of the first portion is parallel to the edge of the slit and parallel to the edge of the data line.

46. 46. ​​The array substrate of claim 45, wherein an edge of the second portion is not parallel to an edge of the slit, and the edge of the second portion is parallel to the data line.

47. 47. The array substrate of claim 46, wherein the minimum distance between an edge of the second portion and an edge of the slit is less than 1 micron.

48. a base substrate including a main surface; a transistor located on the main surface of the base substrate, the transistor including an active layer and a first electrode connected to the active layer; a first insulating layer located between the base substrate and the active layer; a second insulating layer located between the active layer and the first electrode; a pixel electrode connected to the first electrode, The pixel electrode is in contact with a surface of the first electrode opposite to the base substrate and with a side surface of the first electrode.

49. a third insulating layer located on the first electrode; a common electrode located on the third insulating layer, insulated from the pixel electrodes, and configured to form an electric field together with the pixel electrodes; 49. The array substrate of claim 48, wherein the pixel electrode and the common electrode form a main storage capacitor.

50. 50. The array substrate of claim 49, further comprising a fourth insulating layer located between the pixel electrode and the common electrode.

51. 51. The array substrate of claim 50, further comprising a second via hole, wherein the pixel electrode is connected to the first electrode through the second via hole, the second via hole penetrating the third insulating layer or comprising a second via hole penetrating the fourth insulating layer and the third insulating layer and a second groove provided in the second insulating layer, and the pixel electrode contacts a surface of the first electrode opposite the base substrate and a side of the first electrode.

52. 52. The array substrate of claim 49, further comprising a light-shielding layer located between the active layer and the base substrate, wherein an orthogonal projection of the active layer on the base substrate is within an orthogonal projection of the light-shielding layer on the base substrate, and the first electrode and the light-shielding layer form a compensation capacitor.

53. 53. The array substrate of claim 52, wherein the pixel electrode and the common electrode form a main storage capacitor, and a capacitance ratio between the compensation capacitor and the main storage capacitor is 0.2 or greater.

54. 54. The array substrate of claim 53, wherein a capacitance ratio between the compensation capacitor and the main storage capacitor is 0.8 or less.

55. 55. An array substrate according to any one of claims 49 to 54, wherein at least one of the first electrode and the pixel electrode forms a first storage capacitor together with the common electrode, the first storage capacitor including a first capacitor in a plane parallel to the main surface and a second capacitor in a direction perpendicular to the main surface.

56. 56. The array substrate of claim 55, wherein the pixel electrode and the common electrode form a main storage capacitor, and a capacitance ratio between the second capacitor and the main storage capacitor is 0.02 or greater.

57. 57. The array substrate of claim 56, wherein a capacitance ratio between the second capacitor and the main storage capacitor is 0.2 or less.

58. 58. The array substrate according to claim 57, wherein a capacitance ratio between the second capacitor and the main storage capacitor is equal to or greater than 0.06 and equal to or less than 0.

08.

59. A display device comprising the array substrate according to any one of claims 1 to 58.

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