Multi-process substrate treatment for improved substrate doping

Abstract

A method of doping a substrate may include exposing a substrate surface of a semiconductor substrate to plasma cleaning, and after the plasma cleaning, depositing a dopant layer on the substrate surface using a plasma source, the dopant layer comprising a dopant element, and exposing the substrate to an implantation process while the dopant layer is being deposited on the substrate surface, the implantation process comprising introducing an ion species comprising the dopant element into the substrate. The substrate is maintained under vacuum during the plasma cleaning, dopant layer deposition, and implantation process, and during the implantation process, at least a portion of the dopant layer is implanted into the substrate.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Patent Application No. 17 / 980,900, filed November 4, 2022. The contents of the prior application are incorporated herein by reference in their entirety.

[0002] The present embodiments relate to methods for doping a substrate, and more particularly to methods for three-dimensional doping. [Background technology]

[0003] As the dimensions of semiconductor devices, such as logic and memory devices, shrink, the use of conventional processes and materials for fabricating semiconductor devices becomes increasingly problematic. As an example, new approaches for doping semiconductor structures, such as alternatives to ion implantation, are being investigated. For example, in future technology generations, transistors may be formed in three-dimensional structures, such as horizontal gate-all-around (HGAA) structures, in which the active region is formed using so-called nanowires. Doping such high-performance devices may involve ion implantation to introduce dopant ions into the substrate, a process that may be followed by an annealing step to activate the dopants. Among other things, there is a need to achieve very high dopant activation while maintaining shallow dopant junction depths compatible with the dimensions of the high-performance devices.

[0004]

[0004] It is with respect to these considerations and others that this disclosure is presented. Summary of the Invention

[0005] This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended as an aid in determining the scope of the claimed subject matter.

[0006] In one embodiment, a method for doping a substrate may include exposing a substrate surface of a semiconductor substrate to plasma cleaning and, after the plasma cleaning, depositing a dopant layer on the substrate surface using a plasma source. The dopant layer includes a dopant element. The method may include exposing the substrate to an implantation process while the dopant layer is being deposited on the substrate surface. The implantation process includes introducing ion species including the dopant element into the substrate. The semiconductor substrate may be maintained under vacuum during the plasma cleaning, dopant layer deposition, and implantation process. During the implantation process, at least a portion of the dopant layer is implanted into the substrate.

[0007] In another embodiment, a method for doping a substrate may include providing a single-crystal semiconductor material on a surface of the substrate and exposing the surface of the substrate to a plasma cleaning, whereby native oxide is removed from the surface. The method may include, after the plasma cleaning, depositing a dopant layer on the surface of the substrate using a plasma source. The dopant layer includes a dopant element. The method may further include exposing the substrate to an implantation process as the dopant layer is being deposited on the surface of the substrate. The implantation process introduces ion species including the dopant element into the substrate. The substrate may be maintained under vacuum during the plasma cleaning, the dopant layer deposition, and the implantation process. During the implantation process, at least a portion of the dopant layer is implanted into the substrate.

[0008] In a further embodiment, a method for doping a semiconductor substrate may include providing a semiconductor substrate in a beam-line ion implanter and exposing a surface of the semiconductor substrate to plasma cleaning. The method may include, after the plasma cleaning, depositing a dopant layer on the substrate surface using a plasma source. The dopant layer includes a dopant element. The method may include exposing the semiconductor substrate to an implantation process while the dopant layer is being deposited on the substrate surface. The implantation process includes introducing ion species including the dopant element into the semiconductor substrate. The semiconductor substrate may be maintained under vacuum in the beam-line ion implanter during the plasma cleaning, dopant layer deposition, and implantation process. During the implantation process, at least a portion of the dopant layer is driven into the substrate. [Brief explanation of the drawings]

[0009] [Figure 1A-E] 1 illustrates exemplary operations related to doping a substrate according to an embodiment of the present disclosure. [Figure 2A-B] 1A and 1B show exemplary dopant profiles for boron and phosphorus, respectively, of a substrate processed according to the present embodiment. [Figure 3] 1 illustrates an exemplary ion implanter according to some embodiments of the present disclosure. [Figure 4] 1 illustrates an exemplary process flow. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0013] The present embodiments will now be described more fully with reference to the accompanying drawings, which show several embodiments. The subject matter of this disclosure may be embodied in a variety of different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. Like numbers refer to like elements throughout the drawings.

[0011]

[0014] In the present embodiment, the inventors have recognized a novel approach that facilitates improved doping of semiconductor structures, such as single crystal semiconductor materials. In various non-limiting embodiments, suitable semiconductor structures include silicon, silicon-germanium alloys (SiGe), or silicon-phosphorus alloys.

[0012]

[0015] 1A-E illustrate exemplary operations related to doping a substrate, according to embodiments of the present disclosure. With particular reference to FIG. 1A, a first instance is shown in which a semiconductor substrate 100 is provided within an ion implanter 102 or system. The ion implanter 102 may represent a beamline ion implanter in some non-limiting embodiments, or may represent other equipment suitable for performing ion implantation. The ion implanter 102 may include one or more chambers or locations that house the semiconductor substrate 100 during various processes being performed.

[0013]

[0016] It will be appreciated that high vacuum conditions are maintained while the semiconductor substrate 100 is positioned within the ion implanter 102. For example, during ion implantation of the semiconductor substrate 100, the end station housing the semiconductor substrate 100 may be heated to 1000 K. -3 Vacuum levels below 10 torr can be maintained during other processing operations, such as plasma-based operations. -1 A vacuum level below 10 torr can be maintained during idle periods, in accordance with a non-limiting embodiment of the present disclosure. -4 A vacuum level of less than 1000 torr can be maintained. Additionally, exposure to ambient gas species outside of the ion implanter 102 can be prevented during the operations shown in Figures 1A-E.

[0014]

[0017] At the stage depicted in FIG. 1A , a semiconductor substrate 100 may be placed in an ion implanter after undergoing processing through multiple operations to synthesize a device (e.g., a logic device, a memory device, or other device that undergoes implantation processing for doping purposes). In the illustrated example, the semiconductor substrate 100 includes a substrate base 104 formed from a single-crystal semiconductor material. In some embodiments, the semiconductor substrate 100 may include a native oxide layer 106 located on a surface 105. As depicted in FIG. 1A , the substrate base 104 and native oxide layer 106 may represent any suitable portion of a semiconductor substrate, including patterned regions of a semiconductor device, such as source / drain regions, according to various embodiments of the present disclosure. The native oxide layer 106 may represent a layer formed after processing to remove any other material from the surface of the substrate base 104. The formation of native oxides in silicon and similar semiconductors is well known and will not be described in detail herein. However, even if single crystal silicon is treated to remove any oxides or non-silicon materials from its outer surface, native oxides may still form when exposed to oxygen-containing atmospheres (including water vapor) (e.g., the ambient air of a vacuum processing tool). Furthermore, the thickness of the native oxide tends to be self-limiting, and in some non-limiting embodiments, the thickness of the native oxide layer 106 may be estimated to be no more than 4 nm to 8 nm.

[0015]

[0018] 1B, a subsequent example is shown in which the surface 105 of the semiconductor substrate 100 is exposed to a plasma cleaning operation. Initially, the surface 105 may be covered with up to a few nanometers of native oxide, as represented by the native oxide layer 106. In some embodiments, the plasma cleaning operation may utilize a plasma source 110 located within the ion implanter 102. The plasma source 110 may represent any suitable device for generating a plasma. In some cases, it may represent a radical source. In either case, the plasma source 110 may generate cleaning species 108, which may represent a combination of ions and neutrals, including radicals.

[0016]

[0019] For cleaning species 108, including ions during plasma cleaning operations, the energy of the ions may be maintained below 100 eV (e.g., in the range of a few eV to 30 eV) in some non-limiting embodiments. In some embodiments, the cleaning species 108 may represent known reactive species that tend to chemically react to etch the native oxide layer 106, even if the energy of such reactive species is on the order of a few eV. In various embodiments, the cleaning species 108 may selectively etch the native oxide layer 106 relative to the substrate base 104. Thus, due to the low energy of the hydrogen species 108, the native oxide layer 106 may be removed from the substrate base 104 with little or no etching of or damage to the substrate base 104.

[0017]

[0020] 1B can be achieved by generating hydrogen species within the plasma chamber of the plasma source 110 and directing the hydrogen species to the surface 105 while the substrate is at a cleaning temperature between room temperature and 100°C. The hydrogen species can be generated, for example, by supplying H gas to the plasma chamber. Thus, the surface 105 may represent a "clean" semiconductor surface that provides silicon species to the environment within the ion implanter 102, with minimal or no foreign species, such as oxygen or carbon, present on the surface 105.

[0018]

[0021] In some embodiments, a plasma cleaning operation may involve multiple sub-operations. For example, a first plasma cleaning sub-operation may be performed by generating cleaning species from a plasma source that react to remove some or all of the native oxide layer 106. This cleaning species may be, for example, a species other than hydrogen. A second plasma cleaning sub-operation may involve generating a hydrogen plasma, directing the hydrogen species to the surface 105, removing residual oxide, carbon, or other contaminants, and terminating the surface 105 with hydrogen passivation. In other embodiments, hydrogen species alone may be used to remove the native oxide layer and hydrogen terminate the surface 105. In either case, the plasma cleaning operation may be completed by generating a hydrogen plasma, directing the hydrogen species to the surface 105, and forming hydrogen passivation on the surface 105. In other words, the plasma cleaning operation of FIG. 1B may be considered to include the sub-operation of removing the native oxide layer followed by hydrogen terminating the surface 105. Similarly, in some embodiments, the "cleaning species" 108 can represent multiple species (e.g., separate non-hydrogen species for etching the native oxide layer 106 and hydrogen species for hydrogen passivating the surface 105 after removing the native oxide layer 106).

[0019]

[0022] 1C, a subsequent example of FIG. 1B is shown in which deposition of a dopant layer 116 is performed on the surface 105 of the semiconductor substrate 100. Deposition may be performed by a plasma source 114 located within the ion implanter 102. In some embodiments, the plasma source 114 may or may not be the same plasma source as the plasma source 110. Deposition of the dopant layer 116 may be performed by generating dopant species containing the dopant element. The dopant species 112 may be ions or radicals and, in some non-limiting embodiments, may be introduced to the surface 105 when the semiconductor substrate 100 is at a substrate temperature between room temperature and −100° C. The dopant species 112 may be formed by supplying a precursor gas, such as a boron-containing or phosphorus-containing species (e.g., BF, BF, or PF), to the plasma source 110. The gas is ionized and decomposed to form activated species represented by the dopant species 112. When condensing to form dopant layer 116, dopant species 112 may further decompose, leaving primarily the dopant element, such as boron or phosphorus, to form dopant layer 116.

[0020]

[0023] In various non-limiting embodiments of the present disclosure, the dopant species 112 may be delivered to the surface 105 at an energy that may vary from a few eV to 100 eV. In this manner, the energy of the dopant species 112 may be such that little sputtering occurs during deposition of the dopant species 112 and little damage occurs to the surface 105 or nearby regions (including implantation of the dopant species 112 and associated collision cascades within the substrate base 104).

[0021]

[0024] According to various embodiments, dopant layer 116 may have a thickness in the range of 1 nm to 7 nm after deposition is complete, at the processing stage depicted in Figure 1C. As discussed further below, this thickness may be adjusted according to various considerations, including the target dopant concentration in substrate base 104 near surface 105, the target contact resistance of the device being formed, the target junction depth of the source / drain junctions being formed, and other factors.

[0022]

[0025] 1D , a subsequent example is shown in which a dopant layer is disposed on the substrate surface, and the semiconductor substrate 100 is exposed to an implantation process on the surface 105 when the dopant layer is placed in the ion implanter 102. The implantation process thereby introduces ion species 118 containing the dopant element into the semiconductor substrate 100 (particularly the substrate base 104). Note that the ion species 118 may be provided as an ion beam, for example, in a beamline ion implanter. In some embodiments, the ion species 118 may be provided as an analyzed ion beam containing the same dopant element as the dopant element of the dopant layer 116. Thus, the analyzed ion beam may have a well-defined ion energy and composition for the ion species 118.

[0023]

[0026] In various non-limiting embodiments, the ionic species 118 can have an ion energy between 500 eV and 7 keV, depending on the material of the ionic species 118 and the thickness of the dopant layer 116. This process is generally illustrated in FIG. 1E, which represents a case following that of FIG. 1D. In this case, most or all of the dopant layer 116 may be absent from the surface 105. Additionally, a doped layer 120 is formed within the substrate base 104. The doped layer 120 may be formed by direct implantation of the ionic species 118 into the substrate base 104 and driving dopant material from the dopant layer 116 into the substrate base, for example, as a result of knock-on collisions from the ionic species 118. In other words, the implantation range of the ionic species 118 may be greater than the thickness of the dopant layer 116 prior to the implantation process, such that at least some ions of the ionic species 118 are directly implanted within the substrate base 104. Thus, doped layer 120 may represent a mixture of dopants from dopant layer 116 and dopants from ionic species 118 .

[0024]

[0027] 1B-E can be repeated periodically to achieve a target implant dose within the substrate. In other words, the plasma cleaning, dopant layer deposition, and implantation processes can be performed as an implantation cycle. The implantation cycle is repeated one or more times to implant a target dopant level within the substrate.

[0025]

[0028] Referring to FIG. 2A, an experimental example of a dopant profile for a semiconductor substrate processed according to an embodiment of the present disclosure, and in particular according to the operations of FIGS. 1A-1E, is shown. FIG. 2A is a graph of boron concentration as a function of depth in a silicon substrate. As previously described, the silicon substrate is processed, where boron is introduced into the silicon substrate, followed by a plasma clean of the silicon substrate, a boron deposition process, and a treatment implant. FIG. 2A shows the results of a dopant profile for three different thicknesses of dopant layer 116 (2 nm, 3 nm, and 4 nm) using 3 keV BF2 and 5E15 / cm3. 2 Figure 2A shows a series of curves for ion implantation at 3 keV BF2 and 5E15 / cm ion dose and activation annealing at 1000 °C. 2 Also shown is a control curve illustrating the boron dopant profile for an ion implantation process with an ion dose of 0.05E21 / cm followed by an activation anneal at 1000°C without any dopant layer. Note that in Figure 2A, the outer surface of the silicon substrate is represented by a depth of 0 along the X-axis. Thus, the boron concentration at a depth of 1-3 nm below the outer surface is very high, approximately 5E21 / cm. 3 ~5E22 / cm 3 Furthermore, within the illustrated thickness range of the dopant layer 116, the boron concentration near the substrate surface increases with increasing thickness, specifically between 2 nm and 3 nm. In contrast, the boron concentration near the substrate surface of the control sample is relatively low, at 5E21 / cm 3 Furthermore, the junction depth is shallower in the sample with the dopant layer 116 compared to the sample without the dopant layer 116. Furthermore, the junction depth decreases with increasing dopant layer thickness, by at least 4 nm.

[0026]

[0029] FIG. 2B shows a dopant profile of boron doping for a substrate processed according to the present embodiment, where an additional (“adjusted”) curve has been added to those shown in FIG. 2A. In this example, a substrate having a 3 nm dopant layer 116 was processed according to the process of FIGS. 1A-1E. In this case, the adjusted curve shows processing conditions where the implant energy and boron dose were adjusted so that the junction depth substantially matched that of the control sample. However, the surface concentration of boron dopant is much higher than that of the control sample. This demonstrates that the present embodiment provides a mechanism for adjusting the junction depth, for example, to about 10 nm from the surface, independently of the dopant concentration (particularly the dopant concentration near the surface).

[0027]

[0030] In other embodiments of the present disclosure, the above approach of in-situ plasma cleaning, in-situ plasma deposition of a dopant layer, and then ion implantation may be utilized for phosphorus to provide better control of dopant concentration and junction depth.

[0028]

[0031] In accordance with embodiments of the present disclosure, the approach outlined with respect to FIGS. 1A-1E has been implemented on a device substrate and various measurements have confirmed superior performance compared to devices implanted with dopants without the operations of FIGS. 1A-1C. Examples of improved performance include reduced contact resistance of source / drain contacts formed on the doped substrate, reduced on-current (I ON ) and OFF current (I OFF ) reduction.

[0029]

[0032] Without being limited to any particular theory, the improved doping engineering achieved in accordance with the present embodiments (greater control of surface dopant concentration and better control of junction depth) can be realized in part by preserving a semiconductor surface that is largely or completely free of native oxide. During the ion implantation process, many silicon interstitials are created in the bulk of the semiconductor substrate being implanted. These silicon interstitials migrate within the semiconductor substrate, even at room temperature. If native oxide is present, the interstitials can reflect back into the bulk of the semiconductor substrate, causing defects and passivation, which can enhance dopant diffusion. The multi-process substrate processing disclosed herein addresses this issue as follows: While plasma cleaning within the ion implanter removes native oxide from the surface of the semiconductor substrate, maintaining the semiconductor substrate under high vacuum conditions tends to keep the semiconductor surface free of native oxide until dopant deposition is performed. This native-oxide-free surface can expose a rich layer of silicon dangling bonds, which allows the silicon interstitials to terminate at the surface. This end-treatment results in enhanced dopant activation, reduced defects, and reduced interstitial-enhanced diffusion of dopant species. This reduced dopant diffusion and enhanced activation within the semiconductor substrate can be further enhanced by the presence of a dopant deposition layer on the surface during ion implantation of the dopant species. During the resulting knock-in process of ion implantation, the surface concentration of dopants can be increased without excessively increasing the depth of the dopant profile within the semiconductor substrate, resulting in relatively low junction depths. Specifically, this result is achieved because the entire process sequence, including plasma cleaning, dopant layer deposition, and ion implantation, is completed in an integrated beamline architecture that maintains the substrate under a common vacuum.

[0030]

[0033] Referring to FIG. 3 , an exemplary ion implantation system architecture, designated as ion implanter 300, is illustrated in block form in accordance with an embodiment of the present disclosure. The ion implanter 300 includes an ion source 302 that generates an ion beam 318 for implanting ion species 118, as described above. The ion implanter 300 may include various components for accelerating, decelerating, shaping, and filtering the ion beam, as known in the art. These components are designated as a beam line 304. Downstream of the beam line 304 is an end station 306 for receiving the substrate 110 during ion implantation. The ion implanter 300 may include a plasma cleaning chamber 308 as well as a plasma doping chamber 310. These chambers may be a single chamber or separate chambers communicatively coupled to the end station 306. This allows the semiconductor substrate 100 to be transferred between different chambers while being maintained in a vacuum environment for processing, as generally illustrated in FIGS. 1A-1C . In other embodiments, one or more of plasma source 110 and plasma source 114 may be included within end station 306 .

[0031]

[0034] 4, an exemplary process flow 400 according to an embodiment of the present disclosure is shown. Block 402 involves providing a semiconductor substrate in an ion implanter, the semiconductor substrate including a single-crystal semiconductor material on a first surface. It will be appreciated that the first surface may have a native oxide coating that extends up to several nanometers above the first surface. Thus, in this case, the first surface of the single-crystal semiconductor material may be located several nanometers below the outer surface of the semiconductor substrate.

[0032]

[0035] In block 404, a plasma cleaning operation is performed on the semiconductor substrate to remove native oxide from the first surface of the semiconductor substrate. The plasma cleaning can be performed at relatively low energies, such as a few eV to tens of eV, using appropriate species. Examples of suitable species include hydrogen ions or hydrogen radicals and related species. In this manner, the plasma cleaning can remove native oxide without damaging the single-crystalline semiconductor material extending over the first surface.

[0033]

[0036] In block 406, when the semiconductor substrate is placed in the ion implanter, deposition of a dopant layer occurs on the first surface. Deposition of the dopant layer can be performed using a plasma source that provides relatively low-energy ion or radical species, for example, having an energy of less than 100 eV. The dopant layer can have a suitable thickness, such as 1 nm to 7 nm, or 2 nm to 4 nm, according to some non-limiting embodiments.

[0034]

[0037] In block 408, when the dopant layer is disposed on the first surface of the semiconductor substrate, the substrate is exposed to an ion implantation process. The implantation process may involve ion species derived from a plasma source, and the ion energy may range up to 7 keV in some non-limiting embodiments. In this operation, at least a portion of the dopant layer may be implanted into the semiconductor substrate. In other words, during the implantation process, the ion species may drive at least some atoms of the dopant layer into the semiconductor substrate immediately adjacent to the dopant layer.

[0035]

[0038] In view of the above, the present disclosure provides the following advantages. First, by performing multiple process steps to dope a substrate, defects can be reduced, dopant diffusion can be reduced, and dopant activation can be enhanced. Second, dopant concentration can be increased without affecting the depth of the dopant profile, such as junction depth.

[0036]

[0039] The present disclosure should not be limited in scope by the specific embodiments described herein. Indeed, various other embodiments of the present disclosure and modifications thereof, in addition to the embodiments described herein, will be apparent to those skilled in the art from the foregoing description and the accompanying drawings. Accordingly, such other embodiments and modifications are intended to be included within the scope of the present disclosure. Furthermore, although the present disclosure is described herein in the context of particular implementations in particular environments for particular purposes, those skilled in the art will recognize that the usefulness of the present embodiments is not limited to such contexts, and that the present embodiments may be beneficially implemented in any number of environments for any number of purposes. Therefore, the claims set forth below should be construed in light of the full scope and nature of the present disclosure as described herein.

Claims

1. 1. A method of doping a semiconductor substrate, comprising: exposing a substrate surface of the semiconductor substrate to plasma cleaning; after the plasma cleaning, depositing a dopant layer on the substrate surface using a plasma source, the dopant layer comprising a dopant element; exposing the semiconductor substrate to an implantation process while the dopant layer is being deposited on the substrate surface, the implantation process including introducing ion species including the dopant element into the substrate; wherein the substrate is maintained under vacuum during the plasma cleaning, the deposition of the dopant layer, and the implantation process; A method of doping a semiconductor substrate, wherein during the implantation process, at least a portion of the dopant layer is implanted into the substrate.

2. The method of claim 1 , wherein the substrate surface includes a native oxide prior to the plasma cleaning, and the native oxide is removed after the plasma cleaning.

3. The plasma cleaning generating hydrogen species in a plasma chamber; directing the hydrogen species to the substrate surface while the substrate is at a cleaning temperature between room temperature and 100°C; The method of claim 1 , wherein the substrate surface is terminated with a hydrogen passivation after the plasma cleaning.

4. performing said depositing generating dopant species in the plasma source, the dopant species comprising a dopant element; directing the dopant species to the substrate surface when the substrate temperature is between room temperature and -100°C; The method of claim 1 , comprising:

5. The method of claim 4 , wherein the dopant species comprises a boron-containing species or a phosphorus-containing species.

6. The method of claim 4 , wherein the dopant species comprises an energy of a few eV to 100 eV.

7. The method of claim 4 , wherein the dopant layer comprises a thickness of 1 nm to 7 nm before the implantation process.

8. The dopant element is BF ３ or PF ３ 10. The method of claim 1, wherein the ion species is derived from a dopant species comprising:

9. 8. The method of claim 7, wherein the implantation range of the ionic species is greater than the thickness of the dopant layer before the implantation process.

10. 10. The method of claim 1, wherein the plasma cleaning, the deposition of the dopant layer, and the implantation process are performed as an implantation cycle, and the implantation cycle is repeated one or more times to implant a target dopant level into the semiconductor substrate.

11. 1. A method of doping a substrate, comprising: providing a single crystal semiconductor material on a surface of the substrate; exposing the surface to a plasma clean, wherein native oxide is removed from the surface; after the plasma cleaning, depositing a dopant layer on the surface of the substrate using a plasma source, the dopant layer comprising a dopant element; exposing the substrate to an implantation process while the dopant layer is being deposited on the substrate surface, the implantation process including introducing ion species including the dopant element into the substrate; wherein the substrate is maintained under vacuum during the plasma cleaning, the deposition of the dopant layer, and the implantation process; A method of doping a substrate, wherein during the implantation process at least a portion of the dopant layer is implanted into the substrate.

12. The plasma cleaning generating hydrogen species in a plasma chamber; directing the hydrogen species to the surface of the substrate while the substrate is at a cleaning temperature between room temperature and −100° C.; The method of claim 11 , wherein the surface of the substrate is terminated with a hydrogen passivation after the plasma cleaning.

13. performing said depositing generating dopant species in the plasma source, the dopant species comprising a dopant element; directing the dopant species to the surface of the substrate while the substrate is at a substrate temperature between room temperature and 100°C; The method of claim 11 , comprising:

14. 14. The method of claim 13, wherein the dopant species comprises an energy of a few eV to 100 eV.

15. 12. The method of claim 11, wherein the dopant layer comprises a thickness of 1 nm to 7 nm before the implantation process, and the implantation range of the ionic species is greater than the thickness of the dopant layer before the implantation process.

16. 1. A method of doping a semiconductor substrate, comprising: providing the semiconductor substrate in the beamline ion implanter; exposing a substrate surface of the semiconductor substrate to plasma cleaning; after the plasma cleaning, depositing a dopant layer on the substrate surface using a plasma source, the dopant layer comprising a dopant element; exposing the substrate to an implantation process while the dopant layer is being deposited on the substrate surface, the implantation process including introducing ion species including the dopant element into the semiconductor substrate; wherein the substrate is maintained under vacuum in the beam-line ion implanter during the plasma cleaning, the deposition of the dopant, and the implantation process; A method of doping a semiconductor substrate, wherein during the implantation process at least a portion of the dopant layer is driven into the semiconductor substrate.

17. 17. The method of claim 16, wherein the substrate surface comprises a native oxide prior to the plasma cleaning, the native oxide is removed after the plasma cleaning, and the substrate surface is terminated with a hydrogen passivation after the plasma cleaning.

18. performing said depositing generating dopant species in the plasma source, the dopant species comprising a dopant element; directing the dopant species to the semiconductor substrate surface while the semiconductor substrate is at a substrate temperature between room temperature and 100°C; 17. The method of claim 16, comprising:

19. 17. The method of claim 16, wherein the dopant layer comprises a thickness of 1 nm to 7 nm before the implantation process, and the implantation range of the ionic species is greater than the thickness of the dopant layer before the implantation process.

20. 17. The method of claim 16, wherein the plasma cleaning, the deposition of the dopant layer, and the implantation process are performed as an implantation cycle, and the implantation cycle is repeated one or more times to implant a target dopant level into the substrate.

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