Die-to-die bonding package architecture using glass interposer

Abstract

An embodiment of a microelectronic assembly includes a glass interposer structure, a substrate including an organic dielectric material coupled to a first side of the interposer structure, and a plurality of IC dies, wherein a first IC die of the plurality of IC dies is coupled to the substrate by a first interconnect, a second IC die of the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by a second interconnect, the second IC die is coupled to the first side of the interposer structure by a third interconnect, and a third IC die of the plurality of IC dies is coupled to a second side of the interposer structure by a fourth interconnect, the second side of the interposer structure opposite the first side of the interposer structure.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of the priority date of U.S. Application No. 17 / 937,519, filed October 3, 2022.

[0002] The present disclosure relates to techniques, methods, and apparatus for die-to-die bonding package architectures using glass interposers. [Background technology]

[0003] Electronic circuits are generally called integrated circuits (ICs) when they are fabricated on wafers of semiconductor material, such as silicon. Wafers containing such ICs are typically cut into many individual dies. The dies, along with other electronic components such as resistors, capacitors, and inductors, may be packaged into IC packages containing one or more dies. The IC packages may be integrated into electronic systems, such as consumer electronic systems, or servers, such as mainframes.

[0004] The embodiments will be readily understood from the following detailed description read in conjunction with the accompanying drawings, in which: To facilitate this description, like reference numerals refer to like structural elements; and the embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. [Brief explanation of the drawings]

[0005] [Figure 1A] 1 is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 1B] FIG. 1B is a schematic top view of the microelectronic assembly of FIG. 1A. [Figure 2] 1 is a schematic cross-sectional view of a portion of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 3] 1 is a schematic cross-sectional view of a portion of an exemplary microelectronic assembly according to some other embodiments of the present disclosure. [Figure 4]10 is a schematic cross-sectional view of a portion of another exemplary microelectronic assembly according to some other embodiments of the present disclosure. [Figure 5A] 10 is a schematic cross-sectional view of a portion of a passive component of an exemplary microelectronic assembly according to some other embodiments of the present disclosure. [Figure 5B] FIG. 5B is a schematic top view of a portion of the microelectronic assembly of FIG. 5A. [Figure 6] 10 is a schematic cross-sectional view of a portion of a passive component of an exemplary microelectronic assembly according to some other embodiments of the present disclosure. [Figure 7A] 1 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 7B] FIG. 7B is a schematic top view of the microelectronic assembly of FIG. 7A. [Figure 8] FIG. 1 is a simplified flow diagram illustrating various operations that may be associated with manufacturing an exemplary microelectronic assembly, according to various embodiments. [Figure 9] FIG. 1 is a cross-sectional view of a device package including one or more microelectronic assemblies according to any of the embodiments disclosed herein. [Figure 10] FIG. 1 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any of the embodiments disclosed herein. [Figure 11] FIG. 1 is a block diagram of an exemplary computing device including one or more microelectronic assemblies according to any of the embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0006] overview In order to illustrate the IC packages described herein, it is important to understand the phenomena that can occur during IC assembly and packaging. The following basic information can be viewed as a basis for properly explaining the present disclosure. Such information is provided for illustrative purposes only and, therefore, should not be construed as limiting the broad scope of the present disclosure and its potential applications.

[0007] As Moore's Law approaches its natural limits, supercomputing faces inherent physical challenges in the transition to zetascale systems. Zetascale computing aims to achieve a level of computing 1,000 times greater than current levels by around the second half of this decade to capitalize on the high demand for computing resources by both consumers and businesses and implement data-intensive applications such as artificial intelligence and machine learning. Zetascale supercomputers aim to have computing performance on the order of 1 zetaflop. One zetaflop is equivalent to 1,000 exaflops, or one sextillion floating-point operations per second. Although advances in semiconductor processing and logic design have made it possible to increase the number of logic circuits that can be contained in processors and other integrated circuit devices, signal speeds have reached physics-based bottlenecks to achieving zetascale performance due to the inherent limitations of materials used for signal propagation, such as copper as a dielectric medium, heat transfer challenges due to high-intensity calculations, and the inherent constraints of power supplies to run thousands of simultaneous calculations across multiple processors.

[0008] Many processors used in current supercomputers and other processing devices already have multiple cores monolithically integrated on a single die. These types of monolithic ICs are generally called planar because they have a planar geometry and are constructed on a single silicon wafer, typically fabricated from a single-crystal silicon boule. The typical manufacturing process for such monolithic ICs is called a planar process, in which photolithography, etching, thermal diffusion, oxidation, and other processes are performed on the surface of the wafer to form active circuit elements (e.g., transistors and diodes) on the planar surface of the silicon wafer. Current technology allows hundreds or even thousands of active circuit elements to be formed on a single die, enabling numerous logic circuits to be enabled on it. Such monolithic dies require the manufacturing process to be optimized equally for all circuits, resulting in tradeoffs between different circuits. Furthermore, the constraints of having to arrange circuits on a planar surface mean that some circuits are placed farther apart from other circuits, resulting in longer delays and other performance degradation. This can also significantly impact manufacturing yields, as a single circuit failure may require the entire die to be scrapped.

[0009] As a result, the processor industry trend is toward decentralization, using multiple known-good chiplets (smaller-sized IC dies) manufactured using different manufacturing techniques and assembling them into a single microprocessor using new bonding techniques. The smaller dies are part of an assembly of interconnected dies that together form a complete IC in terms of application and / or function, such as memory chips, microprocessors, microcontrollers, commodity ICs (e.g., chips used for repetitive processing routines, simple tasks, application-specific ICs, etc.), and systems-on-chips (SOCs). In other words, the individual dies are connected to form the functionality of the monolithic IC. The use of separate dies allows each die to be optimally designed and manufactured for its specific function. For example, a processor core containing logic circuits may be targeted for performance and therefore require a highly speed-optimized layout. This has different manufacturing requirements compared to a USB controller built to meet a specific Universal Serial Bus (USB) standard, rather than processing speed. Thus, separating various parts of the overall design onto different dies, each optimized from a design and manufacturing perspective, can improve the overall yield and cost of the combined die solution.

[0010] The connections between these dies can be achieved in many ways. For example, in 2.5D packaging solutions, silicon interposers and through-silicon vias (TSVs) connect dies at silicon interconnect speeds in a minimal footprint. Some such architectures also use bridge dies to provide lateral connections between adjacent IC dies. In another example, a silicon bridge embedded under the edges of two interconnecting dies facilitates electrical coupling between them. In three-dimensional (3D) architectures, dies are stacked one on top of the other to reduce the overall footprint. Typically, electrical and mechanical connections in such 3D architectures are achieved using TSVs and high-pitch solder-based bumps (e.g., C2 interconnects). Combining bridge and 3D stack architectures also allows the top-packaged chip to communicate with other chips horizontally using bridges and vertically using through-mold vias (TMVs), which are typically larger than TSVs. However, these current interconnect technologies use silicon-based interposers, which can be costly, or organic interposers, which can be error-prone and unsuitable for fine-pitch interconnects.

[0011] Accordingly, embodiments described herein enable a microelectronic assembly including a glass interposer structure, a substrate including an organic dielectric material (the substrate bonded to a first side of the interposer structure), and a plurality of IC dies, where a first IC die of the plurality of IC dies is bonded to the substrate by a first interconnect, a second IC die of the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is bonded to the first IC die by a second interconnect, the second IC die is bonded to the first side of the interposer structure by a third interconnect, and a third IC die of the plurality of IC dies is bonded to a second side of the interposer structure by a fourth interconnect, the second side of the interposer structure being opposite the first side of the interposer structure.

[0012] Various other embodiments of the microelectronic assemblies disclosed herein include a package substrate including an interposer layer including glass, a substrate layer on a first side of the interposer layer, the substrate layer including an organic dielectric material, and a plurality of IC dies coupled to a second side of the interposer layer by interconnects, the second side being opposite the first side, wherein the IC dies of the plurality of IC dies are conductively coupled to each other by first conductive structures of the interposer layer, the substrate layer includes second conductive structures of the organic dielectric material, and TGVs of the interposer layer conductively couple the plurality of IC dies to the second conductive traces.

[0013] Embodiments disclosed herein further include a method, the method including the steps of providing a substrate including conductive traces of multiple layers of organic dielectric material, attaching an interposer structure including glass to the substrate, attaching multiple IC dies to the interposer structure, and conductively coupling the multiple IC dies via the interposer structure.

[0014] Each of the structures, assemblies, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described herein are set forth in the following description and accompanying drawings.

[0015] In the following detailed description, various aspects of the exemplary embodiments may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

[0016] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a desired function. These terms also refer to analog circuits, digital circuits, hardwired circuits, programmable circuits, microcontroller circuits, and / or other types of physical hardware electrical and / or electronic components.

[0017] The term "integrated circuit" means a circuit integrated into a monolithic semiconductor or similar material.

[0018] In some embodiments, the IC die disclosed herein can include a substantially single-crystalline semiconductor, such as silicon or germanium, as a base material (e.g., substrate, body) from which the integrated circuit is fabricated using conventional semiconductor processing methods. The semiconductor base material can include, for example, an N-type or P-type material. The die can include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In other embodiments, the base material of one or more IC dies can include alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium arsenide gallium, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In yet other embodiments, the base material can comprise a compound semiconductor including, for example, a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In yet other embodiments, the base material can include an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with electrically active impurities. In alternative embodiments, nominal impurity dopant levels may be present. In yet other embodiments, the die can include an amorphous material such as a polymer; for example, the base material can include silica-filled epoxy. In other embodiments, the base material can include a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.Generally, the base material includes one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxide oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdate, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, which may each be gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, magnesium, etc. Although some example die materials are described herein, any material or structure capable of serving as a foundation (e.g., base material) for building IC circuits and structures as described herein is within the spirit and scope of the present disclosure.

[0019] Unless otherwise described, an IC die as described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a particular function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., ICs that implement one or more of: memory devices, memory arrays, control logic configured to control the memory devices and arrays, etc.). In another such example, the term "computing die" may be used to describe a die that includes one or more ICs that implement logic / computing circuitry (e.g., ICs that implement one or more of: I / O functions, arithmetic operations, data pipelining, etc.).

[0020] In other instances, the terms "package" and "IC package" are synonymous, and the terms "die" and "IC die" are synonymous. Note that the terms "chip," "die," and "IC die" are used interchangeably herein.

[0021] The term "optical structure," as described herein, includes an arrangement of features fabricated within an IC for receiving, converting, and / or transmitting optical signals, which may include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light-emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0022] In various embodiments, any photonic integrated circuit (PIC) described herein can have semiconductor materials, including, for example, N-type or P-type materials. PICs can include crystalline-based materials, for example, formed using bulk silicon (or other bulk semiconductor materials) or SOI structures (or, generally, semiconductor-on-insulator structures). In some embodiments, PICs can be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of III-N or IV materials. In some embodiments, PICs can include amorphous materials, such as polymers. In some embodiments, the PIC can be formed on a printed circuit board (PCB). In some embodiments, the PIC is heterogeneous and includes a carrier material (such as glass or silicon carbide) as a base material, on top of which is a thin semiconductor layer with an active surface containing components such as transistors. Some example materials for PICs are described herein, but any material or structure that can serve as a substrate upon which a PIC may be built is within the spirit and scope of the present disclosure.

[0023] Unless otherwise specified, the term "insulating" means "electrically insulating" and the term "conducting" means "electrically conducting." With respect to optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conducting" can also mean "optically conducting."

[0024] The terms "oxide," "carbide," "nitride," and the like refer to compounds that contain oxygen, carbon, nitrogen, and the like, respectively.

[0025] The term "high-k dielectric" refers to a material that has a higher dielectric constant than silicon dioxide, and the term "low-k dielectric" refers to a material that has a lower dielectric constant than silicon dioxide.

[0026] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a substantially non-conductive solid material (and / or a liquid material that solidifies after processing as described herein). These may include, by way of example and without limitation, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and alumina, or combinations thereof. These may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. These may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials include underfills and mold or mold-like materials used in packaging applications, including, for example, materials used in organic interposers, package supports, and other such components.

[0027] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those monolithically integrated within the IC, those mounted on the IC, or those connected to the IC. The ICs described herein may be either analog or digital and may be used in a variety of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The ICs described herein may be used in a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0028] In various embodiments of the present disclosure, the transistors described herein may be field-effect transistors (FETs), such as MOSFETs. In many embodiments, the FET is a four-terminal device. In silicon-on-insulator, nanoribbon, or gate-all-around (GAA) FETs, the FET is a three-terminal device that includes source, drain, and gate terminals and uses an electric field to control current through the device. FETs typically include a gate stack including a channel material, source and drain regions within and / or above the channel material, and a gate electrode material (also known as a "work function" material) above a portion of the channel material between the source and drain regions (the "channel portion"), and optionally a gate dielectric material between the gate electrode material and the channel material.

[0029] In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, facilitating the communication of electrical signals between them. An optical interconnect provides an optical connection between two optical components, facilitating the communication of optical signals between them. As used herein, both electrical and optical interconnects are included in the term “interconnect.” The nature of the interconnect being described should be understood herein with reference to its associated signal medium. Thus, when used with reference to an electronic device, such as an IC, that operates using electrical signals, the term “interconnect” refers to any element formed of a conductive material that provides electrical connection to one or more elements associated with the IC and / or between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (sometimes referred to as “lines,” “wires,” “metal lines,” or “trenches”) and conductive vias (sometimes referred to as “vias” or “metal vias”). Sometimes, conductive traces and vias may be referred to as “conductive traces” and “conductive vias,” respectively, to emphasize the fact that they include conductive materials such as metal. Similarly, when used with respect to devices that also operate with optical signals, such as photonic integrated circuits (PICs), the term "interconnect" may refer to any element formed of an optically conductive material to provide optical connectivity to one or more elements associated with the PIC. In such cases, the term "interconnect" may refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0030] The term "waveguide" typically refers to any structure that serves to guide the propagation of light from one location to another through a substrate material, such as silicon or glass. In various examples, waveguides may be formed from materials such as silicon, doped silicon, silicon nitride, silica (e.g., silicon dioxide, or SiO), and glasses such as borosilicates (e.g., 70-80 wt. % SiO, 7-13 wt. % BO, 4-8 wt. % NaO or KO, and 2-8 wt. % AlO). Waveguides may be formed using various techniques, including, but not limited to, in-situ waveguide formation. For example, in some embodiments, waveguides may be formed in-situ in glass using low-temperature glass-to-glass bonding or by direct laser writing. In-situ formed waveguides may have lower loss characteristics.

[0031] The term "conductive trace" may be used to describe conductive elements insulated (separated) by insulating material. Within an IC die, such insulating material includes interlayer low-k dielectrics disposed within the IC die. Within package substrates and PCBs, such insulating material includes organic materials such as Ajinomoto Build-Up Film (ABF), polyimide, or epoxy resin. Such conductive lines are typically arranged in multiple levels or layers of a metallization stack.

[0032] The term "conductive via" may be used to refer to a conductive element that interconnects two or more conductive lines at different levels of a metallization stack. For this purpose, a via is provided substantially perpendicular to the plane of the support structure on which the IC die / chip or IC structure is provided, and may interconnect two conductive lines at adjacent levels or two conductive lines at non-adjacent levels.

[0033] The term "package substrate" may be used to describe any substrate material that facilitates packaging together any collection of semiconductor dies and / or other electrical components, such as passive electrical components. As used herein, a package substrate may be formed from any material, including, but not limited to, insulating materials such as resin-impregnated fiberglass (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, a package substrate may refer to a substrate that includes build-up layers (e.g., ABF layers).

[0034] The term "metallization stack" may be used to refer to a stack of one or more interconnects to provide connections to different circuit components of an IC die / chip and / or package substrate.

[0035] As used herein, the term "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0036] In the context of a stack of die bonded to one another or a die bonded to a package substrate, the term "interconnect" can also refer to die-to-die (DTD) interconnects and die-to-package substrate (DTPS) interconnects, respectively. DTD interconnects can also be referred to as first-level interconnects (FLI). DTPS interconnects can also be referred to as second-level interconnects (SLI).

[0037] Although not specifically shown in all of the figures to avoid cluttering the drawings, when describing a DTD or DTPS interconnect, a surface of a first die may include a first set of conductive contacts, and a surface of a second die or package substrate may include a second set of conductive contacts, and one or more conductive contacts of the first set may be electrically and mechanically coupled to some of the conductive contacts of the second set by the DTD or DTPS interconnect.

[0038] In some embodiments, the pitch of the DTD interconnects may be different from the pitch of the DTPS interconnects, while in other embodiments, these pitches may be substantially the same.

[0039] The DTPS interconnects disclosed herein can take any suitable form. In some embodiments, the set of DTPS interconnects can include solder (e.g., solder bumps or balls that undergo thermal reflow to form the DTPS interconnects). DTPS interconnects including solder can include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, the set of DTPS interconnects can include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive material can include a conductive material dispersed in a non-conductive material. In some embodiments, the anisotropic conductive material can include fine conductive particles embedded in a binder or a thermosetting adhesive film (e.g., a thermosetting biphenyl-type epoxy resin or an acrylic material). In some embodiments, the conductive particles can include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles can include nickel-coated gold or silver-coated copper, further coated with a polymer. In another example, the conductive particles can include nickel. When an anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other. However, when the anisotropic conductive material is appropriately compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), conductive materials near the compressed region may contact each other and form a conductive path from one side of the film to the other in the compressed region.

[0040] The DTD interconnects disclosed herein can take any suitable form. In some embodiments, some or all of the DTD interconnects in a microelectronic assembly or IC package described herein may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, conductive contacts on either side of a DTD interconnect may be joined to one another (e.g., under high pressure and / or high temperature) without the use of an intervening solder or anisotropic conductive material. In some metal-to-metal interconnects, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the joined metals (e.g., between copper pads or posts that provide the associated conductive contacts). In some embodiments, one side of the DTD interconnect may include a metal pillar (e.g., a copper pillar), and the other side of the DTD interconnect may include a metal contact (e.g., a copper contact) embedded in a dielectric. In some embodiments, a metal-to-metal interconnect (e.g., copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal whose oxide is conductive (e.g., silver). In some embodiments, metal-to-metal interconnects can include metallic nanostructures (e.g., nanorods) that can reduce the melting point. Metal-to-metal interconnects can reliably conduct higher currents than other types of interconnects. For example, some solder interconnects can form brittle intermetallic compounds when current is passed through them, and the maximum current delivered through such interconnects can be limited to mitigate mechanical failure.

[0041] In some embodiments, the die on either side of a set of DTD interconnects may be bare die (eg, unpackaged die).

[0042] In some embodiments, the DTD interconnects may include solder. For example, the DTD interconnects may include conductive bumps or pillars (e.g., copper bumps or pillars) attached to respective conductive contacts by solder. In some embodiments, a thin solder cap may be used to ensure planarity in metal-to-metal interconnects, and this solder may become intermetallic during processing. In some embodiments, the solder used in some or all of the DTD interconnects may have a higher melting point than the solder included in some or all of the DTPS interconnects. For example, if the DTD interconnects in the IC package are formed before the DTPS interconnects are formed, the solder-based DTD interconnects may use a higher temperature solder (e.g., melting point above 200°C), while the DTPS interconnects may use a lower temperature solder (e.g., melting point below 200°C). In some embodiments, the high-temperature solder may include tin, tin and gold, or tin, silver, and copper (e.g., 96.5% tin, 3% silver, 0.5% copper). In some embodiments, the low temperature solder may include tin and bismuth (eg, eutectic tin bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0043] In some embodiments, the set of DTD interconnects may include an anisotropic conductive material, such as any of the materials discussed above for the DTPS interconnects. In some embodiments, the DTD interconnects may be used as data transfer lanes, while the DTPS interconnects may be used for power and ground lines, among other things.

[0044] In the microelectronic assemblies or IC packages described herein, some or all of the DTD interconnects may have a finer pitch than the DTPS interconnects. In some embodiments, the DTPS interconnects disclosed herein may have a pitch of approximately 80 micrometers to 300 micrometers, while the DTD interconnects disclosed herein may have a pitch of approximately 0.5 micrometers to 100 micrometers, depending on the type of DTD interconnect. Examples of silicon-level interconnect densities are provided by the densities of some DTD interconnects. In some embodiments, the DTD interconnects may have a pitch that is too fine to bond directly to the package substrate (e.g., too fine to function as a DTPS interconnect). The DTD interconnects may have a finer pitch than the DTPS interconnects because the material similarity between the different dies on either side of a set of DTD interconnects is greater than the material similarity between the die and package substrate on either side of the set of DTPS interconnects. In particular, differences in the material compositions of the die and package substrate may result in differential expansion and contraction of the die and package substrate due to heat generated during operation (and heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracks, solder bridges, etc.), the DTPS interconnects in any of the microelectronic assemblies or IC packages described herein may be larger and formed farther apart than DTD interconnects, which may experience less thermal stress due to the greater similarity of the materials in the pair of dies on either side of the DTD interconnect.

[0045] It is recognized that the IC packages described herein may be provided with an additional level of underfill (e.g., an organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy), which may not be labeled to avoid cluttering the drawings. In various embodiments, the levels of underfill may comprise the same or different insulating materials. In some embodiments, the levels of underfill may comprise a thermosetting epoxy containing silicon oxide particles. In some embodiments, the levels of underfill may comprise any suitable material capable of performing underfill functions such as supporting the die and relieving thermal stress on the interconnects. In some embodiments, the selection of the underfill material may be based on design considerations such as form factor, size, stress, and operating conditions. In other embodiments, the selection of the underfill material may be based on material properties and processing conditions such as cure temperature, glass transition temperature, viscosity, and chemical resistance, among others. In some embodiments, the selection of the underfill material may be based on both design and processing considerations.

[0046] In some embodiments, one or more levels of soldermask (e.g., epoxy liquid, liquid photopolymer, dry film photopolymer, acrylic, solvent) may be provided in the IC packages described herein and may not be labeled or shown to avoid cluttering the drawings. The soldermask may be a liquid or dry film material including a photopolymer. In some embodiments, the soldermask may not be photosensitive.

[0047] The terms "substantially," "close," "approximately," "near," and "about" generally refer to within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value) based on the context of a particular value described herein or known in the art.

[0048] Terms indicating the orientation of various elements, such as "coplanar," "vertical," "orthogonal," "parallel," or other angles between elements, generally refer to within + / - 5% to 20% of a target value based on the context of specific values ​​described herein or known in the art.

[0049] The term "connected" means that the things connected are directly connected together without any intermediate devices (which may be one or more of a mechanical, electrical, and / or thermal connection), and the term "coupled" means that the things connected are directly connected together or are indirectly connected through one or more intermediate devices, either passive or active.

[0050] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments.

[0051] Furthermore, terms such as "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

[0052] Although this disclosure may use perspective descriptions such as "above," "below," "top," "bottom," "side," etc., such descriptions are used for ease of discussion and are not intended to limit the application of the disclosed embodiments.

[0053] As used herein, the terms "above," "below," "between," and "on" refer to the relative location of one layer of material or component with respect to another layer or component. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described as being "on" a second layer refers to the layer in direct contact with that second layer. Similarly, unless explicitly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature or may have one or more intervening layers.

[0054] As used herein, the term "location" refers to a position, location, placement, and / or arrangement, rather than a particular method of formation.

[0055] The term "between" when used in reference to a measurement range includes both ends of the measurement range.

[0056] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). As used herein, the designation "A / B / C" means (A), (B), and / or (C).

[0057] As used herein, certain elements may be referred to in the singular, but such elements may include multiple subelements. For example, a "conductive material" may include one or more conductive materials. As another example, a "dielectric" may include one or more dielectrics.

[0058] Unless otherwise specified, when ordinal adjectives such as "first," "second," "third," etc. are used to describe a common object, this indicates only that different instances of a similar object are being referred to and does not imply that the objects so described must be in a predetermined order, temporally, spatially, sequentially, or otherwise.

[0059] In the following detailed description, references are made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, possible embodiments. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0060] The accompanying drawings are not necessarily drawn to scale.

[0061] In the drawings, the same reference number refers to the same or similar elements / materials shown, and unless otherwise noted, a description of an element / material having a particular reference number provided in the context of one of the drawings is also applicable to other drawings in which the element / material having the same reference number may be shown. Furthermore, the singular and plural forms of a label, together with a reference number, may be used to indicate one and more, respectively, of the same or similar type, species, or class of elements.

[0062] Additionally, while the drawings may depict schematic representations of some of the exemplary structures of the various devices and assemblies described herein with precise right angles and straight lines, it should be understood that such schematic representations may not reflect actual process limitations, and that features may not appear so "ideal" when inspecting any of the structures described herein using images from an appropriate characterization tool, such as a scanning electron microscope (SEM) image, a transmission electron microscope (TEM) image, or a non-contact profilometer. Such images of actual structures may also reveal processing and / or surface defects, such as surface roughness, curvature or profile deviations, holes or scratches, edges of materials that are not perfectly straight, tapered vias or other openings, unintended corner rounding or thickness variations in different material layers, occasional twist, edge, or combination dislocations within crystalline regions, and / or single-atom or atom-cluster dislocation defects. There may be other defects not listed here but that are common in the field of device manufacturing and / or packaging.

[0063] It should be noted that in the figures, various components (e.g., interconnects) are shown aligned (e.g., at their respective interfaces) for ease of illustration, and that in reality, some or all of them may not be aligned. Furthermore, other components present in the assembly, such as bond pads, landing pads, metallization, etc., may not be shown in the figures to avoid clutter. Furthermore, the figures are intended to show the relative placement of components in the assembly; generally, such assemblies may include other components not shown (e.g., various interface layers, or various other components related to optical functionality, electrical connections, or thermal mitigation). For example, in some further embodiments, the assemblies shown in the figures may include more dies, along with other electrical components. Furthermore, while some components of the assemblies are shown in the figures as flat rectangles or formed as rectangular parallelepipeds, this is solely for ease of illustration; the embodiments of these assemblies are dictated by the manufacturing processes used to fabricate the various components and may, at times, necessarily be curved, rounded, or otherwise irregular.

[0064] In the drawings, specific numbers and arrangements of structures and components are presented for illustrative purposes; in various embodiments, any number and arrangement of such structures and components may be present.

[0065] Additionally, unless otherwise specified, structures shown in the figures may take any suitable form or shape depending on material properties, manufacturing processes, and operating conditions.

[0066] For convenience, where there are sets of drawings designated with different letters (e.g., Figures 10A-10C), such sets may be referred to herein without the letters (e.g., "Figure 10"). Similarly, where there are sets of reference numbers designated with different letters (e.g., 112a-112e), such sets may be referred to herein without the letters (e.g., "112").

[0067] Various operations may be described sequentially as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order presented. The operations described may be performed in a different order than in the described embodiment. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0068] Example of an embodiment FIG. 1A is a schematic cross-sectional view of an exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 includes an interposer structure 102 comprising glass. In some embodiments, the glass can include borosilicate glass, for example, including silica (e.g., 52%-56%), alumina (e.g., 12%-16%), borate (e.g., 5%-10%), sintered material (e.g., 16%-25%), and magnesium oxide (e.g., 0%-6%). In some embodiments, the glass can have a composition that allows for a low coefficient of thermal expansion (CTE), for example, about 2.8 PPM / C. In some such embodiments, the glass can include about 60%-65% silica and 20%-25% alumina. In some other embodiments, the glass can have a composition that allows for low electrical loss, for example, a dielectric constant of about 4.8 at 1 GHz and 4.69 at 10 GHz, and a loss tangent of 0.0043 at 1 GHz. In some such embodiments, the glass may include approximately 52% to 56% silica, 10% to 15% alumina, 15% to 20% borate, 0% to 10% calcinate, and 0% to 5% magnesium oxide.

[0069] The face 103 of the interposer structure 102 can be attached to the substrate 104 at the face 106 of the substrate 104. The substrate 104 includes a build-up layer including an organic dielectric material 108 having a conductive structure 110 therein. In some embodiments, the conductive structure 110 includes bond pads, conductive traces, and conductive vias. In some embodiments, there may be multiple layers of conductive traces, each separated by the organic dielectric material 108 and conductively coupled to each other by the conductive vias. For ease of illustration and to avoid cluttering the drawings, only a portion of such structures are shown. Any suitable configuration of conductive structures 110 can be disposed within the substrate 104 within the broad scope of embodiments. In some embodiments, the substrate 104 can include a core 112 of a different composition than the organic dielectric material 108. For example, the organic dielectric material 108 can include a polyimide and the core 112 can include a fiber-reinforced epoxy. In other embodiments, the organic dielectric material 108 can include one type of epoxy and the core 112 can include a different type of epoxy. Within the broad scope of embodiments, any suitable organic material typically used in package substrates and listed in the previous subsection may be included in the organic dielectric material 108 and / or core 112 within the substrate 104.

[0070] In some embodiments, the substrate 104 can include a build-up layer having an organic dielectric material 108 with conductive structures 110 on either side of a core 112. In some such embodiments, through-hole vias (THVs) 114 through the core 112 provide conductive coupling of the conductive structures 110 on either side of the core 112. The face 116 is the opposite side 106 of the substrate 104 and can include bond pads 118 that can be configured to couple the substrate 104 to a motherboard or a motherboard socket.

[0071] In various embodiments, face 119 of interposer structure 102 is parallel to and opposite face 103 and may be coupled to one or more different IC dies. For example, different IC dies 120, 122, and 124 may be present in microelectronic assembly 100. While each IC die 120 is depicted as a single block in the figures, it may actually comprise a single IC die, a stack of IC dies arranged on top of one another, or a multi-chip package. In some embodiments, IC die 120 may comprise memory circuitry, such as high-bandwidth memory (HBM). In some embodiments, IC die 120 may comprise a semiconductor die manufactured using older technology. IC die 122 may comprise a computing die manufactured with the latest semiconductor technology node or other such advanced process technology. In general, transistors in IC die 120 may be larger than transistors in IC die 122. The die sizes may also vary. The footprint (and thickness) of IC die 120 may be larger than either of IC die 122. In some embodiments, IC die 120 may have an area of ​​100 to 700 square millimeters and a thickness in the range of 100 to 2000 micrometers. In some embodiments, IC die 122 may have an area of ​​25 to 500 square millimeters and a thickness in the range of 5 to 500 micrometers. IC die 124 includes a bridge circuit that functions to conductively couple IC die 120 and IC die 122. As such, IC die 124 may also be referred to herein as a "bridge die 124." In some embodiments, interposer structure 102 may include active circuit elements that can be fabricated using a suitable complementary metal-oxide semiconductor (CMOS) process on a glass substrate.

[0072] In various embodiments, IC die 120 may be directly coupled to substrate 104 by conductive interconnects 126 having a pitch ranging from 10 micrometers to 200 micrometers. IC die 120 may be conductively coupled to IC die 124 by interconnects 128 having the same pitch as interconnects 126 or a different pitch ranging from 10 micrometers to 135 micrometers. IC die 124 may be conductively coupled to interposer structure 102 by interconnects 130. IC die 122 may be conductively coupled to side 119 of interposer structure 102 by interconnects 132. In many embodiments, interconnects 126, 128, 130, and 132 may include DTD interconnects, as described in the previous subsection. Interconnects 130 on side 103 of interposer structure 102 and interconnects 132 on side 119 of interposer structure 102 may be conductively coupled by through-glass vias (TGVs) 134. Additionally, two or more IC dies 122 on face 119 of interposer structure 102 may be conductively coupled together by conductive structures 136 within interposer structure 102 .

[0073] 1B is a schematic top view illustrating the exemplary microelectronic assembly 100 of FIG. 1A. Note that while only a few components are shown, this is merely for ease of explanation and is not intended to be limiting. Any number of components (e.g., IC dies) may be included in the microelectronic assembly 100 within the broad scope of embodiments. A portion of the IC die 124 is shown with a dotted line to indicate that the dotted line portion is beneath the overlying structure (e.g., IC dies 120 and 122).

[0074] The IC die 120 may be coupled to the IC die 122 by a conductive pathway 140. Note that the conductive pathway 140 may include, in various embodiments, multiple conductive traces, conductive vias, and multiple interconnects 128, 130, and 132. The illustrated conductive pathway 140 is merely a conceptual representation and is not intended to be a precise physical or geometric representation. The conductive pathway 140 may run through the IC die 124 within the substrate 104. The conductive pathway 140 may include the interconnect 128 between the IC dies 120 and 124, conductive traces and vias within the IC die 124, the interconnect 130 between the IC die 124 and the interposer structure 102, the TGV 134, and the interconnect 132 between the IC die 122 and the interposer structure 102.

[0075] The IC dies 122 on the interposer structure 102 may be conductively coupled by conductive pathways 142. Note that the conductive pathways 142 may include multiple conductive traces, conductive vias, and multiple interconnects 132 in various embodiments. In some embodiments, the conductive pathways 142 are optical waveguides, enabling optical communication between the IC dies 122. The illustrated conductive pathways 142 are merely conceptual representations and are not intended to be precise physical or geometric representations. The conductive pathways 140 may include interconnects 132 between the IC dies 122 and the interposer structure 102, as well as conductive structures 136 within the interposer structure 102. In various embodiments, the IC dies 122 form a computing array on the interposer structure 102 and communicate with memory circuitry provisioned on the IC dies 120 via a bridge die 124. In some embodiments, one or more IC dies 120 may also include peripheral interconnect circuitry, for example, to enable communication with another component or microelectronic assembly.

[0076] While conductive paths 140 and 142 are shown between adjacent IC dies, it should be noted that within the broad scope of the embodiments, such conductive paths may extend to non-adjacent IC dies as well. For example, two of IC dies 120 may be conductively coupled across IC die 122 (and other components not shown) by appropriate conductive paths within interposer structure 102 and multiple bridge dies 124.

[0077] 2 is a schematic cross-sectional view illustrating a portion of an exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The portion shown is a portion of an interposer structure 102, within which an exemplary conductive structure 136 is shown. The interconnect structure 102 includes a glass material 202. In some embodiments, the interconnect structure 102 may be fabricated with a continuous layer of glass material 202 (e.g., silicon oxide with other elements such as borates) and a layer 204 of another material. For example, the surfaces 103 and 119 of the interposer structure 102 may be coated with a layer 204 that includes primarily silicon nitride. The selection of materials for the layers of the interconnect structure 102 may be based on manufacturing, operational, and other considerations beyond the scope of this disclosure.

[0078] In various embodiments, the conductive structure 136 includes conductive traces 206, conductive vias 208, and conductive bond pads 210. The conductive traces 206 may be disposed on multiple layers of the interconnect structure 102, and the conductive vias 208 may conductively couple the conductive traces 206 on different layers. In some embodiments, the thickness of each layer may be approximately 3 micrometers. In other embodiments, the thickness of each layer may be approximately 1.2 micrometers. For example, the conductive vias 208 may be in a layer with a thickness T1, and the conductive traces 206 may be in an adjacent layer with a thickness T2. In some embodiments, T1 may be the same as T2, while in other embodiments, T1 may not be the same as T2. In some embodiments (as shown), the conductive traces 206 near the face 103 of the interposer structure 102 are approximately the same thickness as the bond pads 210 and the conductive traces 206 near the face 119 of the interposer structure 102.

[0079] The spacing between conductive traces 206 and the width of the conductive traces 206 on any one layer can vary depending on the thickness of each conductive trace 206 on the same layer. In some embodiments, the line spacing between conductive traces 206 can be 1 micrometer, and in other embodiments, the line spacing between conductive traces 206 can be 20 micrometers. Via spacing (e.g., between TGVs 134 and / or conductive vias 208) can vary between 2 micrometers and 15 micrometers in different embodiments. Via diameter (e.g., the diameter of a TGV 134 and / or conductive via 208) can vary between 2 micrometers in some embodiments and 50 micrometers in other embodiments.

[0080] The number of layers of conductive traces 206 may vary depending on factors outside the scope of this disclosure. In some embodiments (shown), some layers of interposer structure 102 may extend entirely through the thickness of interposer structure 102 between faces 103 and 119. In other embodiments (not shown), layers may extend partially through the thickness of interposer structure 102. In some embodiments, conductive structure 136 may extend partially through the thickness of some portions of interposer structure 102 and completely through the thickness of other portions of interposer structure 102. In some embodiments (not shown), conductive traces 206 may be suitably conductively coupled to TGVs 134. In various embodiments, the total thickness of interposer structure 102 may depend on the number of layers of conductive traces 206. In other embodiments, the thickness may not depend on the number of layers of conductive traces 206 (e.g., an increase in the number of layers may be offset by a decrease in the length of TGVs 134 and / or other configuration options). In some embodiments, the thickness of the interposer structure 102 may vary between 100 micrometers in some embodiments and 1000 micrometers in other embodiments.

[0081] In some embodiments, the thickness of layer 204 may vary between 0.4 micrometers and 2.7 micrometers. In some embodiments, layer 204 may be present between conductive bond pads 210 and conductive traces 206. In such embodiments, a subset of conductive vias 208 may pass through such layer 204. The thickness of conductive bond pads 210 may be approximately 6 micrometers in some embodiments. In some embodiments, the size and thickness of conductive bond pads 210 may vary depending on the type of interconnects 126, 128, 130, and / or 132.

[0082] 3 is a schematic cross-sectional view illustrating a portion of an exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. Features of the illustrated embodiment are substantially the same as those of FIG. 2, except that the thicknesses of various layers of conductive traces 206 and conductive vias 208 vary between faces 103 and 119 of interposer structure 102. In the illustrated embodiment, the thickness T3 of conductive traces 206 near face 103 may be less than the thickness T4 of conductive traces near face 119. In some embodiments (as shown), some layers of interposer structure 102 may extend through the thickness of interposer structure 102 between faces 103 and 119. The spacing between conductive traces 206 and the width of conductive traces 206 on any one layer may vary depending on the thickness of the respective conductive traces 206 on the same layer, as will be described in more detail with reference to FIG. 2.

[0083] The number of layers of conductive traces 206 may vary depending on factors outside the scope of this disclosure. In some embodiments (shown), some layers of interposer structure 102 may extend entirely through the thickness of interposer structure 102 between faces 103 and 119. In other embodiments (not shown), layers may extend partially through the thickness of interposer structure 102. In some embodiments, conductive structure 136 may extend partially through the thickness of some portions of interposer structure 102 and completely through the thickness of other portions of interposer structure 102. In some embodiments (not shown), conductive traces 206 may be suitably conductively coupled to TGVs 134.

[0084] FIG. 4 is a schematic cross-sectional view illustrating a portion of an exemplary microelectronic assembly according to some embodiments of the present disclosure. Features of the illustrated embodiment are substantially the same as those of FIG. 2, except that conductive traces 206 may be disposed in a layer of glass material 402 that is different from glass material 202. For example, glass material 402 may include carbon-doped silica in some embodiments. Layers of glass material 202 may alternate with layers of glass material 402, with conductive traces 206 disposed in layers of glass material 402 and conductive vias 208 disposed in layers of glass material 202. In some embodiments, the layers of glass material 402 may have a different thickness than the layers of glass material 202. For example, thickness T5 of layer of glass material 202 may be greater than thickness T6 of layer of glass material 402. In some embodiments, T5 may be approximately 3 micrometers and T6 may be approximately 2 micrometers.

[0085] The number of layers of conductive traces 206 may vary depending on factors beyond the scope of this disclosure. In some embodiments, a layer may extend partially through the thickness of interposer structure 102, and conductive traces 206 may be suitably conductively coupled to TGVs 134. In some embodiments (not shown), some layers of interposer structure 102 may extend partially through the thickness of interposer structure 102 between faces 103 and 119. In some embodiments, conductive structure 136 may extend partially through the thickness of some portions of interposer structure 102 and completely through the thickness of other portions of interposer structure 102. The spacing between conductive traces 206 and the width of conductive traces 206 on any one layer may vary depending on the thickness of each conductive trace 206 on the same layer, as described in more detail with reference to FIG. 2 .

[0086] 5A is a schematic cross-sectional view illustrating a portion of a passive component in an exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. In various embodiments, the interposer structure 102 can include a passive component, such as a capacitor (not shown), and an inductor 502. The inductor 502 has a spiral shape and can be disposed at any suitable location within the interposer structure 102. In the illustrated embodiment, the inductor 502 extends partially through the thickness of the interposer structure 102 and is disposed between the faces 103 and 119. The inductor 502 can include bond pads 504, e.g., 504A and 504B, that are conductively coupled to the face 119 of the interposer structure 102 by conductive vias. A magnetic material 508 can be disposed around the conductive trace 506 to enable inductor functionality. The magnetic material 508 can include any suitable magnetic material known in the art for use in thin-film inductors, such as cobalt alloys and magnesium alloys.

[0087] 5B is a schematic diagram of the inductor 502 of FIG. 5A viewed from above along axis BB'. The conductive trace 506 may include multiple planar coils and may be spirally (e.g., coiled) formed between bond pads 504A and 504B. Multiple such inductors 502 may be disposed within the interposer structure 102 within a wide range of embodiments. In some embodiments, multiple such inductors 502 may be coplanar, while in other embodiments, the inductors 502 may be disposed on different layers within the interposer structure 102.

[0088] FIG. 6 is a schematic cross-sectional view of a portion of another passive component in an exemplary microelectronic assembly 100 according to some other embodiments of the present disclosure. In the illustrated embodiment, the passive component includes an array of capacitors 602. The capacitors 602 may include any suitable type of capacitor compatible with thin-film or CMOS process operations, such as a metal-insulator-metal capacitor, as shown, or a deep trench capacitor 604. In the illustration, the deep trench capacitor 604 is shown in a representative form, excluding structural details such as the conductive plates and the capacitor dielectric between the conductive plates, for ease of illustration only. Any suitable size, shape, and type of capacitor 602 may be included in the interposer structure 102 within the broad scope of the embodiments. The capacitors 602 may be positioned in any suitable location within the interposer structure 102. In the illustrated embodiment, the capacitors 602 are positioned partially through the thickness of the interposer structure 102 between faces 103 and 119. In some embodiments, capacitor 602 may be conductively coupled to bond pad 210 on face 119 by conductive via 208. In other embodiments (not shown), capacitor 602 may be conductively coupled to another bond pad on face 103 by TGV 134.

[0089] FIG. 7A is a schematic cross-sectional view illustrating another exemplary microelectronic assembly according to some embodiments of the present disclosure. The microelectronic assembly 100 includes a package substrate 702 including an interposer layer 704 comprising glass. Examples of glass materials are listed with reference to the interposer 102 of FIG. 1. The package substrate 702 further includes a substrate layer 706 including an organic dielectric material 108 attached to the interposer layer 704 along a common contact interface 708. In some embodiments, the substrate layer 706 may be constructed on top of the interposer layer 704. In other embodiments, the substrate layer 706 may be attached to the interposer layer 704 using a suitable adhesive. In various embodiments, the interposer layer 704 is substantially similar in structure to the interposer 102 of FIG. 1, except that the interposer layer 704 occupies the entire surface of the substrate layer 706. Furthermore, the interposer layer 704 does not have a free surface 119 like the interposer 102 of FIG. 1, and is attached to the substrate layer 706 along a common contact interface 708. It should also be noted that the conductive structures 136 and passive components within the interposer layer 704 are, in various embodiments, substantially identical to the structures shown and described with reference to Figures 2-6.

[0090] In various embodiments, the substrate layer 706 is substantially similar in structure to the substrate 104 of FIG. 1 , except that the substrate layer 706 does not have a free surface 106 like the substrate 104, but is instead attached to the interposer layer 704 along a common contact interface 708. The conductive structures 136 of the interposer layer 704 may be conductively coupled to the conductive structures 110 of the substrate layer 706 by the TGVs 134 of the interposer layer 704. Note that the substrate layer 706 may have appropriate bond pads and other conductive elements to facilitate conductive coupling with the interposer layer 704. Such features are not shown solely for ease of illustration. Additionally, passive components such as inductors (e.g., 502) and capacitors (e.g., 602) may be appropriately located on the interposer layer 704 and / or the substrate layer 706. Those skilled in the art will appreciate that such features, while not shown or labeled, may also be located on the package substrate 702 to enable electrical functionality of the microelectronic assembly 100.

[0091] The IC dies 120, 122 may be coupled to the surface 710 of the interposer layer 704 by interconnects 132. In some such embodiments, the bridge die 124 may not be present. Lateral coupling between the IC dies 120, 122 may be via conductive paths in the conductive structures 136 of the interposer layer 102. The IC dies 120, 122 may be coupled to the conductive structures 110 in the substrate layer 706 by TGVs 134.

[0092] FIG. 7B is a schematic top view illustrating the exemplary microelectronic assembly 100 of FIG. 7A. Note that only a few components are shown. This is merely for ease of explanation and is not intended to be limiting. Any number of components (e.g., IC dies) can be included in the microelectronic assembly 100 within the broad scope of embodiments. The IC die 120 can be coupled to the IC die 122 through the interposer layer 704 by conductive paths 712. Note that the conductive paths 712 can include multiple conductive traces, conductive vias, and multiple interconnects 132 in various embodiments. The illustrated conductive paths 712 are merely conceptual representations and are not intended to be precise physical or geometric representations. The conductive paths 712 can include the interconnects 132 between the IC dies 120, 122, the interposer layer 704, and conductive structures 136 within the interposer layer 704. The IC die 122 on the interposer layer 704 can be conductively coupled by conductive paths 142, as described with reference to FIG. 1B. In some embodiments, the conductive paths 712 and 142 are optical waveguides, enabling optical communication between IC dies 120 and 122, or between two IC dies 122. While the conductive paths 712 and 142 are shown between adjacent IC dies, it should be noted that, within the broad scope of the embodiments, such conductive paths may extend to non-adjacent IC dies. For example, two of the IC dies 120 may be conductively coupled across IC die 122 (and other components not shown) by appropriate conductive paths within the interposer layer 704.

[0093] In various embodiments, any of the features discussed with reference to any of Figures 1-7 herein can be combined with other features to form a package containing one or more IC dies described herein. For example, in some microelectronic assemblies, some IC dies may be joined by interconnects that include solder, while other IC dies may be joined by solderless bonds. While some such combinations have been described above, further combinations and variations are possible in various embodiments. The various different embodiments described in the various figures can be combined as appropriate based on particular needs within the broad scope of embodiments.

[0094] Example of how to 8 is a schematic flow diagram of example operations 800 that may be associated with fabricating a microelectronic assembly 100 according to some embodiments of the present disclosure. At 802, a substrate 104 may be provided, the substrate 104 including multiple layers of conductive structures 110 (e.g., traces and vias) within an organic dielectric material 108. In some embodiments (e.g., as described with reference to FIG. 1), the substrate 104 may include a core 112. In other embodiments (e.g., as described with reference to FIG. 7), the substrate 104 may not include a core 112. The substrate 104 may be fabricated using standard (e.g., known) processes with the conductive structures 110 patterned according to specific needs, for example, based on various functions to be provided for the microelectronic assembly 100.

[0095] At 804, the interposer structure 102, including glass, may be attached to the substrate 104. In various embodiments, the interposer structure 102 may have TGVs 134 and conductive structures 136 disposed thereon before being attached to the substrate 104. Forming the TGVs 134 and conductive structures 136 in the interposer structure 102 may be performed according to known processes, such as laser drilling, electroplating, sequential deposition of silicon oxide, carbon-doped silicon oxide, and silicon nitride, as described with reference to the embodiments of FIGS. 2-4 based on specific needs. In some embodiments, the interposer structure 102 may be attached to the substrate 104 by conductive interconnects 130, as described with reference to FIG. 1, for example. In some such embodiments, the interposer structure 102 may be conductively coupled to a bridge die 124 embedded in the organic dielectric material 108 of the substrate 104. In some other embodiments, for example, as described with reference to Figure 7, attaching the interposer structure 102 to the substrate 104 includes building the substrate 104 on the exposed surface of the interposer structure 102 such that a substrate layer is formed over the interposer layer. In some other embodiments, for example, as described with reference to Figure 7, attaching the interposer structure 102 includes attaching the substrate 104 to the interposer structure 102 using an adhesive.

[0096] At 806, multiple IC dies 122 may be attached to interposer structure 102 by interconnects 132. In some embodiments, multiple other IC dies 120 may also be attached to interposer structure 102 by interconnects 132. In some embodiments, multiple IC dies 120 may be further attached to substrate 104 by interconnects 126. Some of the IC dies 120 in such embodiments may be coupled to bridge die 124 in substrate 104 by interconnects 128.

[0097] At 808, multiple IC dies 122 may be conductively coupled to one another via conductive structures 136 in the interposer structure 102. In some embodiments, the IC die 120 may also be coupled to the IC die 122 by the conductive structures 136 in the interposer structure 102, for example, as described with reference to FIG. 7. In other embodiments, an IC die 120 not directly attached to the interposer structure 102 may be conductively coupled to an IC die 122 attached to the interposer structure 102 via a TGV 134, conductive interconnects 128, 130, and a bridge die 124.

[0098] While FIG. 8 depicts various operations performed in a particular order, this is merely illustrative, and operations discussed herein may be reordered and / or repeated as desired. Additionally, additional processes not shown may be performed without departing from the scope of the present disclosure. Additionally, various operations discussed herein with respect to FIG. 8 may be modified in accordance with the present disclosure to produce other microelectronic assemblies 100 disclosed herein. While various operations are depicted in FIG. 8 , each operation may be performed once, and operations may be repeated as many times as desired. For example, one or more operations may be performed in parallel to fabricate and test multiple microelectronic assemblies substantially simultaneously. In other examples, operations may be performed in a different order to reflect the structure of a particular microelectronic assembly, which may include one or more substrates or other components described herein.

[0099] Additionally, the operations shown in FIG. 8 may be combined or include more details than those described. For example, in the case of IC dies that do not have a semiconductor substrate but are fabricated on other materials, such as glass or ceramic materials, the operations may be modified appropriately without departing from the scope of the disclosure. Furthermore, the various operations shown and described may further include other manufacturing operations related to the fabrication of other components of the microelectronic assemblies described herein or any device that may include the microelectronic assemblies described herein. For example, operations not shown in FIG. 8 may include various cleaning operations, additional surface planarization operations, surface roughening operations, operations including barrier layers and / or adhesion layers as needed, and / or operations incorporating the microelectronic assemblies described herein into or with an IC component, a computing device, or any desired structure or device.

[0100] Device and Component Examples The packages disclosed herein, such as any of the embodiments shown in Figures 1-8, or other embodiments described herein, may be included in any suitable electronic component. Figures 9-11 show various examples of packages, assemblies, and devices that may be used with or include any of the IC packages disclosed herein.

[0101] 9 is a cross-sectional side view of an exemplary IC package 2200, which may include an IC package according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a SiP.

[0102] As shown, package substrate 2252 may be formed of an insulator (e.g., ceramic, build-up film, epoxy film with filler particles, etc.) and may have conductive paths extending through the insulator between first surface 2272 and second surface 2274, or between different locations on first surface 2272 and / or different locations on second surface 2274. These conductive paths may take the form of any of an interconnect structure including lines and / or vias.

[0103] Package substrate 2252 includes conductive contacts 2263 that are coupled to conductive paths 2262 through package substrate 2252, allowing circuitry within die 2256 and / or interposer 2257 to be electrically coupled to various conductive contacts 2264 (or other devices included in package substrate 2252, not shown).

[0104] IC package 2200 can include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257, first level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first level interconnects 2265 shown in the figure are solder bumps, although any suitable first level interconnects 2265 can be used, such as solder bumps, solder posts, or bond wires.

[0105] The IC package 2200 may include one or more dies 2256 coupled to an interposer 2257 via conductive contacts 2254 of the die 2256, first level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) through the interposer 2257, allowing circuitry within the die 2256 to be electrically coupled to various ones of the conductive contacts 2261 (or other devices (not shown) included in the interposer 2257). The first level interconnects 2258 shown in the figure are solder bumps, although any suitable first level interconnects 2258 may be used, such as solder bumps, solder posts, or bond wires. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that serves as an interface between different components. The conductive contacts may be embedded within, flush with, or extend away from the surface of the component, and may take any suitable shape (such as a conductive pad or socket).

[0106] In some embodiments, underfill material 2266 may be disposed between package substrate 2252 and interposer 2257 around first level interconnect 2265, and molding 2268 may be disposed around die 2256 and interposer 2257 and in contact with package substrate 2252. In some embodiments, underfill material 2266 may be the same as molding 2268. Exemplary materials that can be used for underfill material 2266 and molding 2268 include a suitable epoxy. Second level interconnect 2270 may be coupled to conductive contacts 2264. The second level interconnect 2270 shown in the figure is a solder ball (e.g., in a ball grid array (BGA) arrangement), although any suitable second level interconnect 2270 (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement) may be used. Second level interconnect 2270 is known in the art and can be used to couple IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as discussed below with reference to FIG. 10.

[0107] In various embodiments, any of the dies 2256 may be a microelectronic assembly 100 described herein. In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry for performing any desired function. For example, in addition to one or more dies 2256 being a microelectronic assembly 100 described herein, one or more dies 2256 may be logic dies (e.g., silicon-based dies) and one or more dies 2256 may be memory dies (e.g., HBM). In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the previous figures. In some embodiments, at least some of the dies 2256 may not include an implementation as described herein.

[0108] Although the IC package 2200 shown in the figure is a flip-chip package, other package architectures can be used. For example, the IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. While two dies 2256 are shown in the IC package 2200, the IC package 2200 can include any number of dies 2256. The IC package 2200 can include additional passive components, such as surface-mount resistors, capacitors, and inductors, located on the first side 2272 or second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 can include other active or passive components known in the art.

[0109] In some embodiments, IC package 2200 may not include interposer 2257 , and instead, die 2256 may be directly coupled to conductive contacts 2263 on first surface 2272 by first level interconnect 2265 .

[0110] FIG. 10 is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes multiple components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and an opposing second side 2342 of the circuit board 2302. In general, components may be disposed on one or both sides 2340 and 2342. In particular, any suitable ones of the components of the IC device assembly 2300 may include any one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein. For example, any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form of any of the embodiments of the IC package 2200 discussed above with reference to FIG. 9.

[0111] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by layers of insulation and interconnected by conductive vias. Any one or more of the metal layers may be formed with a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in combination with other metal layers). In other embodiments, circuit board 2302 may be a packaging substrate other than a PCB.

[0112] As shown, in some embodiments, IC device assembly 2300 may include a package-on-interposer structure 2336 coupled to a first surface 2340 of circuit board 2302 by coupling components 2316. Coupling components 2316 may electrically and mechanically couple package-on-interposer structure 2336 to circuit board 2302 and may include solder balls (as shown), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0113] Package-on-interposer structure 2336 may include an IC package 2320 coupled to interposer 2304 by a coupling component 2318. Coupling component 2318 may take any suitable form depending on the desired functionality, such as those discussed above with reference to coupling component 2316. In some embodiments, IC package 2320 may be or include IC package 2200, for example, as discussed above with reference to FIG. 9. In some embodiments, IC package 2320 may include at least one microelectronic assembly 100, as described herein. Microelectronic assembly 100 is not specifically shown in the figures to avoid cluttering the drawings.

[0114] Although a single IC package 2320 is shown in the figure, multiple IC packages may be coupled to interposer 2304. In fact, additional interposers may be coupled to interposer 2304. Interposer 2304 may provide an intervening package substrate used to bridge circuit board 2302 and IC package 2320. In general, interposer 2304 may redistribute connections to a wider pitch or reroute connections to different connections. For example, interposer 2304 may couple IC package 2320 to the BGA of coupling component 2316, which in turn couples IC package 2320 to circuit board 2302.

[0115] In the illustrated embodiment, IC package 2320 and circuit board 2302 are mounted on opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 may be mounted on the same side of interposer 2304. In some embodiments, more than two components may be interconnected via interposer 2304.

[0116] The interposer 2304 may be formed of a polymeric material such as epoxy, fiberglass-reinforced epoxy, ceramic material, or polyimide. In some implementations, the interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including, but not limited to, TSVs 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 2304. Package-on-interposer structure 2336 can take the form of any package-on-interposer structure known in the art.

[0117] In some embodiments, IC device assembly 2300 can include IC package 2324 coupled to first surface 2340 of circuit board 2302 by coupling component 2322. Coupling component 2322 can take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 can take the form of any of the embodiments discussed above with reference to IC package 2320.

[0118] In some embodiments, IC device assembly 2300 can include a package-on-package structure 2334 coupled to second surface 2342 of circuit board 2302 by coupling component 2328. Package-on-package structure 2334 can include IC package 2326 and IC package 2332 coupled together by coupling component 2330, with IC package 2326 disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 can take the form of any of the embodiments of coupling component 2316 discussed above, and IC package 2326 and / or 2332 can take the form of any of the embodiments of IC package 2320 discussed above. Package-on-package structure 2334 can be configured according to any of the package-on-package structures known in the art.

[0119] 11 is a block diagram of an exemplary computing device 2400 that may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable one of the components of computing device 2400 may include a microelectronic assembly (e.g., 100) according to any of the embodiments disclosed herein. In another example, one or more components of computing device 2400 may include any embodiment of IC package 2200 (e.g., shown in FIG. 9). In yet another example, one or more components of computing device 2400 may include IC device assembly 2300 (e.g., shown in FIG. 10).

[0120] The figure shows numerous components included in computing device 2400, although one or more of these components may be omitted or duplicated depending on the application. In some embodiments, some or all of the components included in computing device 2400 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SOC die.

[0121] Further, in various embodiments, computing device 2400 may not include one or more components shown in the figures, but computing device 2400 may include interface circuitry for coupling to one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 2406 may couple. In another example, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 2418 or audio output device 2408 may couple.

[0122] Computing device 2400 may include a processing unit 2402 (e.g., one or more processing units). As used herein, the terms “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. Processing unit 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptoprocessors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or other suitable processing units. Computing device 2400 may include memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, memory 2404 may include memory that shares a die with processing unit 2402. This memory can be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0123] In some embodiments, computing device 2400 may include a communications chip 2412 (e.g., one or more communications chips). For example, communications chip 2412 may be configured to manage wireless communications for transferring data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that can communicate data using modulated electromagnetic radiation over a non-solid medium. This term does not imply that the associated devices do not include wires, although in some embodiments they may not.

[0124] The communications chip 2412 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), the LTE project and its amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP®2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, a certification mark for products that pass IEEE 802.16 standard conformance and interoperability testing. The communications chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications chip 2412 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimized (EV-DO), and their derivatives, as well as other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communications chip 2412 can operate according to other wireless protocols. Computing device 2400 may include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0125] In some embodiments, the communications chip 2412 may manage wired communications, such as electrical, optical, or other suitable communications protocols (e.g., Ethernet). As described above, the communications chip 2412 may include multiple communications chips. For example, a first communications chip 2412 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 2412 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communications chip 2412 may be dedicated to wireless communications, and the second communications chip 2412 may be dedicated to wired communications.

[0126] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for connecting components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0127] Computing device 2400 may include a display device 2406 (or corresponding interface circuitry as discussed above), which may include any visual indicator such as, for example, a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0128] Computing device 2400 may include audio output device(s) 2408 (or corresponding interface circuitry as discussed above), which may include any device that produces an audible indicator, such as, for example, a speaker, a headset, or earphones.

[0129] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry as discussed above), which may include any device that generates signals representing sound, such as a microphone, a microphone array, a digital musical instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output), etc.

[0130] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry as discussed above), which can communicate with a satellite-based system to receive the location of computing device 2400, as is known in the art.

[0131] The computing device 2400 may include other output device(s) 2410 (or corresponding interface circuitry as discussed above). Examples of other output device(s) 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0132] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a mouse, a stylus, a cursor control device such as a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader, etc.

[0133] Computing device 2400 can have any desired form factor, such as a handheld or mobile computing device (such as a mobile phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop computing device, server or other network computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, computing device 2400 can be any other electronic device that processes data.

[0134] Selection example Example 1 provides a microelectronic assembly (e.g., 100 in FIG. 1 ), the microelectronic assembly including an interposer structure (e.g., 102) comprising glass; a substrate (e.g., 104) comprising an organic dielectric material, the substrate being coupled to a first surface (e.g., 103) of the interposer structure; and a plurality of IC dies (e.g., 120, 122, 124), wherein a first IC die (e.g., 120) of the plurality of IC dies is coupled to the substrate by a first interconnect (e.g., 126) and a second IC die (e.g., 124) of the plurality of IC dies is coupled to the substrate by a first interconnect (e.g., 126). An IC die (e.g., 124) is embedded in the organic dielectric material of the substrate, a second IC die is coupled to the first IC die by a second interconnect (e.g., 128), the second IC die is coupled to a first surface of the interposer structure by a third interconnect (e.g., 130), and a third IC die (e.g., 122) of the plurality of IC dies is coupled to a second surface (e.g., 119) of the interposer structure by a fourth interconnect (e.g., 132), the second surface of the interposer structure being opposite the first surface of the interposer structure.

[0135] Example 2 provides the microelectronic assembly of Example 1, wherein the third IC die is conductively coupled to the second IC die by a TGV (e.g., 134) in the interposer structure.

[0136] Example 3 provides the microelectronic assembly of any one of Examples 1-2, wherein a fourth IC die of the plurality of IC dies is coupled to a second surface of the interposer structure, and the fourth IC die is conductively coupled to the third IC die by a conductive structure (e.g., 136) in the interposer structure.

[0137] Example 4 provides the microelectronic assembly of example 3, wherein the conductive structure within the interposer structure includes an optical waveguide.

[0138] Example 5 provides the microelectronic assembly of Example 3, wherein the conductive structure within the interposer structure includes conductive bond pads (e.g., 210), multiple layers of conductive traces (e.g., 206), and conductive vias (e.g., 208) that couple the conductive traces and conductive bond pads on different layers (e.g., FIGS. 2-4).

[0139] Example 6 provides the microelectronic assembly of Example 5, wherein the conductive traces proximate the first side of the interposer structure are approximately the same thickness as the conductive traces proximate the second side of the interposer structure (e.g., FIG. 2).

[0140] Example 7 provides the microelectronic assembly of any one of Examples 5-6, wherein the conductive traces have a thickness of about 2 micrometers to 3 micrometers, the line spacing between the conductive traces is about 1 micrometer to 20 micrometers, and the conductive vias have a via diameter of about 2 micrometers to 50 micrometers.

[0141] Example 8 provides the microelectronic assembly of example 5, wherein the conductive traces closer to the first side of the interposer structure are thinner than the conductive traces closer to the second side of the interposer structure (e.g., FIG. 3).

[0142] Example 9 provides the microelectronic assembly of example 5, wherein the conductive vias closer to the first side of the interposer structure are smaller than the conductive vias closer to the second side of the interposer structure (eg, FIG. 3).

[0143] Example 10 provides the microelectronic assembly of any one of Examples 5-6, wherein the interposer structure includes alternating layers of a first glass material (e.g., 202) and a second glass material (e.g., 402), the conductive vias being in the first glass material and the conductive traces being in the second glass material (e.g., FIG. 4).

[0144] Example 11 provides the microelectronic assembly of Example 10, wherein the first layer of glass material is about 2 micrometers thick and the second layer of glass material is about 3 micrometers thick.

[0145] Example 12 provides the microelectronic assembly of example 10, wherein the first glass material comprises silicon and oxygen, and the second glass material comprises carbon, silicon, and oxygen.

[0146] Example 13 provides the microelectronic assembly of any one of Examples 5-12, wherein a layer (e.g., 204) comprising silicon and nitrogen is between the conductive bond pad and the conductive trace, and a subset of the conductive vias is in the layer comprising silicon and nitrogen.

[0147] Example 14 provides the microelectronic assembly of example 13, wherein the layer comprising silicon and nitrogen is about 0.4 micrometers to 2.7 micrometers.

[0148] Example 15 provides the microelectronic assembly of any one of Examples 1-14, wherein the first side of the interposer structure and the second side of the interposer structure each have a layer comprising silicon and nitrogen.

[0149] Example 16 provides the microelectronic assembly of example 15, wherein each of the silicon- and nitrogen-containing layers is about 0.4 micrometers to 2.7 micrometers.

[0150] Example 17 provides the microelectronic assembly of any one of Examples 1-16, wherein the interposer structure further includes passive electronic components including an inductor and a capacitor (eg, FIGS. 5-6).

[0151] Example 18 provides the microelectronic assembly of example 17, wherein the inductor is a spiral inductor.

[0152] Example 19 provides the microelectronic assembly of example 17, wherein the capacitor comprises an array of deep trench capacitors.

[0153] Example 20 provides the microelectronic assembly of any one of Examples 1-19, wherein the substrate includes a plurality of conductive trace layers (eg, 110) within an organic dielectric material (eg, 108).

[0154] Example 21 provides the microelectronic assembly of example 20, wherein the substrate further comprises a core (e.g., 112) and a through-hole via (THV) (e.g., 114) extending through the core.

[0155] Example 22 provides the microelectronic assembly of example 21, wherein the core comprises a fiber reinforced epoxy material.

[0156] Example 23 provides the microelectronic assembly of any one of Examples 21-22, wherein the multiple layers of conductive traces in the organic dielectric material are on both sides of the core.

[0157] Example 24 provides the microelectronic assembly of any one of Examples 1 to 23, wherein the substrate has a first surface (e.g., 106) and an opposite second surface (e.g., 116), the first surface of the interposer structure is bonded to the first surface of the substrate, and the substrate further includes a bond pad (e.g., 118) on the second surface.

[0158] Example 25 provides the microelectronic assembly of any one of Examples 1 to 24, wherein the first IC die includes a memory circuit, the second IC die includes a bridge circuit, and the third IC die includes a computational circuit.

[0159] Example 26 provides the microelectronic assembly of any one of Examples 1 to 25, wherein the interposer structure includes active circuit elements.

[0160] Example 27 provides a microelectronic assembly (e.g., 100 in FIG. 7 ), the microelectronic assembly including a package substrate (e.g., 702) including an interposer layer (e.g., 704) including glass and a substrate layer (e.g., 706) on a first side (e.g., 703) of the interposer layer, the substrate layer including an organic dielectric material; and a plurality of IC dies (e.g., 120, 122) coupled to a second side (e.g., 119) of the interposer layer by interconnects (e.g., 132), the second side being opposite the first side, the IC dies of the plurality of IC dies being conductively coupled to each other by first conductive structures in the interposer layer, the substrate layer including second conductive structures in the organic dielectric material, and TGVs in the interposer layer conductively coupling the plurality of IC dies to the second conductive structures.

[0161] Example 28 provides the microelectronic assembly of Example 27, wherein the first conductive structure in the interposer layer includes conductive bond pads, multiple layers of conductive traces, and conductive vias coupling the conductive traces and the conductive bond pads on different layers (e.g., FIGS. 2-4).

[0162] Example 29 provides the microelectronic assembly of Example 28, wherein the conductive traces proximate the first side of the interposer layer are about the same thickness as the conductive traces proximate the second side of the interposer layer (e.g., FIG. 2).

[0163] Example 30 provides the microelectronic assembly of example 28, wherein the conductive traces near the first side of the interposer layer are thinner than the conductive traces near the second side of the interposer layer (e.g., FIG. 3).

[0164] Example 31 provides the microelectronic assembly of example 28, wherein the conductive vias closer to the first side of the interposer layer are smaller than the conductive vias closer to the second side of the interposer layer (e.g., FIG. 3).

[0165] Example 32 provides the microelectronic assembly of any one of Examples 28-31, wherein the interposer layer includes alternating layers of a first glass material (e.g., 202) and a second glass material (e.g., 402), and the conductive vias are in the first glass material and the conductive traces are in the second glass material (e.g., FIG. 4).

[0166] Example 33 provides the microelectronic assembly of example 32, wherein the first glass material comprises silicon and oxygen, and the second glass material comprises carbon, silicon, and oxygen.

[0167] Example 34 provides the microelectronic assembly of any one of Examples 28-33, wherein a layer (e.g., 204) comprising silicon and nitrogen is between the conductive bond pad and the conductive trace, and a subset of the conductive vias is in the layer comprising silicon and nitrogen.

[0168] Example 35 provides the microelectronic assembly of any one of Examples 27-34, wherein the first surface of the interposer layer and the second surface of the interposer layer each include a layer comprising silicon and nitrogen.

[0169] Example 36 provides the microelectronic assembly of any one of Examples 27-35, wherein the interposer layer further comprises passive electronic components including inductors and capacitors (eg, FIGS. 5-6).

[0170] Example 37 provides the microelectronic assembly of example 36, wherein the inductor is a spiral inductor.

[0171] Example 38 provides the microelectronic assembly of any one of Examples 36-37, wherein the capacitor comprises an array of deep trench capacitors.

[0172] Example 39 provides the microelectronic assembly of any one of Examples 27-38, wherein the second conductive structure in the substrate layer includes multiple layers of conductive traces in an organic dielectric material (e.g., 108).

[0173] Example 40 provides the microelectronic assembly of any one of examples 27-39, wherein a first subset of the plurality of IC dies includes memory circuitry and a second subset of the plurality of IC dies includes computational circuitry.

[0174] Example 41 provides a method, the method including providing a first structure including multiple layers of conductive traces in an organic dielectric material, attaching a second structure including glass to the first structure, attaching multiple IC dies to the second structure, and conductively coupling the multiple IC dies via the second structure.

[0175] Example 42 provides the method of example 41, in which the second structure is attached to the first structure by a conductive interconnect.

[0176] Example 43 provides the method of any one of Examples 41-42, further including attaching another plurality of IC dies to the first structure and conductively coupling the another plurality of IC dies to the plurality of IC dies via the first structure.

[0177] Example 44 provides the method of example 43, wherein conductively coupling the other plurality of IC dies to the plurality of IC dies includes coupling the other plurality of IC dies to a bridge die embedded in the organic dielectric material of the first structure, and the bridge die embedded in the organic dielectric material of the first structure is coupled to the second structure.

[0178] Example 45 provides the method of example 43, in which conductively coupling another plurality of IC dies to the plurality of IC dies includes providing TGVs on the second structure.

[0179] Example 46 provides the method of any one of Examples 41-45, wherein attaching the second structure includes constructing the first structure on the exposed surface of the second structure such that the substrate layer substantially covers the exposed surface of the underlying interposer layer.

[0180] Example 47 provides the method of any one of examples 41-45, wherein attaching the second structure includes attaching the second structure to the first structure with an adhesive.

[0181] Example 48 provides the method of any one of examples 41-47, wherein the plurality of IC dies are attached to the second structure by conductive interconnects.

[0182] Example 49 provides the method of any one of examples 41-48, further comprising conductively coupling a plurality of IC dies to the first structure.

[0183] Example 50 provides the method of example 49, in which conductively coupling the plurality of IC dies to the first structure includes providing TGVs on the second structure.

[0184] Example 51 provides a microelectronic assembly, the microelectronic assembly including a package substrate, a first plurality of IC dies coupled to the package substrate, an interposer structure coupled to the package substrate laterally adjacent to the first plurality of IC dies, and a second plurality of IC dies coupled to the interposer structure on a side of the interposer structure opposite the package substrate, the interposer structure being conductively coupled to the first plurality of IC dies through the package substrate, the interposer structure including glass, a plurality of conductive traces in the glass, and a TGV layer, and individual IC dies of the second plurality of IC dies being conductively coupled by the conductive traces in the interposer structure.

[0185] Example 52 provides the microelectronic assembly of example 51, wherein the interposer structure is conductively coupled to the first plurality of IC dies through a third plurality of IC dies embedded in the package substrate.

[0186] Example 53 provides the microelectronic assembly of example 52, wherein each IC die of the third plurality of IC dies is attached to adjacent faces of the first plurality of IC dies and the interposer structure. It's in between.

[0187] Example 54 provides the microelectronic assembly of any one of Examples 52-53, wherein the package substrate includes multiple layers of conductive traces of an organic dielectric material.

[0188] The above description of illustrated embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. While specific embodiments and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the art will recognize.

Claims

1. 1. A microelectronic assembly, comprising: an interposer structure including glass; a substrate comprising an organic dielectric material coupled to a first surface of the interposer structure; a plurality of IC dies; a first IC die of the plurality of IC dies coupled to the substrate by a first interconnect; a second IC die of the plurality of IC dies embedded in the organic dielectric material of the substrate; the second IC die is coupled to the first IC die by a second interconnect; the second IC die is coupled to the first surface of the interposer structure by a third interconnect; a third IC die of the plurality of IC dies coupled to a second side of the interposer structure by a fourth interconnect; the second surface of the interposer structure is opposite the first surface of the interposer structure; Microelectronic assembly.

2. The microelectronic assembly of claim 1 , wherein the third IC die is conductively coupled to the second IC die by through-glass vias (TGVs) in the interposer structure.

3. a fourth IC die of the plurality of IC dies coupled to the second side of the interposer structure; The microelectronic assembly of claim 2 , wherein the fourth IC die is conductively coupled to the third IC die by conductive structures within the interposer structure.

4. The microelectronic assembly of claim 3 , wherein the conductive structures within the interposer structure include optical waveguides.

5. The conductive structure in the interposer structure comprises: conductive bond pads, Multiple layers of conductive traces; and 4. The microelectronic assembly of claim 3, including conductive vias connecting the conductive traces and the conductive bond pads on different layers.

6. The microelectronic assembly of claim 5 , wherein the conductive traces near the first side of the interposer structure are approximately the same thickness as the conductive traces near the second side of the interposer structure.

7. The microelectronic assembly of claim 5 , wherein the conductive traces closer to the first side of the interposer structure are thinner than the conductive traces closer to the second side of the interposer structure.

8. The microelectronic assembly of claim 5 , wherein the conductive vias closer to the first side of the interposer structure are smaller than the conductive vias closer to the second side of the interposer structure.

9. the interposer structure includes alternating layers of a first glass material and a second glass material; the conductive via is in the first glass material; The microelectronic assembly of claim 6 , wherein the conductive traces are in a second glass material.

10. the first glass material includes silicon and oxygen; The microelectronic assembly of claim 9 , wherein the second glass material comprises carbon, silicon, and oxygen.

11. a layer comprising silicon and nitrogen between the conductive bond pad and the conductive trace; 11. The microelectronic assembly of claim 5, wherein a subset of the conductive vias are in the layer comprising silicon and nitrogen.

12. 11. The microelectronic assembly of claim 1, wherein the first side of the interposer structure and the second side of the interposer structure each comprise a layer comprising silicon and nitrogen.

13. 11. The microelectronic assembly of claim 1, wherein the interposer structure further comprises passive electronic components including inductors and capacitors.

14. 11. The microelectronic assembly of claim 1, wherein the substrate includes multiple layers of conductive traces within the organic dielectric material.

15. 1. A microelectronic assembly, comprising: A package substrate, an interposer layer including glass; a package substrate including a substrate layer on a first surface of the interposer layer, the substrate layer including an organic dielectric material; a plurality of IC dies coupled by interconnects to a second surface of the interposer layer, the second surface being opposite the first surface; the IC dies of the plurality of IC dies are conductively coupled to one another by first conductive structures of the interposer layer; the substrate layer includes a second conductive structure of the organic dielectric material; through-glass vias (TGVs) in the interposer layer conductively couple the plurality of IC dies to the second conductive structure; Microelectronic assembly.

16. The first conductive structure of the interposer layer comprises: a conductive bond pad; multiple layers of conductive traces; 16. The microelectronic assembly of claim 15, further comprising: conductive vias connecting said conductive traces and said conductive bond pads on different layers.

17. 17. The microelectronic assembly of claim 16, wherein the conductive traces near the first side of the interposer layer are approximately the same thickness as the conductive traces near the second side of the interposer layer.

18. 17. The microelectronic assembly of claim 16, wherein the conductive traces closer to the first side of the interposer layer are thinner than the conductive traces closer to the second side of the interposer layer.

19. 17. The microelectronic assembly of claim 16, wherein the conductive vias closer to the first side of the interposer layer are smaller than the conductive vias closer to the second side of the interposer layer.

20. the interposer layer includes alternating layers of a first glass material and a second glass material; the conductive via is in the first glass material; 20. The microelectronic assembly of claim 16, wherein the conductive traces are in the second glass material.

21. the first glass material includes silicon and oxygen; 21. The microelectronic assembly of claim 20, wherein the second glass material comprises carbon, silicon, and oxygen.

22. 1. A microelectronic assembly, comprising: A package substrate; a first plurality of IC dies coupled to the package substrate; an interposer structure coupled to the package substrate laterally adjacent the first plurality of IC dies; a second plurality of IC dies coupled to the interposer structure on a side of the interposer structure opposite the package substrate; the interposer structure is conductively coupled to the first plurality of IC dies through the package substrate; the interposer structure includes glass, a plurality of conductive trace layers within the glass, and through-glass vias (TGVs); individual IC dies of the second plurality of IC dies are conductively coupled by conductive traces within the interposer structure; Microelectronic assembly.

23. 23. The microelectronic assembly of claim 22, wherein the interposer structure is conductively coupled to the first plurality of IC dies through a third plurality of IC dies embedded in the package substrate.

24. 24. The microelectronic assembly of claim 23, wherein an individual IC die of the third plurality of IC dies is between adjacent surfaces of the first plurality of IC dies and the interposer structure.

25. 25. The microelectronic assembly of any one of claims 22 to 24, wherein the package substrate comprises multiple conductive trace layers of organic dielectric material.

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