Horizontal gate-all-around devices with improved channel uniformity.

Abstract

A method for forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed from a second material; removing the second layers of the superlattice; etching the first material layers to form trimmed first layers from the first material layers, wherein the amount of material removed from each of the first layers is different; forming capping layers on the first layers; measuring at least one of the distance between the capping layers formed on each of the first layers, the thickness of each of the capping layers formed on each of the trimmed first layers, and the combined thickness of the trimmed first layer and each of the capping layers formed thereon; and calculating a new thickness of the etched first layers based on the difference in the measurements.

Description

[Technical Field]

[0001] TECHNICAL FIELD

[0001] Examples described herein relate generally to the field of semiconductor processing, and more particularly to integrated semiconductor processing solutions. [Background technology]

[0002]

[0002] Reliable fabrication of sub-nanometer features is one of the key challenges in the next generation of very large scale integration (VLSI) and very large scale integration (ULSI) semiconductor devices. As the limits of circuit technology are pushed, the demand for processing power is increasing due to the shrinking dimensions of VLSI and ULSI technologies. As the dimensions of integrated circuit components shrink (e.g., at nanometer dimensions), the materials and processes used to fabricate the components are typically carefully selected to obtain sufficient levels of electrical performance.

[0003] One known device structure is the horizontal gate-all-around (HGAA) structure, in which multiple semiconductor channels are stacked one above the other, beneath a gate electrode and extending between the source and drain of each semiconductor device. The semiconductor channels are constructed in part by epitaxially depositing multiple alternating layers of semiconductor and sacrificial material, thereby forming a superlattice structure. The superlattice structure is patterned to create multiple superlattice fins or mesas, each with a width slightly greater than the length of the completed channel. The sacrificial material is removed, leaving individual lengths of semiconductor material that form the individual channels. These individual lengths (i.e., wires) of semiconductor material are then trimmed to the desired channel length, resulting in the removal of a portion of each wire on the other surface. A capping layer (e.g., an additional semiconductor layer) is then formed on each wire, which is then coated with a high-k dielectric, after which a work function tuning material is formed thereon. Thus, the high-k dielectric and work function tuning material are deposited on the surface of each wire facing the underlying substrate, as well as on the surface of the wire opposite the wire. In one known structure, the first semiconductor layer in the superlattice structure is silicon, such as single-crystal silicon, which may be a doped single-crystal silicon material epitaxially grown on an underlying single-crystal substrate or layer. In this known structure, the sacrificial material is, for example, silicon germanium, which may be epitaxially grown or formed on the underlying silicon crystalline structure by deposition techniques. The use of silicon and silicon germanium allows the silicon layer of the known structure to be formed as a single-crystal layer. The capping layer may be, for example, a silicon germanium layer.

[0004] To provide repeatable functional performance from device to device, variations in the thickness of the silicon layers, the silicon germanium layers, and the thickness of the high-k dielectric and work function tuning layer materials formed between adjacent silicon layers surrounded by silicon germanium should be minimized. However, it has been found that the thicknesses of these layers can vary significantly in stacks of silicon, silicon germanium, high-k dielectrics, and work function tuning layers. This has resulted in unsatisfactory performance and repeatability of the structure. Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure include a semiconductor processing method. In one aspect herein, a method of forming a semiconductor device includes:

[0006] forming a first superlattice on a first substrate, the first superlattice including alternating sublayers of a first material and sublayers of a second material comprising a semiconductor, the sublayers of the first material having a first thickness and the sublayers of the second material having a second thickness, at least the first sublayer of the first material and the second sublayer of the first material being formed in the first superlattice, the second sublayer of the first material being interposed between the first sublayer of the first material and the substrate;

[0007] removing a sublayer of a second material from the first superlattice;

[0008] etching the first sublayer and the second sublayer of the first material of the first superlattice to remove a portion of the first material of the first superlattice to form a first trimmed sublayer of the first material and a second trimmed sublayer of the first material, wherein an amount of the first material removed from the first sublayer of the first material is greater than an amount of material removed from the second sublayer of the first material;

[0009] depositing a capping layer over the first trimmed sublayer of the first material of the first superlattice, over the second trimmed sublayer of the first material of the first superlattice, and over the exposed surface of the substrate;

[0010] measuring a distance between a capping layer on the first sublayer and a capping layer on the second sublayer, a distance between a capping layer on the second sublayer and a capping layer on the substrate, and determining a first difference in said distances;

[0011] forming a second superlattice on a second substrate, the second superlattice including alternating sublayers of a first material and sublayers of a second material comprising a semiconductor, the sublayers of the first material having a first thickness and the sublayers of the second material having a second thickness, at least the first sublayer of the first material and the second sublayer of the first material being formed in the second superlattice, the second sublayer of the first material being interposed between the first sublayer of the first material and the second substrate;

[0012] removing a sublayer of a second material from the second superlattice and the second substrate;

[0013] etching the first sublayer of the first material and the second sublayer of the second superlattice to remove a portion of the first material of the second superlattice to form a first trimmed sublayer of the first material and a second trimmed sublayer of the first material, wherein process conditions used to remove the portion of the first sublayer of the first material and the portion of the second sublayer of the first material are different from process conditions used to remove the portion of the first sublayer of the first material and the portion of the second sublayer of the first material of the first superlattice;

[0014] depositing a capping layer over the first trimmed sublayer of the first material of the second superlattice, over the second trimmed sublayer of the first material of the second superlattice, and over the exposed surface of the substrate;

[0015] depositing a capping layer, wherein a difference between a distance between the capping layer on the first sublayer of the first material of the second superlattice and a distance between the capping layer on the second sublayer of the first material of the second superlattice and a distance between the capping layer on the second sublayer of the first material of the second superlattice and a capping layer on the second substrate is less than the first difference.

[0006]

[0016] In another aspect herein, a method for forming a semiconductor device on a substrate comprises:

[0017] forming a superlattice on a substrate, the superlattice comprising alternating sublayers of a first material and sublayers of a second material comprising a semiconductor, at least a thickness of the first sublayer of the first material and a thickness of the second sublayer of the first material being different, the second sublayer of the first material being interposed between the first sublayer of the first material and the substrate;

[0018] removing a sublayer of the second material from the superlattice;

[0019] etching the first sublayer of the first material and the second sublayer of the first material such that a different amount of first material is removed from the first sublayer of the first material compared to an amount of material removed from the second sublayer of the first material;

[0020] depositing a capping layer on the etched first sublayer of the first material and on the etched second sublayer of the first material, wherein a thickness of the capping layer deposited on the first sublayer of the first material is different from a thickness of the capping layer deposited on the second sublayer of the first material.

[0007]

[0021] In another aspect, a method for forming a multi-layer semiconductor device comprises:

[0022] providing a first substrate;

[0023] forming a superlattice on a first substrate, the superlattice including a plurality of alternating first layers comprised of a first material and second layers formed of a second material;

[0024] selectively removing the second layer of the superlattice;

[0025] exposing the first layers of the superlattice to an etchant using first process conditions to remove portions of the first material to form trimmed first layers, wherein the amount of material removed from each of the first layers is a different amount;

[0026] forming a capping layer over a first layer in the superlattice stack;

[0027] measuring at least one of the distance between capping layers formed on each of the first layers, the thickness of each of the capping layers formed on each of the trimmed first layers, and the combined thickness of the trimmed first layer and each of the capping layers formed thereon;

[0028] Calculating a new thickness of the trimmed first layer based on a difference between at least one of the distance between the capping layers formed on each of the first layers, the thickness of each of the capping layers formed on each of the trimmed first layers, and the combined thickness of the trimmed first layer and each of the capping layers formed thereon.

[0008]

[0029] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, can be had by reference to examples, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only some examples and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective examples. [Brief explanation of the drawings]

[0009] [Figure 1]

[0030] FIG. 1 is a partial cross-sectional view of a horizontal gate-all-around structure. [Figure 2a]

[0031] 10A-10C are schematic cross-sectional views illustrating the effect of certain operations in the processing of a horizontal gate-all-around structure. [Figure 2b] 10A-10C are schematic cross-sectional views illustrating the effect of certain operations in the processing of a horizontal gate-all-around structure. [Figure 2c] 10A-10C are schematic cross-sectional views illustrating the effect of certain operations in the processing of a horizontal gate-all-around structure. [Figure 2d] 10A-10C are schematic cross-sectional views illustrating the effect of certain operations in the processing of a horizontal gate-all-around structure. [Figure 3a]

[0032] 10A-10C are schematic cross-sectional views illustrating the effect of a first alternative sequence of operations in processing a horizontal gate-all-around structure. [Figure 3b] 10A-10C are schematic cross-sectional views illustrating the effect of a first alternative sequence of operations in processing a horizontal gate-all-around structure. [Figure 3c] 10A-10C are schematic cross-sectional views illustrating the effect of a first alternative sequence of operations in processing a horizontal gate-all-around structure. [Figure 3d] 10A-10C are schematic cross-sectional views illustrating the effect of a first alternative sequence of operations in processing a horizontal gate-all-around structure. [Figure 4a]

[0033] 10A-10C are schematic cross-sectional views illustrating the effect of a first alternative sequence of operations in processing a horizontal gate-all-around structure. [Figure 4b] 10A-10C are schematic cross-sectional views illustrating the effect of a first alternative sequence of operations in processing a horizontal gate-all-around structure. [Figure 4c] 10A-10C are schematic cross-sectional views illustrating the effect of a first alternative sequence of operations in processing a horizontal gate-all-around structure. [Figure 4d] 10A-10C are schematic cross-sectional views illustrating the effect of a first alternative sequence of operations in processing a horizontal gate-all-around structure. [Figure 5]

[0034] 1 is a schematic top view of an exemplary multi-chamber processing system, according to some examples of the present disclosure. [Figure 6]

[0035] 1 illustrates a cross-sectional view of a processing chamber that can be used to perform a cleaning process, according to some examples of the present disclosure. [Figure 7]

[0036] 1A and 1B are cross-sectional views of a processing chamber that can be used to perform selective etching and trimming processes according to some examples of the present disclosure. [Figure 8]

[0037] 1 is a cross-sectional view of a thermal processing chamber that can be used to perform epitaxial growth, according to some examples of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] For ease of understanding, where possible, identical reference numbers have been used to designate identical elements that are common to several figures.

[0011]

[0038] Generally, examples described herein relate to semiconductor device structures, methods for forming semiconductor structures, and semiconductor processing systems for forming individual semiconductor layers within a superlattice, separating the individual semiconductor structures within the superlattice with gaps, trimming the semiconductor layers, and forming a capping layer on the trimmed layers. In one aspect herein, the difference in spacing between the separated semiconductor structures is reduced. In one aspect, the individual semiconductor layers spaced apart by gaps as intermediate structures in device fabrication are single-crystal silicon layers. Additionally, the capping layer can be provided as a silicon germanium layer epitaxially grown or formed on the individual single-crystal silicon layers. As described above, a reduction in variation in spacing or gap between the individual trimmed semiconductor layers can be provided. For example, initially forming each layer of the layers to have a respective thickness results in a more uniform trimmed semiconductor layer thickness due to variations in material removal rate and variations in material removed from each layer of the layers during trimming. In another aspect, variations in the parameters of the trimming process are used to result in a more uniform trimmed semiconductor layer thickness. The structures formed by the above processing can be implemented, for example, in horizontal gate-all-around field-effect transistors (HGAA FETs). The method and semiconductor processing system can provide an integrated solution for trimming the layer to be trimmed and then epitaxially growing a capping layer on the trimmed layer.

[0012]

[0039] 1, there is shown a partial cross-sectional view of a horizontal gate-all-around structure (i.e., HGAA) formed on a substrate 2. Although only one side of the HGAA is shown, those skilled in the art will recognize that the device includes a structure that includes a source or drain on the opposite side of the structure from the illustrated source or drain 60.

[0013]

[0040] Here, multiple "wires" formed of a semiconductor (e.g., epitaxially grown or deposited single-crystal silicon) extend horizontally or laterally from a source or drain 60 to another source or drain (not shown) on the right side of the figure. Each wire is formed as a post-trim composite wire 52'-56', as described later in this document. Each wire (here, post-trim composite wire 52'-56') is covered by a surrounding capping layer 24. This capping layer is preferably epitaxially grown on the post-trim composite wire 52'-56' to surround the post-trim composite wire 52'-56' and also grown on the top surface of the substrate 2. The capping layer is, for example, silicon germanium. An additional gate functional layer is grown or deposited on the capping layer 24, and a gate 62 is formed thereon. Additional intermediate layers, such as barrier layers, high-k dielectric layers, and work function adjustment layers, or other layers, may be incorporated into the stack of layers shown in FIG. 1 . Therefore, the structure of FIG. 1 is provided as an example of an HGAA structure, and is not intended to be limiting.

[0014]

[0041] 2a-2d are cross-sectional views of a portion of the HGAA structure of FIG. 1 illustrating the results of processing operations used to form the stack of post-trim wire composites 52′, 54′, and 56′ and capping layer 24 of the HGAA structure. Referring to FIGS. 2a-2d, the results of a series of steps are sequentially shown to separate individual semiconductor layers of the wire stack from individual layers of the superlattice, trim the individual semiconductor layers separated from the superlattice, and form a capping layer (e.g., a second semiconductor layer) on the trimmed semiconductor layer. Here, the superlattice is formed by sequentially growing multiple alternating layers of sacrificial material (e.g., silicon germanium layer 6) and semiconductor layers (e.g., silicon layer 8) on substrate 2. A first sacrificial layer is epitaxially grown on substrate 2, and a first semiconductor layer is epitaxially grown on the first sacrificial layer. Subsequent sacrificial and semiconductor layers are alternately epitaxially grown thereon.

[0015]

[0042] In Figure 2a, a superlattice with separated fins or mesas 10 on a substrate includes semiconductor layers as doped monocrystalline silicon and sacrificial layers as silicon germanium. The thickness of each semiconductor layer is formed to be the same for each other, within deposition tolerances. In Figure 2a, the thickness of each sacrificial layer is formed to be the same for each other, within deposition tolerances. The thicknesses of the semiconductor layers and sacrificial layers can be the same or different.

[0016]

[0043] First, the left side of Figures 2-4 (here, Figures 2a, 3a, and 4a) represents a cross-sectional view of a fin or mesa 10 of a single superlattice of multiple fins or mesas defined from a superlattice stack by a reactive ion etching process. It should be understood that one or more of these fins or mesas 10 (extending inward and outward of the plane of Figures 5-7) may be aligned with sidewalls facing each other over the width of a trench 11 etched into the superlattice in the Y direction, with the trench width in the X direction of Figures 2a-4a. For ease of illustration, only one of the fins or mesas 10 is shown in Figures 2a-4a. The trench 11 defines or separates the fin or mesa 10 having alternating silicon germanium layers 6 and silicon layers 8 from a superlattice (not shown) of silicon layers 8 and silicon germanium layers 6. This same etching step can be used to etch trenches 11 into the underlying monocrystalline silicon substrate 2 to define separate linear segments or mesas (extending inward or outward from the plane of FIGS. 2a-4a) of the semiconductor substrate 2 below each of the fins or mesas 10. Here, the initial thicknesses of silicon layers t1a, t1b, and t1c within the superlattice in the Y direction (and within the fin or mesa 10) in FIG. 2c are equal to each other and within their respective deposition tolerances or capabilities. In other words, in the original superlattice, the thicknesses t1a, t1b, and t1c of silicon layers 8 are related such that t1a = t1b = t1c. Similarly, the thicknesses s1a, s1b, and s1c of the sacrificial silicon germanium layers within the superlattice in the Y direction (and within the fin or mesa 10) in FIG. 2a are equal to each other and within their respective deposition tolerances or capabilities. In other words, in the original superlattice, the thicknesses s1a, s1b, and s1c of the sacrificial silicon germanium layer 6, i.e., the spacing between the individual silicon layers 8 and the spacing between the bottom silicon layer 8 and the substrate, are related by s1a=s1b=s1c.

[0017]

[0044] After the fins or mesas 10 are defined from the superlattice of alternating silicon germanium layers 6 and silicon layers 8, the isolated portions of the sacrificial silicon germanium layer 6 therein are removed from the stack or fin 10 using a selective removal process with the results shown in FIG. 2b. The silicon germanium layer 6 is selectively removed by a selective etching process (e.g., a selective isotropic etching process) using an etching gas composed of, for example, NF. The NF dissociates into F radicals and F in a remote plasma source and then flows over the substrate 2, passing through the trenches, contacting the silicon germanium layer 6 and selectively removing the silicon germanium therein. This leaves individual isolated portions of the silicon layer 8 in each fin or mesa 10, here three silicon composite wires 52, 54, and 56. These three composite wires are spaced apart in the Y direction of FIG. 2b by the respective thicknesses of the removed sacrificial silicon germanium layers 6 (here, s1a and s1b). These sacrificial layers have equal or nearly equal thicknesses. In other words, the spacing between the individual composite wires 52, 54, and 56 is equal to the original thickness of the removed silicon germanium layers. The third composite wire 56, closest to the isolated mesa of the substrate 2, is similarly spaced apart from the opposing top surface of the substrate 2 by the thickness s1c of the removed sacrificial silicon germanium layer 6. Therefore, the distance in the Y direction between the opposing surfaces of the semiconductor substrate 2 and the third composite wire 56, the distance between the second and third composite wires 54, 56, and the distance between the first and second composite wires 52, 54 are approximately the same distance or width, and are approximately equal to the thicknesses s1a, s1b, and s1c of the silicon germanium layer 6 that once extended between the above-mentioned distances, i.e., s1a=s1b=s1c.

[0018]

[0045] After being separated from the silicon layer 8 of the superlattice, the individual first through third composite wires 52, 54, and 56 are trimmed, i.e., reduced in size. Trimming is performed using an etching process (e.g., a remote plasma etching process), in which a reactive etching gas is at least partially ionized in a plasma located remote from the substrate. Radicals from the etching reactive gas are directed or flowed toward the substrate, etching the silicon of the first through third composite wires 52-56 and producing first through third post-trim composite wires 52', 54', and 56', which, as shown in FIG. 2b, have a smaller thickness in the Y direction of FIG. 2c and a smaller width in the X direction of FIG. 2c than the first through third composite wires 52-56. Here, the original size of each of the first through third composite wires 52-56 is indicated in FIG. 2c by the dashed lines surrounding the corresponding trimmed states.

[0019]

[0046] The processing chamber 120 shown in FIG. 7 can be used to trim the first through third wire composites 52-56, and the trimming process includes flowing a first etching gas, which may include one or more of nitrogen trifluoride (NF), a mixture of nitrogen trifluoride (NF) and helium (He), etc., from a gas source 316 via flow 318, and flowing a second etching gas, which may include one or more of nitrogen trifluoride (NF), etc., from a gas source 338 via flow 340. A mixture of nitrogen trifluoride (NF3) and helium (He) may have a ratio ranging from 1:350 (NF3:He) to 1:120 (NF3:He), and this mixture may flow from gas source 316 at a flow rate ranging from 5000 sccm to 7000 sccm, e.g., a nitrogen trifluoride (NF3) flow rate ranging from 10 sccm to 25 sccm and a helium (He) flow rate ranging from about 3000 sccm to 3500 sccm. The pressure within chamber 120 may be maintained in a range from 0.25 Torr to about 2 Torr. The power supplied by RF power source 320 may range from about 10 W to about 50 W, and the frequency may be from about 10 MHz to about 50 MHz (e.g., 13.56 MHz). This process can be performed in a Selectra™ Etch chamber available from Applied Materials, Inc., Santa Clara, Calif., in which gases are excited into a plasma within the lid assembly 304 and the excited NF3 and H2 gases are then flowed onto the substrate.

[0020]

[0047] Note that this trimming process results in a thickness t1a' of the first post-trim composite wire 52' being slightly thinner than a thickness t1b' of the second post-trim composite wire 54' (which is slightly thinner than a thickness t1c' of the post-trim composite wire 56'). In other words, the thicknesses t1a', t1b', and t1c' of the trimmed composite wires have the relationship t1c' > t1b' > t1a'. This difference in thickness is believed to be the result of depletion of etchant chemicals during the trimming process in the depth direction (i.e., Y direction) of the trenches 11 between adjacent fins or mesas 10, even though the composite wires 52, 54, and 56 initially had the same thicknesses t1a = t1b = t1c. In other words, the relative available amount of etchant in the first composite wire 52, which is furthest from the underlying substrate 2, is greater than the available amount in the second composite wire 54, as a result of some of the etchant being consumed in the etch-based trimming of the first composite wire 52. Similarly, the relative available amount of etchant in the third composite wire 56, which is closest to the substrate 2 and deepest in the trench 11, is likely to be less than the available amount in the second composite wire 54, as a result of some of the etchant being consumed in the etch-based trimming of the first and second composite wires 52, 54.

[0021]

[0048] After the post-trim wire preforms 52', 54', 56' are prepared, an additional second semiconductor layer (here, the silicon germanium capping layer 24 described earlier in this specification) is deposited thereon to complete the final wire 58 structure. The resulting final wire 58 structure includes three individual wires 58, namely, first through third final wires 58a, 58b, and 58c, each composed of a corresponding silicon post-trim wire preform 52'-56' and the silicon germanium capping layer 24 deposited thereon. The first through third final wires 58a, 58b, and 58c are spaced apart from each other and from the underlying semiconductor substrate 2 by spacing distances s1a'-s1c'. Here, the thickness d1 in the Y direction of FIG. 2d of the capping layer 24 deposited on the first post-trim wire composite 52' is thinner than the thickness d2 in the Y direction of FIG. 2d of the capping layer 24 grown on the second post-trim wire composite 54'. Similarly, the thickness d3 in the Y direction of FIG. 2d of the capping layer 24 on the third post-trim wire composite 56' is thinner than the thicknesses grown on both the first and second post-trim wire composites 52, 54. In other words, the relationship between the thicknesses d1, d2, and d3 of the capping layer 24 is d1>d2>d3. As a result of the above and the respective thicknesses of the post-trim wire preforms 52', 54', and 56', the thicknesses T1-T3 of the final wires 58a, 58b, and 58c vary in the Y direction of FIG. 2d. The distances s1a'-s1c' between the first to third final wires 58a-58c and between the third final wire 58c and the opposing surface of the capping layer 24 on the substrate 2 in the Y direction of FIG. 2d also vary. Here, the distance s1a' between the opposing surfaces of the first and second final wires 58a, 58b is smaller than the distance s1b' between the opposing surfaces of the second and third final wires 58b, 58c. The distance s1c' between the opposing surfaces of the third final wire 58c and the opposing surface of the capping layer on the substrate 2 is larger than the distance s1b'. In other words, s1c' > s1b' > s1a'.As a result, the thicknesses of the high-k dielectric layer and the work function adjustment layer subsequently formed to fill the gaps between adjacent first through third final wires 58a-58c and between the third final wire 58c and the opposing surface of the capping layer 24 on the substrate 2 will differ from one another, resulting in different electrical performances for the first through third wires 58a-c, which function as channels. In addition, the spacing between two adjacent first through third final wires 58a-c may be too small to accommodate the thickness of the high-k dielectric layer, the work function adjustment layer, or both. These layers are necessary for one or more of the first through third final wires 58a-c to operate with the desired performance as a functional channel.

[0022]

[0049] Provided herein are procedures and processes for overcoming such layer thickness and spacing variations and for producing more repeatable and more uniform final wire spacing and thickness. These procedures and processes are provided, at least in part, by adjusting the thickness of the individual first through third post-trim wire composites 52'-56' to ensure that a desired minimum spacing is maintained between the first through third final wires 58a-58c after the capping layer is formed. In particular, the thickness of the silicon layer 6 within the superlattice, or the trimming process of the first through third post-trim wire composites 52'-56', or both, are adjusted or modified to produce a resulting stack of spaced-apart first through third final wires 58a-58c with more uniform spacing or distance between the post-trim wire composites in the Y direction and more uniform thickness.

[0023]

[0050] 3a-3d, there is shown a schematic representation of the results of a series of processing operations used to reduce thickness variations of the first through third final wires 58a-58c, and to reduce variations in spacings s1a' and s1b' between the first through third final wires 58a-58c, as well as spacing s1c' between the third final wire 58c closest to the substrate 2 and the opposing surface of the capping layer 24 on the substrate 2. In the process used to form the first through third final wires 58a-58c of FIGS. 2a-2d, variations in thickness of the capping layer 24 and the trimmed wire composite contribute to differences in thickness in the Y direction of the first through third final wires 58a-58c. Here, to compensate for variations between adjacent completed wires 58a-58c and between the third completed wire 58c and the surface of the capping layer 24 on the substrate 2, the relative thicknesses in the Y direction of the individual silicon germanium layers 6 and silicon layers 8 within the superlattice stack are varied compared to those shown in FIG. 2a. Here, on a trimmed wire composite where the capping layer is essentially deposited to a thickness less than the other trimmed wire composites, the thickness of the silicon layer 8 within the superlattice is greater than the other silicon layers 8 within the superlattice and is greater than the thickness of the silicon layer 8 in FIG. 2a. On a trimmed wire composite where the capping layer 24 is deposited to a thickness greater than the other thicknesses of the trimmed wire composite, the silicon layer 8 is formed thinner than the other silicon layers 8 within the superlattice and is thinner than the thickness of the silicon layer 8 in FIG. 2a.

[0024]

[0051] To satisfy the same desirable design constraints of the partially constructed HGAA structure in FIGS. 2a-2d, the overall thickness of the superlattice comprised of the stack of silicon germanium layers 6 and silicon layers 8 should remain the same as that of FIG. 2a, within design and deposition tolerances. Similarly, the X-direction centerlines (not shown) of the first through third final wires 58a-c should preferably be located the same distance in the Y-direction from the top surface of the substrate, as in FIG. 2a. If the thickness of one of the three sets of silicon layers 8 and silicon germanium layers 6 varies because of the above constraints, the thickness of the other silicon layers 8 and silicon germanium layers 6 should also vary, but in the opposite direction. The desired end result is to provide multiple final wires 58 spaced the same or nearly the same distance from each other and from the surface of capping layer 24 on substrate 2, and for the thickness of the final wires to be more uniform than the thickness of the final wires of FIG. 2d.

[0025]

[0052] Here, as described herein, the thickness of silicon layer 8 is selected to result in relatively equal thicknesses of final wires 58a-58c, and the thickness of silicon germanium layer 6 is selected to result in relatively equal spacing between final wires 58a-58c and between final wire 58c and the opposing surface of capping layer 24 on substrate 2. Thus, as shown in FIG. 3a, each silicon layer 8 may have its own thickness within the superlattice, and each silicon germanium layer 6 may have its own thickness. Next, silicon germanium layer 6 is selectively removed in the same manner as described herein with respect to FIGS. 2a-2d, resulting in the result shown in FIG. 3b. Here, the spacing between individual composite wires 52-56 is the spacing of the previously removed silicon germanium layer 6. Note that these spacings are not equal to one another. Also, the thicknesses of composite wires 52-56 are different from one another, as opposed to the equal thicknesses shown in FIG. 2c. Next, the composite wires 52-56 are isotropically etched in the same manner as described herein with respect to Figures 2a-2d, resulting in post-trim composite wires 52'-56' having different thicknesses as shown in Figure 3c. Thereafter, using the same epitaxial deposition process to form capping layer 24 as was used to form capping layer 24 at each thickness shown in Figure 2d, each of the post-trim composite wires 52'-56' and the exposed surface of substrate 2 are now covered with capping layer 24. Using the same process conditions as were used to form capping layer 24 in Figure 2d, the same or approximately the same thickness non-uniformity of capping layer 24 over each of the post-trim composite wires 52'-56' is formed in Figure 3d as formed in Figure 2d. Because the thicknesses of post-trim wire preforms 52'-56' have been modified compared to those in Figures 2c and 2d, the resulting final wire thicknesses 58a-58c are the same or approximately the same, and the spacing between final wires 58a-58c and between final wire 58c and the opposing surface of capping layer 24 on substrate 2 is the same or approximately the same. Depending on the application requirements of the HGAA, there may be variations in wire thickness, spacing, or both within design tolerances, but they are essentially the same.

[0026]

[0053] To implement the resulting structures shown in FIGS. 3a-3d, a preliminary assumption is made that the chemical depletion effects that cause differences in the thickness of the post-trim composite wires 52'-56' shown in FIG. 2c and the thickness of the capping layer 24 deposited on the post-trim composite wires 52'-56' shown in FIG. 2d are not significantly altered by varying the initial thickness of the silicon layer 8 in the superlattice compared to the initial thickness shown in FIG. 2a. Additionally, based on the design specifications of the HGAA device, the minimum spacing between the final wires 58a-58c is known. Therefore, after the silicon trimming process and the subsequent formation of the capping layer 24 thereon, the thickness of the silicon layer 8 can be modified to result in final wires 58a-58c having the same or nearly the same thickness. Similarly, as a result of the variation in the silicon layer thickness, the thickness of the silicon germanium layer can be modified to result in uniform or nearly uniform spacing between adjacent final wires 58a-58c and between the final wires 58c and the opposing surface of the capping layer 24 on the substrate 2. By measuring the thickness of each of the final wires 58a-58d and the thickness of the capping layer 24 on each of these final wires 58a-58c in Figure 2d, the change in thickness of the silicon layer 8 that results in final wires 58a-58c of uniform or more uniform thickness is determined. This assumes that a change in thickness in the Y direction of any one of the silicon layers 8 in the superlattice will result in an equal change in thickness in the Y direction on the post-trim wire composites 52'-56', and that using the same trimming and capping layer deposition process conditions will result in trimming and capping layer properties similar to those shown in Figures 2c and 2d. Next, based on the assumed thicknesses of the post-trim wire preforms 52'-56' and the capping layer 24 thereon, and the assumed thickness of the capping layer on the etched or trimmed surface of the substrate 2, the relative position of each silicon layer 8 with respect to the top surface of the substrate 2 can be defined to create equal spacing between the final wires 58a-58c and between the final wire 58c and the opposing surface of the capping layer 24 on the substrate 2.In this determination, it is assumed that the thickness of the capping layer 24 formed on the trimmed composite wires 52'-56' and on the top surface of the substrate 2 remains substantially unchanged compared to the result in FIG. 2d. Therefore, the desired final thickness of each of the final wires 58a-58c is selected, and the spacing between the composite wires 52-56 is similarly selected. The post-trim composite wire thickness required for each of the final wires 58a-58c is then mathematically determined based on the assumed thickness of the capping layer 24 thereon. The difference between the desired and actual thicknesses of the post-trim composite wires 52'-56' is then determined. If the thickness of the post-trim composite wires 52'-56' is less than the new desired thickness, this difference between the actual and desired thicknesses in FIG. 2d is added to the thickness of the silicon layer 8 within the superlattice in which the target post-trim composite wires are formed. Similarly, if the desired thickness is less than the thickness of post-trim wire composites 52'-56' in Figure 2d, the thickness of silicon layer 8 is reduced within the superlattice. Next, the thickness of silicon germanium layer 6 within the superlattice is defined that is required to result in uniform spacing between final wires 58a-58c, and between final wire 58c and the capping layer on substrate 2.

[0027]

[0054] To determine the thickness of each silicon germanium layer 6 within the superlattice, the Y-direction center position of each of the post-trim wire composites 52'-56' after modification of the equally spaced final wires 58a-58c shown in Figure 3d can be used as the Y-direction center of the silicon layer 8 of the superlattice corresponding to that post-trim wire composite. Next, based on the new thickness of the silicon layer 8 after modification shown in Figure 3c and the center of each silicon layer 8 in the Y direction, the thickness of the silicon germanium layer 6 required to accurately position each silicon layer 8 relative to the substrate can be calculated, and this thickness of the silicon germanium layer 6 can be used to form the superlattice. Again, when determining the locations of the trimmed composite wires 52'-56' to produce the evenly spaced final wires 58a-c, it is assumed that the amount of silicon removed from the composite wires 52-56 is approximately the same as that removed in the example of Figures 2a-2d herein, and that the thickness of the capping layer 24 on each of the post-trimmed composite wires 52'-56' is the same as in the example of Figures 2a-2d herein, where the superlattice thickness of the fin or mesa 10 of Figures 2a and 3 is the same within design tolerances.

[0028]

[0055] In one embodiment herein, the average values ​​of thicknesses T1-T3 of the first through third final wires 58a-58c in FIG. 2a can be calculated to determine the desired thickness of the modified-thickness silicon layer 8 in FIG. 3a. Using this information, the thickness of the silicon layer 8 within the superlattice can then be modified. As a result, corresponding silicon layer 8 thicker than the average thickness of the final wires 58a-58c in FIG. 2d will be thinner, and corresponding silicon layer 8 thinner than the average thickness of the final wires 58a-58c in FIG. 2d will be thicker. Alternatively, a median thickness or other paradigm can be used to resize the thickness from the equivalent thickness of the silicon layer 8 within the superlattice in FIG. 2d. If the median values ​​of thicknesses T1-T3 are used, silicon layer 8 corresponding to final wires thicker than the median thicknesses T1-T3 in FIG. 2b will be modified so that silicon layer 8 having a corresponding final wire 58 with a thickness thicker than the median will be modified to be thinner than silicon layer 8 having a corresponding final wire 58 with a thickness thinner than the median. Using the above methodology, the minimum design thickness of the post-trim wire preforms 52'-56' must be considered.

[0029]

[0056] Using the median or average thickness of the first through third final wires 58a-58c, two different thickness variations are incorporated into the average or median value: the variation in thicknesses t2a'-t2c' of the first through third post-trim wire composites 52, 54, and 56, and the variation in thicknesses d1-d3 of the second silicon germanium layer 24. An additional paradigm for varying the dimensions of the silicon layer 8 within the superlattice is to define the average or median thicknesses d1-d3 of only the second silicon germanium layer 24 of FIG. 2d. The difference in the average (or median) thicknesses is used to modify the thickness of the silicon layer 8 of the superlattice corresponding to a particular one of the first through third final wires 58.

[0030]

[0057] The difference in spacings s1a', s1b', and s1c' of the resulting structure of Figure 2d can also be used to define the value of the thickness change of silicon layer 8 within the superlattice. The difference in spacing reflects the inverse of the change in thickness of first through third final wires 58a-58c, and therefore can be used in the same way as the difference in thickness of first through third final wires 58a-58c to define the thickness change from the silicon layer thickness in Figure 2a to the silicon layer thickness in Figure 3a.

[0031]

[0058] The top silicon layer 8 in the fin or mesa 10 of FIG. 2a results in the first final wire 58a having the largest thickness, and the thickness t2a of the top silicon layer in FIG. 3a is reduced in size relative to the silicon layer 8 in FIG. 2a using one of the variation paradigms described herein. The thickness t2b of the middle silicon layer 8 in the fin or mesa 10 of FIG. 3a results in the second final wire 58b in FIG. 2d having the middle thickness among the first through third final wires 58a through 58c, but the thickness t2b can be varied based on one of the paradigms described herein. Here, the thickness t1b is approximately the same thickness as the corresponding silicon layer 8 in FIG. 2a. The bottom silicon layer in the fin or mesa 10 of FIG. 3a results in the third final wire 58c in FIG. 2d having the smallest thickness among the first through third final wires 58a through 58c, but the layer is increased in size relative to the corresponding silicon layer 8 in FIG. 2a using, for example, a paradigm described herein. As a result, when comparing the thickness of the silicon layer 8 in FIG. 2a and FIG. 3a, t1a>t2a, t1b=t2b, t1c<t2c、t2c> t2b>t2a. Here, the same variation paradigm is preferably used to arrange all thicknesses of silicon layers 8 in the superlattice, provided that more or fewer silicon layers 8 are provided. Known variations in the thickness of silicon layers 8 in the stack define corresponding variations in the thickness of silicon germanium layers 6. The thickness difference of a silicon germanium layer can be defined by varying the thickness of the silicon germanium layer by half the amount of variation of each silicon layer adjacent to it.

[0032]

[0059] Additionally, to achieve greater uniformity in the spacing and thickness of the final wires 58, the relative sizes of the silicon layers within the superlattice can simply be increased or decreased based on the resulting dimensions of the structure in FIG. 2d. By using the same device structure as the initial silicon layer 8 and silicon germanium layer 6 but with different thicknesses, removing the silicon germanium layer, trimming the silicon layer 8, and then forming a silicon germanium capping layer on the trimmed silicon layer 8, the resulting uniformity or non-uniformity can be defined by imaging and measuring the cross-sectional structure shown in FIG. 2d or FIG. 3d, for example, using a TEM or SEM. If the uniformity is acceptable, the new thicknesses of the silicon layer 8 and silicon germanium layer 6 are then used to form the HGAA device. If the spacing of the final wires 58, the thickness of the final wires 58, and the non-uniformity of both are insufficient, new dimensions for the silicon layer 8 and silicon germanium layer 6 can be selected. The superlattice is then processed again, as shown in FIGS. 3a-3d, and the thickness and spacing of the final wires 58 are again evaluated. The relative thicknesses of the silicon and silicon germanium layers can be checked multiple times, if necessary, to determine the final thicknesses of the silicon layer 8 and silicon germanium layer 6.

[0033]

[0060] As described with respect to FIG. 2a, the thickness of the epitaxially grown silicon germanium capping layer 24 is essentially thinner on the trimmed composite wire 56′ closest to the substrate 2 (i.e., deeper within trench 11) than on the first post-trim composite wire 52′ furthest from the substrate 2. Thus, the third silicon layer 8 closest to the substrate 2 is now thicker than the first trimmed silicon layer 8 furthest from the substrate 2 after etching to trim that silicon layer 8. The measured thicknesses of the first through third post-trim composite wires 52′-56′ and the measured thickness of the second silicon germanium layer 24 of FIG. 2d are used to determine the difference between the measured and desired thickness of the final wire 58 in the Y direction, and the resulting change, if any, in the thickness of each silicon layer 8. For example, if the spacing between any of the first through third final wires 58a-58c or the third final wire 58c and the substrate 2 is too small, the thickness of the first silicon germanium layer therebetween can be increased, and the thickness of one or both of the silicon layers 8 adjacent to that thickness can be reduced. Additionally, the thickness of the silicon layer can be increased to form a final wire 58 having a thickness equal to that of the substrate 2. The completed wire formed from that silicon layer will be thinner than the final wires 58 formed from the other silicon layers 8. Here, for example, an increase in the thickness of the lower silicon layer 8 (closer to the substrate 2) can be calculated, assuming that the thickness of the silicon germanium layer when deposited on each silicon layer of each thickness varies approximately the same across the depth of the trench between adjacent fins 10 (as varied in FIG. 2d). Thus, an estimate of the desired thickness of each silicon layer 8 of the superlattice, as well as the corresponding silicon germanium layer between each silicon layer 8 (and between the silicon layer closest to the substrate 2 and the opposing surface of the substrate 2), can be calculated. A superlattice is formed having silicon germanium layers 6 and silicon layers 8 of respective thicknesses in the depth direction of the superlattice (thinner silicon layers 8 furthest from substrate 2 and thicker silicon layers closer to substrate 2).To maintain the superlattice surface farthest from substrate 2 in a desired position relative to the facing surface of the substrate, the thickness of the silicon germanium layer will also vary across the depth of trench 11 (and the superlattice), with the silicon germanium layer 6 farther from substrate 2 being thicker and the silicon germanium layer closer to substrate 2 being thinner. As a result of the above configuration, after selective removal of silicon germanium layer 6, resulting trimming of first through third composite wires 52-56, and deposition of a second silicon germanium layer as capping layer 24 on first through third post-trim composite wires 52'-56', spacings s2a' and s2b' between adjacent completed wires 58a and 58b, and spacing between third completed wire 58c and the facing surface of substrate 2, are more uniform as shown in FIG. 3d compared to FIG. 2d.

[0034]

[0061] If the resulting uniformity of the spacings s2a' and s2b' between adjacent finished wires 58a and 58b, and the spacing s2c' between the third finished wire 58c and the facing surface of the capping layer 24 on the substrate 2, is not sufficiently uniform, a process is performed to measure the resulting dimensions of the new or just-formed set of first through third final wires 58a, 58b, and 58c of the new or just-formed structure, and new thicknesses of the silicon layers in the superlattice stack are defined to provide more uniform thicknesses of the finished wires 58a-58c and spacings s2a', s2b', and s2c'. Thus, for a given horizontal gate-all-around structure, the thicknesses of the silicon layer 8 and the first silicon germanium layer 6 (resulting in uniform spacings s2a', s2b', and s2c' and more uniform finished wire thicknesses 58a-58c) can be iteratively defined and implemented into intermediate preforms for HGAA devices.

[0035]

[0062] 4a-4d, a further approach to reducing spacing variations between adjacent completed wires 58a-58c in a horizontal gate-all-around structure, as well as between the completed wire 58c and the substrate 2, is illustrated schematically. Here, the individual silicon germanium layers 6 and silicon layers 8 are grown or formed to the same thicknesses as those layers in FIG. 3a (e.g., t2a = t2b = t2c). However, to correct for variations in the thickness of the first through third post-trim wire composites 52'-56' across the depth of the trench 11, the characteristics of the trimming process are altered. For example, by reducing the pressure in the processing chamber in which the remote plasma etching process is performed compared to the results for the first through third post-trim wire composites 52-56 in FIG. 2c, where the relative concentrations of gases used in the trimming process remain unchanged, the amount of etching removed from the first post-trim wire composite 52', farthest from the substrate 2, is greater than the amount removed from the second post-trim wire composite 54'. The amount of material removed from the second post-trim composite wire 54' is greater than the amount of material removed or etched from the third post-trim composite wire 56' closest to the substrate 2. The process time for forming the trimmings may be extended compared to the process time required to form the post-trim composite wires 52'-56' in FIG. 2c. As a result, the same thickness as the capping layer 24 in FIG. 2d is deposited thereon, but the spacings s1-s3 between the first through third final wires 58a-58c and the bottom-most third final wire 58c and the opposing surfaces of the capping layer 24 on the substrate 2 are more uniform. The silicon layer 8, i.e., the first through third composite wires 52-56, all have the same thickness and spacing, within deposition and design tolerances. By adjusting the deposition parameters as described, the thickness t2a' of the first post-trim composite wire 52' is thinner than the thickness t2b' of the second post-trim composite wire 54'. Similarly, the thickness t2b' of the second post-trim wire preform 54' is less than the thickness t2c' of the third post-trim wire preform 56'.In other words, by varying the process parameters used to trim the silicon layer 8 and using the same silicon and silicon germanium layer 6 thicknesses as used in the superlattice of Figure 2a, thicknesses of each of the silicon layers 8 can be achieved after trimming compared to the thicknesses of Figure 2c, where by adjusting the above parameters, the thickness of the post-trimmed composite wire follows the paradigm t2c' > t2b' > t2a'. For example, by depositing a silicon germanium capping layer 24 on the first through third post-trim wire composites 52'-56' and the exposed surface of the substrate 2, the spacings s1a', s1b', s1c' of the final wires 58a-58d will be more uniform in thickness than spacings formed using the process described with respect to Figure 2d for the same relative thickness of the capping layer 24 because the capping layers 24 deposited on the first through third post-trim wire composites 52'-56' have different thicknesses on each layer of the first through third post-trim wire composites 52'-56' as described herein with respect to Figure 2d.

[0036]

[0063] The desired relative thicknesses of the first through third post-trim composite wires 52'-56' of FIG. 4c can be defined using the same variation paradigm described for the process described with respect to FIGS. 3a-3c. The difference here is that the desired thickness difference is applied to the formation of the first through third post-trim composite wires 52'-56' rather than the formation of the original silicon layer 8. Here, preferably, the non-uniform thicknesses T1, T2, and T3 of the first through third final wires 58a, 58b, and 58c (e.g., those thicknesses of FIG. 2d) are used to define the desired thicknesses of the first through third post-trim composite wires 52', 54', and 56'. Because the same superlattice stack as FIG. 2a is used, the locations of the individual first through third composite wires 52', 54', and 56' are predetermined by the thickness of the first silicon germanium layer 6. Here, the etching for trimming the first to third composite wires 52 to 56 is isotropic, or primarily isotropic, so that approximately equal thicknesses of silicon are uniformly removed from the exposed outer surfaces of each of the first to third composite wires 52 to 56, but essentially each thickness is etched away on each of the composite wires 52, 54, 56 at different distances from the top surface of the substrate 2.

[0037]

[0064] The relative thicknesses of the first through third post-trim wire preforms 52'-56' and the relative thickness of the capping layer 24 thereon can be simply increased or decreased to experimentally and iteratively achieve acceptable results in terms of thickness differential in the Y direction for the final wires 58a-58c. However, a first approximation useful for defining these thicknesses can be approached mathematically. Here, the thicknesses t1a', t1b', and t1c' of each of the first through third post-trim wire preforms 52'-56' in FIG. 2d are measured, along with the total thicknesses T1, T2, and T3 of each of the finished wires 58a-58c in FIG. 2d. The average of the thicknesses T1, T2, and T3 is calculated mathematically as Tave = (T1 + T2 + T3) / 3. If Tave is subtracted from a given finished wire thickness and is positive, that positive value is subtracted from the desired post-trim wire thickness of the finished wire to determine the target thickness of the post-trimmed wire. If the subtraction of Tave from a given finished wire thickness is negative, the negative value is added to the desired post-trim wire thickness of the finished wire to determine the target post-trim wire thickness. The goal here is to provide a target post-trim wire preform 52'-56' thickness based on the difference in thickness of the final wire 58a-58c in which the post-trim wire preforms 52'-56' reside. The same etch chemistry and remote plasma approach used to trim the wire preforms 52-56 of FIG. 2d can then be used to achieve the target or desired post-trim wire preform 52'-56' thickness by varying the process parameters (e.g., process pressure) of the trimming process. By simply repeating the process with different process parameters and trim etch concentrations, a reasonable approximation of the desired post-trim wire preform 52'-56' thickness and the relative thicknesses of the post-trimmed wire preforms 52'-56' can be achieved.

[0038]

[0065] For example, as shown in Figure 2d, the first final wire 58a is thicker than both the second and third final wires 58b and 58c, and is thicker than the average thickness of the final wires 58. Therefore, the difference between the thickness T1 of the final wire in Figure 2d and Tave is subtracted from the thickness t1a' of the first post-trim wire preform 52' to obtain the target thickness T1 of the first post-trim wire preform 52'. tar Similarly, as shown in FIG. 2d, the third final wire 58c is thinner than both the first and second final wires 58a and 58b, i.e., thinner than the average thickness of the finished wire 58. Therefore, the difference between the thickness T3 of the third final wire 58c in FIG. 2d and Tave is added to the thickness t1c' of the post-trim wire preform 56' to obtain the target thickness T1c' of the post-trim wire preform 56'. tar Similarly, any difference between the values ​​of T2 and Tave is used to adjust the thickness of the trimmed composite wire 54'. Therefore, the etching characteristics of the trimming process can be modified to adjust the T of each composite wire. tar By obtaining this, after the capping layer 24 is formed on each preform wire, the resulting final wires 58a-58c will have equal or approximately equal thickness values ​​in the Y direction. Therefore, the spacing between the completed wires 58a-58c, as well as the spacing between the completed wires 58c and the opposing surface of the capping layer 24 formed on the substrate, will have the same or approximately the same width or gap value.

[0039]

[0066] If the resulting spacings 32a', s2b', and s2c' and the final wire thicknesses T1-T3 are not sufficiently uniform, the etching process for trimming the wire composites 52-56 can be modified again to iteratively reach the desired uniformity.

[0040]

[0067] 5 is a schematic top view of an example multi-chamber processing system 100 useful for forming individual semiconductor layers and capping layers, according to some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 116 with respective transfer robots 110, 118, holding chambers 112, 114, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates within the processing system 100 may be processed within and transferred between the various chambers without exposing the substrates to an ambient environment outside the processing system 100 (e.g., an ambient atmospheric environment that may exist within a factory). For example, substrates may be processed within and transferred between the various chambers in a low-pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low-pressure or vacuum environment during the various processes performed on the substrates within the processing system 100. Thus, the processing system 100 can provide an integrated solution for processing portions of a substrate.

[0041]

[0068] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems commercially available from Applied Materials, Inc., Santa Clara, Calif., or other suitable processing systems. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from aspects described herein.

[0042]

[0069] 5, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate the transfer of substrates. The docking station 140 is configured to receive one or more front-opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally includes a blade 148 disposed at one end of each factory interface robot 142 configured to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0043]

[0070] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 112, 114 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 116 has respective ports 166, 168 coupled to the holding chambers 112, 114 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 may be, for example, slit valve openings with slit valves to allow substrates to pass through by transfer robots 110, 118 and provide seals between chambers to prevent gas from passing between the chambers. Generally, either port is open to transfer a substrate through the port, and the port is otherwise closed.

[0044]

[0071] The load lock chambers 104, 106, transfer chambers 108, 116, holding chambers 112, 114, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps, etc.), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 142 transfers a substrate from a FOUP 144 to the load lock chamber 104 or 106 through port 150 or 152. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains an internal low-pressure or vacuum environment (which may include an inert gas) within the transfer chambers 108, 116 and holding chambers 112, 114. Thus, pumping down the load lock chambers 104 or 106 facilitates passing substrates between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 .

[0045]

[0072] With the substrate in the load lock chamber 104 or 106 pumped down, the transfer robot 110 transfers the substrate from the load lock chamber 104 or 106 to the transfer chamber 108 via port 154 or 156. The transfer robot 110 can then transfer the substrate to either of the processing chambers 120, 122 via respective ports 162, 164 for processing, or to the holding chambers 112, 114 via respective ports 158, 160 for holding awaiting further transfer. Similarly, the transfer robot 118 can access the substrate in the holding chambers 112 or 114 via port 166 or 168 and transfer the substrate to either of the processing chambers 124, 126, 128, 130 via respective ports 170, 172, 174, 176 for processing, or to the holding chambers 112, 114 via respective ports 166, 168 for holding awaiting further transfer. Transfer and holding of the substrate within and between the various chambers may occur in a low pressure or vacuum environment provided by a gas and pressure control system.

[0046]

[0073] Processing chambers 120, 122, 124, 126, 128, and 130 may be any suitable chambers for processing substrates. In some examples, processing chamber 122 may perform a cleaning process, processing chamber 120 may perform an etching process, and processing chambers 124, 126, 128, and 130 may perform respective epitaxial growth processes. Processing chamber 122 may be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc. of Santa Clara, California. Processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials, Inc. of Santa Clara, California.

[0047]

[0074] A system controller 190 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 190 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 112, 114, 116, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling the controllers associated with the chambers 104, 106, 108, 112, 114, 116, 120, 122, 124, 126, 128, 130. During operation, the system controller 190 enables data collection and feedback from each chamber to adjust the performance of the processing system 100.

[0048]

[0075] The system controller 190 generally includes a central processing unit (CPU) 192, memory 194, and support circuits 196. The CPU 192 can be any type of general-purpose processor useful in an industrial environment. The memory 194, or non-transitory computer-readable medium, is accessible by the CPU 192 and can be one or more memories, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or other forms of local or remote digital storage. The support circuits 196 are coupled to the CPU 192 and can include cache, clock circuits, an input / output subsystem, power supplies, etc. The various methods disclosed herein can generally be implemented by the CPU 192 executing computer instruction code stored in the memory 194 (or the memory of a particular process chamber) as, for example, a software routine under the control of the CPU 192. When the computer instruction code is executed by the CPU 192, the CPU 192 controls the chamber to perform processing according to the various methods.

[0049]

[0076] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 116 and holding chambers 112, 114. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer apparatus in a processing system.

[0050]

[0077] 6 is a cross-sectional view of a processing chamber 122 that can be used to perform a cleaning process. The processing chamber 122 can be a SiCoNi™ Preclean chamber available from Applied Materials, Inc., Santa Clara, California. The processing chamber 122 includes a chamber body 212, a lid assembly 214, and a support assembly 216. The lid assembly 214 is disposed on top of the chamber body 212, and the support assembly 216 is disposed at least partially within the chamber body 212. The chamber body 212, the lid assembly 214, and the support assembly 216 together define an area in which a substrate can be processed.

[0051]

[0078] The lid assembly 214 includes at least two stacked components configured to form a plasma region therebetween. A first electrode 220 is vertically disposed above a second electrode 222 to confine a plasma space therebetween. The first electrode 220 is connected to a radio frequency (RF) power source 224, and the second electrode 222 is connected to ground, forming a capacitance between the first electrode 220 and the second electrode 222.

[0052]

[0079] The lid assembly 214 also includes one or more gas inlets 226 for supplying a cleaning gas to the substrate surface via a blocker plate 228 and a gas distribution plate 230 (e.g., a showerhead). The cleaning gas can be an etchant, an ionized gas, or an active radical, such as ionized fluorine, chlorine, or ammonia. Alternatively, a different cleaning process can be used to clean the substrate surface. For example, a remote plasma containing He and NF3 can be introduced into the processing chamber 122 via the gas distribution plate 230, while NH3 can be injected directly into the processing chamber 122 via a separate gas inlet 225 located on the side of the chamber body 212.

[0053]

[0080] The support assembly 216 may include a substrate support 232 for supporting the substrate 210 thereon during processing. The substrate support 232 has a flat substrate support surface for supporting a substrate being processed thereon. The substrate support 232 may be coupled to an actuator 234 by a shaft 236 extending through a centrally located opening formed in the bottom of the chamber body 212. The actuator 234 may be flexibly sealed to the chamber body 212 by a bellows (not shown) that prevents vacuum leakage near the shaft 236. The actuator 234 allows the substrate support 232 to be moved vertically within the chamber body 212 between a processing position and a lower transfer position. The transfer position is slightly below a slit valve opening formed in a sidewall of the chamber body 212. During operation, the substrate support 232 may be raised and lowered to a position in close proximity to the lid assembly 214 to control the temperature of the substrate 210 during processing. In this manner, the substrate 210 may be heated via radiation or convection emitted from the gas distribution plate 230.

[0054]

[0081] A bias radio frequency (RF) power supply 280 may be coupled to the substrate support 232 through a matching network 284. The bias radio frequency (RF) power supply 280 provides a bias to the substrate 210 and directs ionized cleaning gas toward the substrate 210.

[0055]

[0082] The vacuum system may be part of the gas and pressure control system of the processing system 100 and may be used to remove gases from the processing chamber 122. The vacuum system includes a vacuum pump 218 coupled to a vacuum port 221 disposed in the chamber body 212. The processing chamber 122 also includes a controller (not shown), which may be the system controller 190 or a controller controlled by the system controller 190, for controlling the process in the processing chamber 122.

[0056]

[0083] 7 is a cross-sectional view of a processing chamber 120 that can be used to perform selective etching and trimming processes. The processing chamber 120 can be a Selectra™ Etch chamber available from Applied Materials, Inc., Santa Clara, California. The processing chamber 120 includes a chamber body 302, a lid assembly 304, and a support assembly 306. The lid assembly 304 is disposed on top of the chamber body 302, and the support assembly 306 is disposed at least partially within the chamber body 302. The chamber body 302, the lid assembly 304, and the support assembly 306 together define a region in which a substrate can be processed. As will be apparent from the following description, the processing chamber 120 can implement one or more capacitively coupled plasmas (CCPs).

[0057]

[0084] The lid assembly 304 includes an RF electrode 308. A gas inlet tube 310 extends through the RF electrode 308 and is further coupled to a gas manifold 312. A flow centering insert 314 may be disposed within the gas inlet tube 310. A gas source 316 is fluidly coupled to the gas inlet tube 310 through the gas manifold 312. The gas source 316 may provide a gas flow 318 through the gas inlet tube 310 and through the flow centering insert 314. An RF power supply 320 and an RF matching circuit 322 are coupled to the RF electrode 308 and, therefore, to the gas inlet tube 310.

[0058]

[0085] The blocker plate 324 is coupled to the RF electrode 308 and may be maintained at the same potential as the RF electrode 308. The blocker plate 324 has apertures through which gas can flow. The gas distribution plate 326 is similarly coupled to the RF electrode 308 and may be maintained at the same potential as the RF electrode 308. The gas distribution plate 326 is further from the RF electrode 308 than the blocker plate 324. The gas distribution plate 326 also has apertures through which gas can flow. The blocker plate 324 and the gas distribution plate 326 may serve to redirect the gas flow, thereby making the gas flow more uniform on each side of the blocker plate 324 and the gas distribution plate 326 opposite the gas source (e.g., gas inlet tube 310) in the chamber 120.

[0059]

[0086] An insulator 330 separates and electrically insulates the gas distribution plate 326 from the gas distribution device 334. The gas distribution device 334 is grounded. The gas distribution device 334 is grounded and has apertures therethrough. The gas distribution plate 326, the gas distribution device 334, and the surface of the insulator 330 define a first plasma region 332 (e.g., a remote plasma region). When a gas flow 318 is supplied through the gas inlet tube 310 and passes through the blocker plate 324 and the gas distribution plate 326, and RF energy is supplied by the RF power supply 320 through the RF electrode 308 and the gas distribution plate 326, a plasma can be generated in the first plasma region 332. Plasma products (e.g., radicals, ions, and electrons) can pass through the gas distribution device 334 as plasma is generated in the first plasma region 332. Generally, the location of the grounded gas distribution device 334 between the gas distribution plate 326 and the process region 352 minimizes or prevents gases ionized in the plasma formed above the gas distribution device 334 from reaching the surface of the substrate during processing. The reduced exposure to ion-containing process gases prevents or minimizes damage to the substrate caused by bombardment of the substrate surface by ions generated by the plasma.

[0060]

[0087] The gas distribution device 334 further includes a channel 336 fluidly coupled to a gas source 338, which may be used to introduce one or more additional gases to a side of the gas distribution device 334 away from the first plasma region 332. The gas source 338 may provide a gas flow 340 through the channel 336. A heating element 342 may be disposed on the gas distribution device 334 or other component to facilitate thermal distribution and maintenance of the plasma in the first plasma region 332.

[0061]

[0088] The support assembly 306 includes a substrate support 348 supported by the chamber body 302. The support assembly 306 is configured to support a substrate 350. A second plasma region (e.g., a direct plasma region) is defined in a process region 352 between the gas distribution device 334 and the substrate 350. Gas from the flow 318 and plasma products from the first plasma region 332 may pass through the gas distribution device 334 to reach the process region 352. The substrate support 348 is further connected to an RF power source 354 to provide a bias during processing. In the second plasma region within the process region 352, a plasma may be generated when the gas flow 340 is provided through the channel 336 of the gas distribution device 334 and RF energy is provided to the substrate support 348 by the RF power source 354.

[0062]

[0089] The support assembly 306 may include an electrostatic chuck (ESC). The substrate support 348 may be coupled to an actuator 356 by a shaft 358 extending through a centrally located opening formed in the bottom of the chamber body 302. The actuator 356 may be flexibly sealed to the chamber body 302 by a bellows (not shown) that prevents vacuum leakage near the shaft 358. The actuator 356 allows the substrate support 348 to be moved vertically within the chamber body 302 between a processing position and a lower transfer position. The transfer position is slightly below a slit valve opening (not shown) formed in a sidewall of the chamber body 302. During operation, the substrate support 348 may be raised and lowered to a position adjacent to the lid assembly 304. Although not specifically shown, the substrate support 348 may include heating and cooling elements to maintain the substrate 350 at a target temperature during processing.

[0063]

[0090] The vacuum system may be part of the gas and pressure control system of the processing system 100 and may be used to remove gases from the processing chamber 120. The vacuum system includes a vacuum pump 362 coupled to a vacuum port 364 located in the chamber body 302.

[0064]

[0091] The processing chamber 120 also includes a controller (not shown), which may be the system controller 190 or a controller controlled by the system controller 190, for controlling the process within the processing chamber 120.

[0065]

[0092] 8 is a cross-sectional view of a thermal processing chamber 400 that can be used to perform epitaxial growth. The processing chamber 400 includes a chamber body 402, a support system 404, and a controller 406. The chamber body 402 includes an upper portion 412 and a lower portion 414. The upper portion 412 includes the region within the chamber body 402 between an upper dome 416 and the substrate 401. The lower portion 414 includes the region within the chamber body 402 between a lower dome 430 and the bottom of the substrate 401. The deposition process typically occurs on the top surface of the substrate 401 within the upper portion 412.

[0066]

[0093] The support system 404 includes components used to perform and monitor a predetermined process, such as growing an epitaxial film, in the processing chamber 400. The controller 406 is coupled to the support system 404 and adapted to control the processing chamber 400 and the support system 404. The controller 406 may be the system controller 190 or a controller controlled by the system controller 190, for controlling the process in the processing chamber 400.

[0067]

[0094] The processing chamber 400 includes a plurality of heat sources, such as lamps 435, adapted to provide thermal energy to components positioned within the process chamber 400. For example, the lamps 435 may be adapted to provide thermal energy to the substrate 401, the susceptor 426, and / or the preheat ring 423. The lower dome 430 may be formed from an optically transmissive material, such as quartz, to facilitate the passage of thermal radiation. It is contemplated that the lamps 435 may be positioned to provide thermal energy through the upper dome 416 as well as the lower dome 430.

[0068]

[0095] The chamber body 402 includes multiple plenums formed therein. The plenums are fluidly coupled to one or more gas sources 476, such as a carrier gas, and one or more precursor sources 478, such as a deposition gas and a dopant gas. For example, a first plenum 420 may be adapted to pass and supply a deposition gas 450 to an upper portion 412 of the chamber body 402, while a second plenum 424 may be adapted to exhaust the deposition gas 450 from the upper portion 412. In this manner, the deposition gas 450 may flow parallel to the top surface of the substrate 401.

[0069]

[0096] If a liquid precursor is used, the thermal treatment chamber 400 may include a liquid vaporizer 480 in fluid communication with a liquid precursor source 482. The liquid vaporizer 480 is used to vaporize the liquid precursor and deliver it to the thermal treatment chamber 400. Although not shown, it is contemplated that the liquid precursor source 482 may include, for example, one or more ampoules of precursor liquid and solvent liquid, shut-off valves, and a liquid flow meter (LFM).

[0070]

[0097] A substrate support assembly 432 is positioned in the lower portion 414 of the chamber body 402. The substrate support assembly 432 is shown supporting a substrate 401 in a processing position. The substrate support assembly 432 includes a susceptor support shaft 427 formed from an optically transparent material and a susceptor 426 supported by the susceptor support shaft 427. A shaft 460 of the susceptor support shaft 427 is positioned within a shroud 431 to which lift pin contacts 442 are coupled. The susceptor support shaft 427 is rotatable to facilitate rotation of the substrate 401 during processing. Rotation of the susceptor support shaft 427 is facilitated by an actuator 429 connected to the susceptor support shaft 427. The shroud 431 is normally fixed in position and therefore does not rotate during processing. Support pins 437 couple the susceptor support shaft 427 to the susceptor 426.

[0071]

[0098] The lift pins 433 are disposed through openings (not numbered) formed in the susceptor support shaft 427. The lift pins 433 are vertically movable and adapted to contact the underside of the substrate 401 and lift the substrate 401 from a processing position (as shown) to a substrate removal position.

[0072]

[0099] The preheat ring 423 is removably disposed on a lower liner 440 coupled to the chamber body 402. The preheat ring 423 is disposed around the interior space of the chamber body 402 and surrounds the substrate 401 while the substrate 401 is in a processing position. The preheat ring 423 facilitates preheating of the process gas as it enters the chamber body 402 through the first plenum 420 adjacent to the preheat ring 423.

[0073]

[0100] The central window portion of upper dome 416 and the bottom 417 of lower dome 430 may be formed from an optically transparent material such as quartz. A peripheral flange 419 of upper dome 416 contacts central window portion 415 around the periphery thereof, and a peripheral flange 421 of lower dome 430 contacts the bottom around the periphery thereof, and these peripheral flanges may all be formed from opaque quartz to protect adjacent O-rings 422 from direct exposure to thermal radiation. Peripheral flange 419 may be formed from an optically transparent material such as quartz.

[0074]

[0101] As previously described, HGAA structures use multiple semiconductor layers, stacked one on top of the other, extending between source and drain regions of a substrate. To form the structure, a superlattice, individual semiconductor layers (e.g., semiconductor sheet layers) are deposited or formed sequentially using an epitaxial deposition process, with alternating sacrificial layers deposited or formed between each semiconductor layer. In one embodiment, the semiconductor layers are monocrystalline silicon, e.g., doped monocrystalline silicon, and the sacrificial layers are silicon germanium layers. This process results in a stack of silicon and silicon germanium layers, which are subsequently separated into individual fins or mesas of the superlattice that extend between the source and drain regions of the device.

[0075]

[0102] While the forgoing is directed to various embodiments of the present disclosure, other and further embodiments may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a first superlattice on a first substrate, the first superlattice comprising alternating sublayers of a first material and sublayers of a second material comprising a semiconductor, the sublayers of the first material having a first thickness and the sublayers of the second material having a second thickness, at least the first sublayer of the first material and the second sublayer of the first material being formed within the first superlattice, the second sublayer of the first material being interposed between the first sublayer of the first material and the first substrate; removing the sublayer of the second material from the first superlattice; etching the first sublayer of the first material and the second sublayer of the first material of the first superlattice to remove a portion of the first material of the first superlattice to form a first trimmed sublayer of the first material and a second trimmed sublayer of the first material, wherein an amount of the first material removed from the first sublayer of the first material is greater than an amount of material removed from the second sublayer of the first material; depositing a capping layer over the first trimmed sublayer of the first material of the first superlattice, over the second trimmed sublayer of the first material of the first superlattice, and on the exposed surface of the first substrate; measuring a distance between the capping layer on the first sub-layer and the capping layer on the second sub-layer and a distance between the capping layer on the second sub-layer and the capping layer on the first substrate, and determining a first difference between these distances; forming a second superlattice on a second substrate, the second superlattice including alternating sublayers of the first material and sublayers of the second material comprising a semiconductor, the sublayers of the first material having a first thickness and the sublayers of the second material having a second thickness, at least the first sublayer of the first material and the second sublayer of the first material being formed in the second superlattice, the second sublayer of the first material being interposed between the first sublayer of the first material and the second substrate; removing the sublayer of the second material from the second superlattice and the second substrate; etching the first sublayer of the first material and the second sublayer of the first material of the second superlattice to remove a portion of the first material of the second superlattice to form a first trimmed sublayer of the first material and a second trimmed sublayer of the first material, wherein process conditions used to remove the portion of the first sublayer of the first material and the portion of the second sublayer of the first material are different from process conditions used to remove the portion of the first sublayer of the first material and the portion of the second sublayer of the first material of the first superlattice; depositing a capping layer over the first trimmed sublayer of the first material of the second superlattice, over the second trimmed sublayer of the first material of the second superlattice, and over the exposed surface of the second substrate; Including, a difference between a distance between the capping layer on the first sublayer of the first material and the capping layer on the second sublayer of the first material of the second superlattice and a distance between the capping layer on the second sublayer of the first material of the second superlattice and the capping layer on the second substrate is less than the first difference; method.

2. 10. The method of claim 1, wherein a process pressure during etching of the first sublayer of the first material and the second sublayer of the first material on the second superlattice is lower than a process pressure during etching of the first sublayer of the first material and the second sublayer of the first material on the first superlattice.

3. 3. The method of claim 2, wherein a relative concentration of gases during etching of the first sublayer of the first material and the second sublayer of the first material on the second superlattice is the same as a relative concentration of gases used to etch the first sublayer of the first material and the second sublayer of the first material on the first superlattice.

4. 3. The method of claim 2, wherein a process time during which the first sublayer of the first material and the second sublayer of the first material on the second superlattice are etched is longer than a process time used to etch the first sublayer of the first material and the second sublayer of the first material on the first superlattice.

5. 3. The method of claim 2, wherein a sum of a thickness of the capping layer formed on the first trimmed sublayer of the first material of the second superlattice and a thickness of the first trimmed sublayer of the first material of the second superlattice is equal to a sum of a thickness of the capping layer formed on the second trimmed sublayer of the first material of the second superlattice and a thickness of the second trimmed sublayer of the first material of the second superlattice.

6. 6. The method of claim 5, wherein a thickness of the capping layer formed on the first trimmed sublayer of the first material of the second superlattice is greater than a thickness of the capping layer formed on the second trimmed sublayer of the first material of the second superlattice.

7. 1. A method for forming a semiconductor device on a substrate, comprising: forming a superlattice on the substrate, the superlattice comprising alternating sublayers of a first material and sublayers of a second material comprising a semiconductor, the superlattice having a thickness that is different from that of at least the first sublayer of the first material and the second sublayer of the first material, the second sublayer of the first material being interposed between the first sublayer of the first material and the substrate; removing the sublayer of the second material from the superlattice; etching the first sublayer of the first material and the second sublayer of the first material such that a different amount of the first material is removed from the first sublayer of the first material compared to an amount of material removed from the second sublayer of the first material; depositing a capping layer over the etched first sublayer of the first material and over the etched second sublayer of the first material, wherein a thickness of the capping layer deposited over the first sublayer of the first material is different from a thickness of the capping layer deposited over the second sublayer of the first material. A method comprising:

8. the first sublayer of the first material is disposed farther from the substrate than the second sublayer of the first material; The method of claim 7 , wherein the thickness of the first sublayer of the first material before being etched is greater than the thickness of the second sublayer of the first material before being etched.

9. 9. The method of claim 8, wherein a thickness of the capping layer over the etched first sublayer of the first material is greater than a thickness of the capping layer over the etched second sublayer of the first material.

10. the etched first sublayer of the first material has a first side facing away from the second sublayer of the first material and a second side facing the second sublayer of the first material; the etched second sublayer of the first material has a first side facing the first sublayer of the first material and a second side facing the substrate; the capping layer is formed on at least the first side and the second side of the etched first sublayer of the first material and on at least the first side and the second side of the etched second sublayer of the first material; 10. The method of claim 9, wherein a sum of a thickness of the etched first sublayer of the first material and a thickness of the capping layer formed on the first side and the second side of the first sublayer is equal to a sum of a thickness of the etched second sublayer of the first material and a thickness of the capping layer formed on the first side and the second side of the second sublayer.

11. the etched first sublayer of the first material has a first side facing away from the second sublayer of the first material and a second side facing the second sublayer of the first material; the etched second sublayer of the first material has a first side facing the first sublayer of the first material and a second side facing the substrate; the capping layer is formed on the first side and the second side of the etched first sublayer of the first material and on the first side and the second side of the etched second sublayer of the first material; 10. The method of claim 9, wherein a distance between an outer surface of the capping layer over the etched first sublayer of the first material facing the etched second sublayer of the first material and a surface of the capping layer over the etched second sublayer of the first material facing the etched first sublayer of the first material is equal to a spacing between a surface of the capping layer over the etched second sublayer of the first material facing the substrate and a surface of the capping layer on the substrate that is furthest from the substrate.

12. 11. The method of claim 10, wherein the etched first sublayer of the first material and the etched second sublayer of the first material are silicon layers that form a channel in an HGAA device.

13. 12. The method of claim 11 , wherein the capping layer comprises silicon germanium, and the etched first sublayer of the first material and the capping layer thereon, and the etched second sublayer of the first material and the capping layer thereon form a channel in an HGAA device.

14. 1. A method for forming a multi-layer semiconductor device, comprising: providing a first substrate; forming a superlattice on a first substrate, the superlattice including a plurality of alternating first layers comprised of a first material and second layers formed from a second material; selectively removing the second layer of the superlattice; exposing the first layers of the superlattice to an etchant using first process conditions to remove a portion of the first material from the first layers to form trimmed first layers, wherein the amount of material removed from each of the first layers is a different amount; forming a capping layer over the first layer in the superlattice stack; measuring at least one of the distance between the capping layers formed on each of the first layers, the thickness of each of the capping layers formed on each of the trimmed first layers, and the combined thickness of the trimmed first layer and each of the capping layers formed thereon; calculating a new thickness of the trimmed first layer based on a difference between at least one of a distance between the capping layers formed on each of the first layers, a thickness of each of the capping layers formed on each of the trimmed first layers, and a combined thickness of the trimmed first layer and each of the capping layers formed thereon; A method comprising:

15. providing a second substrate; forming a superlattice on the second substrate, the superlattice including a plurality of alternating first layers comprised of a first material and second layers formed from a second material, at least two of the first layers of the superlattice having different thicknesses selected based at least in part on a difference between at least one of a distance between the capping layers formed on each of the first layers on the first substrate, a thickness of each of the capping layers formed on each of the trimmed first layers on the first substrate, and a combined thickness of the trimmed first layers and each of the capping layers formed on the first substrate; selectively removing the second layer of at least a first portion of the superlattice; exposing the first layer of the at least a first portion of the superlattice stack to an etchant to remove a portion of the first material from the first layer to form a trimmed first layer; 15. The method of claim 14, further comprising:

16. providing a second substrate; forming a superlattice on the second substrate, the superlattice including a plurality of alternating first layers comprised of a first material and second layers formed of a second material, the first layers having a common first thickness and the second layers having a common second thickness; selectively removing the second layer of the at least first portion of the superlattice; exposing the first layers of the at least a first portion of the superlattice stack to an etchant and removing a portion of the first material from the first layers using second process conditions different from the first process conditions to form trimmed first layers, wherein the amount of material removed from each of the first layers is a different amount, the different amount being selected based on at least one of a distance between the capping layers formed on each of the first layers on the first substrate, a thickness of each of the capping layers formed on each of the trimmed first layers on the first substrate, and a combined thickness of the trimmed first layer and each of the capping layers formed on the first substrate.

15. The method of claim 14, further comprising:

17. 16. The method of claim 15, wherein the spacing between adjacent layers of capping material on each of the trimmed first layers of the second substrate is equal to one another.

18. 17. The method of claim 16, wherein the spacing between adjacent layers of capping material on each of the trimmed first layers of the second substrate is equal to one another.

19. 17. The method of claim 16, wherein a thickness of the capping layer on the layer of the first material closest to the substrate is less than a thickness of the capping layer on the layer of the first material furthest from the substrate.

20. The method of claim 15 , wherein the first layer and the second layer are epitaxial layers.

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