Backside power with on-die power switches

Abstract

Apparatus and methods are provided for efficiently routing power signals across a semiconductor die. In various embodiments, an integrated circuit includes micro through-silicon vias (TSVs) that traverse a silicon substrate layer to a backside metal layer. The integrated circuit includes a power switch. The integrated circuit uses the micro TSVs and the backside metal layer to route a power signal from an output of the power switch to a frontside power rail. The integrated circuit uses the frontside metal layer to route a power signal from an output of the power switch to the frontside power rail. Thus, the frontside metal layer and the backside metal layer provide power connection redundancy that increases charge sharing, improves wafer yield, reduces voltage droop, and reduces on-die area. Additionally, the process routes a ground reference voltage level using both the frontside power rail and the backside power rail.

Description

[Background technology]

[0001] Description of Related Art As semiconductor manufacturing processes improve and on-die geometric dimensions decrease, semiconductor chips offer more functionality and performance. While much progress has been made, design issues still arise with modern techniques in processing and integrated circuit design that limit potential benefits. For example, voltage droop in modern integrated circuits is an increasing design problem with each generation of semiconductor chips. Voltage droop is the reduction in voltage value, or ΔV, on a node that causes the voltage value to drop below a minimum threshold. In the case of memories and latches without recovery circuits, stored values ​​may be lost. Voltage droop constraints are not only a problem for portable computers and mobile communication devices, but also for high-performance desktop and server computers that use superscalar microprocessors. Dynamic voltage droop exists on semiconductor chips due to capacitive and inductive elements in the circuit. Circuit techniques such as signal shielding and reducing the length of buses between repeaters are used to reduce this type of voltage droop on semiconductor chips.

[0002] Additionally, there is a resistive voltage droop, also referred to as "IR droop," which is proportional to the product of the current (I) flowing through a metal trace and the resistance (R) of the metal trace. Some of these metal traces are between the motherboard and the transistor's node. Typically, a semiconductor chip includes 12 or more metal layers between the motherboard and the transistor's node. Voltage droop, such as IR droop, increases as the number of metal layers increases. In addition to control and data signals, power supply voltage references are also routed through these 12 or more metal layers. As the number of nodes and signals on a semiconductor chip increases to provide more functionality, the area for routing power signals, such as power supply voltage references and ground voltage references, is reduced. Therefore, these power signals are again routed through multiple metal layers, which further increases IR droop.

[0003] Furthermore, traversing multiple metal layers to route power signals across a semiconductor chip increases the distance between contacts to the power signals. This distance widens the floorplan. Unless the semiconductor package size increases, the floorplan of the semiconductor die is limited. If there is no area in the floorplan for a component of the die, the component will not fit on the same die. Therefore, significant redesign is required, along with possible movement or shifting of macroblocks within the floorplan. Such redesign consumes a significant amount of design time and delays the release of the product.

[0004] In view of the above, a method and system for efficiently routing power signals across a semiconductor die is desired. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a generalized diagram of a top view of a standard cell layout utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 2] FIG. 1 is a generalized block diagram of a cross section of power connections utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 3] FIG. 1 is a generalized block diagram of a cross section of power connections utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 4] FIG. 1 is a generalized block diagram of a cross section of power connections utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 5] FIG. 1 is a generalized block diagram of a cross section of power connections utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 6] FIG. 1 is a generalized diagram of a top view of a standard cell layout utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 7] FIG. 7 is a generalized block diagram shown in cross section of a power connection 700 using a stack of metal layers. [Figure 8] FIG. 1 is a generalized block diagram of a method for efficiently generating integrated circuit layouts for standard cells that utilize techniques to reduce voltage droop and reduce on-die area. [Figure 9] FIG. 1 is a generalized diagram of a top view of a standard cell layout utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 10] FIG. 10 is a generalized block diagram of a computing system 1000 having standard cells that utilize techniques to reduce voltage droop and reduce on-die area. [Figure 11] FIG. 1 is a generalized diagram of a top view of a standard cell layout utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 12] FIG. 1 is a generalized diagram of a top view of a standard cell layout utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 13] FIG. 1 is a generalized diagram of a top view of a standard cell layout utilizing techniques to reduce voltage droop and reduce on-die area. [Figure 14] FIG. 1 is a generalized diagram of a top view of a standard cell layout utilizing techniques to reduce voltage droop and reduce on-die area. DETAILED DESCRIPTION OF THE INVENTION

[0006] While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

[0007] In the following specification, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art should recognize that the present invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention. Furthermore, it should be understood that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements are exaggerated relative to other elements.

[0008] Apparatuses and methods are contemplated for efficiently routing power signals across a semiconductor die. In various embodiments, an integrated circuit includes micro through silicon vias (TSVs) that traverse a silicon substrate layer to a backside metal layer. The integrated circuit also includes power switches on the semiconductor die. The integrated circuit uses the micro TSVs and the backside metal layer to route power signals from the outputs of the power switches to frontside power rails. The integrated circuit also uses the frontside metal layer to route power signals from the outputs of the power switches to the frontside power rails. Thus, the front and backside metal layers provide power connection redundancy, which increases charge sharing, improves wafer yield, reduces voltage droop, and reduces on-die area. Additionally, the process routes ground reference voltage levels using both the front and backside power rails. Further details of the integrated circuit are provided in the following description of FIGS. 1-10.

[0009] Referring to FIG. 1 , a generalized block diagram of a top view of a standard cell layout 100 utilizing techniques for reducing voltage droop and reducing on-die area is shown. In the illustrated embodiment, the standard cell layout 100 is for any of various types of Boolean and composite gates, including transistors arranged in a particular manner to provide data processing functionality or data storage. As used herein, “transistor” is also referred to as “semiconductor device” or “device.” For ease of illustration, several layers used to complete the circuitry of the layout 100 are not shown. For example, at least the active area and upper metal layers (Metal 1 through Metal 12 or higher) and corresponding contacts are not shown. The Metal 0 (M0 or Metal 0) layer is the front metal layer of several front metal layers that is closest to the transistor on the surface of the silicon substrate. In some embodiments, the active area for a p-type metal oxide semiconductor (PMOS) field effect transistor FET (or pFET) is located near the frontside unregulated VDD M0 rail 130 and the frontside regulated VDD M0 rail 160. The silicon substrate in the active area for p-type devices is doped with boron or gallium during the semiconductor fabrication process. The active area for n-type metal oxide semiconductor (NMOS) FET (or nFET) is located near the front VSS M0 rail 140. The silicon substrate in the active area for p-type devices is doped with phosphorus or arsenic during the semiconductor fabrication process.

[0010] Although the orientation of standard cell layout 100 (or layout 100) is shown such that front-side unregulated VDD M0 rail 130, front-side regulated VDD M0 rail 160, and front-side VSS M0 rail 140 are each routed horizontally, other orientations are possible and contemplated. It should be understood that silicon wafers, integrated circuits, and semiconductor packages using silicon substrate layers can be rotated and flipped. Accordingly, the materials and layers described are rotated and flipped, and orientations and directions will have different meanings. Accordingly, the terms “top,” “bottom,” “horizontal,” “vertical,” “upper,” and “lower” may change when layout 100 is rotated or flipped, and the use of these terms in the following description corresponds to the orientation shown in layout 100.

[0011] In some embodiments, the devices (or transistors) in standard cell layout 100 are planar devices. In other embodiments, the devices (or transistors) in standard cell layout 100 are non-planar devices. Non-planar transistors are used in semiconductor processing to reduce short-channel effects. Tri-gate transistors, fin field effect transistors (FETs), and gate-all-around (GAA) transistors are examples of non-planar transistors. In some embodiments, the devices in standard cell layout 100 are fabricated using immersion lithography, double patterning, extreme ultraviolet lithography (EUV), and directed self-assembly (DSA) lithography techniques. These techniques provide at least the resolution of the width and pitch of the layout, such as horizontal front VDD M0 rail 130 and horizontal front VSS M0 rail 140. When choosing between immersion lithography, double patterning, EUV and DSA techniques, and other techniques, cost is a consideration, as costs increase from immersion lithography to EUV. However, over time, the costs of these techniques adjust, and additional, newer techniques are developed to provide higher resolution. Therefore, any of a variety of lithography techniques can be used to provide higher resolution for width and pitch.

[0012] As used herein, a "terminal" of a transistor is also referred to as a "region" of the transistor. For example, a source region is also referred to as a source terminal, a drain region is also referred to as a drain terminal, and a gate region is also referred to as a gate terminal. In the illustrated embodiment, the standard cell layout 100 uses vertical source and drain regions 102. An example of the source and drain regions 102 is trench silicide contacts. In some embodiments, the source and drain regions 102 comprise cobalt silicide (CoSi2). In other embodiments, the source and drain regions 102 comprise titanium silicide (TiSi2).

[0013] Layout 100 uses multiple power switches 110-124. In one embodiment, each of power switches 110-124 is implemented by a p-type device with a power enable control signal routed to the gate terminal. The metal gates (not shown) of the power switches are vertically routed. Similarly, the source terminals (regions) 104 and drain terminals (regions) 106 of power switches 110-124 are also vertically routed. Source terminal 104 receives front unregulated VDD M0 rail 130 through via 108. Drain terminal 106 delivers a gated (regulated) power supply reference voltage level to one or more of front regulated VDD M0 rails 160. To do so, drain terminal 106 is connected to front metal 1 (M1 or Metal1) rail 180 through an M0 layer (e.g., a stub) and via 132. Note that via 132 is not visible from the top view of layout 100 because it is covered by M1 rail 180, via 170, and the M0 layer (stub, etc.). However, via 132 is shown here to indicate the location of the connection from drain terminal 106 to the M0 layer (stub, etc.) to the front M1 rail 180.

[0014] Via 170 is used to route regulated (power-gated) power reference voltage levels to one or more of the front-side regulated VDD M0 rails 160. Like via 132, via 170 would not be visible from a top view of layout 100 because it is covered by M1 rail 180. The difference between via 132 and via 170 is that below via 170 is a micro-through-silicon via (TSV) that traverses the silicon substrate layer to the backside power M0 rail 150. The backside power M0 rail 150 is below the silicon substrate layer. Thus, in layout 100, the backside power M0 rail 150 is used to route power connections in addition to the front-side regulated VDD M0 rail 160. Like vias 132 and 170, the backside power M0 rail 150 would typically not be visible from a top view of a standard cell layout because the silicon substrate layer and other elements cover the backside signal paths. However, here, the backside power M0 rail 150 is shown to further illustrate the use of power connection redundancy to increase charge sharing, reduce voltage droop, and reduce on-die area. For example, the backside power M0 rail 150 routed below the frontside regulated VDD M0 rail 160 provides an additional conductive routing layer. To transport current from the off-chip power supply to the p-type devices, current flows from the off-chip power supply to the frontside unregulated VDD M0 rail 130, through the power switches 110-124, through the frontside M1 rail 180, and then to each of the frontside regulated VDD M0 rail 160 and the backside power M0 rail 150.

[0015] When voltage droop is reduced to a value below a threshold, performance is increased and data corruption is avoided. Furthermore, without adding extra routing to the front metal layer, the use of backside power M0 rail 150 scales with standard cells as on-die geometries decrease and the number of nodes and signals increases. In various embodiments, one or more of the width and thickness of backside power M0 rail 150 is greater than the width and thickness of frontside regulation VDD M0 rail 160. These larger dimensions of backside power M0 rail 150 further increase charge sharing and further reduce voltage droop.

[0016] By increasing charge sharing and reducing voltage droop, power supply reference voltage levels can be routed using the front M1 rail 180 rather than upper metal layers that use wider and possibly thicker metal layer dimensions than the front M1 rail 180. Despite the front M1 rail 180 having a greater resistivity, the routing redundancy provided by the backside power M0 rail 150 still reduces overall voltage droop. The micro TSVs (not shown) used to access the backside power M0 rail 150 cannot be located by the power switches 110-124. The combined area of ​​the micro TSVs and drain region 106 could cause an electrical short connection with the front side VSS M0 rail 140. Therefore, the front side M1 rail 180 is used for routing. In other embodiments, a front side metal 3 (M3 or Metal3) rail (not shown) is used to connect the front side unregulated VDD M0 rail 130 to one or more of the front side regulated VDD M0 rails 160. Additionally, in some embodiments, a backside metal 1 (M1 or Metal1) rail (not shown) is used to connect the frontside regulation VDD M0 rail 160. In such embodiments, no further routing is provided by the frontside vertical rail, thereby providing on-die area for other signal paths.

[0017] Referring now to FIG. 2, a generalized block diagram of a cross-section of a power connection 200 utilizing techniques for reducing voltage droop and reducing on-die area is shown. Previously described contacts (or vias), materials, structures, and other layout elements are numbered identically. A top view of a standard cell layout is provided at the top of FIG. 2. This top view is a portion of the layout 100 previously shown in FIG. 1. A cross-section of this layout is shown at the bottom of FIG. 2. A backside power M0 rail 150 is disposed below the silicon substrate layer and any oxide layer used for isolation. In the illustrated embodiment, the backside power M0 rail 150 routes a power supply reference voltage level that is also routed by the frontside regulation VDD M0 rail 160. Note that the following description is for routing a power supply reference voltage level (VDD) to one or two source regions 102 of a p-type device. However, the materials, components, and connections can also be used to route a ground reference voltage level (VSS) to one or two source regions 102 of an n-type device.

[0018] The backside power M0 rail 150 is electrically connected to the frontside regulated VDD M0 rail 160 through the micro TSV 210 and the source contact 220. Note that the source contact 220 has the same function as the via 132 (in FIG. 1 ); from the top view of the power connection 200, the source contact 220 is not visible because it is covered by the frontside M1 rail 180, the via 170, and the frontside regulated VDD M0 rail 160. In various embodiments, the frontside regulated VDD M0 rail 160 is the frontside metal layer of multiple frontside metal layers that is closest to the transistors on the surface of the silicon substrate layer. The frontside M1 rail 180 is connected to the frontside regulated VDD M0 rail 160 through the via 170. The frontside M1 rail 180 is routed in and out of the page. The frontside regulated VDD M0 rail 160 and the backside power M0 rail 150 provide power connection redundancy for routing the power supply reference voltage level (VDD), which increases charge sharing, improves wafer yield, reduces on-die area, and reduces voltage droop.

[0019] The microTSVs 210 are formed after lithographic patterning, etching the silicon substrate layer, and depositing either cobalt (Co), ruthenium (Ru), or other materials. Subsequently, cobalt silicide (CoSi2) is patterned and formed (etched and filled) to form the source regions 102. The source regions 102 have sidewall connections to the microTSVs 210. Next, a CMP step planarizes the source regions 102 and the microTSVs 210 together. The CMP step also polishes away any remaining material from the microTSVs 110 and the source regions 102. The CMP step achieves an almost perfectly flat and smooth surface on which further layers of the integrated circuit can be built.

[0020] Referring now to FIG. 3 , a generalized block diagram of a cross-section of a power connection 300 utilizing techniques for reducing voltage droop and reducing on-die area is shown. Previously described contacts (or vias), materials, structures, and other layout elements are numbered identically. A top view of a standard cell layout is provided on the right side of FIG. 3 . This top view is a portion of the layout 100 previously shown in FIG. 1 . A cross-section of this layout is shown on the left side of FIG. 3 . Note that the following description is for routing a power supply reference voltage level (VDD) to one or two source regions 102 of a p-type device. However, similar to the power connection 200 (of FIG. 2 ), materials, components, and connections can also be used to route a ground reference voltage level (VSS) to one or two source regions 102 of an n-type device.

[0021] The backside power M0 rail 150 is disposed below the silicon substrate layer 330 and the oxide layer 320 used for isolation. The backside power M0 rail 150 is electrically connected to the frontside regulated VDD M0 rail 160 through the microTSV 210. As shown, the dimensions of the backside power M0 rail 150 include a width 340 and a thickness 342, and the dimensions of the frontside regulated VDD M0 rail 160 include a width 350 and a thickness 352. In some embodiments, one or more of the width 340 and thickness 342 of the backside power M0 rail 150 are greater than the width 350 and thickness 352, respectively, of the frontside regulated VDD M0 rail 160. Thus, the backside power M0 rail 150 provides a lower resistance path than the frontside regulated VDD M0 rail 160 for transporting current from a power supply to the p-type device including two source regions 102 abutting the microTSV 210.

[0022] Referring now to FIG. 4, a generalized block diagram of a cross-section of a power connection 400 utilizing techniques for reducing voltage droop and reducing on-die area is shown. Previously described contacts (or vias), materials, structures, and other layout elements are numbered identically. A top view of a standard cell layout is provided at the top of FIG. 4. This top view is a portion of the layout 100 previously shown in FIG. 1. A cross-section of this layout is shown at the bottom of FIG. 4. The power connection 400 includes multiple microTSVs 210 between the backside power M0 rail 150 and the frontside regulation VDD M0 rail 160. The additional microTSVs 210 increase charge sharing, improve wafer yield, and reduce voltage droop for routing of power reference voltage levels (VDD). Referring now to FIG. 5, a generalized block diagram of a cross-section of a power connection 500 utilizing techniques for reducing voltage droop and reducing on-die area is shown. The power connection 500 includes the same contacts (or vias), materials, structures, and other layout elements as the power connection 400. However, power connection 500 additionally includes vias 510 and backside (BS) power M1 rail 520 that provide further power connection redundancy to increase charge sharing, improve wafer yield, reduce on-die area, and reduce voltage droop for routing of power supply reference voltage levels (VDD).

[0023] Referring now to FIG. 6, a generalized block diagram of a top view of a standard cell layout 600 utilizing techniques for reducing voltage droop and reducing on-die area is shown. The standard cell layout 600 includes the same contacts (or vias), materials, structures, and other layout elements as the standard cell layout 100 (of FIG. 1). However, here, the circles represent the area where multiple metal layers would be used to provide power reference voltage levels to the front-side regulated VDD M0 rail 160 if the backside power M0 rail 150 were not used. These stacks of multiple metal layers, such as Metal0 (M0) through Metal15 (M15), consume a significant amount of area and determine the minimum distance between vias connecting the front-side M1 rail 180 to the front-side unregulated VDD M0 rail 130 and the front-side regulated VDD M0 rail 160. Using the backside power M0 rail 150 eliminates the use of these stacks at each location except for the connection to the front-side unregulated VDD M0 rail 130 at the inputs of the power switches 110-124. Each of these stacks contains a significant amount of voltage droop in addition to consuming area between metal layers used for signal routing. Again, note that vias 132 and 170 and backside power M0 rail 150 are not visible from the top view of layout 600 because they are covered by one or more of M1 rail 180, other vias, silicon substrate layers, M0 layers (stubs or signal paths, etc.), etc. However, these components are shown here to illustrate certain power connections.

[0024] Referring to FIG. 7, a generalized block diagram of a cross-section of a power connection 700 using a stack of metal layers is shown. Metal layers are shown as blocks labeled "M" followed by the layer number. Corresponding vias are shown between the metal layers. In the illustrated embodiment, the stack of metal layers includes 16 metal layers, Metal0 (M0) through Metal15 (M15). The M15 layer receives a power reference voltage level from an off-chip source. For example, microbumps used to connect a semiconductor die to an interposer or silicon substrate core provide the off-chip power reference voltage level. This voltage level is passed from the M15 layer to the M0 layer. As shown, the width, and in some cases the thickness, of the metal layers are reduced relative to the lower metal layers. Therefore, the resistivity of these metal layers increases. The stack of metal layers (M0 through M15) has a corresponding IR droop. Each metal layer and via in the stack provides a corresponding resistance that combines in series with other resistances.

[0025] Power switch 710 receives voltage levels from a stack of metal layers. The output of power switch 710 can provide a regulated (power-gated) version of the voltage level to nearby nodes 720 and 722. If a backside metal rail is not used, additional stacks are needed to route the voltage levels to other nodes on the semiconductor die. Layout 600 (of FIG. 6) indicates the locations of some of these stacks with circles. To route the voltage levels to standard cell 730, another stack of metal layers is used to send the voltage levels on specific metal layers, such as the Metal13 (M13) layer. The M13 layer provides signal paths with the same orientation as the M1 layer previously described and illustrated. Another stack of metal layers is used to route the voltage levels from the M13 layer to the frontside M0 layer. The use of these stacks increases voltage droop and consumes area of ​​metal layers used for signal paths. The location of vias on the frontside M0 layer is set by the size of these stacks, which can increase the distance to these locations. Therefore, the on-die area increases. The use of backside metal routing reduces these effects.

[0026] 8, a generalized block diagram of a method 800 for efficiently generating integrated circuit layouts for standard cells that utilize techniques for reducing voltage droop and reducing on-die area is shown. For purposes of explanation, the steps in this embodiment are shown sequentially. However, in other embodiments, some steps occur in a different order than that shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are not present.

[0027] A semiconductor fabrication process forms a first micro through-silicon via (TSV) that traverses a silicon substrate layer to a backside metal layer on a first node that receives a power reference (block 802). The semiconductor fabrication process (or processes) places a cell, such as a standard cell, in an integrated circuit (block 804). The process also places a power switch on the semiconductor die. The process routes a power signal from the output of the power switch to a frontside power rail using the micro TSV and the backside metal layer (block 806).

[0028] The process uses the front metal layer to route power signals from the outputs of the power switches to the front power rails (block 808). Thus, the front and back metal layers provide power connection redundancy that increases charge sharing, improves wafer yield, reduces voltage droop, and reduces on-die area. In addition, the process uses both the front and back power rails to route ground reference voltage levels. If no potential is applied to the input nodes of the integrated circuit (conditional block 810: "NO"), the integrated circuit waits for power-on (block 812). However, if a potential is applied to the input nodes of the integrated circuit (conditional block 810: "YES"), the integrated circuit carries current from the input nodes to the output nodes through the given cells (block 814).

[0029] 9, a generalized block diagram of a top view of a standard cell layout 900 utilizing techniques for reducing voltage droop and reducing on-die area is shown. The standard cell layout 900 includes the same contacts (or vias), materials, structures, and other layout elements as the standard cell layout 100 (of FIG. 1). However, here, the backside power M0 rail 150 is routed below the frontside VSS M0 rail 140 to provide a ground voltage reference and to provide an additional conductive routing layer. To transport current from the off-chip ground reference to the n-type devices, current flows from the off-chip ground reference to the frontside VSS M0 rail 140 at the bottom of the layout 900, to vias 170, to the backside power M0 rail 150, and in some embodiments, to the backside power M1 rail.

[0030] Referring to FIG. 10 , a generalized block diagram of a computing system 1000 having a standard cell that utilizes techniques for reducing voltage droop and reducing on-die area is shown. The computing system 1000 includes a processor 1010 and memory 1030. Interfaces such as a memory controller, a bus or communication fabric, one or more phase-locked loops (PLLs) and other clock generation circuits, a power management unit, etc. are not shown for ease of illustration. It should be understood that in other embodiments, the computing system 1000 includes one or more of the following: other processors of the same or different type as the processor 1010, one or more peripheral devices, a network interface, one or more other memory devices, etc. In some embodiments, the functionality of the computing system 1000 is integrated onto a system-on-chip (SoC). In other embodiments, the functionality of the computing system 1000 is integrated onto a peripheral card inserted into a motherboard. The computing system 1000 may be used in any of a variety of computing devices, such as a desktop computer, a tablet computer, a laptop, a smartphone, a smartwatch, a game console, a personal assistant device, etc.

[0031] The processor 1010 includes hardware such as circuits. For example, the processor 1010 includes at least one integrated circuit 1020. The integrated circuit 1020 includes cells 1022, one or more of which use power connection redundancy to increase charge sharing, improve wafer yield, and reduce voltage droop. In various embodiments, one or more of the cells 1022 use power connection techniques used in standard cell layouts 100 and 900 (of FIGS. 1 and 9) and power connections 200-500 (of FIGS. 2-5). In some embodiments, the processor 1010 includes one or more processing units. In some embodiments, each of the processing units includes one or more processor cores capable of general-purpose data processing and an associated cache memory subsystem. In such embodiments, the processor 1010 is a central processing unit (CPU). In another embodiment, the processing cores are compute units, each of which has a highly parallel data microarchitecture with multiple parallel execution lanes and associated data storage buffers. In such embodiments, processor 1010 may be a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

[0032] In some embodiments, memory 1030 includes one or more of a hard disk drive, a solid state disk, other types of flash memory, a portable solid state drive, a tape drive, etc. Memory 1030 stores an operating system (OS) 1032, one or more applications represented by code 1034, and at least source data 1036. Memory 1030 may also store intermediate and final result data generated by processor 1010 when executing a particular application of code 1034. While a single operating system 1032 and a single instance of code 1034 and source data 1036 are shown, in other embodiments, other numbers of these software components are stored in memory 1030. Operating system 1032 includes instructions for initiating the boot-up of processor 1010, assigning tasks to hardware circuits, managing resources of computing system 1000, and hosting one or more virtual environments.

[0033] Each of the processor 1010 and memory 1030 includes an interface unit for communicating with each other and with any other hardware components included in the computing system 1000. The interface units include queues for handling memory requests and responses, and control circuitry for communicating with each other based on a particular communication protocol. The communication protocol determines various parameters such as supply voltage levels, power performance states that determine operating supply voltages and clock frequencies, data rates, one or more burst modes, etc.

[0034] Referring now to FIG. 11 , a generalized block diagram of a top view of a standard cell layout 1100 utilizing techniques for reducing voltage droop and reducing on-die area is shown. The standard cell layout 1100 includes the same contacts (or vias), materials, structures, and other layout elements as the standard cell layouts 100, 600, and 900 (of FIGS. 1, 6, and 9). The backside power M0 rail 150 is routed below the frontside VSS M0 rail 140 to provide an additional conductive routing layer. A micro through-silicon via (TSV) 1110 traverses the silicon substrate layer to reach the backside power M0 rail 150. The backside power M0 rail 150 is below the silicon substrate layer. Previously, vias 170 and a frontside metal 1 (M1 or Metal1) rail 180 obscured the microTSV 1110. To transport current from the off-chip ground reference to the device, current flows from the off-chip ground reference, to the front VSS M0 rail 140, to the micro TSV 1110, to the backside power M0 rail 150, and in some embodiments to the backside power M1 rail.

[0035] In various embodiments, the microTSV 1110 has the same materials, function, and structure as the microTSV 210 (of FIG. 2). The microTSV 1110 traverses through the silicon substrate layer from the backside power M0 rail 150 to the frontside VSS M0 rail 140, terminating in physical contacts at each of the backside power M0 rail 150 and the frontside VSS M0 rail 140. The distance between the backside power M0 rail 150 and the frontside VSS M0 rail 140 defines the height or length of the microTSV 1110, which traverses only the silicon substrate layer and any oxide layers above the backside power M0 rail 150. The microTSV 1110 does not physically extend into the multiple insulating layers of the semiconductor die used to route multiple frontside metal layers. Similarly, the microTSV 1110 does not physically extend into the multiple insulating layers of the semiconductor die used to route multiple backside metal layers. The front VSS M0 rail 140 is routed over the microTSV 1110, which is shown here to further illustrate the use of power connection redundancy to improve wafer yield and reduce voltage droop.

[0036] Like layouts 100, 600, and 900 (of FIGS. 1, 6, and 9), layout 1100 uses multiple power switches, which do not include callouts due to lack of area in the figures. However, these power switch embodiments are the same as those used in layouts 100, 600, and 900 (of FIGS. 1, 6, and 9). The source terminals (areas) of the devices are located to the left of the drain terminals (areas) in the figures. The source terminals receive the front unregulated VDD M0 rail 130 through vias 108. The drain terminals route a gated (regulated) power supply reference voltage level to one or more of the front regulated VDD M0 rails 160 through vias 108. Additionally, as shown at the top of FIG. 11, the drain terminals of some of the power switches are connected to the front metal 1 (M1 or Metal1) rail 180 through the M0 layer (e.g., stubs) and vias 132. 11 may be connected to a front M1 rail 180 (not shown) located at the bottom of layout 1100. Again, note that vias 132 and 170 and backside power M0 rail 150 are not visible from the top view of layout 1100 because they are covered by one or more of M1 rail 180, other vias, the silicon substrate layer, the M0 layer (such as stubs or signal paths), etc. However, these components are shown here to illustrate certain power connections.

[0037] 12, a generalized block diagram of a top view of a standard cell layout 1200 utilizing techniques to reduce voltage droop and reduce on-die area is shown. Standard cell layout 1200 includes the same contacts (or vias), materials, structures, and other layout elements as standard cell layout 1100 (of FIG. 12). Layout 1200 has the power switches and corresponding vias removed to provide a clearer image of the power connections used in both the front and back M0 layers.

[0038] Referring to FIG. 13, a generalized block diagram of a top view of a standard cell layout 1300 utilizing techniques for reducing voltage droop and reducing on-die area is shown. Standard cell layout 1300 includes the same contacts (or vias), materials, structures, and other layout elements as standard cell layouts 100, 600, 900, 1100-1200 (of FIGS. 1, 6, 9, and 11-12). Layout 1300 uses the same patterned front M0 layer as layout 1100, such as using the same metal width, metal pitch, and metal layer placement as layout 1100. However, layout 1300 modifies the assignment of signals to these front M0 layers. The front M0 layer includes a front-side unregulated VDD M0 rail 130, a front-side VSS M0 rail 140, and a front-side regulated VDD M0 rail 160. As shown, layout 1100 has a relatively narrow front unregulated VDD M0 rail 160 on either side of a relatively wide front unregulated VDD M0 rail 130. In contrast, layout 1300 has a relatively narrow front unregulated VDD M0 rail 130 on either side of a relatively wide front VSS M0 rail 140.

[0039] Additionally, layout 1100 (and layout 1200) has a relatively wide front VSS M0 rail 140 between a group of relatively narrow front-side regulated VDD M0 rails 160 on either side of a relatively wide front-side unregulated VDD M0 rail 130. The relatively wide front-side VSS M0 rail 140 has a power connection to a back-side power M0 rail 150 via a microTSV 1110. In contrast, layout 1300 has a relatively narrow front-side unregulated VDD M0 rail 130 on either side of a relatively wide front-side VSS M0 rail 140. The relatively wide front-side regulated VDD M0 rail 160 has a power connection to a back-side power M0 rail 150 via a microTSV 1110.

[0040] Additionally, the relatively wider front VSS M0 rail 140 of layout 1300 has a power connection to the backside power M0 rail 150 via microTSV 1110. Thus, by switching the signal assignments in layout 1300 while using the same front side M0 layer pitch, width, and placement as found in layout 1100 (and layout 1200), layout 1300 includes more power connections to the backside power M0 rail 150 via microTSV 1110 than found in layout 1100. Furthermore, layout 1300 does not need to use the front side M1 rail 180 to connect the front side unregulated VDD M0 rail 130 to the front side regulated VDD M0 rail 160. The absence of the front side M1 rail 180 for this type of connection allows standard cells to use the available front side M1 track.

[0041] 14, a generalized block diagram of a top view of a standard cell layout 1400 utilizing techniques to reduce voltage droop and reduce on-die area is shown. Standard cell layout 1400 includes the same contacts (or vias), materials, structures, and other layout elements as standard cell layout 1300 (of FIG. 13). Layout 1400 has the power switches and corresponding vias removed to provide a clearer image of the power connections used in both the front and back M0 layers.

[0042] It should be noted that one or more of the above-described embodiments include software. In such embodiments, program instructions implementing the methods and / or mechanisms are carried or stored on a computer-readable medium. Many types of media configured to store program instructions are available, including hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage. Generally speaking, a computer-accessible storage medium includes any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, a computer-accessible storage medium may include magnetic or optical media, such as a disk (fixed or removable), tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray. Storage media further include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (Rambus DRAM, RDRAM), static RAM (SRAM), etc.), ROM, flash memory, non-volatile memory (e.g., flash memory) accessible via a peripheral interface such as a Universal Serial Bus (USB) interface, etc. Storage media include microelectromechanical systems (MEMS), and storage media accessible via a communication medium such as a network and / or wireless link.

[0043] Additionally, in various embodiments, the program instructions include a behavioral or register-transfer level (RTL) description of the hardware functionality in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDS II stream format (GDS II). In some cases, the description is read by a synthesis tool, which synthesizes the description to generate a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the system. The netlist can then be placed and routed to generate a data set that describes the geometric shapes that are applied to a mask. The mask can then be used in various semiconductor manufacturing steps to generate a semiconductor circuit or circuits corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are a netlist (with or without a synthesis library) or a data set, as appropriate. Additionally, the instructions are utilized for emulation by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0044] Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated, and it is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. 1. An integrated circuit comprising: a first power rail on a plurality of front metal layers, the first power rail having a voltage equal to an off-chip power reference received through the plurality of front metal layers; a backside metal layer connected to each of the first power rail and a second power rail different from the first power rail, the backside metal layer configured to route the off-chip power reference from the first power rail to the second power rail; In response to an electrical potential being applied to an input node of a cell of the integrated circuit, a current is transmitted from the input node through one of the first power rail and the second power rail to an output node of the cell. Integrated circuit.

2. a micro through-silicon via (TSV) through a silicon substrate layer between the first power rail and the backside metal layer; 10. The integrated circuit of claim 1.

3. a power switch between the first power rail and a third power rail connected to the off-chip power reference through the plurality of front metal layers; The power switch In response to the power switch being enabled, connecting the third power rail to the micro TSV; disconnecting the first power rail from the micro TSV in response to the power switch being disabled; configured to:

3. The integrated circuit of claim 2.

4. a first front metal layer of the plurality of front metal layers configured to route the off-chip power reference from the third power rail to the first power rail and connected to an output of the power switch and each of the first power rails; 4. The integrated circuit of claim 3.

5. the first front metal layer is connected to the second power rail and routes the off-chip power reference from the first power rail to the second power rail; 5. The integrated circuit of claim 4.

6. At least one of the thickness and width of the back metal layer is greater than the thickness and width of the first front metal layer.

5. The integrated circuit of claim 4.

7. each of the first power rail and the second power rail is a metal layer of the plurality of front metal layers disposed closest to active devices of the integrated circuit; the first front metal layer is a metal layer adjacent to the first power rail; 5. The integrated circuit of claim 4.

8. 1. A method comprising: growing a silicon substrate layer of an integrated circuit; forming a plurality of transistors in the integrated circuit along a first surface of the silicon substrate layer; forming a first power rail in a plurality of front metal layers, the first power rail having a voltage equal to an off-chip power reference received through the plurality of front metal layers; forming a backside metal layer connected to each of the first power rail and a second power rail different from the first power rail, the backside metal layer configured to route the power supply reference from the first power rail to the second power rail; and transmitting a current from an input node of a cell of the integrated circuit through one of the first power rail and the second power rail to an output node of the cell in response to a power supply voltage being applied to the input node of the cell. method.

9. forming a micro through-silicon via (TSV) through a silicon substrate layer between the first power rail and the backside metal layer; 9. The method of claim 8.

10. forming a power switch between the first power rail and a third power rail connected to the off-chip power reference through the plurality of front metal layers; The method comprises: In response to the power switch being enabled, the power switch connects the third power rail to the micro TSV; in response to the power switch being disabled, the power switch disconnecting the first power rail from the micro TSV.

10. The method of claim 9.

11. forming a first front metal layer of the plurality of front metal layers connected to each of the outputs of the power switch and the first power rail; The method comprises: the first front metal layer including routing the off-chip power reference from the third power rail to the first power rail; The method of claim 10.

12. the first front metal layer connected to the second power rail includes routing the off-chip power reference from the first power rail to the second power rail; The method of claim 11.

13. At least one of the thickness and width of the back metal layer is greater than the thickness and width of the first front metal layer. The method of claim 11.

14. each of the first power rail and the second power rail is a metal layer of the plurality of front metal layers disposed closest to active devices of the integrated circuit; the first front metal layer is a metal layer adjacent to the first power rail; The method of claim 11.

15. 1. A computing system comprising: a memory configured to store instructions for one or more tasks and source data to be processed by said one or more tasks; an integrated circuit configured to execute the instructions using the source data; The integrated circuit comprises: a first power rail on a plurality of front metal layers, the first power rail having a voltage equal to an off-chip power reference received through the plurality of front metal layers; a backside metal layer connected to each of the first power rail and a second power rail different from the first power rail, the backside metal layer configured to route the off-chip power reference from the first power rail to the second power rail; In response to an electrical potential being applied to an input node of a cell of the integrated circuit, a current is transmitted from the input node through one of the first power rail and the second power rail to an output node of the cell. Computing system.

16. the integrated circuit comprises a micro through-silicon via (TSV) through a silicon substrate layer between the first power rail and the backside metal layer; 16. The computing system of claim 15.

17. the integrated circuit includes a power switch between the first power rail and a third power rail connected to the off-chip power reference through the plurality of front metal layers; The power switch In response to the power switch being enabled, connecting the third power rail to the micro TSV; disconnecting the first power rail from the micro TSV in response to the power switch being disabled; configured to:

17. The computing system of claim 16.

18. the integrated circuit includes a first front metal layer of the plurality of front metal layers configured to route the off-chip power reference from the third power rail to the first power rail and connected to an output of the power switch and each of the first power rails; 20. The computing system of claim 17.

19. the first front metal layer is connected to the second power rail and routes the off-chip power reference from the first power rail to the second power rail; 20. The computing system of claim 18.

20. one or more of the thickness and width of the back metal layer is greater than the thickness and width of the first front metal layer; 20. The computing system of claim 18.

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