Reduction of aspect ratio dependent etching by pulsing DC bias.

Abstract

FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing processes. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of RF bias signals and pulsed voltage waveforms to one or more electrodes in a plasma processing chamber. The apparatus and methods disclosed herein can be useful for at least minimizing or eliminating microloading effects that occur during processing of small dimension features that vary in density across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve control of various characteristics of the generated plasma and control the ion energy distribution (IED) of plasma-generated ions that interact with the surface of the substrate during plasma processing. The ability to synchronize and control the waveform characteristics of the voltage waveform bias established on the substrate during processing enables improved control of the generated plasma and processes for forming high aspect ratio features on the substrate surface, for example, by reactive ion etching processes. As a result, greater precision can be achieved for plasma processing, as described in more detail herein.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate generally to systems used in semiconductor device manufacturing. More particularly, embodiments of the present disclosure relate to plasma processing systems used to process substrates.

[0002] 2. Description of Related Art

[0002] Reliably fabricating high aspect ratio features is one of the key technological challenges for next generation semiconductor devices. One method for forming high aspect ratio features uses a plasma-assisted etching process to impinge material formed on a surface of a substrate through openings formed in a patterned mask layer formed on the surface of the substrate.

[0003] As technology nodes advance toward 2 nanometers (nm), atomic-level precision is required in plasma processing to fabricate smaller features with larger aspect ratios. For etching processes in which plasma ions play a key role, ion energy control has always been a challenge in developing reliable and reproducible device formation processes in the semiconductor device industry. In a typical plasma-assisted etching process, a substrate is positioned on a substrate support disposed within a processing chamber. A radio frequency (RF) generator coupled to an electrode disposed on or within the plasma processing chamber forms a plasma over the substrate, and ions are accelerated from the plasma across a plasma sheath toward the substrate. Furthermore, RF substrate biasing methods, which require the use of a separate RF bias source in addition to the RF generator used to initiate and maintain the plasma within the processing chamber, have not provided desirable control over the plasma sheath characteristics and have not been able to achieve the desired plasma processing results that enable the formation of such smaller device feature sizes. Conventional RF generators and RF biasing techniques utilize sinusoidal RF waveforms to excite the plasma and form the plasma sheath, but often lead to undesirable and inconsistent process results due to the sinusoidal shape of the RF waveform and the inability of RF biasing techniques to adjust ion energy during processing due to the limited characteristics of the sinusoidal waveform provided.

[0004]

[0004] Furthermore, one of the problems when etching features with small feature dimensions is the occurrence of the microloading effect, which is a measure of the variation in etched dimensions between regions with high and low feature density. Low feature density regions (e.g., isolated regions) receive more reactive etchant per unit surface area compared to high feature density regions (e.g., high density regions) due to the larger total exposed surface area of ​​these regions, thereby resulting in a faster etch rate in the low-density regions. Sidewall passivation generated from etching byproducts also exhibits a similar pattern density dependence, with more byproducts generated in low feature density regions, resulting in more passivation formed on isolated features. The difference in reactive etchant and passivation per surface area between these two regions increases as the difference in feature density increases. Therefore, low feature density regions are often etched at a faster rate than high feature density regions, resulting in deformation of etched features, rough line edges, or tapered tops of the etched layer in the low feature density regions. Poor selectivity between material layers disposed in a film stack in high and low feature density regions often results in poor pattern transfer due to an inability to preserve the critical dimensions of the features being etched.

[0005]

[0005] Therefore, there is a need in the art for desirable plasma-assisted processes that address the above-mentioned problems. Summary of the Invention

[0006]

[0006] Embodiments provided herein generally include an apparatus, plasma processing system, and method for generating a waveform for plasma processing a substrate in a processing chamber.

[0007]

[0007] Embodiments of the present disclosure provided herein include a method of processing a substrate, including performing a processing sequence on a substrate disposed in a processing region of a plasma processing chamber. The processing sequence includes a first processing sequence interval, a second processing sequence interval, and a third processing sequence interval, wherein the processing region of the plasma processing chamber is evacuated to a pressure below atmospheric pressure during the first processing sequence interval, the second processing sequence interval, and the third processing sequence interval. The first processing sequence interval includes delivering, by a voltage waveform generator, a first burst of a first asymmetric voltage pulse to a bias electrode disposed in the plasma processing chamber, wherein the first burst of the first asymmetric voltage pulse is supplied for a first time period, and delivering, by using a radio frequency (RF) generator, an RF signal to an RF electrode disposed in the plasma processing chamber for a first time period, wherein the RF signal supplied during the first time period includes a first RF power level. The second processing sequence interval includes ceasing delivery of the first burst of the first asymmetric voltage pulses for a second time period and delivering, using a radio frequency (RF) generator, an RF signal to the RF electrode for the second time period, the RF signal provided during the second time period comprising a second RF power level. The third processing sequence interval includes continuing to cease delivery of the first burst of the first asymmetric voltage pulses for a third time period and ceasing delivery of the RF signal to the RF electrode for the third time period.

[0008]

[0008] Embodiments of the present disclosure may further provide a plasma processing chamber including a voltage waveform generator; a radio frequency (RF) generator; a bias electrode disposed within the plasma processing chamber; the RF electrode disposed within the plasma processing chamber; a vacuum pump configured to evacuate a processing region of the plasma processing chamber; and a memory for storing a program executed by use of a processor. The program, including instructions, when executed by the processor causes a processing sequence to be performed. The processing sequence includes a first processing sequence interval, a second processing sequence interval, and a third processing sequence interval, and the processing region of the plasma processing chamber is evacuated to a pressure below atmospheric pressure by use of the vacuum pump during the first processing sequence interval, the second processing sequence interval, and the third processing sequence interval. The first processing sequence section includes delivering a first burst of first asymmetric voltage pulses to a bias electrode disposed within the plasma processing chamber by a voltage waveform generator, the first burst of the first asymmetric voltage pulses being supplied for a first time period, and delivering an RF signal to an RF electrode disposed within the plasma processing chamber by using a radio frequency (RF) generator for a first time period, the RF signal supplied during the first time period comprising a first RF power level. The second processing sequence section includes ceasing delivery of the first burst of the first asymmetric voltage pulses for a second time period, and delivering an RF signal to the RF electrode by using the radio frequency (RF) generator for a second time period, the RF signal supplied during the second time period comprising a second RF power level. The third processing sequence section includes continuing to cease delivery of the first burst of the first asymmetric voltage pulses for a third time period, and ceasing delivery of the RF signal to the RF electrode for a third time period.

[0009]

[0009] So that the features of the present disclosure described above can be understood in detail, a more particular description of the present disclosure briefly summarized above will be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, as other equally effective embodiments may also be recognized. [Brief explanation of the drawings]

[0010] [Figure 1]

[0010] FIG. 1 is a schematic diagram of a conventional plasma processing system. [Figure 2A]

[0011] 1 is a schematic cross-sectional view of a plasma processing system according to one or more embodiments configured to perform methods described herein. [Figure 2B]

[0012] FIG. 1 is a simplified diagram of a pulsed voltage (PV) waveform generator in association with a control system that can be configured to implement methods described herein, according to one or more embodiments. [Figure 3]

[0013] 1 illustrates an example of a voltage waveform according to certain embodiments of the present disclosure. [Figure 4]

[0014] 10A-10C illustrate bursts of voltage pulses within generated voltage waveforms and RF waveforms utilized during one or more methods described herein, in accordance with one or more embodiments of the present disclosure provided herein. [Figure 5]

[0015] A method for plasma processing a substrate by using a process for synchronizing the delivery of an RF signal generated by an RF generator with voltage pulse bursts generated by a pulsed voltage waveform generator is shown, according to certain embodiments.

[0011]

[0016] For ease of understanding, where possible, the same reference numerals have been used to designate identical elements that are common to multiple figures. It is intended that elements and features of one implementation may be beneficially incorporated in other implementations without further recitation. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0017] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing processes. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of RF bias signals and pulsed voltage waveforms to one or more electrodes in a plasma processing chamber. The apparatus and methods disclosed herein can be useful for at least minimizing or eliminating microloading effects that occur during processing of small dimension features that vary in density across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve control of various characteristics of the generated plasma and control the ion energy distribution (IED) of plasma-generated ions that interact with the surface of the substrate during plasma processing. The ability to synchronize and control the waveform characteristics of the voltage waveform bias established on the substrate during processing enables improved control of the generated plasma and processes for forming high aspect ratio features on the substrate surface, for example, by reactive ion etching processes. As a result, greater precision can be achieved for plasma processing, as described in more detail herein.

[0013]

[0018] 1 is a schematic diagram of a conventional plasma processing system 10 adapted to process a substrate 13 disposed on a substrate support 40 by generating a plasma 11 in a processing region 15 surrounded by multiple walls 50 of a plasma processing chamber 99. The plasma processing system 10 is configured to form an inductively coupled plasma (ICP), and the processing chamber 99 includes a coil 73 positioned above a portion of the processing region 15 such that the coil faces a lower electrode 46 disposed within the substrate support 40, at least a portion of which is disposed within the processing region 15. The ICP plasma processing source includes an RF generator 71 electrically coupled to the upper coil 73 via a radio frequency (RF) match 72, and delivers a tuned RF signal configured to ignite and sustain the plasma 11 formed within the processing region 15. Typically, the lower electrode 46 is grounded or coupled to a second RF power generator, which may include radio frequency (RF) generators 61 and 62 electrically coupled to the lower electrode 46 via an RF match 60. 1A, in which an RF signal is simultaneously supplied to one or more electrodes to form plasma 11, the impedance of the composite load presented by plasma 11 varies, at least in part, due to varying RF power levels. A gas inlet 16 disposed through chamber lid 51 is used to deliver one or more process gases to process space 15 from a process gas source 17 in fluid communication with process space 15.

[0014] Plasma Processing System Example

[0019] 2A is a schematic diagram of a plasma processing system 200 adapted to process a substrate 13 disposed on a substrate support assembly 240 by generating a plasma 11 in a processing space 234 of a plasma processing chamber 250. The plasma processing system 200 is configured to form an inductively coupled plasma (ICP), and the processing chamber 250 includes a coil 273 positioned above a portion of the processing space 234 to face a bias electrode 214 also disposed in the substrate support assembly 240, at least a portion of which is disposed within the processing space 234. The bias electrode 214 is sometimes referred to herein as a substrate support electrode. The ICP plasma processing source similarly includes a radio frequency (RF) generator 271 electrically coupled to the upper coil 273 via an RF match 272 to deliver a tuned RF signal configured to ignite and sustain the plasma 11 formed in the processing space 234. The bias electrode 214 is coupled to a pulsed voltage (PV) waveform generator 210, which is electrically coupled to the bias electrode 214 through an RF filter 211 configured to prevent RF signals from being directed to the PV waveform generator 210 during processing. In some embodiments, the RF generator 271 is configured to deliver an RF waveform signal having a frequency of 1 MHz or greater, or about 2 MHz or greater (e.g., about 13.56 MHz or greater) through an RF match 272 connected to a coil 273.

[0015]

[0020] The processing chamber 250 typically includes a chamber body 230 including one or more sidewalls 231 and a chamber base 232, which, together with a chamber lid 233, collectively define a processing space 234. The sidewalls 231 and the chamber base 232 are generally made of a material sized and shaped to provide structural support for the elements of the processing chamber 250 and configured to withstand the pressure and energy applied when a processing plasma 11 is generated in a vacuum environment maintained within the processing space 234 of the processing chamber 250 during processing. In one example, the sidewalls 231 and the chamber base 232 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy. A gas inlet 235 disposed through the chamber lid 233 is used to deliver one or more processing gases to the processing space 15 from a processing gas source 219 that is in fluid communication with the processing space 234. The processing gases supplied by the processing gas source 219 include reactive etchant gases and inert gases. The pressure within the processing chamber 250 is controlled by the use of a vacuum pump 255 and the amount of gas flow provided by the processing gas source 219. The substrate 13 is loaded into and removed from the processing space 234 through an opening (not shown) in one of the sidewalls 231, which is sealed with a slit valve (not shown) during plasma processing of the substrate 13.

[0016]

[0021] The substrate support assembly 240 may include a substrate support 205 (e.g., an ESC substrate support) and one or more bias electrodes coupled to the PV waveform generator 210. In some embodiments, the substrate support assembly 240 may further include a support structure 206 including a support base that supports the substrate support 205, an insulator plate, and a ground plate coupled to the chamber base 232. The support base is electrically isolated from the chamber base by the insulator plate, and the ground plate is interposed between the insulator plate 111 and the chamber base 232. The substrate support 205 is thermally coupled to and disposed on the support base configured to regulate the temperature of the substrate support 205 during processing.

[0017]

[0022] Typically, the substrate support 205 is formed of a dielectric material, such as a bulk-sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material. In embodiments herein, the substrate support assembly 240 further includes a bias electrode 214 embedded in the dielectric material. In one configuration, the bias electrode 214 is a chucking pole used to secure (i.e., chuck) the substrate 13 to the substrate support surface of the substrate support assembly 240 and bias the substrate 13 relative to the processing plasma 11 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 214 is formed of one or more conductive components (e.g., one or more metal meshes, foils, plates, or combinations thereof). In some embodiments, the bias electrode 214 is also electrically coupled to a clamping network configured to supply a chucking voltage, such as a static DC voltage between about −5000 V and about +5000 V.

[0018]

[0023] The system controller 226, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 227, memory 228, and support circuits 229. The system controller 226 is used to control the process sequences and methods used to process substrates 13, including the substrate processing methods described herein. The CPU 227 is a general-purpose computer processor configured for use in an industrial environment to control the processing chambers and their associated sub-processors. The memory 228 described herein is typically non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuits 229 are conventionally coupled to the CPU 227 and include cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (software programs) and data may be coded and stored in the memory 228 to instruct the processor within the CPU 227. The software programs (or computer instructions) readable by the CPU 227 in the system controller 226 determine which tasks are executable by the components within the processing system 200. Typically, a software program readable by the CPU 227 in the system controller 226 includes code that, when executed by the processor (CPU 227), performs tasks related to the plasma processing methods described herein. The program may include instructions used to control various hardware and electrical components in the processing chamber 250 and processing system 200 to perform various process tasks and various process sequences used to implement the methods described herein.

[0019]

[0024] As described above, the PV waveform generator 210 is adapted to supply a voltage waveform to one or more electrodes, such as the bias electrode 214, disposed within the process chamber 200. FIG. 2B is a simplified diagram of a pulsed voltage (PV) waveform generator 210 associated with a control system that can be configured to implement methods described herein, according to one or more embodiments. The PV waveform generator 210 typically includes a PV source controller 225 and at least one voltage source assembly including a direct current (DC) voltage source 220 configured to supply a PV waveform to at least one generator output 201 coupled to the bias electrode 214. As an example, as shown in FIG. 2B, the PV waveform generator 210 includes the PV source controller 225 and one DC voltage source 220 configured to supply a PV waveform to the generator output 201. The generator output 201 can be coupled to a source node N coupled to the bias electrode 214, which is capacitively or inductively coupled to a composite load 202 formed by the plasma 11 during plasma processing. The composite load 202 is shown as a standard electrical plasma model that represents the plasma 11 as three circuit elements: (a) a diode; (b) a current source I ion , and (c) capacitor C SH , each of which is present during delivery of at least a portion of the asymmetric voltage waveform supplied by PV waveform generator 210 to the electrodes during the plasma process. In some embodiments, PV waveform generator 210 is a switched-mode power supply. In some embodiments, each PV waveform generator 210 is configured to deliver between 1 and 25 kilowatts (kW) of DC power to the electrodes at a voltage between 100 and 10,000 volts, e.g., between 1,000 and 5,000 volts.

[0020]

[0025] 2B , switches S1 and S2 in PV waveform generator 210 are coupled to and in communication with PV source controller 225, allowing PV source controller 225 to separately open and close switches S1, S2 at desired intervals to create an asymmetric voltage waveform, as disclosed below. Switches S1, S2 depicted in PV waveform generator 210 may be implemented by single-pole, single-throw, normally-open switches controllable by electrical or optical signals provided by PV source controller 225, or by MOSFET devices whose gates are controlled by signals provided by PV source controller 225. PV source controller 225 is also configured to control and / or adjust the voltage levels generated by DC voltage source 220 (e.g., a DC supply) and delivered to the output based on commands received from system controller 226. In some embodiments, PV source controller 225 is in direct communication with switches S1, S2 and DC voltage source 220 to enable the generation of asymmetric voltage waveforms delivered to the generator output on nanosecond or microsecond timescales.

[0021]

[0026] In one or more embodiments disclosed herein, PV waveform generation 210 includes a sensor assembly 205 positioned to measure characteristics of the PV waveform generated at the generator output. Sensor assembly 205 can include one or more electrical components configured to measure one or more electrical characteristics of the asymmetric voltage waveform provided by PV waveform generator 210, such as voltage, current, and offset / phase, and transmit the one or more electrical characteristic data to system controller 226. The electrical characteristic data received by system controller 226 from PV waveform generator 210 can be used together to synchronize the delivery of PV waveform generator 210 and other PV waveforms generated by RF generator 271, as described further below.

[0022]

[0027] System controller 226 and support circuitry are configured to control and / or adjust the voltage waveform generated by PV waveform generator 210. PV waveform generator 210, system controller 226, and support circuitry can adjust a number of electrical parameters used to change one or more of the voltage waveform characteristics, such as frequency, waveform shape, applied voltage on-time, etc., during a pulse of the supplied asymmetric voltage waveform.

[0023]

[0028] Although the disclosure provided herein primarily discusses the use of the processing system 200 for performing plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processing techniques, this configuration is not intended to limit the scope of the disclosure provided herein. It should be noted that the embodiments described herein can be used with processing systems configured for use in other plasma-assisted processes, such as plasma-enhanced deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes), plasma processing fabrication, or plasma-based ion implantation processes (e.g., plasma doping (PLAD) processes).

[0024] Examples of plasma treatment methods

[0029] As described above, embodiments of the present disclosure describe a biasing scheme configured to provide a radio frequency (RF)-generated RF waveform from an RF generator to electrodes in a processing chamber and a pulsed voltage (PV) waveform delivered from a pulsed voltage (PV) generator to one or more electrodes in the processing chamber. Generally, the generated RF waveform is configured to establish and maintain a plasma in the processing chamber, and the delivered PV waveform is configured to establish a desired sheath voltage across the surface of the substrate during one or more phases of the plasma process, thereby creating a desired ion energy distribution function (IEDF) and electron energy distribution function (EEDF) at the surface of the substrate during one or more plasma processing phases performed on the substrate in the processing chamber. The plasma process I disclosed herein can be used to control the shape of the EDF and EEDF, thereby controlling the interaction of the plasma with the substrate surface during processing. In some configurations, the plasma process I disclosed herein is used to control the profile of features formed on the substrate surface during processing. During some semiconductor plasma processes, ions are intentionally accelerated toward the substrate by a voltage drop across an electron repulsion sheath formed above a substrate 13 placed on top of a substrate support assembly 240. Although not intended to be limiting as to the scope of the disclosure provided herein, the substrate support assembly 240 may also be referred to herein as a "cathode assembly" or a "cathode."

[0025]

[0030] 3 illustrates an example of a pulsed voltage waveform including asymmetric voltage pulses provided in pulsed voltage waveform 325 established at a substrate by delivering a series of asymmetric voltage pulses to bias electrode 214 during plasma processing using PV waveform generator 210, according to certain embodiments. As discussed above, it has been determined that establishing a PV waveform at a substrate during plasma processing can be advantageously used to control aspects of the plasma sheath formed over the substrate surface during plasma processing. Controlling the size and shape of the plasma sheath formed over the substrate surface allows for control of ion interactions with the substrate surface during processing, including control of the ion energy distribution function (IEDF), electron energy distribution function (EEDF), ion directionality, and other plasma-related properties. Waveform 325 is an example of an uncorrected pulsed voltage (PV) waveform established at substrate 13 during plasma processing by delivering a PV waveform provided to bias electrode 214. Alternatively, the corrected pulse voltage (PV) waveform seen at the substrate can be established by applying a negative voltage ramp to the PV waveform 325 supplied to the bias electrode 214 by the PV waveform generator 210 during the ion current phase of the pulse voltage waveform 325.

[0026]

[0031] 3, waveform 325 includes two main phases: ion current phase 324 and sheath collapse phase 322. Both portions of the pulse within waveform 325 can be sequentially established at substrate 13 during plasma processing. At the beginning of ion current phase 324, the negative portion of the PV waveform supplied by PV waveform generator 210 to bias electrode 214 is delivered, causing a voltage drop at substrate 13 (i.e., falling edge 323) and forming a high-voltage sheath above substrate 13. The high-voltage sheath allows positive ions generated in the plasma to be accelerated toward the biased substrate during the ion current phase, and thus, in the case of an RIE process, controls the amount and characteristics of the etching process that occurs on the surface of the substrate during plasma processing. In some embodiments, ion current phase 324 generally desirably includes a region of the pulse voltage waveform that achieves a voltage at substrate 13 that is stable or changes minimally throughout the phase. It should be noted that significant variations in the voltage established at the substrate 13 during the ion current phase 324, as indicated by the positive slope of waveform 325, can cause undesirable variations in the ion energy distribution function (IEDF) and / or electron energy distribution function (EEDF), and therefore undesirable characteristics of the etched features formed in the substrate during the RIE process.

[0027]

[0032] At the end of the ion current phase 324 and the beginning of the sheath collapse phase 322, a rising edge 321 of the PV waveform 325 is produced by the PV source assembly, which forms part of a typically short, narrow positive pulse that transitions from a negative voltage level to a positive voltage greater than zero volts. The duration of the positive portion of the pulse can be varied, and in some embodiments, the waveform period (T P ) between 1% and 20% of the waveform period (T P ) In one example, the repetition frequency of the voltage pulses in waveform 325 may be between about 100 kHz and 500 kHz, such as between 200 kHz and 400 kHz.

[0028]

[0033] In some embodiments, the PV waveform 325 generated by the PV waveform generator 210 includes multiple voltage pulse bursts 401 shown in Figure 4. Each burst 4011, 4012, 4013 includes a portion of a pulsed voltage waveform that includes multiple asymmetric voltage pulses, such as the pulses shown in Figure 3. In some embodiments, a bias voltage is applied during each asymmetric voltage pulse of the ion current phase 324. In other words, the off time T of each voltage pulse OFF occurs during the sheath collapse phase, and the application of the bias voltage occurs during the ion current phase 324 during the on-time T ON This is done during the on-time T ON and off time T OFF is the period of each voltage pulse T P The frequency of each voltage pulse is set as a percentage of T P can be adjusted by increasing or decreasing T ON and T OFF is the period T P Further, the voltage pulse has an applied bias voltage V, defined as the peak voltage during the ion current phase.

[0029]

[0034] 4 illustrates synchronized delivery of an RF signal 411 generated by an RF generator 271 and voltage pulse bursts 401 generated by a PV waveform generator 210 and delivered to an electrode (e.g., bias electrode 214) in a plasma processing chamber, according to certain embodiments. FIG. 5 illustrates a method 500 used to synchronize delivery of the RF signal 411 generated by the RF generator 271 and the voltage pulse bursts 401 to at least control improved etch profile results and reduced microloading effects observed in features formed on a surface of a substrate after plasma processing. During processing, the PV waveform generator 210 is configured to generate a PV waveform 325 including multiple voltage pulse bursts 401 of voltage pulses. Characteristics of the voltage pulses within each burst 401 of voltage pulses are controlled by the PV source controller 225 and / or the system controller 226. At least one parameter of the asymmetric voltage pulses that make up each burst 401, such as the pulse on-time, the ratio of the pulse on-time to the pulse period (i.e., the percentage on-time), the pulse voltage, the voltage pulse repetition rate, and combinations thereof, can be adjusted during processing by the PV source controller 225 and / or the system controller 226. In some embodiments, to accommodate undesirable characteristics such as variations in IDEF, EEDF, and non-uniformity of the etched features, the PV waveform generator 210 may be configured to deliver bursts with different parameters based on information received by the controller 226.

[0030]

[0035] Referring to FIG. 4, each voltage pulse burst 401 in the PV waveform 325 is a burst-on time T BO The PV waveform 325 includes a burst off time T during which no asymmetric voltage pulse is delivered to the electrodes 214. BF Also included is the burst on time T BO and burst off time T BF The sum of these is the burst period T BP In some embodiments, the burst on time T BOcan be between about 50 μs and about 50 milliseconds (ms), for example, between about 200 μs and about 5 ms, and the burst duty cycle (i.e., T BO / T BP ) can be between about 5% and about 100%, for example, between about 50% and about 95%. ON is about 800 μs and the burst duty cycle of the voltage pulse burst 401 is about 80%.

[0031]

[0036] As mentioned above, Figure 5 illustrates a method 500 for using a plasma processing chamber according to certain embodiments. Method 500 may be performed through the use of a computer or programmable controller including hardware (e.g., electrical circuitry, dedicated logic, programmable logic, microcode, processing device, etc.), software (e.g., instructions executed by a processing device, general-purpose computer system, or dedicated machine), firmware, microcode, or a combination thereof. In some embodiments, method 500 is performed in part by one or more components within system controller 226. In some embodiments, a non-transitory storage medium stores instructions that, when executed by a processor within the system controller, cause a controller device to perform method 500.

[0032]

[0037] For ease of explanation, method 500 is shown and described as a series of steps. However, steps according to this disclosure may occur in various orders and / or simultaneously, and with other steps not shown and described herein. Furthermore, in some embodiments, not all illustrated steps are performed to implement method 500 in accordance with the disclosed subject matter. Additionally, those skilled in the art will understand and appreciate that method 500 can alternatively be represented as a series of interrelated states via a state diagram or events.

[0033]

[0038] In activity 502 of method 500, a first burst 4011 (FIG. 4) of a series of bursts in a PV waveform 325 is delivered to an electrode 214 in a plasma processing system 200, and an RF signal having a first RF power level P1 is simultaneously supplied to an RF electrode (e.g., coil 273) in the plasma processing system 200 using an RF generator 271. The burst-on time T of the first burst 4011 is BO is the length of time spanning, for example, between time T0 and T1. In one example, the burst-on time T of the first burst 4011 is BO is between about 10 μs and 800 μs, such as between 100 μs and 500 μs, or even between about 100 μs and 300 μs. In one example, the first burst 4011 has a peak negative voltage that can be between −100 volts (V) and −2000 volts, a pulse period T P The RF signal may include a series of asymmetric voltage pulses having an on-time of between about 5% and 95% (e.g., 85%) of the pulse width and a repetition frequency of between 100 kHz and 500 kHz, e.g., between 200 kHz and 400 kHz. The RF signal may include an RF waveform having a frequency greater than 1 MHz, e.g., about 13.56 MHz or greater, and may have a first RF power level P1 of between about 500 watts (W) and 2,000 W.

[0034]

[0039] Activity 502 is generally provided in method 500 to bombard the surface of the substrate with ions to cause etching of a portion of the substrate. The etching process also typically involves the removal of material from the substrate surface through the use of one or more reactive gases and other components formed in the plasma generated by delivery of RF signal 411. The process of bombarding the surface of substrate 13 during activity 502 moves etched material from the exposed surface of substrate 13 away from the surface from which it was removed. However, as the aspect ratio of features formed in the substrate increases, the etched material found within the feature tends to inhibit the etching process at the bottom of narrower features than wider features due to more collisions between plasma-generated ions and the migrating etched material (i.e., etch byproducts) as the etching process performed on the substrate continues. The variation in etch rate caused by the inhibiting material found in features of different configurations results in a microloading effect across different regions of the substrate.

[0035]

[0040] During activity 504, the output of the PV waveform generator 210 is stopped and one or more characteristics of the RF signal delivered to the RF electrodes are adjusted. During activity 504, the PV waveform 325 is turned off with a burst off time T BF As shown in Figure 4, the first part of the burst-off time T BF The first portion of the period is, for example, the length of time spanning between times T1 and T2. In one example, the first period is between about 100 μs and 1.2 milliseconds (ms), such as between 0.5 ms and 1 ms, or even between about 0.7 ms and 0.9 ms. The burst-off time T BFThe RF power applied during the first portion of the period may be applied at a second RF power level P2 that is different from the first RF power level P1, such as being less than the first RF power level P1. In one example, the second RF power level P2 is between about 100 Watts and about 1,000 Watts, e.g., between 400 Watts and 700 Watts, at an RF frequency of about 13.56 MHz or greater. Activity 504 is generally used to enable safe passivation of the exposed surface of the substrate etched during activity 502 due to the presence of components found in the plasma maintained by delivery of the RF signal supplied at the second RF power level P2.

[0036]

[0041] During activity 506, the output of the PV waveform generator 210 remains stopped and one or more characteristics of the RF signal delivered to the RF electrodes are further adjusted. During activity 506, the PV waveform 325 is adjusted with a burst off time T BF The second part of the period begins. The burst-off time T BF The second portion of the period is, for example, a length of time spanning between times T2 and T3. In one example, the second period is between about 500 μs and 2 milliseconds (ms), such as between 0.7 ms and 1.5 ms, or even between about 0.8 ms and 1.2 ms. In one example, the second period is between about 0.8 ms and 1.2 ms, and the burst period T BP The burst off time T is between approximately 2ms and 3ms. BFThe RF power applied during the second portion of the period may be applied at a third RF power level P3 different from the first RF power level P1 and the second RF power level P2, such as being less than the first RF power level P1 and the second RF power level P2. In one example, the third RF power level P3 is adjusted to a level at or near zero watts. Activity 504 is generally used to enable removal of etched material from features formed on the exposed surface of the substrate by a pumping process that allows material migrating from the etched features formed in the substrate to be pumped out of the processing space 234 by the vacuum pump 255 (FIG. 2). The pumping process is also referred to herein as a process of evacuating the processing space 234. By periodically removing etching material (e.g., etching by-products) from the features formed in the substrate, the etchant is more effectively delivered to the features being etched in a desired ion trajectory, such as a vertical trajectory.

[0037]

[0042] In some embodiments, the pressure within processing space 234 is adjusted during each activity 502-506 by adjusting the flow of gases supplied from process gas source 219 and / or by a flow control valve (not shown) located in the exhaust line connecting vacuum pump 255 to processing chamber 250. In certain embodiments, the pressure within processing space 234 is reduced during activity 506 compared to the pressure maintained in processing space 234 during activities 502 and 504.

[0038]

[0043] After activity 506 is completed, method 500 may include completing activities 502-506 multiple times. In one example, the total time it takes to sequentially complete one cycle of activities 502-506 is between approximately 1 ms and 3 ms, and activities 502-506 are repeated multiple times in a sequential, cyclical manner over a period of between approximately 1 second and 60 seconds.

[0039]

[0044] In some embodiments, the length of time between each interval, such as the first interval between times T0 and T1, the second time interval between T1 and T2, and the third time interval between T2 and T3, varies between different cycles of activities 502-506. In one example, during the second cycle of activities 502-506, after performing the first cycle of activities 502-506, the second time interval is decreased by a first amount of time and the third time interval is increased by a second amount of time. The same burst period T for each cycle of activities is maintained. BP In other cases, it may be desirable to adjust the length of one or more time intervals as needed between cycles to achieve a desired processing result on the substrate, and thus the burst period T BP The length of the third time interval may vary from cycle to cycle. In one example, during a second cycle of activities 502-506, after performing a first cycle of activities 502-506, the third time interval is increased by an amount of time to account for the increase in the depth of the etched feature observed after performing the first cycle of activities. In this example, the third time interval during the second cycle may be increased after multiple intermediate cycles are performed between the first and second cycles. The length of one or more time intervals may vary over time, for example, the third time interval may increase an amount of time every cycle, every other cycle, or every number of cycles.

[0040]

[0045] 4, while the voltage pulse bursts 4011, 4012, 4013 include a single coherent type of burst (i.e., a voltage pulse within the PV waveform 325), it is contemplated that the bursts within the series of bursts may include different configurations of bursts, including voltage pulses with different voltage pulse characteristics. In one example, two or more voltage pulse bursts 4011, 4012, 4013 include a series of asymmetric voltage pulses, each having a different peak negative voltage, a different voltage pulse on-time, or a different repetition frequency. Similarly, in some embodiments, the RF waveform within the RF signal 411 may include a series of different configurations of RF signal levels or may include RF pulses (not shown).

[0041]

[0046] Advantageously, it is believed that controlling certain characteristics of the pulse voltage waveform and RF waveform delivered during a plasma process performed on a substrate may improve the etched features formed across the surface of the substrate. In one example, the pulse period T of burst 401 may be adjusted to 1 / 2 . P Pulse-on time (T ON ) vs. pulse off time (T OFFIt has been found that adjusting the voltage pulse repetition rate (VPR) can improve microloading results in features formed on the substrate surface. It has been found that the voltage pulse repetition rate can affect other important plasma processing parameters, such as etch selectivity. In another example, controlling the pulse voltage level, such as increasing the voltage level in one phase of the plasma process relative to another, can improve the ability to etch deep features in the substrate surface, leading to faster etch rates and larger plasma sheaths (and vice versa for pulse rate), while lower voltage levels can be beneficially used to form certain types of etched features. In another example, adjusting the rest time between bursts of voltage pulses, or the second portion of the burst off-time period, can be used to provide extra time for etch byproducts to be pumped out of the processing space 234, which can improve etch uniformity and reduce microloading, while shortening the rest time between bursts can improve substrate throughput during plasma processing. Thus, in some embodiments, at least one parameter of the voltage pulses in different voltage pulse bursts 401 in the PV waveform 325 can be adjusted during processing to achieve desired plasma processing results. Various combinations of bursts with voltage pulses having different characteristics can be used to tailor the plasma processing results seen on the substrate.

[0042]

[0047] As used herein, the term "coupled" refers to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B physically contacts object C, objects A and C are still considered coupled to each other even though they are not in direct physical contact with each other. For example, a first object can be coupled to a second object even though the first object is not in direct physical contact with the second object.

[0043]

[0048] While the above description is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. 1. A method of processing a substrate, comprising, for a substrate disposed in a processing region of a plasma processing chamber, a processing sequence comprising: A first processing sequence section, delivering, by a voltage waveform generator, a first burst of a first asymmetric voltage pulse to a bias electrode disposed within the plasma processing chamber, the first burst of the first asymmetric voltage pulse being provided for a first time period; a first processing sequence interval comprising: delivering, by use of a radio frequency (RF) generator, an RF signal to an RF electrode disposed within the plasma processing chamber for the first time period, the RF signal provided during the first time period comprising a first RF power level; A second processing sequence section, ceasing delivery of the first burst of first asymmetric voltage pulses for a second period of time; a second processing sequence section including using the radio frequency (RF) generator to deliver the RF signal to the RF electrode during the second time period, the RF signal provided during the second time period including a second RF power level; A third processing sequence section, continuing to suspend delivery of the first burst of first asymmetric voltage pulses for a third period of time; ceasing delivery of the RF signal to the RF electrode for the third period of time. and evacuating a processing volume of the plasma processing chamber to a pressure below atmospheric pressure during the first, second, and third processing sequence intervals. A method for processing a substrate.

2. The method of claim 1 , further comprising sequentially repeating the first, second, and third processing sequence intervals a plurality of times.

3. The method of claim 1 , wherein the third period of time is longer than the first period of time and the second period of time.

4. The method of claim 3 , wherein the second RF power level is less than the first RF power level.

5. 2. The method of claim 1, wherein delivering the first burst of first asymmetric voltage pulses comprises delivering a plurality of asymmetric voltage pulses each having a pulse on-time between 5% and 95% of the pulse period and a repetition frequency between 200 kHz and 500 kHz.

6. 6. The method of claim 5, wherein delivering the plurality of asymmetric voltage pulses with the voltage waveform generator comprises applying a negative voltage to the bias electrode during the pulse-on time.

7. The method of claim 6 , wherein the first period of time is between 0.1 milliseconds (ms) and 0.5 ms.

8. The method of claim 5 , wherein the first period of time is between 0.1 milliseconds (ms) and 0.5 ms.

9. The method of claim 8 , wherein the first period of time is less than the second period of time, and the second period of time is less than the third period of time.

10. The method of claim 5 , wherein the RF electrode comprises a coil and the bias electrode comprises an electrode disposed within a substrate support within the plasma processing chamber.

11. 2. The method of claim 1, wherein the third period of time is between 0.5 ms and 1.5 ms, and the sum of the first period of time, the second period of time, and the third period of time is between 2 ms and 3 ms.

12. The method of claim 11 , further comprising sequentially repeating the first, second, and third processing sequence intervals a plurality of times.

13. The method of claim 12 , wherein the third period of time is longer than the first period of time and the second period of time.

14. The method of claim 13 , wherein the second RF power level is less than the first RF power level.

15. 1. A plasma processing chamber comprising: Voltage waveform generator; Radio frequency (RF) generator; a bias electrode disposed within the plasma processing chamber; an RF electrode disposed within the plasma processing chamber; a vacuum pump configured to evacuate a processing volume of the plasma processing chamber; and memory for storing programs executed by a processor When the program is executed, The processing sequence includes: A first processing sequence section, delivering, by the voltage waveform generator, a first burst of first asymmetric voltage pulses to the bias electrodes, the first burst of first asymmetric voltage pulses being supplied for a first time period; a first processing sequence interval including: delivering, by using the radio frequency (RF) generator, an RF signal to the RF electrode during the first time period, the RF signal provided during the first time period including a first RF power level; A second processing sequence section, ceasing delivery of the first burst of first asymmetric voltage pulses for a second period of time; a second processing sequence interval including: delivering, by using the radio frequency (RF) generator, the RF signal to the RF electrode during the second time period, wherein the RF signal provided during the second time period includes a second RF power level; and A third processing sequence section, continuing to suspend delivery of the one burst of first asymmetric voltage pulses for a third period of time; ceasing delivery of the RF signal to the RF electrode for the third time period; and evacuating the processing region of the plasma processing chamber to a pressure below atmospheric pressure using the vacuum pump during the first, second, and third processing sequence intervals. including instructions to execute Plasma processing chamber.

16. When the program is executed, 16. The plasma processing chamber of claim 15, further comprising instructions to sequentially repeat the first, second, and third processing sequence intervals a plurality of times.

17. 16. The plasma processing chamber of claim 15, wherein the third period of time is longer than the first period of time and the second period of time.

18. 20. The plasma processing chamber of claim 17, wherein the second RF power level is less than the first RF power level.

19. 16. The plasma processing chamber of claim 15, wherein delivering the first burst of first asymmetric voltage pulses comprises delivering a plurality of asymmetric voltage pulses each having a pulse on-time between 5% and 95% of a pulse period and a repetition frequency between 200 kHz and 500 kHz.

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