Correcting internal clearances at circuit board connector pin openings

Abstract

A method of manufacturing a multilayer circuit board includes forming a layer of the multilayer circuit board adjacent an opening in the multilayer circuit board with an internal clearance area having a modified conductive material voltage-to-ground clearance, the modified conductive material voltage-to-ground clearance being based on the configuration of a connector pin press-fit into the opening in the multilayer circuit board, and the internal clearance area is enlarged in the direction of maximum normal force outward from the opening due to insertion of the connector pin into the opening.

Description

[Background technology]

[0001] One or more aspects relate generally to circuit board assemblies and their manufacture, and more particularly to improved multilayer circuit board layouts, circuit board assemblies, and methods of manufacturing circuit board assemblies.

[0002] A press-fit, interference fit, or friction fit is a physical fastening of parts achieved by friction after pressing the two parts together, rather than by the application of a fastener or adhesive. Press-fit connectors are used in the electronics industry by circuit board manufacturers; press-fit connections allow manufacturers to avoid, for example, soldering the connector to the circuit board. In this context, a press-fit connection is typically formed when pins are inserted or assembled into plated through holes in the circuit board. The use of press-fit connectors in circuit board assemblies is widespread in the electronics industry.

[0003] Press-fit connectors can include solid pins or compliant pins. Most press-fit connections use compliant pin technology because the reduced force required on the pins during the insertion process creates a more reliable connection with less damage to the plated-through holes in the circuit board. Press-fit connectors are used in a variety of applications, including, for example, data and communications applications. Summary of the Invention

[0004] According to one aspect of the present invention, a method for manufacturing a multilayer circuit board is provided. The method includes forming layers of the multilayer circuit board with an internal clearance area having a modified conductive material voltage-to-ground clearance adjacent an opening in the multilayer circuit board. The modified conductive material voltage-to-ground clearance is based on the configuration of a connector pin press-fit into the opening in the multilayer circuit board. The internal clearance area is enlarged in the direction of maximum normal force outward from the opening due to insertion of the connector pin into the opening. Advantageously, the modified conductive material voltage-to-ground clearance adjacent the opening in the multilayer circuit board improves critical clearances between conductors, such as power and ground conductors, within the multilayer circuit board, thereby improving product reliability and integrity in multilayer circuit board assemblies, for example, using connector pins to couple components to the multilayer circuit board.

[0005] Preferably, the invention provides a method wherein the internal clearance region includes an elongated clearance region around the opening in the layer, the major axis of the elongated clearance region being oriented based at least in part on a configuration of the connector pin received in the opening so as to provide improved clearance between the conductive materials in the direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening. Advantageously, the elongated clearance region around the opening provides an improved clearance region or area within a layer to ensure that sufficient dielectric material exists between conductive materials, for example, between non-common power and ground conductors of a multilayer circuit board, despite potential deformation of the multilayer circuit board due to insertion of the connector pin.

[0006] Preferably, the present invention provides a method wherein the step of forming the layer further includes a step of orienting the major axis of the extended clearance region based on the configuration and orientation of the connector pin to be received in the opening so as to provide improved clearance between the conductive materials in the direction of the maximum normal force directed outward from the opening due to insertion of the connector pin into the opening.

[0007] Preferably, the present invention provides a method wherein the opening is a power routing related via in the multilayer circuit board, and the extended clearance area defines an improved voltage-to-ground clearance between the power routing related via and the conductors on each layer of the multilayer circuit board. By defining an improved voltage-to-ground clearance between the power routing related via and the conductors on each layer of the multilayer circuit board, product reliability and integrity are improved.

[0008] Preferably, the present invention provides a method further comprising inserting the connector pin into the opening in the multilayer circuit board to couple a component to the multilayer circuit board, the insertion causing deformation of the layers of the multilayer circuit board in the direction of the maximum normal force directed outward from the opening due to insertion of the connector pin into the opening, and the extended clearance area providing the improved clearance between conductive materials in the direction of the maximum normal force directed outward from the opening, reducing the risk of electrical shorts occurring due to the deformation caused by insertion of the connector pin. By reducing the risk of electrical shorts occurring due to deformation of one or more layers of the multilayer circuit board due to insertion of the connector pin, a more reliable printed circuit board assembly is provided.

[0009] According to another aspect of the present invention, there is provided a circuit board assembly including a multilayer circuit board having one or more openings configured to receive one or more connector pins, the multilayer circuit board being press-fit connectable via the one or more connector pins. The multilayer circuit board includes an internal clearance region within a layer of the multilayer circuit board adjacent to an opening of the one or more openings, the internal clearance region having a modified conductive material voltage-to-ground clearance based on the configuration of each of the one or more connector pins. By improving the conductive material voltage-to-ground clearance based on the configuration of each connector pin, improved product reliability and integrity of the multilayer circuit board assembly can be achieved, for example, using the connector pins to couple components to the multilayer circuit board.

[0010] According to another aspect of the present invention, there is provided a computer-implemented method for generating a multilayer circuit board layout, the computer-implemented method including: generating, using a circuit board design tool, a circuit board layout for a multilayer circuit board being manufactured, the generating step including: identifying, by the circuit board design tool, layers of the multilayer circuit board having internal clearance areas around an opening in the multilayer circuit board having a modified conductive material voltage-to-ground clearance; and determining, by the circuit board design tool, a configuration and orientation of connector pins to be press-fit connected into the openings in the multilayer circuit board. The generating step further includes modifying, by the circuit board design tool, the conductive material voltage-to-ground clearance of the layers in the internal clearance areas around the openings based on the determined configuration and orientation of the connector pins to be press-fit connected into the openings in the multilayer circuit board, wherein the ground voltage clearance is modified in the direction of a maximum normal force directed outward from the opening due to insertion of the connector pin into the opening. Advantageously, using a circuit board design tool to generate a circuit board layout with modified voltage-to-ground clearance of conductive material within the layer's internal clearance area around the opening based on the determined configuration and orientation of the connector pins improves the reliability and integrity of the resulting multilayer circuit board assembly, where the connector pins are used, for example, to couple components to the multilayer circuit board.

[0011] According to another aspect of the present invention, a computer system for facilitating generation of a multilayer circuit board layout is provided. The computer system includes a memory and at least one processor in communication with the memory. The computer system is configured to execute a method, the method including generating, via a circuit board design tool, a circuit board layout for a multilayer circuit board being manufactured. The generating step includes identifying, via the circuit board design tool, layers of the multilayer circuit board having internal clearance areas around openings in the multilayer circuit board having modified conductive material voltage-to-ground clearances. The generating step further includes determining, via the circuit board design tool, a configuration and orientation of connector pins to be press-fit connected into the openings in the multilayer circuit board. The generating step further includes modifying, via the circuit board design tool, the conductive material voltage-to-ground clearances in the internal clearance areas of the layers around the openings based on the determined configuration and orientation of the connector pins to be press-fit connected into the openings in the multilayer circuit board. The ground voltage clearances are modified in the direction of a maximum normal force directed outward from the opening due to insertion of the connector pins into the openings. Advantageously, modifying the voltage-to-ground clearance of the conductive material within the internal clearance area of ​​the layer around the opening based on the determined configuration and orientation of the connector pins improves product reliability and integrity of the multilayer circuit board assembly.

[0012] According to another aspect of the present invention, a computer program product is provided that facilitates generating a multilayer circuit board layout. The computer program product includes one or more computer-readable storage media and program instructions embodied therewith. The program instructions are readable by a processing circuit to cause the processing circuit to execute a method, the method including generating, via a circuit board design tool, a circuit board layout for a multilayer circuit board being manufactured. The generating step includes identifying, via the circuit board design tool, layers of the multilayer circuit board having internal clearance areas around openings in the multilayer circuit board that have conductive material voltage-to-ground clearances to be modified. The generating step further includes determining, via the circuit board design tool, a configuration and orientation of connector pins to be press-fit into the openings in the multilayer circuit board. Additionally, the generating step includes modifying, via the circuit board design tool, the conductive material voltage-to-ground clearances in the internal clearance areas of the layers around the openings based on the determined configuration and orientation of the connector pins to be press-fit into the openings in the multilayer circuit board. The voltage-to-ground clearance is modified in the direction of maximum normal force outward from the opening due to insertion of the connector pin into the opening, which advantageously improves the generated circuit board layout design and thereby the resulting multilayer circuit board during manufacture. Advantageously, specifying improved clearances between conductive materials and at least one of these interior regions based on the configuration of the connector pin received in the opening improves critical clearances between conductors, such as power and ground conductors, within the multilayer circuit board, thereby improving product reliability and integrity in multilayer circuit board assemblies, for example, using connector pins to couple components to the multilayer circuit board.

[0013] Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects. [Brief explanation of the drawings]

[0014] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The above, and other objects, features, and advantages of one or more aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Figure 1] 1 illustrates an example of a computing environment that can include and / or use one or more aspects of the present invention; [Figure 2] FIG. 1 is a partial cross-sectional elevation view of one embodiment of a circuit board assembly including and / or using one or more aspects of the present invention; [Figure 3A] showing the insertion of press-fit pins into openings in multilayer circuit boards; [Figure 3B] showing the insertion of press-fit pins into openings in multilayer circuit boards; [Figure 3C] Demonstrates deformations that may occur within multilayer circuit boards due to insertion forces; [Figure 3D] Demonstrates deformations that may occur within multilayer circuit boards due to insertion forces; [Figure 4] FIG. 1 is a partial cross-sectional elevation view of one embodiment of a multilayer circuit board assembly having an improved internal clearance area around an opening within a connector pin and opening interaction zone in accordance with one or more aspects of the present invention; [Figure 5A] FIG. 1 is a partial cross-sectional plan view showing layers of a circuit board assembly, illustrating one embodiment of a pin-eye connector pin within an opening in a multilayer circuit board, illustrating normal force directions with potential laminate cracking addressed by one or more aspects of the present invention; [Figure 5B]FIG. 1 is a partial schematic diagram of one embodiment of a multilayer circuit board and pin assembly layout with specific interior regions of the multilayer circuit board surrounding selected openings modified with improved clearances oriented based on connector pin configuration, in accordance with one or more aspects of the present invention; [Figure 5C] FIG. 1 is a partial cross-sectional plan view of an embodiment of a circuit board assembly layer having an extended clearance area surrounding a selected opening that provides improved conductor clearance in the direction of maximum normal force outward from a pin-eye connector pin within the selected opening, in accordance with one or more aspects of the present invention; [Figure 5D] 5D is an enlarged partial cross-sectional plan view of the circuit board assembly layers of FIG. 5C taken along line 5D, showing an elongated internal clearance area around the opening and showing a pin-eye connector pin present within the opening, according to one or more embodiments of the present invention; [Figure 5E] FIG. 1 is another partial cross-sectional plan view showing layers of a circuit board assembly, illustrating one embodiment of an action-type connector pin within an opening in a multilayer circuit board, illustrating normal force directions with potential laminate cracking addressed by one or more aspects of the present invention; [Figure 5F] FIG. 1 is a partial schematic diagram of one embodiment of a multilayer circuit board and pin assembly layout with specific interior regions of the multilayer circuit board surrounding selected openings modified with improved clearances oriented based on connector pin configuration, in accordance with one or more aspects of the present invention; [Figure 5G] FIG. 1 is a partial cross-sectional plan view of an embodiment of a circuit board assembly layer having an extended clearance area surrounding a selected opening that provides improved conductor clearance in the direction of maximum normal force outward from an action-type connector pin within the selected opening, in accordance with one or more aspects of the present invention; [Figure 5H] 5H is an enlarged partial cross-sectional plan view of the circuit board assembly layers of FIG. 5G taken along line 5H, showing an elongated internal clearance area around the opening and illustrating an action-type connector pin present within the opening, in accordance with one or more embodiments of the present invention; [Figure 6] 1 illustrates one embodiment of a computer program product according to one or more aspects of the present invention; [Figure 7] 1 illustrates one embodiment of a workflow according to one or more aspects of the present invention; and [Figure 8] 1 illustrates another embodiment of a computing environment that may include and / or use one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, further illustrate the present invention and, together with this detailed description of the invention, serve to explain aspects of the present invention. In this regard, it should be noted that descriptions of well-known systems, devices, processing techniques, etc. have been omitted so as not to obscure the invention in unnecessary detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the present invention, are given by way of illustration only and not limitation. Various substitutions, modifications, additions, and / or other configurations within the scope of the underlying inventive concept will be apparent to those skilled in the art from this disclosure. It should be further noted that, while numerous aspects or features of the present invention are disclosed herein, and, to the extent not inconsistent, each disclosed aspect or feature can be combined with any other disclosed aspect or feature as desired for a particular application of the disclosed concept.

[0016] It should also be noted that the exemplary embodiments are described below by way of example only, and not by way of limitation, using particular code, designs, architectures, protocols, layouts, schematics, or tools. Furthermore, the exemplary embodiments are described in particular instances using particular software, tools, or data processing environments, by way of example only, for clarity of explanation. The exemplary embodiments may be used in conjunction with other comparable or similarly purposed structures, systems, applications, or architectures. One or more aspects of the exemplary embodiments may be implemented in software, hardware, or a combination thereof.

[0017] As will be appreciated by those skilled in the art, program code referred to herein may include software and / or hardware. For example, program code in certain embodiments of the present invention may utilize software-based implementations of the described functionality, while other embodiments may include fixed-function hardware. In certain embodiments, both types of program code are combined. Examples of program code, also referred to as one or more programs, are illustrated in FIG. 1 as operating system 122 and circuit board design code 126 stored in persistent storage 113, as well as cloud orchestration module 141, set of virtual machines 143, and set of containers 144 that are part of public cloud 105, in exemplary computing environment 100 of FIG. 1. In another example, the program code illustrated in the computing environment of FIG. 8 includes, in part, application program 816, operating system 818, circuit board design code 820, and computer-readable program instructions 822 stored in memory 806 of computer system 802.

[0018] Before describing embodiments of the present invention, an example computing environment for including and / or using one or more aspects of the present invention is discussed below with reference to FIG.

[0019] Various aspects of the present disclosure are described through text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. For any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in the reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0020] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media"), collectively contained in one or more storage devices, that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded device (such as pits / lands formed on a major surface of a punch card or disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but this does not make the storage device temporary because the data is not temporary while it is stored.

[0021] Computing environment 100 includes an example of an environment for execution of at least a portion of computer code involved in performing the method of the present invention, such as a circuit board design tool or code block 175. In addition to block 126, computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, computer 101 includes a processor set 110 (including processing circuitry 120 and cache 121), a communications fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and block 175 shown above), a peripheral device set 114 (including a user interface (UI) device set 123, storage 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. Remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140, a cloud orchestration module 141, a set of host physical machines 142, a set of virtual machines 143, and a set of containers 144.

[0022] Computer 101 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 130. As is well understood in the field of computer technology, and depending on the technology, execution of a computer-implemented method may be distributed among multiple computers and / or multiple locations. However, in this description of computing environment 100, for purposes of brevity, the detailed discussion focuses on a single computer, specifically computer 101. Although computer 101 is not depicted in FIG. 1 within a cloud, it may be located within a cloud. However, computer 101 need not reside within a cloud except to any extent that may be expressly indicated.

[0023] Processor set 110 includes one or more computer processors of any type now known or later developed. Processing circuitry 120 may be distributed across multiple packages, e.g., multiple tailored integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on processor set 110. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all caches for a processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to operate with qubits and perform quantum computing.

[0024] Computer-readable program instructions are typically loaded onto computer 101 and cause processor set 110 of computer 101 to execute a series of operational steps, thereby enabling a computer-implemented method, such that the instructions so executed instantiate the methods specified in the computer-implemented method flowcharts and / or descriptions contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by processor set 110 to control and direct the execution of the methods of the present invention. In computing environment 100, at least some of the instructions for executing the methods of the present invention may be stored in block 175 in persistent storage 113.

[0025] Communications fabric 111 is the signal-conducting pathway that allows various components of computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as switches and conductive pathways that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways may be used, such as fiber optic communication pathways and / or wireless communication pathways.

[0026] Volatile memory 112 may be any type of volatile memory now known or later developed. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory is characterized by random access, although this is not required unless expressly indicated. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 101.

[0027] Persistent storage 113 is any form of non-volatile storage for a computer, now known or later developed. The non-volatility of this storage means that stored data remains regardless of whether power is supplied to computer 101 and / or to persistent storage 113 directly. While persistent storage 113 can be read-only memory (ROM), typically at least a portion of persistent storage allows data to be written, data to be deleted, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 122 can take several forms, including various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems employing a kernel. The tools or code included in block 175 typically include at least a portion of the computer code involved in performing the methods of the present invention.

[0028] The peripheral device set 114 includes a set of peripheral devices of the computer 101. Data communication connections between the peripheral devices and other components of the computer 101 may be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cable (such as a Universal Serial Bus (USB)-type cable), insertion-type connections (e.g., a Secure Digital (SD) card), connections made through a local area communication network, and even connections made through a wide area network such as the Internet. In various embodiments, the UI device set 123 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. The storage 124 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. The storage 124 may be persistent and / or volatile. In some embodiments, the storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (e.g., where computer 101 stores and manages large databases locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple, geographically distributed computers. IoT sensor set 125 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.

[0029] Network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers over WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing Software-Defined Networking (SDN)), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages multiple different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention may be downloaded to computer 101 from an external computer or external storage device, typically through a network adapter card or network interface included in network module 115.

[0030] WAN 102 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances using any technology for communicating computer data now known or later developed. In some embodiments, a WAN may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0031] End-user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and may take any of the forms discussed above in connection with computer 101. EUD 103 typically receives useful and useful data from the operation of computer 101. For example, in a hypothetical case where computer 101 is designed to provide recommendations to the end user, the recommendations would typically be communicated from network module 115 of computer 101 over WAN 102 to EUD 103. In this manner, EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, and the like.

[0032] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on past data, this past data may be provided to computer 101 from remote database 130 of remote server 104.

[0033] A public cloud 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer capabilities, particularly data storage (cloud storage) and computing power, without direct active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of public cloud 105 computing resources is performed by computer hardware and / or software in cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments running on various computers comprising host physical machine set 142, which is the universe of physical computers within and / or available in public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It is understood that these VCEs can be stored as images and can be transferred among and between various physical machine hosts, either as images or after instantiation of the VCE. The cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of the VCE, and manages active instantiations of VCE deployments. The gateway 140 is a collection of computer software, hardware, and firmware that enables the public cloud 105 to communicate over the WAN 102.

[0034] Some further discussion of virtualized computing environments (VCEs) is now provided. A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from the image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of an operating system in which the kernel allows the existence of multiple isolated user space instances, called containers. These isolated user space instances typically act as actual computers from the perspective of programs running within them. A computer program running on a typical operating system can utilize all of the computer's resources, such as attached devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0035] Private cloud 106 is similar to public cloud 105, except that its computing resources are available only for use by a single enterprise. While private cloud 106 is shown in communication with WAN 102, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often each implemented by a different vendor. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both public cloud 105 and private cloud 106 are part of a larger hybrid cloud.

[0036] Circuit boards, or printed circuit boards, mechanically support and electrically connect components, such as electronic and / or electrical components, using conductive lines, pathways, and other features etched from one or more sheet layers, such as copper, laminated onto and / or between sheet layers of a non-conductive material or substrate, such as woven glass or fiber cloth. The components are then mounted on the printed circuit board, for example, by soldering, press-fit connectors, etc., to both electrically connect and mechanically secure the components to the board. A basic circuit board layer or subassembly can include a flat sheet of insulating material with a layer of conductor foil laminated to the substrate. Chemical etching divides the foil into separate conductive lines, traces, pathways, and vias for passing connections between copper layers. Circuit board designs can have many conductive layers. Multilayer circuit boards sandwich additional conductive layers between layers of insulating material. Conductors on different layers connect with vias within the circuit board, which can be, for example, copper-plated holes that act as electrical tunnels through the insulating substrate. Through-hole component leads may also function as vias connecting multiple layers in a multi-layer circuit board.

[0037] In many circuit board layouts, multiple layers may be provided as power supply and ground planes. Depending on the implementation, there may be one or more power domains and several power supply or power planes within a circuit board. Typically, the power and ground planes are wider in shape than the signal traces. For example, in one or more embodiments of a multilayer circuit board, the entire layer, except for the area of ​​any connection or through-hole vias, may be primarily a solid conductor (e.g., copper) that serves as a ground plane for both shielding and power recovery. Additionally, the power plane may be designed in one or more implementations as, for example, a substantially rectangular conductor plane sized to distribute power from a source location on the power plane to one or more sink locations.

[0038] Modern circuit boards can generally be designed using dedicated circuit board design (or layout) tools or software, with the following steps: schematic capture through electronic design automation (EDA) tools; hard dimensions and templates are determined based on the required circuit configuration; in the case of a circuit board, component and heat sink locations are determined; and the circuit board layer stack is determined. Ground-to-power plane locations are determined. Power planes, the counterpart to ground planes, serve as AC signal grounds while providing DC power to the circuits mounted on the printed circuit board. Signal interconnects are traced on signal planes. Signal planes may be on outer and inner layers, and line impedances are determined using the thickness of the dielectric layer, the thickness of the wiring copper, and the width of the traces. Components are placed, taking into account thermal considerations and geometry, including via and land markings. Signal traces are routed, and the electronic design automation tool typically automatically creates layout clearances and connections in the power and ground planes based on specified rules documented in one or more design libraries. Gerber files can then be generated for producing the resulting circuit board design. As is known, circuit board manufacturing uses a variety of processes including, for example, subtractive, additive, and semi-additive processes, chemical etching, lamination, drilling, plating and coating, and soldermask application and assembly of the resulting circuit board.

[0039] 2 illustrates one embodiment of a circuit board assembly (generally designated 200), such as a printed circuit board assembly, including a multilayer circuit board 210 and one or more components 201 operably coupled to a surface of the multilayer circuit board 210. In one or more implementations, the components 201 are operably coupled to the multilayer circuit board 210 by a plurality of connector pins, such as a plurality of press-fit pins 202, that are pressed into respective openings 211 or connection vias, e.g., respective plated-through holes, in the multilayer circuit board 210. One or more power planes 212 and one or more ground planes 213 may be provided within the multilayer circuit board 210. Additionally, the multilayer circuit board 210 may include one or more signal trace layers 214, for example, for interconnecting signals and electrically routing between the multiple components 201 mounted on the multilayer circuit board 210.

[0040] In one or more embodiments, the use of press-fit technology in circuit board assembly involves the insertion of connector pins or press-fit pins into openings or connection vias, e.g., plated-through holes, in a multilayer circuit board. The resulting press-fit connection provides a reliable interconnection without the need for soldering. The diameter of the press-fit interaction or deformation zone may be larger than the diameter of the opening, i.e., the interaction or deformation zone may be extended into the multilayer circuit board by the insertion of the press-fit pin into the opening. During the press-fit process, mechanical deformation occurs primarily within the compliant pin, but a certain amount of interaction or deformation may also occur in the opening barrel (e.g., plated-through hole) and surrounding circuit board laminate.

[0041] By way of example, FIGS. 3A and 3B illustrate one embodiment of a pinhole connector pin 202 or terminal pin with a compliant press-fit region 300 inserted into an opening 211, e.g., a plated-through hole, in a multilayer circuit board 210. Note that the pinhole connector pin 202 illustrated in FIGS. 3A-3D is shown by way of example only. Other compliant connector pins with different sizes and / or configurations of press-fit regions can be utilized to establish reliable press-fit connections, for example, between a connector pin of a component and a respective opening in a multilayer circuit board. FIG. 3B illustrates the resulting connection with the connector pin 202 residing within the opening 211 in the multilayer circuit board 210, showing the direction of the maximum normal force F directed outward from the opening due to the insertion of the connector pin with the compliant press-fit region 300. During the press-fit process, the press-fit region absorbs deformation of the press-fit pin, resulting in a secure connection of the connector pin within the plated-through hole, forming a reliable connection, including a reliable electrical and mechanical connection.

[0042] By way of example only, Figures 3C and 3D illustrate damage that can occur as a result of one or more press-fit connections made into openings in a multilayer circuit board. As shown in Figure 3C, connector pin insertion can (potentially) result in laminate cracking 310 in the multilayer circuit board due to the outward normal force F exerted from connector pin 201 through opening 211 into the surrounding layers of the circuit board. This problem can be exacerbated if the multilayer circuit board assembly is reworked, resulting in the removal and reinsertion of one or more press-fit pins. The example in Figure 3C illustrates potential laminate cracking 310 between layers of the multilayer circuit board resulting from connector pin insertion. This localized damage in the multilayer circuit board in the area of ​​the pin contact can enable conductive anodic filament (CAF) growth in the damaged dielectric. Furthermore, this problem may not be captured in a time-zero test; rather, it may be a latent failure that can occur in the field over time. An example of CAF growth 320 along a cracked layer of a multilayer circuit board is shown in FIG. 3D. Laminate cracking and other deformations within the multilayer circuit board can be exacerbated when a connector pin encounters, for example, a nodule at or near the board's insertion surface, resulting in greater forces being generated within the insertion zone. Additionally, in one or more implementations, any pre-existing voids and / or other lamination resin fill defects can combine with press-fit damage in the zone of connector pin / opening interaction to reduce or destroy continuous dielectric spacing between conductors within the multilayer circuit board around the opening.

[0043] Press-fit-induced cracks have been observed in the dielectric material between surrounding internal planes and inserted connector pins on multilayer circuit boards with standard anti-pad clearance. In some cases, cracks along the fiber bundles of a circuit board can create potential CAF leakage paths between openings or connection vias and internal planes, such as internal ground or power planes, in a multilayer circuit board. The risk of damage can be exacerbated by any defects or out-of-specification conditions, including out-of-specification hole sizes, out-of-specification press-fit pin sizes, dielectric voids, dewetting of glass bundles in multilayer circuit boards, and plating nodules or other copper-plated through-hole plating conditions that exacerbate the risk of failure. This press-fit insertion problem can be more severe in the case of openings and pins related to power wiring. Industry specifications, such as the IPC-A-600K Guide for Circuit Boards and the IPC-A-610G Guide for Circuit Board Assemblies, include standards that define electrical clearance requirements, including around openings or connector vias, e.g., plated through-holes. Minimum tolerances are typically specified to provide a guide to the acceptability of printed circuit boards. The keep-out or clearance area around the opening for the press-fit connection may be improved from the industry standard as described herein.

[0044] Disclosed herein, in one or more aspects, are methods for manufacturing multilayer circuit boards and circuit board assemblies, as well as computer-implemented methods, computer systems, and computer program products, wherein program code executing on one or more processors enhances processing and performance within a computing environment by facilitating the manufacture of multilayer circuit boards, including generating a circuit board layout for the multilayer circuit board during manufacture using a circuit board design tool.

[0045] In one or more embodiments, a method for manufacturing a multilayer circuit board includes forming layers of the multilayer circuit board with an internal clearance area having a modified conductive material voltage-to-ground clearance adjacent an opening in the multilayer circuit board. The modified conductive material voltage-to-ground clearance is based on the configuration of a connector pin that is press-fit connected within the opening in the multilayer circuit board, and the internal clearance area is expanded in the direction of maximum normal force outward from the opening due to insertion of the connector pin into the opening. Advantageously, the modified conductive material voltage-to-ground clearance adjacent the opening in the multilayer circuit board improves critical clearances between conductors, such as power and ground conductors, within the multilayer circuit board, thereby improving product reliability and integrity in multilayer circuit board assemblies, for example, using connector pins to couple components to the multilayer circuit board.

[0046] In one or more implementations, the internal clearance region includes an elongated clearance region around the opening in the layer, the major axis of the elongated clearance region being oriented based at least in part on the configuration of the connector pin received in the opening to provide improved clearance between conductive materials in the direction of maximum normal force outward from the opening due to insertion of the connector pin into the opening. Advantageously, the elongated clearance region around the opening provides an improved clearance region or area within the layer to ensure sufficient dielectric material exists between conductive materials, for example, between non-common power and ground conductors of a multilayer circuit board, despite potential deformation of the multilayer circuit board due to insertion of the connector pin.

[0047] In one or more embodiments, forming the layer further includes orienting the long axis of the elongated clearance region based on the configuration and orientation of the connector pin to be received in the opening so as to provide improved clearance between the conductive materials in the direction of the maximum normal force directed outward from the opening due to insertion of the connector pin into the opening.

[0048] In one or more implementations, the openings are power routing related vias in a multilayer circuit board, and the extended clearance areas define improved voltage-to-ground clearances between the power routing related vias and the conductors on the respective layers of the multilayer circuit board. By defining improved voltage-to-ground clearances between the power routing related vias and the conductors on the respective layers of the multilayer circuit board, product reliability and integrity are improved.

[0049] In one or more implementations, the method further includes inserting a connector pin into the opening in the multilayer circuit board to couple a component to the multilayer circuit board. The insertion may cause deformation of layers of the multilayer circuit board in the direction of the maximum normal force directed outward from the opening due to insertion of the connector pin into the opening, and the extended clearance area provides improved clearance between conductive materials in the direction of the maximum normal force directed outward from the opening, reducing the risk of an electrical short occurring due to any deformation due to insertion of the connector pin. By reducing the risk of an electrical short occurring due to deformation of one or more layers of the multilayer circuit board due to insertion of the connector pin, a more reliable printed circuit board assembly is provided.

[0050] In one or more other aspects, a circuit board assembly is provided that includes a component having one or more connector pins and a multilayer circuit board having one or more openings. The one or more connector pins of the component are press-fit connected into the one or more openings of the multilayer circuit board. The multilayer circuit board includes an internal clearance region within a layer of the multilayer circuit board adjacent to an opening of the one or more openings, the internal clearance region having a modified conductive material voltage-to-ground clearance based on the configuration of each of the one or more connector pins. The configuration of each connector pin indicates a direction of maximum normal force outward from the opening due to insertion of the connector pin therein, and the internal clearance region is at least partially enlarged in the direction of maximum normal force outward from the opening. By improving the conductive material voltage-to-ground clearance based on the configuration of each connector pin, improved product reliability and integrity of the multilayer circuit board assembly can be achieved, for example, using the connector pins to couple components to the multilayer circuit board.

[0051] Disclosed herein, in one or more implementations, is a novel process for improving printed circuit board layout for connector pin-to-aperture applications. In one or more embodiments, the improved layout provides a process for optimizing critical clearances, for example, between power and ground conductors and surrounding anti-pads around apertures. The disclosed process improves processing and performance in computing environments, including improving critical clearances between conductors, such as power and ground conductors, in multilayer circuit boards, thereby improving product reliability and integrity in multilayer circuit board assemblies, for example, using connector pins to couple components to the multilayer circuit board.

[0052] 4 is a partial cross-sectional elevation view of printed circuit board assembly 200′ showing connector pins 202 press-fit into respective openings 211, e.g., respective plated-through holes, of multilayer circuit board 210′. As shown, multilayer circuit board 210′ ​​includes multiple layered planes of dielectric and conductive material, including, for example, power plane 212, ground plane 213, and multiple signal planes 214. In the illustrated embodiment, power plane 212 is electrically connected to the conductive material in opening 211, by way of example only.

[0053] In one or more implementations, the program code identifies a connector pin-aperture interaction zone 400 extending into the multilayer circuit board 210′ ​​from a surface of the multilayer circuit board, such as a surface where an associated component (not shown) is mounted via one or more connector pins 202. In one or more implementations, when the connector pin 202 is inserted into the aperture 211, a normal force F acts from the top surface of the multilayer circuit board 210′ ​​outwardly from the aperture to the final position of the connector pin within the aperture. In one embodiment, this normal force defines an interaction zone 400 or insertion zone within which one or more internal clearance areas of the multilayer circuit board around the aperture 211 may be improved, as described herein.

[0054] In one embodiment, interaction zone 400 is the area of ​​multilayer circuit board 210′ ​​from the surface of the board to the final insertion contact location of the connector pin within the opening, within which deformation of the layer planes can arise primarily from the outward normal force F exerted by the inserted pin. Similar interaction zones can be determined for any type of compliant press-fit pin technology used in circuit board assembly fabrication processes. By way of example only, in the embodiment of FIG. 4 , layer L2 can be ground plane 213 with significant anti-pad clearance relative to opening 211 containing press-fit connector pin 202, which can be a power pin, such as (in one embodiment) a 12 volt power pin. Layer L3 can be power plane 212 that electrically connects directly to the opening or plated-through hole and, therefore, to the connector pin 202 operably positioned within the opening. Additionally, in the illustrated embodiment, layers L4 and L7, e.g., as part of their respective ground planes 213, comprise conductive material that also provides improved clearance, at least in part, in a direction based on the configuration (and size and orientation) of connector pins 202 within the multilayer circuit board, and particularly based on the normal force F exerted by connector pins 202 within interaction zone 400.

[0055] By way of example, Figures 5A-5D illustrate one embodiment of an industry-specified anti-pad clearance around an opening or connector via in a multilayer circuit board assembly (Figure 5A) and a selectively enhanced or customized clearance area around the opening (Figures 5B-5D) in accordance with one or more aspects of the present invention.

[0056] 5A shows an industry-specified anti-pad clearance area 500 between conductive material 501 of a layer of a multilayer circuit board and aperture 211, e.g., a conductive via or plated-through hole, that accommodates a connector pin 202, such as a pin-eye press-fit pin. As shown, the pin-eye press-fit connector exerts a maximum normal force F directed outward from aperture 211 along axis 502, resulting in a maximum probability of failure of region 505 in dielectric material 503 separating conductive material 501 and aperture 211, which, as noted, can potentially result in reliability or integrity issues for the printed circuit board assembly.

[0057] FIG. 5B is a partial schematic diagram of one embodiment of a layout 510 or layout geometry of a multilayer circuit board assembly as discussed herein, in which a particular internal clearance area of ​​a multilayer circuit board surrounding a selected opening is modified or customized with an enhanced clearance 500′ oriented based on the configuration and orientation of a particular press-fit connector within the board. The schematic diagram of FIG. 5B assumes that the press-fit connector is a pin-eye type press-fit pin oriented as shown in FIG. 5A . In one embodiment, the enhanced clearance 500′ may be an elongated internal clearance area, such as a rectangular anti-pad with rounded corners. In just one embodiment, the elongated clearance area may have a width W defined, for example, as 0.204 + 1.05D, where D is the diameter of the drilled hole in the opening. The length L of the elongated clearance area may be defined, in one embodiment, as 0.90P, where P is the pitch distance between adjacent or neighboring openings in the layout 510. In one embodiment, the corners of the rectangular elongated clearance area 500' in Figure 5B may be rounded with a radius Rk, which is defined as the radius of the corner keepout clearance shape. Note that the eye of the pin connector pin configuration and orientation shown is just one example of a compliant connector pin and orientation that may be referenced when creating a specific elongated clearance area for an interaction zone in a multilayer circuit board assembly.

[0058] FIG. 5C is a partial cross-sectional plan view of one embodiment of a circuit board assembly layer having an extended clearance area surrounding a selected opening that provides, for example, a power or ground connection to a multilayer circuit board, and FIG. 5D is an enlarged view of one improved internal clearance area for a pinhole connector pin, in accordance with one or more aspects of the present invention.

[0059] 5C and 5D collectively, in one embodiment, a layout can be revisited by program code to apply improved clearance areas to selected openings within the interaction zones of connector pins connected to a multilayer circuit board. Layers of the multilayer circuit board within the expected interaction zone or insertion depth of the press-fit pins can have (at least) voltage-to-ground clearance areas modified with improved clearance between the conductive materials. As described, the improved clearance areas can be specified based on the configuration, size, and orientation of the particular connector pin type received in each opening; FIGS. 5A-5D illustrate, by way of example only, a pinhole-type connector pin. As shown in FIG. 5C , in one or more implementations, only selected openings, such as those associated with power wiring, are reconfigured or modified with improved internal clearance areas by program code depending on the connector pin type inserted into the printed circuit board assembly. In this manner, improved voltage-to-ground clearance can be readily provided between non-common power and ground conductive materials.

[0060] 5C, other openings, such as opening 520, may not require the extended clearance area. For example, in one embodiment, conductive material 501 may be a ground plane conductor in a multilayer circuit board, where opening 520 is a plated through hole that electrically connects to the ground plane material, and openings with improved clearance 500′ may be, in one example, power-related vias that connect to different power plane levels of the multilayer circuit board.

[0061] In one or more implementations, the expanded clearance is aligned with the direction of the maximum normal force F directed outward from each opening due to connector pin insertion, which is along axis 502 when the eye-of-the-pin is oriented as shown, as shown in FIG. 5A . Note that this particular layout assumes that the configuration, size, and orientation of the compliant press-fit pins inserted into the openings are known at design layout time. The improved clearance in the most deformable press-fit area provides a larger dielectric margin, ensuring that even minor press-fit laminate cracks 505 ( FIG. 5A ) do not result in dielectric failure. This results in a more reliable printed circuit board assembly because sufficient dielectric material continues to exist between non-common power and ground conductors in the multilayer circuit board. By providing selectively expanded areas of intact dielectric material in the anti-pad, product reliability and integrity are improved.

[0062] 5E-5H illustrate another embodiment of an industry-specified anti-pad clearance around an opening or connector via in a multilayer circuit board assembly (FIG. 5E) and a selectively enhanced or customized clearance area around the opening (FIGS. 5F-5H) in accordance with one or more aspects of the present invention. In this embodiment, the connector pin is, by way of further example, a compliant-action connector pin 202'.

[0063] 5E illustrates an industry-specified anti-pad clearance area 500 between conductive material 501 of a layer of a multilayer circuit board and opening 211, e.g., a conductive via or plated-through hole, that accommodates a connector pin 202′, such as an action-type connector pin. As shown, the action-type connector pin exerts a maximum normal force F directed outward from opening 211 along axis 502′, resulting in a maximum probability of failure of region 505 in dielectric material 503 separating conductive material 501 and opening 211, which, as noted, can potentially result in reliability or integrity issues for the printed circuit board assembly.

[0064] FIG. 5F is a partial schematic diagram of one embodiment of a layout 510′ or layout geometry for a multilayer circuit board as discussed herein, in which a particular internal clearance area of ​​the multilayer circuit board surrounding a selected opening is modified or customized with an enhanced clearance 500″ oriented based on the configuration and orientation of a particular press-fit connector within the board. The schematic diagram of FIG. 5F assumes that the press-fit connector is an action-type press-fit connector oriented as shown in FIG. 5E. In one embodiment, the enhanced clearance 500″ may be an elongated internal clearance area, such as an oval area, or, optionally, a rectangular area. In one embodiment, the elongated clearance area has width, length, and pitch defined by the rules set forth above in connection with FIG. 5B, with some modifications. For action-type connector pins, the location of the enhanced clearance area is angled to utilize the space between adjacent pins. In one embodiment, this angling may be 34 degrees for an interstitial grid pin array, as shown in the example of FIGS. 5F and 5G. Furthermore, in the embodiment of FIG. 5F, for action type connector pins, the improved clearance area may have a geometric radius Rk=0.5W in one embodiment.

[0065] FIG. 5G is a partial cross-sectional plan view of one embodiment of a circuit board assembly layer having an extended clearance area surrounding a selected opening that provides, for example, a power or ground connection to a multilayer circuit board, and FIG. 5H is an enlarged view of one improved internal clearance area for an action-type connector pin as discussed herein.

[0066] 5G and 5H collectively, in one embodiment, a layout may be reviewed by program code to apply enhanced clearance areas to selected openings within the interaction zones of connector pins that will be connected to a multilayer circuit board. In one embodiment, as shown in FIG. 5F, layers of a multilayer circuit board within the expected interaction zone or insertion depth of a press-fit pin may have (at least) voltage-to-ground clearance areas that are modified with enhanced clearance between the conductor materials. As described, the enhanced clearance areas may be specified based on the configuration, size, and orientation of the particular connector pin type that will be received in each opening, with FIGS. 5E-5H illustrating, by way of example only, an action-type connector pin. Other openings, such as opening 520, as shown in Figure 5G, may not require the extended clearance area. For example, in one embodiment, conductive material 501 (Figure 5E) may be a ground plane conductor in a multilayer circuit board, and opening 520 is a plated through hole that is electrically connected to the ground plane material. An opening with improved clearance 500'' may, in one example, be a power-related via that connects different power plane levels in a multilayer circuit board.

[0067] Similar to the expanded clearances of FIGS. 5B-5D, the expanded clearances of FIGS. 5F-5H, in one or more implementations, are aligned with the direction of maximum normal force F directed outward from the opening due to connector pin insertion, which, as shown in FIG. 5E, is along axis 502′ when the action-type pin is oriented as shown. Note that this particular layout assumes that the configuration, size, and orientation of the compliant press-fit pin inserted into a particular opening are known at layout design time. In one embodiment, typical press-fit laminate deformation or cracking is most likely to occur within the expanded clearance regions in the modified layouts of FIGS. 5F-5H. The extended clearance within the most susceptible interaction zone provides improved margin, ensuring that even minor press-fit laminate cracking will not compromise dielectric integrity. This results in more reliable printed circuit board assemblies, especially since sufficient dielectric material continues to exist between non-common power and ground conductors in multilayer circuit boards. By providing a selectively enlarged area of ​​intact dielectric material in the anti-pad area, product reliability and integrity are improved.

[0068] Further details of an embodiment that facilitates processing within a computing environment relating to one or more aspects of the present invention are described below with reference to the embodiment of FIGS.

[0069] As described herein, in one or more aspects, computer-implemented methods, computer systems, and computer program products are provided for facilitating the generation of a multilayer circuit board layout. By way of example, FIG. 6 illustrates one embodiment of such a computer program product according to one or more aspects of the present invention. As shown, in one or more embodiments, the computer program product includes or utilizes a circuit board design tool 175, which includes, for example, program instructions embodied therein. The program instructions are readable by a processing circuit, such as the processing circuitry 120 of the computer 101 of the computing environment 100 of FIG. 1 , to execute a method. The program instructions or program code, in one embodiment, include a circuit board layout module 600 including program code that, when read and executed by the processing circuit, causes the processing circuit to generate a circuit board design layout for a multilayer circuit board being manufactured. In the illustrated embodiment, the circuit board layout module 600 includes a layer identification sub-module 602 for facilitating the identification of layers of the multilayer circuit board having internal clearance areas around openings in the multilayer circuit board that have a modified conductive material voltage-to-ground clearance. 6, circuit board layout module 600 includes a configuration and orientation determination submodule 604 that includes program code for determining a configuration and orientation of connector pins to be press-fit connected within openings in the multilayer circuit board. Circuit board layout module 600 also includes a voltage-to-ground clearance modification submodule 606 that includes program code for modifying a voltage-to-ground clearance of conductive material within an internal clearance area within a layer around the opening based on the determined configuration and orientation of the connector pins to be press-fit connected within the openings in the multilayer circuit board, where the voltage-to-ground clearance is modified in the direction of a maximum normal force directed outward from the opening due to insertion of the connector pin into the opening.In one or more implementations, one or more aspects of circuit board design tool 175, including circuit board layout module 600 and the noted sub-modules, may be implemented in one or more libraries of the circuit board design tool, such as a library of a computer-aided design system. In this regard, it should be noted that in one or more embodiments, the orientation of the pins may be specified as a known attribute in the library, for example, based on the part number of the connector pins. It should also be noted that different components connected to a multilayer circuit board may use different connector pin types, and thereby have different part numbers associated with them, depending on the implementation.

[0070] 7 illustrates one embodiment of a circuit board design layout workflow according to one or more aspects of the present invention. As shown, in one or more implementations, generating 700 a circuit board layout for a circuit board under manufacture includes identifying 702, by a circuit board design tool, layers of the multilayer circuit board having internal clearance areas around an opening in the multilayer circuit board with modified conductive material voltage-to-ground clearances. Generating the circuit board layout further includes determining 704, by the circuit board design tool, a configuration and orientation of connector pins to be press-fit connected into the opening in the multilayer circuit board. Additionally, generating the circuit board layout includes modifying 706, by the circuit board design tool, the conductive material voltage-to-ground clearances in the internal clearance areas of the layers around the opening based on the determined configuration and orientation of the connector pins to be press-fit connected into the opening in the multilayer circuit board, where the voltage-to-ground clearances are modified in the direction of maximum normal force outward from the opening due to insertion of the connector pins into the opening.

[0071] 8, in another example, a computing environment 800 includes, for example, a computer system 802, shown, for example, in the form of a general-purpose computing device. The computer system 802 may include, but is not limited to, one or more processors or processing units 804 (e.g., central processing units (CPUs) and / or special-purpose processors), memory 806 (also known, for example, as system memory, main memory, main storage, central storage, or storage), and one or more input / output (I / O) interfaces 808, coupled together via one or more buses and / or other connections. For example, the processor 804 and memory 806 are coupled to the I / O interface 808 via one or more buses 810, and the processor 804 is coupled together via one or more buses 811.

[0072] Bus 811 may be, for example, a memory bus or cache coherence bus, and bus 810 may represent one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA), MicroChannel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI).

[0073] The memory 806 may include a cache 812, such as, for example, a shared cache, which may be coupled to a local cache 814 of one or more processors 804, for example, via one or more buses 811. Additionally, the memory 806 may include one or more programs or applications 816, at least one operating system 818, and a circuit board design tool 175 that implements and / or is used in accordance with one or more aspects of the present invention, as well as one or more computer-readable program instructions 822. The computer-readable program instructions 822 may be configured to perform the functions of an embodiment of an aspect of the present invention.

[0074] The computer system 802 may communicate with one or more external devices 830, such as, for example, a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 834, via the I / O interface 808. The data storage devices 834 may store one or more programs 836, one or more computer-readable program instructions 838, and / or data, etc. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0075] The computer system 802 may also communicate with a network interface 832 that enables the computer system 802 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), for example, via the I / O interface 808, to provide communication with other computing devices or systems.

[0076] Computer system 802 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, it may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and / or an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical media. It should be understood that other hardware and / or software components may be used in conjunction with computer system 802. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archive storage systems, and the like.

[0077] Computer system 802 is capable of operation with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with computer system 802 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments, including any of the systems or devices described above and the like.

[0078] The computing environment described herein is only one example of a computing environment that may be used. Other environments may be used, including, but not limited to, non-partitioned, partitioned, cloud, distributed, non-distributed, virtual, and / or emulated environments; embodiments are not limited to any one environment. While various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environment provided herein is only one example.

[0079] Further to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider offering to manage a customer environment. For example, a service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from customers, by way of example, under subscription and / or commission agreements. Additionally or alternatively, the service provider may receive payments from sales of advertising content to one or more third parties.

[0080] In one aspect, an application may be deployed to perform one or more embodiments. By way of example, deploying an application includes providing a computer infrastructure operable to perform one or more aspects of one or more embodiments.

[0081] As a further aspect, a computing infrastructure may be deployed that includes computer-readable code integrated into a computing system, where the code combined with the computing system is capable of performing one or more embodiments.

[0082] As a still further aspect, there may be provided a process for integrating a computing infrastructure comprising integrating computer-readable code into a computer system including a computer-readable medium, wherein the computer medium includes one or more embodiments, and the code combined with the computer system is capable of performing one or more embodiments.

[0083] While various embodiments have been described above, these are by way of example only. For example, additional, fewer, and / or other features, constraints, tasks, and / or events may be considered. Many variations are possible.

[0084] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprise" (and any form of comprise, e.g., "comprises" and "comprising"), "have" (and any form of have, e.g., "has" and "having"), "include" (and any form of include, e.g., "includes" and "including"), and "contain" (and any form of contain, e.g., "contains" and "containing") are open-ended linking verbs. Consequently, a method or device that "comprises," "has," "includes," or "contains" one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Similarly, a method step or device element that "comprises," "has," "includes," or "contains" one or more features possesses those one or more features, but is not limited to possessing only those features. Furthermore, a device or structure that is configured in a particular way is configured in at least that way, but may also be configured in ways not listed.

[0085] In the following claims, corresponding structure, material, acts, and equivalents of all means-plus-function or step-plus-function elements are intended to include, when present, any structure, material, or act for performing the function in combination with other claimed elements that are specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described to best explain various aspects and practical applications and to enable others skilled in the art to understand various embodiments with various modifications as suitable for the particular use contemplated.

Claims

1. 1. A method for manufacturing a multilayer circuit board, the method comprising: forming a layer of the multilayer circuit board having an interior clearance area having a ground voltage clearance of modified conductive material adjacent an opening in the multilayer circuit board; a voltage-to-ground clearance of the modified conductive material based on a connector pin configuration press-fit into the opening of the multilayer circuit board, the internal clearance area being enlarged in the direction of maximum normal force directed outward from the opening due to insertion of the connector pin into the opening; method.

2. 2. The method of claim 1, wherein the internal clearance region comprises an elongated clearance region around the opening in the layer, the major axis of the elongated clearance region being oriented based at least in part on a configuration of the connector pin received in the opening to provide improved clearance between the conductive materials in a direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening.

3. 3. The method of claim 2, wherein forming the layer further comprises orienting the major axis of the elongated clearance region based on the configuration and orientation of the connector pin received in the opening so as to provide improved clearance between the conductive materials in the direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening.

4. 3. The method of claim 2, wherein the opening is a power routing related via of the multilayer circuit board, and the extended clearance area defines an improved voltage-to-ground clearance between the power routing related via and a conductor within the layer of the multilayer circuit board.

5. further comprising inserting the connector pins into the openings in the multilayer circuit board to couple a component to the multilayer circuit board; 3. The method of claim 2, wherein the insertion causes deformation of the layers of the multilayer circuit board in the direction of the maximum normal force directed outward from the opening due to insertion of the connector pin into the opening, and the extended clearance area provides the improved clearance between conductive materials in the direction of the maximum normal force directed outward from the opening, reducing the risk of an electrical short occurring based on the deformation due to insertion of the connector pin.

6. 1. A circuit board assembly comprising a multilayer circuit board having one or more openings, the one or more openings are configured to receive one or more connector pins, and the multilayer circuit board is press-fit connectable via the one or more connector pins; the multilayer circuit board includes an internal clearance area within a layer of the multilayer circuit board adjacent an opening of the one or more openings, the internal clearance area having a conductive material voltage-to-ground clearance modified based on a connector pin configuration of each of the one or more connector pins. Circuit board assembly.

7. a component press-fit connected to the multilayer circuit board via the one or more connector pins inserted into the one or more openings; The configuration of each connector pin exhibits a direction of maximum normal force outward from the opening upon insertion of the connector pin therein, and the internal clearance area is at least partially enlarged in the direction of maximum normal force outward from the opening; the internal clearance areas of the layers in the multilayer circuit board adjacent the opening include elongated clearance areas around the opening in the respective layers, the major axes of the elongated clearance areas being oriented based on the configuration of the connector pins to provide improved clearance in the direction of maximum normal force outward from the opening due to insertion of the connector pins; 7. The circuit board assembly of claim 6.

8. 8. The circuit board assembly of claim 7, wherein another of the internal regions includes a circular clearance region around the opening, wherein the offset of the conductive material in the respective layer around the opening is at least partially less, the extended clearance region being within a zone of interaction between the connector pin and the opening upon insertion of the connector pin into the opening, and the another internal region being outside the zone of interaction between the connector pin and the opening.

9. 8. The circuit board assembly of claim 7, wherein the connector pin is one of a plurality of different connector pin types, the different connector pin types including a plurality of compliant press-fit pin types, and the direction of the maximum normal force directed outward from the opening due to insertion of the connector pin differs among the different connector pin types.

10. 10. The circuit board assembly of claim 9, wherein the plurality of compliant press-fit pin types include a pin-eye press-fit pin type and an action press-fit pin type.

11. 1. A computer-implemented method for generating a multilayer circuit board layout, the computer-implemented method comprising: generating a circuit board layout for the multilayer circuit board being manufactured using a circuit board design tool; wherein the generating step comprises: identifying, with the circuit board design tool, a layer of the multilayer circuit board having an internal clearance area around an opening in the multilayer circuit board having a modified conductive material voltage-to-ground clearance; determining, with the circuit board design tool, a configuration and orientation of connector pins to be press-fit connected within the openings of the multilayer circuit board; and modifying, with the circuit board design tool, a voltage-to-ground clearance of the conductive material in the internal clearance area of ​​the layer around the opening based on the determined configuration and orientation of the connector pins press-fit into the opening of the multilayer circuit board; wherein the ground voltage clearance is modified in the direction of maximum normal force outward from the opening due to insertion of the connector pin into the opening. Computer-implemented methods.

12. 12. The computer-implemented method of claim 11, wherein the modifying step includes stretching the internal clearance area around the opening in the layer, wherein a major axis of the stretched clearance area is oriented based at least in part on a configuration of the connector pin received in the opening to provide improved clearance between the conductive material in a direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening.

13. 13. The computer-implemented method of claim 12, wherein the modifying step further comprises orienting the major axis of the extended clearance region based on the configuration and orientation of the connector pin received in the opening to provide improved clearance between the conductive materials in the direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening.

14. 12. The computer-implemented method of claim 11, wherein the identifying step includes determining that the layer of the multilayer circuit board is within a zone of connector pin and opening interaction upon insertion of the connector pin into the opening.

15. 12. The computer-implemented method of claim 11, further comprising: commencing manufacturing of the multilayer circuit board using the circuit board layout with the modified voltage-to-ground clearance of the conductive material in the interior region of the layer around the opening.

16. 1. A computer system for facilitating the generation of a multilayer circuit board layout, the computer system comprising: Memory and at least one processor in communication with the memory; The computer system is configured to perform a method, the method comprising: generating a circuit board layout for the multilayer circuit board being manufactured via a circuit board design tool; and the generating step comprises: identifying, with the circuit board design tool, a layer of the multilayer circuit board having an internal clearance area around an opening in the multilayer circuit board having a modified conductive material voltage-to-ground clearance; determining, with the circuit board design tool, a configuration and orientation of connector pins to be press-fit connected within the openings of the multilayer circuit board; and modifying, with the circuit board design tool, a voltage-to-ground clearance of the conductive material in the internal clearance area of ​​the layer around the opening based on the determined configuration and orientation of the connector pins press-fit into the opening of the multilayer circuit board; wherein the ground voltage clearance is modified in the direction of maximum normal force outward from the opening due to insertion of the connector pin into the opening. Computer system.

17. 17. The computer system of claim 16, wherein the modifying step includes stretching the internal clearance area around the opening in the layer, wherein a major axis of the stretched clearance area is oriented based at least in part on a configuration of the connector pin received in the opening to provide improved clearance between the conductive material in a direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening.

18. 18. The computer system of claim 17, wherein the modifying step further comprises orienting the major axis of the extended clearance region based on the configuration and orientation of the connector pin received in the opening to provide improved clearance between the conductive materials in the direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening.

19. 17. The computer system of claim 16, wherein the identifying step includes determining that the layer of the multilayer circuit board is within a zone of connector pin and opening interaction upon insertion of the connector pin into the opening.

20. 17. The computer system of claim 16, further comprising: commencing manufacturing of the multilayer circuit board using the circuit board layout with the modified voltage-to-ground clearance of the conductive material in the interior region of the layer around the opening.

21. 1. A computer program product for facilitating the generation of a multilayer circuit board layout, the computer program product comprising: one or more computer-readable storage media and program instructions embodied therewith; The program instructions are readable by a processing circuit to cause the processing circuit to perform a method, the method comprising generating, via a circuit board design tool, a circuit board layout for a multilayer circuit board being manufactured. and the generating step comprises: identifying, with the circuit board design tool, a layer of the multilayer circuit board having an internal clearance area around an opening in the multilayer circuit board having a modified conductive material voltage-to-ground clearance; determining, with the circuit board design tool, a configuration and orientation of connector pins to be press-fit connected within the openings of the multilayer circuit board; and modifying, with the circuit board design tool, a voltage-to-ground clearance of the conductive material in the internal clearance area of ​​the layer around the opening based on the determined configuration and orientation of the connector pins press-fit into the opening of the multilayer circuit board; wherein the ground voltage clearance is modified in the direction of maximum normal force outward from the opening due to insertion of the connector pin into the opening. Computer program products.

22. 22. The computer program product of claim 21, wherein the modifying step includes stretching the interior clearance area around the opening in the layer, a major axis of the stretched clearance area being oriented based at least in part on a configuration of the connector pin received in the opening to provide improved clearance between the conductive material in a direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening.

23. 23. The computer program product of claim 22, wherein the modifying step further comprises orienting the major axis of the extended clearance region based on the configuration and orientation of the connector pin received in the opening to provide improved clearance between the conductive materials in the direction of the maximum normal force outward from the opening due to insertion of the connector pin into the opening.

24. 22. The computer program product of claim 21, wherein the identifying step includes determining that the layer of the multilayer circuit board is within a zone of connector pin and opening interaction upon insertion of the connector pin into the opening.

25. 22. The computer program product of claim 21, further comprising: commencing manufacturing of the multilayer circuit board using the circuit board layout with the modified conductive material voltage-to-ground clearance in the interior region of the layer around the opening.

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