Back contact battery and its manufacturing method, solar module

Abstract

This application relates to the technical field of photovoltaic power generation, and specifically discloses a back-contact cell, a manufacturing method thereof, and a solar module. The back-contact cell includes a semiconductor substrate having opposing first and second textured surfaces, and a tunnel passivation layer and an N-type doped polysilicon layer sequentially stacked on a portion of the second surface in a thickness direction of the semiconductor substrate, wherein the thickness ratio of a portion of the N-type doped polysilicon layer located in an edge region of the second surface to a portion of the N-type doped polysilicon layer located in a central region of the second surface is 1 to 1.2.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application bearing application number 202310702158.2 and entitled "Back-contact battery and manufacturing method thereof, solar module," filed with the China Patent Office on June 13, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of photovoltaics, and in particular to back-contact cells and their manufacturing methods, and solar modules. [Background technology]

[0003] A tunnel passivation back-contact solar cell is a solar cell with a tunnel passivation contact structure, in which both the positive and negative electrodes are located on the back surface of the cell, and there is no shielding by a metal electrode on the front surface. Passivation back-contact solar cells have attracted widespread attention in the academic and industrial photovoltaic fields due to their advantages such as a large light absorption area and a low back surface recombination rate of carriers, and have become a major development trend in high-efficiency solar cell technology.

[0004] However, in the tunnel passivation back contact solar cell formed by the related manufacturing method, the N-type doped polycrystalline silicon layer containing phosphorus as a doping element has a poor morphology, which results in poor performance of the tunnel passivation back contact solar cell. Summary of the Invention

[0005] The present application aims to provide a back contact battery, a manufacturing method thereof, and a solar module.

[0006] Specifically, the present application relates to the following aspects: In a first aspect, the present application discloses a back-contact cell including a semiconductor substrate having opposing first and second surfaces each having a textured structure, and a tunnel passivation layer and an N-type doped polysilicon layer sequentially stacked in a thickness direction of the semiconductor substrate on a portion of the second surface, wherein a thickness ratio of a portion of the N-type doped polysilicon layer located in an edge region of the second surface to a portion of the N-type doped polysilicon layer located in a central region of the second surface is 1 or more and 1.2 or less.

[0007] When the above technical solution is adopted, the tunnel passivation contact structure, which can be composed of the tunnel passivation layer and the N-type doped polysilicon layer, can achieve excellent interface passivation and carrier-selective collection, thereby facilitating the improvement of the photoelectric conversion efficiency of back-contact cells. Furthermore, while the thickness ratio between the edge and central portions of the N-type doped polysilicon layer in the related art is greater than 1.3, the thickness ratio between the portion of the N-type doped polysilicon layer located at the edge region of the second surface and the portion of the N-type doped polysilicon layer located at the central region of the second surface in the present application is greater than 1 and less than 1.2, thereby reducing the difference in thickness between the edge and central portions of the N-type doped polysilicon layer. In actual manufacturing processes, the tunnel passivation material layer and the intrinsic amorphous silicon material layer used to manufacture the tunnel passivation layer and the N-type doped polysilicon layer are typically formed by processes such as chemical vapor deposition. Based on this, when the difference in thickness between the edge portions and the central portion of the N-type doped polycrystalline silicon layer is small, the difference in thickness between the edge portions and the central portion of the intrinsic amorphous silicon material layer forming the N-type doped polycrystalline silicon layer is also small. Because each portion of the intrinsic amorphous silicon material layer in a direction parallel to the second surface is formed simultaneously, and the stoichiometric ratios of the intrinsic amorphous silicon material located in the edge regions of the second surface and the intrinsic amorphous silicon material located in the central region of the second surface are approximately the same, when the difference in thickness between the edge portions and the central portion of the intrinsic amorphous silicon material layer is small, the difference in structural compactness between the edge portions and the central portion of the intrinsic amorphous silicon material layer is small.Accordingly, when the intrinsic amorphous silicon material layer is subjected to phosphorus diffusion treatment, the phosphosilicate glass layer obtained by the reaction between the silicon in the intrinsic amorphous silicon material layer and oxygen in the diffusion environment has a small difference in density between the edge portion and the center portion, so that the edge portion of the phosphosilicate glass layer has almost the same high corrosion resistance as the center portion. During the texturing treatment of at least the first surface of the semiconductor substrate, the phosphosilicate glass layer can well protect the portion of the underlying N-type doped polycrystalline silicon material layer where the N-type doped polycrystalline silicon layer will be formed, so that the morphology and formation area of ​​the obtained N-type doped polycrystalline silicon layer can meet the target requirements, which is beneficial for carrier collection and reducing reverse leakage, and further facilitates improving the photoelectric conversion efficiency of back-contact cells.

[0008] In a possible realization, the size uniformity of the texture structures in each region of said first surface is 85% or more and less than 100%.

[0009] When the above technical solution is adopted, the size uniformity of the textured surface structure in each region of the first surface is high, which helps each region of the first surface to have high light transmittance and allows more light to penetrate into the semiconductor substrate through the first surface, further improving the photoelectric conversion efficiency of the back-contact cell.

[0010] In a possible implementation, the area of ​​the second surface where the tunnel passivation layer and the N-type doped polycrystalline silicon layer are not deposited is polished or has a textured structure.

[0011] In a possible implementation, the thickness of the portion of the N-type doped polycrystalline silicon layer located in the edge region of the second surface is 175 nm to 225 nm.

[0012] The above technical solution, by ensuring that the thickness of the portion of the N-type doped polysilicon layer located at the edge region of the second surface is within the above range, can prevent the overall thickness of the N-type doped polysilicon layer from being small and not meeting the target requirements due to a small thickness value, and can prevent difficulties in manufacturing an N-type doped polysilicon layer with high thickness uniformity, which is beneficial for obtaining a back-contact battery. It also prevents the corrosion resistance of the phosphosilicate glass layer located at the edge portion of the N-type doped polysilicon material layer from being reduced after the phosphorus diffusion process due to a large thickness value. During the texturing process, the phosphosilicate glass layer can effectively protect the portions of the N-type doped polysilicon material layer where the N-type doped polysilicon layer will be formed, ensuring that the N-type doped polysilicon layer has a good morphology and a formation range that meets the target requirements.

[0013] In a possible embodiment, the thickness of the portion of the N-type doped polycrystalline silicon layer located in the central region of the second surface is 150 nm or more and 200 nm or less.

[0014] In a possible implementation, the average doping concentration of impurities in the N-type doped polycrystalline silicon layer is 3.5×10 20 / cm 3 Over 4.0 x 10 20 / cm 3 The following is the result.

[0015] When the above technical solution is adopted, the average doping concentration of impurities in the N-type doped polycrystalline silicon layer is within the above range, so that the N-type doped polycrystalline silicon layer has excellent carrier selective collection function and does not affect the contact resistance between the N-type doped polycrystalline silicon layer and the negative electrode. 20 / cm 3In the present application, the doping concentration of impurities in the N-type doped polycrystalline silicon layer can be appropriately reduced compared to the N-type doped polycrystalline silicon layer (larger than the N-type doped polycrystalline silicon layer). Accordingly, the average doping concentration of impurities in the N-type doped polycrystalline silicon material layer for fabricating the N-type doped polycrystalline silicon layer is also low. Based on this, in the actual manufacturing process, after the phosphorus diffusion process, the average doping concentration of impurities in the N-type doped polycrystalline silicon material layer is proportional to the average doping concentration of impurities in the phosphosilicate glass layer formed thereon. Therefore, appropriately reducing the doping concentration of impurities in the N-type doped polycrystalline silicon layer means that the average doping concentration of impurities (including phosphorus) in the phosphosilicate glass layer is also reduced. In this case, since the phosphorus doping concentration in the phosphosilicate glass layer is inversely proportional to its own corrosion resistance, appropriately reducing the phosphorus doping concentration in the phosphosilicate glass layer can improve its own corrosion resistance and further ensure that the N-type doped polycrystalline silicon layer has good morphology and a formation range that meets the target requirements.

[0016] In a second aspect, the present application further discloses a solar module including a back-contact cell as provided in the first aspect and its various implementations.

[0017] The beneficial effects of the second aspect of the present application can be referred to the analysis of the beneficial effects of the first aspect and its various implementation forms, and a description thereof will be omitted here.

[0018] In a third aspect, the present application further discloses a method for manufacturing a back-contact battery, including the following steps: First, a semiconductor substrate having a first surface and a second surface facing each other is prepared. Next, a tunnel passivation material layer and an intrinsic amorphous silicon material layer are sequentially formed on the second surface side of the semiconductor substrate in a thickness direction of the semiconductor substrate. Subsequently, a phosphorus diffusion process is performed on the intrinsic amorphous silicon material layer to convert the intrinsic amorphous silicon material layer into an N-type doped polycrystalline silicon material layer, and a phosphosilicate glass layer is formed on the N-type doped polycrystalline silicon material layer. The thickness ratio of a portion of the N-type doped polycrystalline silicon material layer located in an edge region of the second surface to a portion located in a central region of the second surface is 1 or more and 1.2 or less. Next, a texturing process is performed on the first surface of the semiconductor substrate using the phosphosilicate glass layer as a mask, thereby forming a textured structure on the first surface. Then, the phosphosilicate glass layer, the stacked tunnel passivation material layer, and the stacked N-type doped polycrystalline silicon material layer are patterned to form a stacked tunnel passivation layer and an N-type doped polycrystalline silicon layer in a partial region of the second surface, and then the remaining phosphosilicate glass layer is removed.

[0019] The beneficial effects of the third aspect of the present application can be referred to the analysis of the beneficial effects of the first aspect and its various implementation forms, and a description thereof will be omitted here.

[0020] In a possible implementation, the atmospheric pressure when forming the intrinsic amorphous silicon material layer is 100 mTorr or more and 150 mTorr or less.

[0021] When the above technical solution is adopted, in the actual manufacturing process of the intrinsic amorphous silicon material layer, reducing the atmospheric pressure within a certain range can improve the molecular free path, allowing reactive molecular groups to reach each region of the surface of the tunnel passivation material layer more quickly without agglomerating in the same location. Therefore, by maintaining the atmospheric pressure within the above range during the formation of the intrinsic amorphous silicon material layer, it is possible to prevent the thickness of the edge portion of the intrinsic amorphous silicon material layer from increasing due to high atmospheric pressure, ensure that the thickness difference between the edge portion and the center portion of the intrinsic amorphous silicon material layer is small, and ensure that the structure of the edge portion of the intrinsic amorphous silicon material layer is as dense as the structure of its center portion. Furthermore, each portion of the phosphosilicate glass layer formed after the phosphorus diffusion treatment in the direction parallel to the second surface has high corrosion resistance, and ensure that the shape and formation area of ​​the formed N-type doped polycrystalline silicon layer meet the target requirements. It also prevents a decrease in process efficiency due to low atmospheric pressure.

[0022] In a possible implementation, the gas flow rate when forming the intrinsic amorphous silicon material layer is 0.9 slm or more and 1.2 slm or less.

[0023] The above technical solution, when used in the actual manufacturing process of an intrinsic amorphous silicon layer, can reduce the total gas flow rate in the diffusion device by reducing the gas flow rate within a certain range, thereby reducing the degree of perturbation caused by the air flow in the diffusion device, which helps optimize the deposition quality of the portion located in the edge region of the second surface of the intrinsic amorphous silicon layer, ensuring that the structure of the edge portion of the intrinsic amorphous silicon layer is as dense as the structure of its central portion, and further ensuring that each portion of the phosphosilicate glass layer formed after the phosphorus diffusion process in the direction parallel to the second surface has high corrosion resistance, ensuring that the shape and formation area of ​​the formed N-type doped polycrystalline silicon layer meet the target requirements, and also preventing a decrease in process efficiency due to a low gas flow rate.

[0024] In a possible implementation, after the phosphorus diffusion process on the intrinsic amorphous silicon material layer, only the phosphosilicate glass layer is patterned so that remaining portions of the phosphosilicate glass layer are formed in some areas of the N-type doped polycrystalline silicon material layer before the first side of the semiconductor substrate is textured under the masking effect of the phosphosilicate glass layer, in which case the deposited tunnel passivation material layer and the N-type doped polycrystalline silicon material layer are patterned simultaneously with the texturing process on the first side of the semiconductor substrate under the masking effect of the phosphosilicate glass layer.

[0025] When the above technical solution is adopted, the phosphosilicate glass layer located on the second surface side is patterned before the texturing process. This not only allows the texturing etchant to make at least the first surface into a textured surface in the subsequent texturing process, but also allows the N-type doped polycrystalline silicon material layer to be patterned under the masking effect of the remaining part of the phosphosilicate glass layer to obtain an N-type doped polycrystalline silicon layer, thereby ensuring that the morphology and formation area of ​​the N-type doped polycrystalline silicon layer meet the target requirements, and improving the process efficiency of back-contact batteries.

[0026] In one possible embodiment, an intrinsic amorphous silicon material layer is formed on the second surface side of the semiconductor substrate in the thickness direction of the semiconductor substrate, while a wraparound amorphous silicon layer is formed on the side surface of the semiconductor substrate and a portion of the first surface. The width of the formation region of the wraparound amorphous silicon layer on the first surface is greater than or equal to 0 mm and less than 10 mm. The width direction of the formation region is parallel to the radial direction of the semiconductor substrate. Furthermore, after a phosphorus diffusion process, the wraparound amorphous silicon layer becomes a wraparound doped layer, and a wraparound phosphosilicate glass layer is formed on the wraparound doped layer. In the above case, after performing the phosphorus diffusion process on the intrinsic amorphous silicon material layer and before performing a texturing process on the first surface of the semiconductor substrate under the masking effect of the phosphosilicate glass layer, the method for manufacturing a back-contact cell further includes removing the wraparound phosphosilicate glass layer and the wraparound doped layer.

[0027] When the above technical solution is adopted, the wraparound phosphosilicate glass layer and the wraparound doped layer must be sequentially removed before texturing. The etchant used to remove the wraparound doped layer also affects the surface of the portion of the first surface of the semiconductor substrate covered with the wraparound doped layer, resulting in the formation of a porous structure on that surface. However, the surface of the central region of the first surface of the semiconductor substrate that is not covered with the wraparound doped layer remains flat. As a result, after the subsequent texturing process, the sizes of the textured structures located in the edge and central regions of the first surface will not be consistent, which will further affect the light trapping effect of the first surface. In this case, compared to the width of the wraparound doped layer formed on the first surface in the related art, which is greater than 10 mm during the fabrication of back-contact cells, when the width of the wraparound amorphous silicon layer formed on the first surface in the present application is between 0 and 10 mm, the wraparound width is small, which helps to improve the size uniformity of the textured structures located in each region of the first surface, which in turn helps to improve the light trapping effect of the first surface and further improve the photoelectric conversion efficiency of the back-contact cell.

[0028] In a possible realization, the thickness of the phosphosilicate glass layer is between 60 nm and 65 nm.

[0029] The above technical solution ensures that the thickness of the phosphosilicate glass layer is within the above range, thereby preventing the corrosion resistance of the phosphosilicate glass layer from being reduced due to a small thickness, ensuring that the morphology and area of ​​the formed N-type doped polycrystalline silicon layer meet the target requirements, and preventing the consumption of consumables for manufacturing the intrinsic amorphous silicon material layer and the phosphosilicate glass layer from being increased due to a large thickness of the phosphosilicate glass layer, thereby helping to reduce the manufacturing costs of back-contact batteries.

[0030] In a possible implementation, the average thickness of the intrinsic amorphous silicon material layer is H1, the average thickness of the phosphosilicate glass layer is H2, and the average thickness of the N-type doped polycrystalline silicon material layer is H3.

[0031] When the above technical solution is adopted, as mentioned above, it is necessary to consume silicon elements in the N-type doped polycrystalline silicon material layer to form the phosphosilicate glass layer. Based on this, if the average thicknesses of the intrinsic amorphous silicon material layer, the phosphosilicate glass layer and the N-type doped polycrystalline silicon material layer satisfy the above conditions, it indicates that the formed thickness of the intrinsic amorphous silicon material layer is appropriate, and the density of each region in the direction parallel to the second surface of the intrinsic amorphous silicon material layer and the uniformity of the structure are all high. After the phosphosilicate glass layer is formed, the consumed thickness of the N-type doped polycrystalline silicon material layer meets the theoretical consumption of a highly dense N-type doped polycrystalline silicon material layer (i.e., the thickness of the phosphosilicate glass layer is approximately equal to half the thickness reduction amount of the N-type doped polycrystalline silicon material layer) or is small compared to the theoretical consumption amount, which further indicates that the formed quality of the phosphosilicate glass layer after optimization is high, and the formed N-type doped polycrystalline silicon layer has a good morphology and a formation range that meets the target requirements.

[0032] In a possible implementation, the process conditions for the phosphorus diffusion process are: The temperature of the deposition process is 850°C or higher and 900°C or lower, and / or the atmospheric pressure of the deposition process is 150 mbar or higher and 200 mbar or lower, and / or the phosphorus source pressure of the deposition process is 250 mbar or higher and 450 mbar or lower, and / or the nitrogen flow rate of the deposition process is 1500 sccm or higher and 2000 sccm or lower, and / or the oxygen flow rate of the deposition process is 750 sccm or higher and 1000 sccm or lower, and / or the temperature of the post-oxidation process is 850°C or higher and 900°C or lower, and / or the oxygen flow rate of the post-oxidation process is 5000 sccm or higher and 10000 sccm or lower.

[0033] ​When the above technical solution is adopted, in actual manufacturing, the average doping concentration of impurities in the formed phosphosilicate glass layer and the N-type doped polycrystalline silicon material can be adjusted by changing the deposition temperature, deposition atmosphere pressure, phosphorus source pressure, nitrogen flow rate, and oxygen flow rate during the phosphorus diffusion process. Based on this, when at least one of the deposition temperature, deposition atmosphere pressure, phosphorus source pressure, nitrogen flow rate, and oxygen flow rate is within the corresponding range, the average doping concentration of phosphorus in the phosphosilicate glass layer can be appropriately reduced, resulting in the phosphosilicate glass layer with high corrosion resistance. Furthermore, the N-type doped polycrystalline silicon layer formed based on the N-type doped polycrystalline silicon material layer can have a good morphology and a formation range that meets the target requirements. Furthermore, the thickness of the formed phosphosilicate glass layer can be adjusted by changing the post-oxidation temperature and post-oxidation oxygen flow rate during the phosphorus diffusion process. Based on this, when at least one of the post-oxidation temperature and post-oxidation oxygen flow rate is within the corresponding range, the formed thickness of the phosphosilicate glass layer can be appropriately increased, resulting in improved corrosion resistance of the phosphosilicate glass layer.

[0034] The above has outlined the technical solution of the present application. In order to make the technical solution of the present application more clearly understood and implemented according to the content of the specification, and to make the above and other objectives, features and advantages of the present application more comprehensible, specific examples of the present application are specifically given below. [Brief explanation of the drawings]

[0035] In order to more clearly describe the technical solutions in the embodiments of the present application or related technologies, the following will briefly describe the drawings used in the description of the embodiments or related technologies. Of course, the drawings described below are part of the embodiments of the present application, and those skilled in the art can conceive of other drawings based on these drawings without any creative efforts. [Figure 1]1 is a longitudinal cross-sectional view of a back-contact battery structure provided in an embodiment of the present application. [Figure 2] 1 is a SEM schematic view of a portion located in an edge region of a second surface of an N-type doped polycrystalline silicon layer formed in a related art; [Figure 3] FIG. 2 is a SEM schematic diagram of a portion located in an edge region of a second surface of an N-type doped polycrystalline silicon layer in an example of the present application. [Figure 4] 1 is a longitudinal cross-sectional view (part 1) of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process. [Figure 5] FIG. 2 is a longitudinal cross-sectional view (part 2) of the back-contact battery structure during the manufacturing process provided in the examples of the present application. [Figure 6] FIG. 3 is a longitudinal cross-sectional view (part 3) of the back-contact battery structure during the manufacturing process provided in the examples of the present application. [Figure 7] FIG. 4 is a schematic longitudinal cross-sectional view (part 4) of the structure of the back-contact battery provided in the examples of the present application during the manufacturing process. [Figure 8] FIG. 5 is a schematic longitudinal cross-sectional view of the back-contact battery structure in the manufacturing process provided in the examples of the present application (part 5). [Figure 9] FIG. 6 is a longitudinal cross-sectional view (part 6) of the back-contact battery structure during the manufacturing process provided in the examples of the present application. [Figure 10] FIG. 7 is a schematic longitudinal cross-sectional view of the back-contact battery structure during the manufacturing process provided in the examples of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0036] In order to clarify the objectives, technical solutions and advantages of the embodiments of the present application, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application, and it should be understood that the described embodiments are only a part of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, all other embodiments that can be obtained by those skilled in the art without any creative efforts fall within the scope of protection of the present application.

[0037] A tunnel passivation back-contact solar cell is a solar cell with a tunnel passivation contact structure, in which both the positive and negative electrodes are located on the back surface of the cell, and there is no shielding by a metal electrode on the front surface. Due to its advantages such as a large light absorption area and a low back surface recombination rate, tunnel passivation back-contact solar cells have attracted widespread attention in the academic and industrial photovoltaic fields, and have become a major development trend in high-efficiency solar cell technology.

[0038] Specifically, a tunnel passivation back-contact solar cell in the related art typically includes at least a semiconductor substrate, a tunnel passivation layer, and an N-type doped polycrystalline silicon layer, which are sequentially stacked on a portion of the non-light-receiving surface of the semiconductor substrate in the thickness direction of the semiconductor substrate. In this case, during the actual manufacturing process of the tunnel passivation back-contact solar cell, a tunnel passivation material layer and an intrinsic amorphous silicon material layer are sequentially formed to entirely cover the non-light-receiving surface of the semiconductor substrate. After that, a phosphorus diffusion process is performed on the intrinsic amorphous silicon material layer to convert the intrinsic amorphous silicon material layer into an N-type doped polycrystalline silicon material layer, and a phosphosilicate glass layer is formed on the N-type doped polycrystalline silicon material layer. Next, a texturing process is performed on at least the light-receiving surface of the semiconductor substrate using the phosphosilicate glass layer as a mask, thereby forming a textured surface on at least the light-receiving surface. This allows more light to penetrate into the semiconductor substrate through the light-receiving surface, thereby facilitating the improvement of the photoelectric conversion efficiency of the tunnel passivation back-contact solar cell. In addition, the phosphosilicate glass layer formed by the phosphorus diffusion process can be used as a mask layer to protect the N-type doped polycrystalline silicon layer, eliminating the need to form another mask layer to protect the N-type doped polycrystalline silicon layer. This simplifies the process steps for tunnel passivation back contact solar cells and improves process efficiency.

[0039] However, the intrinsic amorphous silicon material layer formed by the related manufacturing method has a large thickness at its edge portions and a small thickness at its central portion, and the thickness difference between the edge portions and the central portion of the intrinsic amorphous silicon material layer is large (the thickness ratio between the two is usually greater than 1.3). In this case, each portion of the intrinsic amorphous silicon material layer in the direction parallel to the non-light-receiving surface is formed simultaneously, and the stoichiometric ratio of the intrinsic amorphous silicon material located in the edge region of the non-light-receiving surface and the intrinsic amorphous silicon material located in the central region of the non-light-receiving surface is approximately the same, so when the thickness difference between the edge portions and the central portion of the intrinsic amorphous silicon material layer becomes large, the structure of the edge portions of the intrinsic amorphous silicon material layer becomes more sparse. During the phosphorus diffusion process, the formation of the phosphosilicate glass layer is achieved by consuming silicon elements in the intrinsic amorphous silicon material layer and reacting with oxygen in the diffusion environment. Therefore, when the structure of the edge portion of the intrinsic amorphous silicon material layer becomes more sparse, the formation quality of the phosphosilicate glass layer located at the edge portion of the intrinsic amorphous silicon material layer also deteriorates, and the corrosion resistance of the phosphosilicate glass layer in this portion decreases. As a result, the phosphosilicate glass layer is less able to effectively protect the underlying N-type doped polycrystalline silicon material layer during the texturing process. Furthermore, the morphology of the N-type doped polycrystalline silicon layer formed based on the N-type doped polycrystalline silicon material layer becomes poor, and the formation area of ​​the edge region becomes small, which is unfavorable for carrier collection and deteriorates the operating performance of the tunnel passivation back contact solar cell.

[0040] To solve the above technical problems, in a first aspect, an embodiment of the present application provides a back-contact battery. As shown in Figure 1, the back-contact battery includes a semiconductor substrate 11 having a first surface and a second surface, each having a textured structure, and a tunnel passivation layer 20 and an N-type doped polycrystalline silicon layer 21, which are sequentially stacked in a partial region of the second surface in the thickness direction of the semiconductor substrate 11. The doping element in the N-type doped polycrystalline silicon layer 21 includes phosphorus, and the thickness ratio of the portion of the N-type doped polycrystalline silicon layer 21 located in the edge region of the second surface to the portion of the N-type doped polycrystalline silicon layer 21 located in the central region of the second surface is 1 to 1.2.

[0041] It should be noted that when the first surface of the semiconductor substrate 11 is a light-receiving surface, the second surface is a non-light-receiving surface. When the first surface of the semiconductor substrate 11 is a non-light-receiving surface, the second surface is a light-receiving surface. However, the present application does not specifically limit this. In the following description, an example will be given in which the first surface of the semiconductor substrate 11 is a light-receiving surface and the second surface is a non-light-receiving surface.

[0042] Specifically, in terms of material, the material of the semiconductor substrate may be a semiconductor material such as silicon, germanium silicon, germanium, etc. In terms of conductivity type, the semiconductor substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate.

[0043] From the structural point of view, the specific structure of the semiconductor substrate can be determined based on the conductivity type of the semiconductor substrate and the actual application scenario.

[0044] For example, if the semiconductor substrate is a P-type semiconductor substrate, the non-light-receiving surface of the semiconductor substrate has P-type regions that are alternately spaced apart from stacked tunnel passivation layers and N-type doped polycrystalline silicon layers in a direction parallel to the non-light-receiving surface. In this case, the P-type regions are the back surface field of the back-contact cell. That is, the back surface field in the back-contact cell provided in the embodiments of the present application is a region included in the P-type semiconductor substrate, eliminating the need for an additional doping process to form the back surface field, simplifying the back-contact cell process and improving process efficiency. In addition, this prevents problems such as a short minority carrier lifetime in the semiconductor substrate and difficulty in removing edge PN junctions, which are caused by the need for two high-temperature doping processes, N-type and P-type, on the non-light-receiving surface, thereby improving the yield of back-contact cells.

[0045] Of course, if the semiconductor substrate is a P-type semiconductor substrate, a P-type doped region may be formed in a portion of the non-light-receiving surface of the semiconductor substrate, and the P-type doped region and the stacked tunnel passivation layer and N-type doped polycrystalline silicon layer are alternately distributed and spaced apart in a direction parallel to the non-light-receiving surface.

[0046] For example, when the semiconductor substrate is an N-type semiconductor substrate, a P-type doped region is formed in or on a portion of the non-light-receiving surface of the semiconductor substrate, and the P-type doped region and the stacked tunnel passivation layer and N-type doped polycrystalline silicon layer are alternately distributed and spaced apart in a direction parallel to the non-light-receiving surface.

[0047] In terms of morphology, the light-receiving surface of the semiconductor substrate is a textured surface. The side surfaces of the semiconductor substrate may be polished or textured. The surface of the non-light-receiving surface of the semiconductor substrate in the region not covered with the stacked tunnel passivation layer and N-type doped polycrystalline silicon layer may be textured or polished.

[0048] The material and thickness of the tunnel passivation layer can be set according to actual needs, and are not specifically limited herein. For example, the material of the tunnel passivation layer can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride.

[0049] With regard to the N-type doped polycrystalline silicon layer, the thickness ratio between the portion of the N-type doped polycrystalline silicon layer located in the edge region of the non-light-receiving surface and the portion of the N-type doped polycrystalline silicon layer located in the central region of the non-light-receiving surface may be any value between 1 and 1.2. For example, the thickness ratio between the portion of the N-type doped polycrystalline silicon layer located in the edge region of the non-light-receiving surface and the portion of the N-type doped polycrystalline silicon layer located in the central region of the non-light-receiving surface may be 1, 1.12, 1.14, 1.16, 1.18, 1.2, or the like.

[0050] When the above technical solution is adopted, the tunnel passivation contact structure, which can be composed of the tunnel passivation layer and the N-type doped polycrystalline silicon layer, can achieve excellent interface passivation and carrier-selective collection, facilitating the improvement of the photoelectric conversion efficiency of back-contact cells. Furthermore, while the thickness ratio between the edge and central portions of the N-type doped polycrystalline silicon layer (see FIG. 2) in the related art is greater than 1.3, the thickness ratio between the portion of the N-type doped polycrystalline silicon layer located in the edge region of the non-light-receiving surface and the portion of the N-type doped polycrystalline silicon layer located in the central region of the non-light-receiving surface in the embodiment of the present application is greater than 1 and less than 1.2. As shown in FIG. 1, in this case, the difference in thickness between the edge and central portions of the N-type doped polycrystalline silicon layer 21 is small. In this case, in an actual manufacturing process, as shown in FIG. 4, the tunnel passivation material layer 12 and the intrinsic amorphous silicon material layer 13 for manufacturing the tunnel passivation layer and the N-type doped polycrystalline silicon layer are typically formed by a process such as chemical vapor deposition. Based on this, when the difference in thickness between the edge and central portions of the N-type doped polycrystalline silicon layer is small, the difference in thickness between the edge and central portions of the intrinsic amorphous silicon material layer 13 forming the N-type doped polycrystalline silicon layer is also small. Because the portions of the intrinsic amorphous silicon material layer 13 parallel to the non-light-receiving surface are formed simultaneously, and the stoichiometric ratios of the intrinsic amorphous silicon material located in the edge regions of the non-light-receiving surface and the intrinsic amorphous silicon material located in the central region of the non-light-receiving surface are approximately the same, when the difference in thickness between the edge and central portions of the intrinsic amorphous silicon material layer 13 is small, the difference in structural density between the edge and central portions of the intrinsic amorphous silicon material layer 13 is small (see FIG. 3).Accordingly, as shown in FIG. 5, when the intrinsic amorphous silicon material layer 13 is subjected to phosphorus diffusion treatment, the phosphosilicate glass layer 16 obtained by the reaction between the silicon in the intrinsic amorphous silicon material layer 13 and oxygen in the diffusion environment has a small difference in density between the edge portion and the center portion, so that the edge portion of the phosphosilicate glass layer 16 has almost the same high corrosion resistance as the center portion. During the texturing treatment of at least the light-receiving surface of the semiconductor substrate 11, the phosphosilicate glass layer 16 can well protect the underlying portion of the N-type doped polycrystalline silicon material layer 15 where the N-type doped polycrystalline silicon layer 21 will be formed (see FIGS. 7 and 8), so that the shape and formation area of ​​the obtained N-type doped polycrystalline silicon layer 21 can meet the target requirements, which is beneficial for carrier collection and reducing reverse leakage, and further facilitates improving the photoelectric conversion efficiency of back-contact cells.

[0051] As can be seen from the above, the thickness ratio between the edge region of the N-type doped polysilicon layer on the non-light-receiving surface and the central region of the N-type doped polysilicon layer on the non-light-receiving surface affects the corrosion resistance of the phosphosilicate glass layer formed after the phosphorus diffusion treatment, and also affects its shape and the area of ​​its non-light-receiving surface. Based on this, the specific thickness of each portion of the N-type doped polysilicon layer in the direction parallel to the non-light-receiving surface can be determined based on the requirements for the shape and area of ​​the non-light-receiving surface of the N-type doped polysilicon layer in actual applications, and can be applied to the back-contact battery provided in the examples of this application.

[0052] 1, the thickness of the portion of the N-type doped polycrystalline silicon layer 21 located in the edge region of the non-light-receiving surface may be 175 nm to 225 nm. For example, the thickness of the portion of the N-type doped polycrystalline silicon layer 21 located in the edge region of the non-light-receiving surface may be 175 nm, 185 nm, 195 nm, 205 nm, 215 nm, or 225 nm. In this case, by ensuring that the thickness of the portion of the N-type doped polycrystalline silicon layer 21 located in the edge region of the non-light-receiving surface is within the above range, it is possible to prevent the overall thickness of the N-type doped polycrystalline silicon layer 21 from being small and not meeting the target requirements due to a small thickness value, and to prevent difficulties in manufacturing an N-type doped polycrystalline silicon layer 21 with high thickness uniformity, which is useful for obtaining a back-contact battery. In addition, the corrosion resistance of the phosphosilicate glass layer located at the edge of the N-type doped polycrystalline silicon material layer is prevented from being reduced after the phosphorus diffusion process due to the large thickness value. During the texturing process, the phosphosilicate glass layer can ensure that each portion of the N-type doped polycrystalline silicon material layer for forming the N-type doped polycrystalline silicon layer 21 can be well protected, and the N-type doped polycrystalline silicon layer 21 has a good morphology and a formation range that meets the target requirements.

[0053] 1, the thickness of the portion of N-type doped polycrystalline silicon layer 21 located in the central region of the non-light-receiving surface may be 150 nm or more and 200 nm or less. For example, the thickness of the portion of N-type doped polycrystalline silicon layer 21 located in the central region of the non-light-receiving surface may be 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, etc.

[0054] In terms of doping, the N-type doped polycrystalline silicon layer may be doped with only N-type impurities such as phosphorus, or may be further doped with N-type impurities such as nitrogen or arsenic. The doping concentration of the impurities in the N-type doped polycrystalline silicon layer can be set according to actual needs and is not specifically limited here.

[0055] For example, the average doping concentration of impurities in the N-type doped polycrystalline silicon layer is 3.5×10 20 / cm 3 Over 4.0 x 10 20 / cm 3 For example, the average doping concentration of impurities in the N-type doped polycrystalline silicon layer may be 3.5×10 20 / cm 3 , 3.6×10 20 / cm 3 , 3.7 × 10 20 / cm 3 , 3.8×10 20 / cm 3 , 3.9 × 10 20 / cm 3 or 4.0 x 10 20 / cm 3 In this case, the average doping concentration of impurities in the N-type doped polycrystalline silicon layer is within the above range, so that the N-type doped polycrystalline silicon layer has an excellent carrier selective collection function and does not affect the contact resistance between the N-type doped polycrystalline silicon layer and the negative electrode. 20 / cm 3In the embodiment of the present application, the doping concentration of the impurities in the N-type doped polycrystalline silicon layer can be appropriately reduced compared to the N-type doped polycrystalline silicon layer (larger than the N-type doped polycrystalline silicon layer). Accordingly, the average doping concentration of the impurities in the N-type doped polycrystalline silicon layer for fabricating the N-type doped polycrystalline silicon layer is also low. Based on this, in the actual manufacturing process, after the phosphorus diffusion process, the average doping concentration of the impurities in the N-type doped polycrystalline silicon layer is proportional to the average doping concentration of the impurities in the phosphosilicate glass layer formed thereon. Therefore, appropriately reducing the doping concentration of the impurities in the N-type doped polycrystalline silicon layer means that the average doping concentration of the impurities (including phosphorus) in the phosphosilicate glass layer is also reduced. In this case, since the phosphorus doping concentration in the phosphosilicate glass layer is inversely proportional to its own corrosion resistance, appropriately reducing the phosphorus doping concentration in the phosphosilicate glass layer can improve its own corrosion resistance and further ensure that the N-type doped polycrystalline silicon layer has a good morphology and a formation range that meets the target requirements.

[0056] In actual applications, during the process of forming an N-type doped polysilicon layer on the non-light-receiving side, a wraparound doped layer and a wraparound phosphosilicate glass layer are formed on the side surfaces and part of the light-receiving surface of the semiconductor substrate due to wraparound. Furthermore, before texturing at least the light-receiving surface of the semiconductor substrate, the wraparound phosphosilicate glass layer and the wraparound doped layer must be sequentially removed. The etchant used to remove the wraparound doped layer also affects the surface of the part of the light-receiving surface covered by the wraparound doped layer, resulting in the formation of a porous structure on that surface. However, the surface of the central region of the light-receiving surface, which is not covered by the wraparound doped layer, remains flat. As a result, the sizes of the textured structures located on the edge and central regions of the light-receiving surface are not consistent after the subsequent texturing process, further affecting the light-confining effect of the light-receiving surface. Specifically, the size uniformity of the textured structures in each region of the light-receiving surface can be determined depending on the formation conditions of the N-type doped polysilicon layer and is not specifically limited herein.

[0057] For example, as shown in Figure 1, the size uniformity of the textured structure in each region of the light-receiving surface is 85% to 100%. The specific value of the size uniformity of the textured structure in each region of the light-receiving surface can be determined based on the actual manufacturing process and is not specifically limited herein. In this case, the high size uniformity of the textured surface structure in each region of the light-receiving surface allows each region of the light-receiving surface to have high light transmittance, which helps more light to penetrate through the light-receiving surface into the semiconductor substrate 11, further improving the photoelectric conversion efficiency of the back-contact cell.

[0058] 10, the back-contact battery provided in the embodiments of the present application may include a positive electrode 22 and a negative electrode 23. Here, the positive electrode 22 is in ohmic contact with a P-type region of the semiconductor substrate 11. The negative electrode 23 is in ohmic contact with an N-type doped polycrystalline silicon layer 21. The materials of the positive electrode 22 and the negative electrode 23 may be conductive materials such as copper, aluminum, or silver.

[0059] In a second aspect, embodiments of the present application further provide a solar module including a back-contact cell provided in the first aspect and its various implementations.

[0060] The beneficial effects of the second aspect in the embodiments of the present application can be referred to the analysis of the beneficial effects of the first aspect and its various implementation forms, and will not be described here.

[0061] In a third aspect, the embodiments of the present application further provide a method for manufacturing a back-contact battery, which will be described below based on the operational cross-sectional views shown in Figures 4 to 10.

[0062] Specifically, the method for fabricating the back-contact battery includes the following steps: First, a semiconductor substrate is prepared. Next, as shown in FIG. 4, a tunnel passivation material layer 12 and an intrinsic amorphous silicon material layer 13 are sequentially stacked in the thickness direction of the semiconductor substrate 11 on the non-light-receiving side of the semiconductor substrate 11. Next, as shown in FIG. 5, a phosphorus diffusion process is performed on the intrinsic amorphous silicon material layer to convert the intrinsic amorphous silicon material layer into an N-type doped polycrystalline silicon material layer 15, and a phosphosilicate glass layer 16 is formed on the N-type doped polycrystalline silicon material layer 15. The thickness ratio of the edge region of the non-light-receiving side of the N-type doped polycrystalline silicon material layer 15 to the central region of the non-light-receiving side of the N-type doped polycrystalline silicon material layer 15 is between 1 and 1.2. Next, as shown in FIG. 8, the light-receiving side of the semiconductor substrate 11 is textured using the phosphosilicate glass layer 16 as a mask, to form a textured surface 19 on the light-receiving side. Thereafter, as shown in Fig. 8, the phosphosilicate glass layer 16 and the stacked tunnel passivation material layer and N-type doped polycrystalline silicon material layer are patterned to form a tunnel passivation layer 20 and an N-type doped polycrystalline silicon layer 21 stacked in a partial region of the non-light-receiving surface. Next, as shown in Fig. 9, the remaining phosphosilicate glass layer is removed.

[0063] The beneficial effects of the third aspect in the embodiments of the present application can be referred to the analysis of the beneficial effects of the first aspect and its various implementation forms, and the description thereof will be omitted here.

[0064] Specifically, the specific structure, conductivity type, material, etc. of the semiconductor substrate can be referred to the above, and the description is omitted here. After preparing the semiconductor substrate, the tunnel passivation material layer and the intrinsic amorphous silicon material layer can be formed by a process such as chemical vapor deposition. Here, the material, thickness, etc. of the tunnel passivation material layer can be referred to the above. For the intrinsic amorphous silicon material layer, the intrinsic amorphous silicon material layer is used to manufacture the N-type doped polycrystalline silicon layer included in the back contact battery. In addition, since the phosphosilicate glass layer formed after the phosphorus diffusion treatment needs to consume a part of the silicon in the intrinsic amorphous silicon material layer, the thickness of the N-type polycrystalline silicon material layer formed based on the intrinsic amorphous silicon material layer after the phosphorus diffusion treatment becomes smaller. Based on this, the thickness of each part of the intrinsic amorphous silicon material layer can be determined based on the thickness of each part of the N-type doped polycrystalline silicon material layer and the phosphosilicate glass layer, and the thickness ratio of the intrinsic amorphous silicon material that needs to be consumed to form the corresponding thickness of the phosphosilicate glass layer.

[0065] Exemplarily, assuming that the average thickness of the intrinsic amorphous silicon material layer is H1, the average thickness of the phosphosilicate glass layer is H2, and the average thickness of the N-type doped polycrystalline silicon material layer is H3, then 40%H2 < H1 - H3 < 60%H2. In this case, the fact that the average thicknesses of the intrinsic amorphous silicon material layer, the phosphosilicate glass layer, and the N-type doped polycrystalline silicon material layer satisfy the above conditions indicates that the formed thickness of the intrinsic amorphous silicon material layer is appropriate, and both the density and the structural density uniformity of each region in the direction parallel to the non-light-receiving surface of the intrinsic amorphous silicon material layer are high. After forming the phosphosilicate glass layer, the consumed thickness of the N-type doped polycrystalline silicon material layer helps to satisfy the theoretical consumption amount of the N-type doped polycrystalline silicon material layer with high density (that is, the thickness of the phosphosilicate glass layer is approximately equal to half of the thickness reduction amount of the N-type doped polycrystalline silicon material layer), or the difference from the above theoretical consumption amount is small. Furthermore, it shows that the formed quality of the phosphosilicate glass layer after optimization is high, and it is ensured that the formed N-type doped polycrystalline silicon layer has a formation range that satisfies good morphology and target requirements.

[0066] Furthermore, the N-type doped polycrystalline silicon material layer formed based on the intrinsic amorphous silicon material layer has a thickness ratio between the edge region of its non-light-receiving surface and the central region of the non-light-receiving surface of 1 or more and 1.2 or less. Accordingly, the thickness ratio between the edge region of the non-light-receiving surface and the central region of the non-light-receiving surface of the intrinsic amorphous silicon material layer is also 1 or more and 1.2 or less. In this case, during the actual manufacturing process, the thickness of the corresponding region of the intrinsic amorphous silicon material layer can be adjusted by adjusting any parameters that can affect the thickness of different regions of the intrinsic amorphous silicon material layer, such as the atmospheric pressure and gas flow rate during the formation of the intrinsic amorphous silicon material layer. Specifically, the specific values ​​of the parameters that affect the thickness of different regions of the intrinsic amorphous silicon material layer can be determined depending on the specific thickness of the different regions of the intrinsic amorphous silicon material layer, and this may be applicable to the manufacturing method of the back-contact battery provided in the embodiments of the present application.

[0067] For example, the atmospheric pressure during the formation of the intrinsic amorphous silicon material layer may be 100 mTorr or more and 150 mTorr or less. For example, the atmospheric pressure during the formation of the intrinsic amorphous silicon material layer may be 100 mTorr, 110 mTorr, 120 mTorr, 130 mTorr, 140 mTorr, or 150 mTorr. In this case, during the actual manufacturing process of the intrinsic amorphous silicon material layer, the atmospheric pressure may be reduced within a certain range to improve the molecular free path, allowing reactive molecular groups to reach each region of the surface of the tunnel passivation material layer more quickly without agglomerating in the same location. Therefore, by maintaining the atmospheric pressure within the above range when forming the intrinsic amorphous silicon material layer, it is possible to prevent the thickness of the edge portions of the intrinsic amorphous silicon material layer from increasing due to high atmospheric pressure, ensure that the thickness difference between the edge portions and the center portion of the intrinsic amorphous silicon material layer is small, ensure that the structure of the edge portions of the intrinsic amorphous silicon material layer is as dense as the structure of its center portion, and further ensure that each portion of the phosphosilicate glass layer formed after the phosphorus diffusion treatment in the direction parallel to the non-light-receiving surface has high corrosion resistance, and ensure that the shape and formation area of ​​the formed N-type doped polycrystalline silicon layer meet the target requirements. It is also possible to prevent a decrease in process efficiency due to low atmospheric pressure.

[0068] For example, the gas flow rate during the formation of the intrinsic amorphous silicon layer may be 0.9 slm or more and 1.2 slm or less. For example, the gas flow rate during the formation of the intrinsic amorphous silicon layer may be 0.9 slm, 1.0 slm, 1.1 slm, or 1.2 slm. In this case, during the actual manufacturing process of the intrinsic amorphous silicon layer, reducing the gas flow rate within a certain range reduces the total gas flow rate within the diffusion device and further reduces the degree of perturbation caused by the air flow within the diffusion device, which helps optimize the deposition quality of the portion located at the edge region of the non-light-receiving surface of the intrinsic amorphous silicon layer, ensuring that the structure of the edge portion of the intrinsic amorphous silicon layer is as dense as the structure of its central portion. Furthermore, each portion of the phosphosilicate glass layer formed after the phosphorus diffusion process in the direction parallel to the non-light-receiving surface has high corrosion resistance, ensuring that the shape and formation area of ​​the formed N-type doped polycrystalline silicon layer meet the target requirements. This also prevents a decrease in process efficiency due to a low gas flow rate.

[0069] 4, an intrinsic amorphous silicon material layer 13 is formed on the non-light-receiving surface side of the semiconductor substrate 11 in the thickness direction of the semiconductor substrate 11, and a wraparound amorphous silicon layer 14 is formed on the side surface of the semiconductor substrate 11 and part of the light-receiving surface. The width of the formation region of the wraparound amorphous silicon layer 14 on the light-receiving surface (the width direction of the formation region is parallel to the radial direction of the semiconductor substrate 11) is affected by parameters such as the atmospheric pressure and gas flow rate during the manufacture of the intrinsic amorphous silicon material layer 13. For example, within a certain range, the lower the atmospheric pressure during the manufacture of the intrinsic amorphous silicon material layer 13, the smaller the width of the formation region of the wraparound amorphous silicon layer 14 on the light-receiving surface. In the above case, the width of the formation region of the wraparound amorphous silicon layer 14 on the light-receiving surface can be determined depending on the manufacturing conditions of the intrinsic amorphous silicon material layer 13.

[0070] For example, the width of the region where the wraparound amorphous silicon layer is formed on the light-receiving surface may be 0 mm or more and less than 10 mm. For example, the width of the region where the wraparound amorphous silicon layer is formed on the light-receiving surface may be 1 mm, 3 mm, 6 mm, 9 mm, or 9.5 mm. In this case, the wraparound phosphosilicate glass layer and the wraparound doped layer must be sequentially removed before the texturing process is performed. The etching solution used to remove the wraparound doped layer also affects the surface of the portion of the light-receiving surface of the semiconductor substrate that is covered with the wraparound doped layer, resulting in the formation of a porous structure on the surface of that portion. However, the surface of the central region of the light-receiving surface of the semiconductor substrate that is not covered with the wraparound doped layer remains flat. As a result, after the subsequent texturing process, the sizes of the textured structures located in the edge region and central region of the light-receiving surface will not match, further affecting the light-confining effect of the light-receiving surface. In this case, compared to the related art where the width of the formation region of the wraparound doped layer on the light-receiving surface formed during the manufacture of back-contact cells is greater than 10 mm, when the width of the formation region of the wraparound amorphous silicon layer on the light-receiving surface in the examples of the present application is 0 to less than 10 mm, the wraparound width is small, which helps to improve the size uniformity of the texture structure located in each region of the light-receiving surface, and further helps to improve the light confinement effect of the light-receiving surface and further improve the photoelectric conversion efficiency of the back-contact cell. Therefore, the specific numerical value of the size uniformity of the texture structure in each region of the light-receiving surface of the semiconductor substrate can be determined based on the width of the formation region of the wraparound amorphous silicon layer on the light-receiving surface during the actual manufacturing process and the size of the semiconductor substrate, and is not specifically limited here.

[0071] In actual manufacturing processes, after the intrinsic amorphous silicon layer is formed, a phosphorus diffusion process is performed on the intrinsic amorphous silicon layer to form the N-type doped polycrystalline silicon layer and the phosphosilicate glass layer. The phosphorus diffusion process includes a phosphorus source deposition process, a crystallization promotion process, and a post-oxidation process, which are performed sequentially. The phosphorus source deposition process adjusts the phosphorus doping concentration in the N-type doped polycrystalline silicon layer and the phosphosilicate glass layer, and the post-oxidation process adjusts the thickness of the N-type doped polycrystalline silicon layer and the phosphosilicate glass layer. Furthermore, the phosphorus doping concentration in the N-type doped polycrystalline silicon layer and the phosphosilicate glass layer, as well as the thickness of the phosphosilicate glass layer, all affect the corrosion resistance during the texturing process of the phosphosilicate glass layer. Therefore, the specific process parameters for the phosphorus diffusion process can be determined according to the thickness and doping concentration of the N-type doped polycrystalline silicon layer and the phosphosilicate glass layer, as well as the requirements for the morphology and formation area of ​​the N-type doped polycrystalline silicon layer in actual applications, and are not specifically limited herein.

[0072] Exemplary conditions for the phosphorus diffusion treatment are as follows: The temperature of the deposition process is equal to or greater than 850° C. and equal to or less than 900° C. For example, the temperature of the deposition process may be 850° C., 860° C., 870° C., 880° C., 890° C., or 900° C., etc.

[0073] The atmospheric pressure of the deposition process is 150 mbar or more and 200 mbar or less. For example, the atmospheric pressure of the deposition process may be 150 mbar, 160 mbar, 170 mbar, 180 mbar, 190 mbar, 200 mbar, etc.

[0074] The phosphorus source pressure of the deposition process is 250 mbar or more and 450 mbar or less. For example, the phosphorus source pressure of the deposition process may be 250 mbar, 300 mbar, 350 mbar, 400 mbar, or 450 mbar, etc.

[0075] The nitrogen flow rate of the deposition process is between 1500 sccm and 2000 sccm, for example, 1500 sccm, 1600 sccm, 1700 sccm, 1800 sccm, 1900 sccm, or 2000 sccm.

[0076] The oxygen flow rate for the deposition process is between 750 sccm and 1000 sccm, for example, 750 sccm, 800 sccm, 850 sccm, 900 sccm, 950 sccm, or 1000 sccm.

[0077] The temperature of the post-oxidation process is 850° C. or higher and 900° C. or lower. For example, the temperature of the post-oxidation process may be 850° C., 860° C., 870° C., 880° C., 890° C., 900° C., or the like.

[0078] The oxygen flow rate in the post-oxidation process is 5000 sccm or more and 10000 sccm or less, for example, 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, etc.

[0079] Here, any one of the process parameters may satisfy the corresponding range requirement, or at least two of the process parameters may satisfy the corresponding range requirement.

[0080] When the above technical solution is adopted, in actual manufacturing, the average doping concentration of impurities in the formed phosphosilicate glass layer and the N-type doped polycrystalline silicon material can be adjusted by changing the deposition temperature, deposition atmosphere pressure, phosphorus source pressure, nitrogen flow rate, and oxygen flow rate during the phosphorus diffusion process. Based on this, when at least one of the deposition temperature, deposition atmosphere pressure, phosphorus source pressure, nitrogen flow rate, and oxygen flow rate is within the corresponding range, the average doping concentration of phosphorus in the phosphosilicate glass layer can be appropriately reduced, resulting in the phosphosilicate glass layer with high corrosion resistance. Furthermore, the N-type doped polycrystalline silicon layer formed based on the N-type doped polycrystalline silicon material layer can have a good morphology and a formation range that meets the target requirements. Furthermore, the thickness of the formed phosphosilicate glass layer can be adjusted by changing the post-oxidation temperature and post-oxidation oxygen flow rate during the phosphorus diffusion process. Based on this, when at least one of the post-oxidation temperature and post-oxidation oxygen flow rate is within the corresponding range, the formed thickness of the phosphosilicate glass layer can be appropriately increased, resulting in improved corrosion resistance of the phosphosilicate glass layer.

[0081] For example, the thickness of the phosphosilicate glass layer may be 60 nm to 65 nm. For example, the thickness of the phosphosilicate glass layer may be 60 nm, 61 nm, 62 nm, 63 nm, 64 nm, or 65 nm. In this case, by ensuring that the thickness of the phosphosilicate glass layer is within the above range, it is possible to prevent the corrosion resistance of the phosphosilicate glass layer from being reduced due to a small thickness of the phosphosilicate glass layer and ensure that the morphology and formation area of ​​the formed N-type doped polycrystalline silicon layer meet the target requirements. It is also possible to prevent the consumption of consumable materials for manufacturing the intrinsic amorphous silicon material layer and the phosphosilicate glass layer from being increased due to a large thickness of the phosphosilicate glass layer, which helps to reduce the manufacturing costs of back-contact batteries.

[0082] 5, after the phosphorus diffusion process, the wraparound amorphous silicon layer becomes a wraparound doped layer 17, and a wraparound phosphosilicate glass layer 18 is formed on the wraparound doped layer 17. In this case, after the N-type doped polycrystalline silicon material layer 15 is formed, and before texturing is performed on at least the light-receiving surface of the semiconductor substrate 11, the wraparound phosphosilicate glass layer and the wraparound doped layer can be sequentially removed by a process such as wet etching, as shown in FIG.

[0083] Furthermore, after the phosphorus diffusion process is performed on the intrinsic amorphous silicon material layer, and before the texturing process is performed on at least the light-receiving surface of the semiconductor substrate, as shown in Fig. 7, a patterning process can be performed on only the phosphosilicate glass layer 16 by laser etching or the like so that the remaining portion of the phosphosilicate glass layer 16 is formed on a partial region of the N-type doped polycrystalline silicon material layer 15. In this case, as shown in Fig. 8, under the masking effect of the phosphosilicate glass layer 16, the laminated tunnel passivation material layer and the N-type doped polycrystalline silicon material layer can be patterned simultaneously with the texturing process on the light-receiving surface of the semiconductor substrate 11. That is, by patterning the phosphosilicate glass layer 16 located on the non-light-receiving side before the texturing process, not only can the texturing etchant be used to turn at least the light-receiving side into a textured surface 19 in the subsequent texturing process, but also the N-type doped polycrystalline silicon material layer and the tunnel passivation material layer can be patterned under the masking effect of the remaining portion of the phosphosilicate glass layer 16 to obtain the N-type doped polycrystalline silicon layer 21 and the tunnel passivation layer 20, thereby ensuring that the shape and formation area of ​​the N-type doped polycrystalline silicon layer 21 meet the target requirements and improving the process efficiency of the back-contact cell.

[0084] Of course, after removing the wraparound phosphosilicate glass layer and wraparound doping layer, texturing may be performed directly on at least the light-receiving surface of the semiconductor substrate while masking the entire phosphosilicate glass layer. In this case, the texturing etchant does not affect the regions of the N-type doped polycrystalline silicon material layer parallel to the non-light-receiving surface. In this case, after texturing, the phosphosilicate glass layer can be patterned by laser etching or the like. Then, using wet or dry etching or the like to mask the remaining portions of the phosphosilicate glass layer, the tunnel passivation material layer and the N-type doped polycrystalline silicon material layer can be further patterned to obtain the tunnel passivation layer and the N-type doped polycrystalline silicon layer.

[0085] Next, as shown in Fig. 9, the remaining portion of the phosphosilicate glass layer can be removed by wet etching, dry etching, or the like. Thereafter, as shown in Fig. 10, a positive electrode 22 and a negative electrode 23 can be formed on the non-light-receiving surface side by screen printing, electroplating, or the like. The positive electrode 22 is in ohmic contact with the P-type region of the semiconductor substrate 11, and the negative electrode 23 is in ohmic contact with the N-type doped polycrystalline silicon layer 21.

[0086] The above-described device embodiments are merely illustrative, and the units described herein as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. According to actual needs, some or all of the modules may be selected to achieve the objectives of the solutions of the present embodiment. Those skilled in the art can understand and implement the present invention without any creative effort.

[0087] The terms "one embodiment," "embodiment," or "one or more embodiments" used herein mean that a particular feature, structure, or characteristic described by the embodiment is included in at least one embodiment of the present application. It should also be noted that the phrase "in one embodiment" used herein does not necessarily refer to the same embodiment. In the specification provided herein, numerous specific details have been set forth. However, it will be understood that embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail in order to avoid obscuring an understanding of this specification.

[0088] In the claims, any reference signs placed between parentheses shall not limit the claim. The word "comprising" does not exclude the presence of elements or steps not stated in a claim. The word "a" or "one" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In each claim enumerating several devices, these several devices may be embodied by the same hardware item. The terms first, second, third, etc. do not denote any order. These terms may also be interpreted as names.

[0089] Finally, it should be noted that the above examples are only for illustrating the technical solutions of the present application, and are not intended to limit the same. Although the present application has been described in detail with reference to the above examples, it is naturally understood by those skilled in the art that modifications to the technical solutions described in the above examples or equivalent substitutions for some technical features thereof are possible, and such modifications or substitutions do not deviate the essence of the relevant technical solutions from the spirit and scope of the technical solutions of the examples of the present application. [Explanation of symbols]

[0090] 11 Semiconductor substrate 12 Tunnel passivation material layer 13 Intrinsic amorphous silicon material layer 14 Wraparound amorphous silicon layer 15 N-type doped polycrystalline silicon material layer 16 Phosphorus silicate glass layer 17. Parallel doping layer 18 Wrap-around phosphosilicate glass layer 19 Textured Surfaces 20 Tunnel passivation layer 21 N-type doped polycrystalline silicon layer 22 Positive electrode 23 Negative electrode

Claims

1. a semiconductor substrate having a first surface and a second surface, the first surface and the second surface being provided opposite to each other and having a textured structure; a tunnel passivation layer and an N-type doped polycrystalline silicon layer sequentially stacked on a portion of the second surface in a thickness direction of the semiconductor substrate, wherein a thickness ratio of a portion of the N-type doped polycrystalline silicon layer located in an edge region of the second surface to a portion of the N-type doped polycrystalline silicon layer located in a central region of the second surface is 1 or more and 1.2 or less.

2. 10. The back contact battery of claim 1, wherein the size uniformity of the textured structure in each region of the first surface is 85% or more but less than 100%.

3. 10. The back contact battery of claim 1, wherein the area of ​​the second surface where the tunnel passivation layer and the N-type doped polycrystalline silicon layer are not stacked is a polished surface or has a textured structure.

4. The thickness of the portion of the N-type doped polycrystalline silicon layer located in the edge region of the second surface is 175 nm or more and 225 nm or less, and / or 2. The back contact battery of claim 1, wherein the thickness of the portion of the N-type doped polycrystalline silicon layer located in the central region of the second surface is 150 nm or more and 200 nm or less.

5. The average doping concentration of impurities in the N-type doped polycrystalline silicon layer is 3.5×10 ２０ / cm ３ Above 4.0 x 10 ２０ / cm ３ 5. The back contact battery of any one of claims 1 to 4, wherein:

6. A solar module comprising the back contact cell of any one of claims 1 to 5.

7. providing a semiconductor substrate having opposed first and second surfaces; sequentially stacking a tunnel passivation material layer and an intrinsic amorphous silicon material layer on the second surface side in a thickness direction of the semiconductor substrate; performing a phosphorus diffusion process on the intrinsic amorphous silicon material layer to convert the intrinsic amorphous silicon material layer into an N-type doped polycrystalline silicon material layer, and forming a phosphosilicate glass layer on the N-type doped polycrystalline silicon material layer, wherein a thickness ratio of a portion of the N-type doped polycrystalline silicon material layer located in an edge region of the second surface to a portion of the N-type doped polycrystalline silicon material layer located in a central region of the second surface is 1 or more and 1.2 or less; performing a texturing process on the first surface under the masking effect of the phosphosilicate glass layer to form a textured surface on the first surface; performing a patterning process on the phosphosilicate glass layer and the stacked tunnel passivation material layer and N-type doped polycrystalline silicon material layer to form a stacked tunnel passivation layer and N-type doped polycrystalline silicon layer on a partial region of the second surface; removing the remaining phosphosilicate glass layer; A method for manufacturing a back contact battery, comprising:

8. The atmospheric pressure during the formation of the intrinsic amorphous silicon material layer is 100 mTorr or more and 150 mTorr or less, and / or 8. The method for manufacturing a back contact battery according to claim 7, wherein the gas flow rate during the formation of the intrinsic amorphous silicon material layer is 0.9 slm or more and 1.2 slm or less.

9. after the step of performing a phosphorus diffusion process on the intrinsic amorphous silicon material layer and before the step of texturing the first surface under the masking effect of the phosphosilicate glass layer, performing the patterning process only on the phosphosilicate glass layer such that remaining portions of the phosphosilicate glass layer are formed in some areas of the N-type doped polycrystalline silicon material layer; 8. The method for fabricating a back contact battery of claim 7, wherein the first surface is textured under the masking effect of the phosphosilicate glass layer, and the stacked tunnel passivation material layer and N-type doped polycrystalline silicon material layer are simultaneously patterned.

10. In a thickness direction of the semiconductor substrate, an intrinsic amorphous silicon material layer is formed on the second surface side, and at the same time, a wraparound amorphous silicon layer is formed on a side surface of the semiconductor substrate and a part of the first surface, the wraparound amorphous silicon layer having a width on the first surface in a formation region that is equal to or greater than 0 mm and less than 10 mm, and the width direction of the formation region is parallel to a radial direction of the semiconductor substrate; After the phosphorus diffusion treatment, the wraparound amorphous silicon layer becomes a wraparound doped layer, and a wraparound phosphosilicate glass layer is formed on the wraparound doped layer; 8. The method for manufacturing a back contact battery of claim 7, wherein after the step of performing a phosphorus diffusion treatment on the intrinsic amorphous silicon material layer and before the step of performing a texturing treatment on the first surface under the masking action of the phosphosilicate glass layer, the method for manufacturing a back contact battery further includes the step of removing the wraparound phosphosilicate glass layer and the wraparound doped layer.

11. The thickness of the phosphosilicate glass layer is 60 nm or more and 65 nm or less, and / or 11. The method for manufacturing a back contact battery according to claim 7, wherein, where H1 is an average thickness of the intrinsic amorphous silicon material layer, H2 is an average thickness of the phosphosilicate glass layer, and H3 is an average thickness of the N-type doped polycrystalline silicon material layer, 40%H2<H1-H3<60%H2.

12. The treatment conditions for the phosphorus diffusion treatment are:

11. The method for manufacturing a back contact battery of claim 7, wherein the deposition process temperature is from 850° C. to 900° C., and / or the deposition process ambient pressure is from 150 mbar to 200 mbar, and / or the deposition process phosphorus source pressure is from 250 mbar to 450 mbar, and / or the deposition process nitrogen flow rate is from 1500 sccm to 2000 sccm, and / or the deposition process oxygen flow rate is from 750 sccm to 1000 sccm, and / or the post-oxidation process temperature is from 850° C. to 900° C., and / or the post-oxidation process oxygen flow rate is from 5000 sccm to 10000 sccm.

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