Image management method, chip, image transmission method and electronic device

Abstract

This application provides an image management method, a chip, an image transmission method, and an electronic device, belonging to the field of data transmission. The image management method includes the steps of: in response to writing of an image block, assigning address granules to the image block; storing the image block in a memory area corresponding to the address granules; and, when the memory area corresponding to the address granules is filled with data of the stored image block, writing the address of the memory area corresponding to the address granules to a predetermined information buffer, where each address granule corresponds to a different memory area in memory, and the information buffer is configured to provide the address of the memory area corresponding to the address granules to an acquirer of the image block, and the acquirer is configured to acquire the image block from the memory based on the address of the memory area corresponding to the address granules. The image management method described above can reduce the chip area required for temporarily storing image blocks during the image transmission process.

Description

[Technical Field]

[0001] The present application belongs to the field of image transmission, and specifically relates to an image management method, a chip, an image transmission method and an electronic device. [Background technology]

[0002] In order to improve the efficiency of image transmission, image data may be compressed during the image transmission process. When compressing an image, the image data is generally converted into image blocks, and the image blocks are arranged in a linear sequence and ready to be read.

[0003] When image blocks are arranged in linear sequence, a relatively large memory space is required to temporarily store the image blocks. Currently, registers are used to temporarily store the image blocks. When the image width of the image block to be stored is relatively large or the number of rows of the image block is relatively large, the image block requires a large memory space and a relatively large number of registers. Too many registers occupy a relatively large chip area, affecting subsequent circuit design and wiring. When multiple rows of image blocks are written simultaneously, additional memory space must be provided to store the addresses of the data for each row, further increasing the register area. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application aims to provide an image management method, a chip, an image transmission method, and an electronic device that can reduce the chip area occupied by a circuit that temporarily stores image blocks during the image data transmission process. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present application provides an image management method, the image management method including the steps of: in response to writing of an image block, allocating address granules to the image block, storing the image block in a memory area corresponding to the address granules, and, when the memory area corresponding to the address granules is filled with data of the stored image block, writing addresses of the memory area corresponding to the address granules to a predetermined information buffer, wherein each of the address granules corresponds to a different memory area in a memory, and the address granules are data recording addresses of the corresponding memory areas, the memory includes a plurality of memory areas of a first predetermined size, the information buffer is configured to provide addresses of the memory areas corresponding to the address granules to an acquiring side of the image block, and the acquiring side is configured to acquire the image block from the memory based on the addresses of the memory areas corresponding to the address granules.

[0006] Compared with registers, memory requires less chip area to store the same amount of image blocks. In the embodiments of the present application, storing image blocks in memory reduces the chip area occupied by circuits that temporarily store image blocks during image transmission. Memory is directly controlled by the processor, while registers require memory to store a larger amount of data and be controlled by read / write commands. Failure to record image blocks stored in memory can result in overwriting, duplicated reading, and other issues. Therefore, in the embodiments of the present application, address granules are used to record the storage and reading of image blocks. When the address of a memory area corresponding to an address granule is within a specified information buffer, the image block stored in that memory area can be read, but the image block corresponding to that address granule cannot be overwritten with new data. Therefore, when multiple rows of image blocks are written continuously or simultaneously within a short period of time, using address granules can accurately output the image blocks and reduce the possibility of data loss. This allows address granules and memory to achieve normal storage, management, and output of image blocks while reducing the chip area occupied.

[0007] In one embodiment, before allocating address granules to the image block, the method further includes a step of determining allocation parameters of the memory based on a predetermined transformation format, the allocation parameters being for allocating the memory, the predetermined transformation format being a predetermined compression format of the image block, the predetermined transformation format including a maximum image width of the image block, and an arrangement manner of Y components and UV components of pixel points in the image block, the Y component being the luminance of the pixel point, and the UV components being the chrominance of the pixel point, the allocation parameters of the memory including the number, width and depth of memory units in the memory, the memory being configured by a plurality of the memory units, and the total memory space of the plurality of the memory units being divided into a plurality of memory areas.

[0008] In the image transmission process, the format of the image block obtained by image data conversion can be determined in advance. In the embodiment of the present application, the memory allocation parameters can be determined based on the image block format, so that, on the premise that the configured memory meets the current image transmission needs, image transmission can be realized with a relatively small memory space, thereby making rational use of storage resources, and reusing memory resources for other scenes, thereby reducing resource waste.

[0009] In one embodiment, after determining the memory layout parameters based on a predetermined translation format, the method further includes setting the number of address granules and the first predetermined size based on the memory layout parameters and the predetermined translation format.

[0010] In the embodiment of the present application, the number of address granules and the first predetermined size are dynamically configured based on the memory configuration parameters and the predetermined conversion format, so that the number of address granules and the first predetermined size are configured to match the image block format and memory in the current image transmission process, thereby reducing the waste of memory space caused by the mismatch between the first predetermined size and the image block format, improving the utilization efficiency of the memory area, and reducing the chip area occupied by the memory.

[0011] In one embodiment, the information buffer includes a plurality of information buffers corresponding to the Y component and a plurality of information buffers corresponding to the UV component, and the step of writing the address of the memory area corresponding to the address granule to a predetermined information buffer includes writing the address corresponding to the memory area to an information buffer corresponding to the component type based on a component type of the pixel point written to the memory area, and the component type of the pixel point includes the Y component and the UV component.

[0012] In the embodiment of the present application, different pixel point components are stored in different memory areas, and addresses of memory areas corresponding to different pixel point components are stored in different information buffers, so that corresponding addresses in memory of different Y components and UV components can be obtained from different information buffers, and then the Y components or UV components can be obtained from the memory areas corresponding to the addresses. By storing the Y components and UV components separately, the Y components and UV components can be accurately distinguished to obtain the required component types, which reduces the difficulty of managing image blocks and the possibility of confusion.

[0013] In one embodiment, after writing the granule information of the address granule to a predetermined information buffer, the method includes the steps of: providing the acquiring side with an address of a memory area corresponding to the address granule via the information buffer, so that the acquiring side reads an image block from the memory area based on the address of the memory area corresponding to the address granule; and, in response to reading the image block in the memory area, releasing the address granule corresponding to the memory area, wherein, once the address granule is released, a new image block can be written to the memory area corresponding to the address granule.

[0014] In an embodiment of the present application, after an image block in a memory area is read, the address granule corresponding to the memory area is released, so that the address granule can be reallocated to a newly written image block and stored in the memory area. Storing and releasing address granules in an information buffer realizes image block address management, reduces the possibility that an image block will be overwritten and lost by a new image block, and improves the accuracy of image transmission. Furthermore, because the address granules occupy a relatively small space, image block address management can be realized with a relatively small chip area.

[0015] In one embodiment, the image block includes UV components, the UV components being the chrominance of a pixel point, and there are multiple information buffers. Before releasing the address granule, the method further includes determining whether the read UV components need to be reused based on an initial format when writing the image block and a target format when writing it out. If it is determined that the UV components need to be reused, rewriting the address of the memory area corresponding to the address granule into the next information buffer.

[0016] During the transmission of an image block, compression and format conversion of the image block occur, resulting in differences between the initial format and the target format. The compression and conversion are primarily reflected in the UV components. Therefore, when returning to an image block or converting the image block to the target format, the UV components must be used repeatedly. In the embodiment of the present application, to use the UV components repeatedly, the address of the memory area corresponding to the address granule is written again to the next information buffer. Therefore, it is not necessary to store the same UV components twice in memory for the overlapping use. Instead, the address can be written to the next information buffer and then re-read based on the address in the next information buffer. Since the information buffer for storing addresses occupies a smaller chip area than the memory for storing image blocks, excessive chip area increase due to the overlapping use of UV components can be reduced.

[0017] In one embodiment, the written image block includes a plurality of image blocks, and before assigning address granules to the image blocks, the method further includes a step of shifting and splicing the inputted plurality of image blocks to form an image block of a second predetermined size; correspondingly, after the information buffer provides the acquiring side with addresses of memory areas corresponding to the address granules, the method further includes a step of shifting the image blocks in the memory areas corresponding to the address granules to restore the arrangement order of the image blocks to the order at the time of input.

[0018] In the embodiments of the present application, by shifting and splicing multiple image blocks, the sizes of the input image blocks can be unified, and image blocks of different sizes can be written in the same size, so as to meet the usage needs of different scenes and expand the range of use, and also reduce the difficulty of managing image blocks of different sizes and reduce the use of circuits for managing image blocks of different sizes, thereby reducing the chip area occupied.

[0019] In a second aspect, an embodiment of the present application provides an image management chip, the image management chip comprising: a memory, an address resource pool, and a plurality of information buffers, the memory including a plurality of memory areas of a first predetermined size, the address resource pool storing a plurality of address granules, different address granules corresponding to different memory areas, the address granules being data recording corresponding memory area addresses, the write memory module connected to each of the address resource pool and the memory and configured to receive written image blocks, each of the information buffers connected to the write memory module, the address resource pool responding to writing of image blocks and storing address granules for the image blocks, the write memory module is further configured to allocate memory areas corresponding to the address granules, the write memory module is further configured to store the image blocks in memory areas corresponding to the address granules, the write memory module is further configured to write addresses of the memory areas corresponding to the address granules to the information buffer when the memory areas corresponding to the address granules are filled with data of the stored image blocks, the information buffer is configured to provide addresses of the memory areas corresponding to the address granules to a receiver of the image blocks, and the receiver is configured to retrieve the image blocks from the memory based on the addresses of the memory areas corresponding to the address granules.

[0020] In one embodiment, the memory is configured to determine layout parameters of the memory based on a predetermined transformation format, the layout parameters being for allocating the memory, the predetermined transformation format being a predetermined compression format of the image block, the predetermined transformation format including a maximum image width of the image block and an arrangement manner of Y components and UV components of pixel points in the image block, the Y component being the luminance of the pixel point and the UV component being the chrominance of the pixel point, the layout parameters of the memory including the number, width and depth of memory units in the memory, the memory being configured by a plurality of the memory units, and the total memory space of the plurality of the memory units being divided into a plurality of memory areas.

[0021] In one embodiment, the memory is further configured to set the number of address granules and the first predetermined size based on an arrangement parameter of the memory and the predetermined translation format.

[0022] In one embodiment, the plurality of information buffers include a plurality of information buffers corresponding to the Y component and a plurality of information buffers corresponding to the UV component, and the write memory module is further configured to write an address corresponding to the memory area to an information buffer corresponding to the component type based on a component type of a pixel point written to the memory area, and the component type of the pixel point includes the Y component and the UV component.

[0023] In one embodiment, the image management device further includes a read memory module, the read memory module being connected to each of the memory, the address resource pool, and the information buffer and configured as the acquisition side, the read memory module being further configured to acquire an address of a memory area corresponding to an address granule stored in the information buffer, and to read and output an image block in the memory area corresponding to the address granule from the memory based on the address of the memory area corresponding to the address granule, the read memory module being further configured to release the address granule corresponding to the memory area in response to reading of the image block in the memory area, and when the address granule is released, it becomes possible to write a new image block to the memory area corresponding to the address granule.

[0024] In one embodiment, the image block includes UV components, which are the chrominance of a pixel point, and the memory is further configured to determine whether the read UV components need to be reused based on the initial format when writing the image block and the target format when writing it out, and if it is determined that it is necessary, to write the address of the memory area corresponding to the address granule into the next information buffer again.

[0025] In one embodiment, the image management chip further includes an input data shift module and an output data shift module, the input data shift module is connected to the write memory module and configured to receive written image blocks and shift and connect the input image blocks to form an image block of a second predetermined size, and the output data shift module is connected to the read memory module and configured to shift the image block output by the read memory module to return the pixels in the image block to the order in which they were input.

[0026] In a third aspect, an embodiment of the present application provides an image transmission method, including: compressing, by a first device, image data into image blocks, and then storing the image blocks in an image management chip according to any one of the second aspects; and sending, by a second device, a read command to the image management chip to read the image blocks from the image management chip.

[0027] In a fourth aspect, an embodiment of the present application provides an electronic device, the electronic device comprising an image management chip according to any one of the second aspects.

[0028] In the embodiment of the present application, image blocks are stored in memory, thereby reducing the chip area occupied by the circuit that temporarily stores image blocks during the image transmission process. Address granules are used to record the storage and reading of image blocks. When multiple rows of image blocks are written continuously or simultaneously within a short period of time, the use of address granules can ensure accurate output of the image blocks and reduce the possibility of data loss. This allows the address granules and memory to achieve normal storage, management, and output of image blocks while reducing the chip area occupied.

[0029] In order to more clearly explain the technical solutions of the embodiments of the present application, the drawings used in the embodiments of the present application will be briefly described below. The drawings described are only for illustrating some embodiments of the present application and are not intended to limit the scope. Those skilled in the art can obtain other related drawings based on these drawings without using inventive abilities. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a schematic diagram of an image management chip according to an embodiment of the present application; [Figure 2] FIG. 1 is a schematic diagram of another aspect of an image management chip according to an embodiment of the present application. [Figure 3]FIG. 2 is a schematic diagram of one image block according to an embodiment of the present application; [Figure 4] FIG. 2 is a schematic diagram of a row of image blocks according to an embodiment of the present application; [Figure 5] 1 is a flowchart of an image management method according to an embodiment of the present application. [Figure 6] FIG. 1 is a schematic diagram of a memory unit according to an embodiment of the present application. [Figure 7] FIG. 2 is a schematic diagram of a Y component according to an embodiment of the present application. [Figure 8] FIG. 1 is a schematic diagram of a UV component according to an embodiment of the present application. [Figure 9] FIG. 2 is a schematic diagram of a multi-row image block according to an embodiment of the present application; [Figure 10] FIG. 2 is a schematic diagram illustrating writing of multiple rows of image blocks according to an embodiment of the present application; [Figure 11] FIG. 2 is a schematic diagram illustrating the reallocation of address granules in a first scene according to an embodiment of the present application; [Figure 12] FIG. 10 is a schematic diagram illustrating the reallocation of address granules in a second scene according to an embodiment of the present application; [Figure 13] 1 is a schematic diagram of an application scene of an image transmission method according to an embodiment of the present application; [Figure 14] 1 is a flowchart of an image transmission method according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0031] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the present application will be described in more detail below with reference to the drawings and examples. The specific embodiments described are only for the purpose of interpreting the present application, and are not intended to limit the present application.

[0032] 1 is a schematic diagram of an image management chip according to an embodiment of the present application. As shown in FIG. 1, the image management chip includes a memory 110, an address resource pool 120, a write memory module 130, and an information buffer 140.

[0033] The memory 110 includes a plurality of memory units, which may be, but are not limited to, SRAMs (Single Port Static Random-Access Buffers).

[0034] In this embodiment, the memory space of the memory 110 is the sum of the memory spaces of multiple memory units, and the memory space of the memory 110 is divided into multiple memory areas of a first predetermined size according to needs, and different image blocks are stored in different memory areas, each of which has the same first predetermined size.

[0035] The memory 110 further includes a memory controller, which is connected to the write memory module 130, the address resource pool 120, and each memory unit, and is configured to control each part of the image management chip to implement the functions of the image management method of the present application.

[0036] An address resource pool 120 is connected to the memory 110, and stores a plurality of address granules, each of which corresponds to a different memory region.

[0037] In this embodiment, the address resource pool 120 includes a buffer, the memory space of which is divided into different regions of the same size, each of which stores the address of a memory region in the memory 110, and an address granule includes the memory region address and the region in the corresponding buffer.

[0038] The write memory module 130 is connected to each of the address resource pool 120 and the memory 110 .

[0039] In this embodiment, write memory module 130 includes a buffer that allows write memory module 130 to receive and temporarily store image blocks to be written.

[0040] The plurality of information buffers 140 are respectively connected to the write memory module 130. The information buffers 140 may be registers, FIFOs (First In First Out), etc., and are configured to store memory area addresses corresponding to address granules.

[0041] The data of an image block includes different types of pixel point components, for example, compressed into YUV (a type of color encoding method) format during image transmission, and an image block in YUV format includes Y, U, and V components, where Y represents luminance and U and V represent chrominance (also called color saturation). In this embodiment, the Y and UV components of an image block are stored in different memories 110, and correspondingly, different information buffers 140 store the memory area addresses of the different components.

[0042] In an embodiment of the present application, after the write memory module 130 receives the written image block, the address resource pool 120 allocates an address granule to the written image block and sends the address granule to the write memory module 130. The write memory module 130 further stores the image block in a memory area corresponding to the address granule.

[0043] In the embodiment of the present application, when the memory area corresponding to an address granule is filled with the data of the stored image block, the memory area address corresponding to the address granule is stored in the information buffer 140, thereby indicating that the image block is available for reading. Then, when the memory area address corresponding to the address granule is stored in the information buffer 140, the address granule is not reallocated, thereby preventing the newly written image block from overwriting the unread image block and reducing the possibility of data loss.

[0044] Accordingly, the address of the memory area corresponding to the address granule is written to the information buffer 140. The information buffer 140 is configured to provide the address of the memory area corresponding to the address granule to the acquirer of the image block.

[0045] The acquirer may be a receiving side in an image transmission process. The acquirer is connected to the information buffer 140, the memory 110, and the address resource pool 120 and is provided by the information buffer 140. The acquirer acquires an image block from the memory 110 based on the address of a memory area corresponding to an address granule. After acquiring the image block in the memory 110, the acquirer can also release the address granule back to the address resource pool 120, so that the address granule can be assigned to a newly written image block, and the memory area corresponding to the address granule can be overwritten with the newly written image block.

[0046] Please refer to FIG. 2, which is a schematic diagram of another embodiment of an image management chip according to an embodiment of the present application.

[0047] In one embodiment, the image management chip further comprises a read memory module 150. The read memory module 150 is connected to each of the memory 110, the address resource pool 120 and the information buffer.

[0048] In this embodiment, the read memory module 150 is configured as the acquiring side, and the receiving side in the image transmission process is connected to the read memory module 150. The receiving side in the image transmission process sends a command to the read memory module 150, which causes the read memory module 150 to acquire the address of the memory area corresponding to the address granule stored in the information buffer 140. The read memory module 150 then reads and outputs the image block in the memory area corresponding to the address granule from the memory 110 based on the address of the memory area corresponding to the address granule.

[0049] Similar to the write memory module 130 , the read memory module 150 includes a buffer to temporarily store image blocks read from the memory 110 .

[0050] Correspondingly, the read memory module 150 further releases the address granule corresponding to the memory area in response to the image block being read out from the memory area, allowing a new image block to be stored in the memory area corresponding to the address granule.

[0051] In one embodiment, the image management chip further includes an input data shifting module 160. The input data shifting module 160 is connected to the write memory module 130 to receive the written image blocks, and shifts and joins the input image blocks to form an image block of a second predetermined size.

[0052] As shown in Figures 3 and 4, P represents a pixel and T represents an image block. As shown in Figure 3, one image block includes multiple rows, for example, the one shown in Figure 3 includes L rows, and each row includes multiple pixels, for example, the one shown in Figure 3 includes K pixels, so that different image blocks have different lengths and widths. In the image transmission process, multiple image blocks need to be arranged in one row of image blocks as shown in Figure 4, so that the lengths and widths of each image block in one row of image blocks are made to match.

[0053] In the image transmission process, the image blocks to be compressed and converted may have different formats, for example, the transmitted components may be of different components, for example, the Y and UV components may have a Y component of 16x8 and a U component of 8x4, and the transmitted images may be of different frames, for example, the image block of one frame may be 16x8 and the image block of another frame may be 8x4, resulting in different image block formats. In this embodiment, an input data shifting module 160 is provided, which receives the image blocks and shifts and joins the input image blocks to form an image block of a second predetermined size, thereby making it possible for the image blocks input to the memory 110 to be image blocks of the same size.

[0054] Accordingly, the image management chip further includes an output data shift module 170. The output data shift module 170 is connected to the read memory module 150 and is configured to shift the image block output by the read memory module 150 so as to restore the pixels in the image block to the input order.

[0055] Through the shifting and splicing of image blocks, the image management chip can temporarily store different types of image blocks, which can meet the needs of temporary image storage in different image transmission scenes.

[0056] Based on the same inventive idea, an embodiment of the present application further provides an image management method, which is used in the image management chip according to any one of the above embodiments, and the image management chip is connected to each of the sending side and the receiving side of image transmission.

[0057] The content of the image management chip described above will be further explained below with reference to an image management method. Figure 5 is a flowchart of an image management method according to an embodiment of the present application. As shown in Figure 5, the image management method includes the following steps:

[0058] S110: In response to writing of an image block, an address granule is allocated to the image block.

[0059] In this embodiment, after the image data is compressed into an image block by the sending side of the image transmission, the image block is sent to the image management chip, the write memory module 130 in the image management chip receives the image block, and the address resource pool 120 allocates an address granule to the image block in response to the image block being written in the write memory module 130.

[0060] In one embodiment, before the image blocks are assigned address granules, the input image blocks are shifted and joined together to form an image block of a second predetermined size.

[0061] If the image management chip needs to support simultaneous writing of multiple image blocks and the written image blocks can be in different formats, in this embodiment, the input data shift module 160 of the image management chip shifts and joins the written image blocks, shifting and joining multiple image blocks to form one or one row of image blocks of a second predetermined size. In this way, the write memory module 130 and the memory can store and manage image blocks of a uniform format, and can realize temporary storage and management of the simultaneous writing of multiple image blocks.

[0062] In the embodiment of the present application, each address granule corresponds to a different memory area in the memory 110, and the address granule is data that records the address of the corresponding memory area. The memory 110 includes a plurality of memory areas each having a first predetermined size.

[0063] During the image transmission process, the format of the image block after image data compression may be different, and the first predetermined size of the memory area will be different accordingly. In addition to the image block, the memory 110 may also store data being processed by other modules. Therefore, when temporarily storing the image block, it is necessary to select a memory 110 with a relatively small memory space that can achieve the function of temporarily storing the image block.

[0064] In this embodiment, the memory 110 can be dynamically configured, i.e., a single relatively large memory 110 is provided, which includes multiple memory units, and the width and depth of the memory units can be configured as needed. In this way, when transmitting an image, the memory 110 including memory units of the required size is used to temporarily store image blocks.

[0065] When dynamically allocating the memory 110, it is necessary to first determine the allocation parameters of the memory 110. In an embodiment of the present application, before allocating address granules to the image blocks, the memory controller determines the allocation parameters of the memory 110 based on a predetermined conversion format, and allocates the memory 110 based on the allocation parameters.

[0066] In this embodiment, the predetermined conversion format is the predetermined compression format of the image block, that is, the format when the image data is compressed with the image block during the image transmission process, which can be directly obtained, and further detailed description will be omitted here.

[0067] The layout parameters of the memory 110 include the number, width, and depth of memory units in the memory 110. Figure 6 is a schematic diagram of a memory unit according to one embodiment of the present application. As shown in Figure 6, Bank Width represents the width of the memory unit, Bank Depth represents the depth of the memory unit, and Granularity0 to GranularityN represent different address granules, i.e., one memory unit can correspond to multiple address granules.

[0068] In this embodiment, since one memory unit can write one row of data at the same time, multiple memory units are provided in the memory to allow different data to be written simultaneously, and each memory unit reads and writes data of at least one row of the image block at a time, i.e., stores data corresponding to at least one address granule. The depth of the memory units is set based on the size of the data to be stored. In this embodiment, the number of memory units is equal to the width of the input image block (i.e., the second predetermined size) divided by the width of the memory unit, and the width of one memory unit is equal to the smaller of the size of the Y component of one row or the size of the UV component of one row in the image block, and the depth of one memory unit is equal to the size of the memory space of the memory 110 divided by the width of the memory 110 and then divided by the memory 110.

[0069] In addition, if the written image blocks include image blocks of different formats, they are shifted and stitched to a unified format, and the placement parameters are determined based on the unified format, that is, the predetermined conversion format may be the second predetermined size input to the shifting and stitching module.

[0070] The predetermined conversion format includes the maximum image width of an image block and the arrangement of the Y and UV components of pixel points in the image block. For example, if the maximum image width of an image block is 4096 pixels (pixel points) and NV12 (image format) is used as an example, as shown in Figure 7, the Y component arrangement is 16x8, i.e., there are a total of 8 rows, with 16 Ys per row, each Y being 1 B byte in size, and each row being 16 B bytes. As shown in Figure 8, the UV component arrangement is 8x4, with 4 rows, with 8 UVs per row, each UV being 2 B bytes in size, and each row being 16 B bytes. Here, the Y and UV components are the Y and UV components of a pixel point, respectively, and one pixel point includes both a Y component and a UV component. One image block consists of multiple pixel points, and the UV component may be the component to be compressed.

[0071] When transmitting image data, image blocks are linearly arranged, and when one row of image blocks is transmitted at a time, memory 110 stores at least one row of image blocks. In the case of the NV12 format described above, the memory space required to store the Y component is 4096 x 1 x 8 = 32 Kbytes, where the maximum image width of the Y component is 4096, 1 ​​is one Y component, and 8 is the number of rows of the Y component. The space required to store the UV component is 2048 x 2 x 4 = 16 Kbytes, where there are only eight UV components in one row, so the width is 2048, half the width of the Y component. Because NV12 is YUV420 compressed, the width of the UV component is half the width of the Y component. Because the UV component includes a U component and a V component, the size of one UV component is 2, and the number of rows of UV components in a single image block is 4. Therefore, the calculated size of memory 110 required is 48 Kbytes.

[0072] The width of one memory unit is the number of bytes of data in one line of an image block (image block width). If multiple types of image blocks are supported, the smallest image block width is selected. For example, in the above example, if the width required for one line of Y components or one line of UV components is the same and both are 16 bytes, the memory unit width is 16 bytes. If the width required for one line of Y components or one line of UV components is different, the smaller of the two is selected as the memory unit width. Also, for example, if the input image block width is 64 bytes, multiple image blocks are joined together to form a width of 64 bytes, and the joined image block is input. The number of memory units required is 64 / 16 = 4. Correspondingly, the depth of one memory unit is 48 x 1024 / 16 / 4 = 768. That is, the memory 110 includes four memory units, each 16 bytes wide and 768 deep.

[0073] In some scenarios, image blocks are transmitted in rows. As shown in FIG. 9, line0 to line3 represent different image block rows, each containing N image blocks. The image blocks in different rows need to be transmitted and stored in different memory units. Because the size of a row of image blocks transmitted at one time may be larger than the first predetermined size, in some embodiments of the present application, multiple address granules are assigned to the image blocks in one row. However, if the image block data stored in the memory areas corresponding to the address granules is relatively small, this will result in wasted memory resource usage. For example, if the size of a row of image blocks is 120 Kbytes and the data size that can be stored in one memory area is 50 Kbytes, three address granules and their corresponding memory areas need to be assigned to the image blocks in that row, and only 20 Kbytes will be stored in the third memory area, resulting in wasted memory space of 30 Kbytes.

[0074] For the above reasons, it is necessary to reasonably set the number of address granules and the first predetermined size of the corresponding memory area. In some embodiments of the present application, the memory controller is configured to set the number of address granules and the first predetermined size based on the layout parameters and the predetermined translation format of the memory 110.

[0075] For example, the number of address granules and the first predetermined size are determined based on the arrangement of the Y and UV components and the maximum image width in a predetermined conversion format. For example, if the maximum image width of an image block is 4096 pixels, and in NV12, the Y component is 16x8, the UV component is 8x4, and the width of the Y and UV components is 16 Kbytes, the first predetermined size is 1 Kbyte. Accordingly, the total memory space size of the memory 110 is 48 Kbytes. In this case, 48 memory areas can be divided and 48 address granules can be set.

[0076] The maximum image width is a multiple of the first predetermined size. For example, if the image width is 768 and the set first predetermined size is 1 KB, then 1024-768=256 bytes of space will be wasted each time one row of image blocks is stored. However, if the first predetermined size is set to 64 bytes, no wasted space will occur because 768 is a multiple of 64.

[0077] Accordingly, the number of information buffers 140 may be determined based on the predetermined conversion format, and the number of information buffers of the first predetermined size is equal to the number of rows of each component in the image block. For example, in the case of the NV12 format, if the Y component has 8 rows and the NV component has 4 rows, eight information buffers 140 are required to store the addresses of the memory areas where the Y component of each row of the image block is stored, and four information buffers 140 are required to store the addresses of the memory areas where the NV component of each row of the image block is stored.

[0078] The size of the memory space of the information buffer 140 may be set based on the size of the memory area address corresponding to the address granule and the number of address granules. Since the memory area address corresponding to the address granule may not be read out in a timely manner, the information buffer 140 may store multiple addresses. For example, the Y component requires eight information buffers 140. The first information buffer 140 stores the Y component address of the 0th row in the image block, and the 8th, 16th, and 24th rows of the Y component of the image block, the second information buffer 140 stores the Y component address of the 1st row in the image block, and the 9th, 17th, and 25th rows of the Y component of the corresponding image block, and so on. The addresses in the preceding information buffers 140 are read out earlier. For example, the first information buffer 140 stores only four addresses, the second and third information buffers 140 store five addresses, the fourth to sixth information buffers 140 store six addresses, and the seventh and eighth information buffers 140 store seven addresses. If the size of one memory area address is 6 bits, all information buffers 140 that store the Y component must store a size of 6 bits×(4+5×2+6×3+7×2)=276 bits.

[0079] Similarly, four information buffers 140 are required to store UV components, and if the first to fourth information buffers 140 store four addresses, five addresses, six addresses, and seven addresses, respectively, then all of the information buffers 140 storing UV components require a total memory space of 6 x (4 + 5 + 6 + 7) = 132 bits.

[0080] S120: The image block is stored in a memory area corresponding to the address granule.

[0081] In this embodiment, different address granules correspond to different memory areas, and an address granule includes the address of the corresponding memory area, so that an image block is stored in the memory area corresponding to the address of the corresponding memory area based on the address of the corresponding memory area in the address granule.

[0082] In an embodiment of the present application, the memory is configured to allow writing of multiple rows of image blocks.

[0083] For example, FIG. 10 is a schematic diagram showing writing of image blocks in multiple rows according to an embodiment of the present application, in which four tables each represent records in which different address granules are stored in the image blocks, bank0 to bank3 each represent different memory units, T0 to T60 each represent image blocks in different rows, and L0 to L3 represent different image blocks in the same row.

[0084] As shown in FIG. 10, when multiple address granules are assigned to one row of image blocks, different image blocks in the row of image blocks are stored in memory units corresponding to different address granules. For example, in the case of four image blocks L0 to L3 in one row of image block T0, the first address granule is assigned to the first image block in each row, the second address granule is assigned to the second image block in each row, and so on. Images in the image blocks in the same row are stored in different memory units using different address granules, and so on.

[0085] Specifically, for each image block in the first row of image block T0, the first image block (T0_L0) is placed at bank0 in the 0th row, the second image block (T0_L1) is placed at bank1 in the first row, the third image block (T0_L2) is placed at bank2 in the second row, and the fourth image block (T0_L3) is placed at bank3 in the third row.

[0086] To utilize all memory units in each row's address granule, that is, to store image blocks uniformly in each memory unit and rationally utilize the space in each memory unit, for the image blocks in row T1, the first image block (T1_L0) is written to bank1 in row 0, the second image block (T1_L1) is written to bank2 in row 1, the third image block (T1_L2) is written to bank3 in row 2, and the fourth image block (T1_L3) is written to bank0 in row 3. In this way, multiple image blocks are written until all 1Kbyte of address memory granules are used.

[0087] S130: When the memory area corresponding to the address granule is filled with the data of the stored image block, the address of the memory area corresponding to the address granule is written to a predetermined information buffer 140.

[0088] In this embodiment, when the memory area is full, the address of the memory area corresponding to the address granule is written to the information buffer 140, so that the address of the memory area is provided to the acquisition side through the information buffer 140, and the acquisition side can read the image block from the memory 110 based on the address.

[0089] If an image block is allocated to multiple address granules, after the memory area corresponding to the current address granule becomes full, the address of the memory area corresponding to the address granule is written to the information buffer 140, and the memory area corresponding to the next address granule continues to store the data of the image block.

[0090] In some embodiments, the image management method further includes S140: S140: The information buffer 140 provides the acquirer with an address of a memory area corresponding to the address granule.

[0091] In this embodiment, the acquiring side is the receiving side or the read memory module 150 in the image transmission process. The read memory module 150 reads the image block from the memory 110 according to the address in the information buffer 140, or the receiving side sends a command to the read memory module 150 to control the read memory module 150 to read the image block from the memory 110 according to the address. After acquiring the image block, the read memory module 150 can output the image block.

[0092] Furthermore, if the image blocks have already been shifted and spliced ​​before being written to the memory 110, the image blocks in the memory area corresponding to the address granule are shifted when output to restore the arrangement order of the image blocks to the order at the time of input. The output data shift module 170 can shift the output image blocks.

[0093] After reading the image block from the memory region, the read memory module 150, in response to reading the image block in the memory region, releases the address granule corresponding to the memory region and returns it to the address resource pool 120. In this way, the address granule can be allocated by the address resource pool 120 to a newly written image block, and the memory region corresponding to the address granule becomes available for overwriting; that is, the released address granule indicates that a new image block can be written to the memory region corresponding to the address granule.

[0094] During image transmission, an image is compressed, and the format of the image block changes as a result of the compression. The image undergoes format conversion, where the image data format is converted to another format. The change in image block format is primarily a change in the UV component. During transmission, the UV component is duplicated to restore the image or change the image format. For example, in YUV420, the Y component and UV component have a 2:1 ratio in the vertical direction, while in YUV444, the Y component and UV component have a 1:1 ratio. When converting an image from YUV420 to YUV444, the UV component in the vertical direction must be interpolated between the UV components of the two adjacent rows above and below, i.e., the UV component must be duplicated once. The specific principles of format conversion can be found in the prior art, and will not be described in detail here.

[0095] In one embodiment of the present application, before releasing the address granule, the image management method further includes the following steps: determine whether the read UV components need to be overlapped based on the initial format when writing the image block and the target format when writing it out; if overlapping is required, rewrite the address of the memory area corresponding to the address granule into the next information buffer 140.

[0096] In this embodiment, when a UV component needs to be used for duplication, it is stored in the next adjacent information buffer 140. Therefore, when the acquiring side acquires the address of that UV component in memory 110 from the next information buffer 140, it reads that UV component from the memory area and outputs it again, thus realizing duplicate output of the UV component, which is equivalent to duplicating and outputting the UV component. Compared to direct duplication and storage, by writing the address to the information buffer 140, the information buffer 140 only needs to store the address, and memory 110 does not need to store the same UV component twice, reducing the amount of UV component data to be stored and reducing the chip area occupied by memory 110.

[0097] For example, FIG. 11 is a schematic diagram illustrating address granule reallocation in a first scene according to an embodiment of the present application. As shown in FIG. 11, G0 to G15 are different address granules, and line0 to line7 are different rows of image blocks. As shown in the first table in FIG. 11, line0 to line3 are respectively assigned to different address granules, and the address granules used for line0 are G0, G4, G8, and G12, respectively. After the image block for line0 is read, address granule reallocation is required, and the address granules corresponding to line0 are respectively assigned to line4 to line7 and used to store the first image block of each row. Similarly, line1 originally corresponds to address granules G1, G5, G9, and G13. After the image block for line1 is read, the address granules are reallocated, i.e., assigned to line4 to line7 and used to store the second image block of each row, and so on, thereby realizing the reuse of each address granule.

[0098] FIG. 12 is a schematic diagram illustrating address granule reallocation in a second scene according to an embodiment of the present application. Similarly, as shown in FIG. 12, G0 to G31 respectively represent different address granules, and line0 represents an image block in a different row. As shown in the first table in FIG. 12, line0 to line7 are respectively assigned to different address granules, and the address granules used for line0 are G0, G8, G16, and G24, respectively. As shown in the second table in FIG. 12, after the image block in line0 is read, address granule reallocation is required, and each address granule corresponding to line0 is assigned to line8 to line11, respectively, and used to store the first image block in each row. As shown in the third table in FIG. 12, line1 originally corresponds to address granules G1, G9, G17, and G25, and after the image block in line1 is read, the address granules are reallocated, i.e., assigned to line12 to line15, and used to store the first image block in each row. As shown in the fourth table in FIG. 12, G2, G10, G18, and G26, which are address granules that originally correspond to line2, are reassigned to line8 to line11, and so on. This allows each address granule to be reused.

[0099] In the embodiment of the present application, the memory 110 requires a smaller chip area to store the same amount of image blocks as a register, and storing image blocks in the memory 110 can reduce the chip area occupied by circuits that temporarily store image blocks during image transmission. Compared to registers, which are directly controlled by the processor, the memory 110 must store a larger amount of data and be controlled by read / write commands. Failure to record image blocks stored in the memory 110 can result in overwriting, duplicated reading, and the like. Therefore, in the embodiment of the present application, address granules are used to record the storage and reading of image blocks. When the address of a memory area corresponding to an address granule is within a predetermined information buffer 140, the image block stored in the memory area can be read, but the image block corresponding to the address granule cannot be overwritten by new data. Therefore, when multiple rows of image blocks are written continuously or simultaneously within a short period of time, using address granules can accurately output image blocks and reduce the possibility of data loss. This allows the address granules and memory 110 to achieve proper storage, management and output of image blocks while occupying a smaller chip area.

[0100] Based on the same inventive idea, an embodiment of the present application further provides an image transmission method. As shown in Figure 13, the image transmission method is used in a scene including a first device 310, a second device 320, and an image management chip 100 according to any of the above embodiments. The first device 310 and the second device 320 are the sender and receiver of the image transmission, respectively.

[0101] 14 is a flowchart of an image transmission method according to an embodiment of the present application. As shown in FIG. 14, the image transmission method includes the following steps:

[0102] S210: The first device compresses the image data into image blocks, and then stores the image blocks using an image management chip.

[0103] In this embodiment, the first device 310 can compress image data, thereby compressing the image data as image blocks for transmission. To transmit the image blocks, the image blocks must be converted into a linear sequential array, so the image blocks can be stored in an image management chip. Because the image blocks are stored in the memory 110 in the image management chip, the memory 110 occupies a smaller chip area than a register storing the same data, which is convenient for later circuit design.

[0104] S220: The second device sends a read command to the image management chip to read an image block from the image management chip.

[0105] In this embodiment, the second device 320 is the receiving end in the image transmission process, and is connected to the information buffer 140, the address resource pool 120, and the memory 110 in the image management chip, respectively. It sends a read command to obtain an address from the information buffer 140, reads an image block from the memory 110 based on the address, and releases the address granule corresponding to the memory area from which the image is read back to the address resource pool 120.

[0106] Based on the same inventive idea, an embodiment of the present application further provides an electronic device, which includes the image management chip according to the above embodiment, and the electronic device is a device for transmitting images.

[0107] The technical features of the above embodiments can be freely combined as long as there is no contradiction, and the combined embodiments fall within the scope of protection of the present application.

[0108] The above are only specific embodiments of the present application, and the scope of protection of the present application is not limited thereto. Any modifications or substitutions made by those skilled in the art within the technical scope disclosed in the present application will fall within the scope of protection of the present application. Therefore, the scope of protection of the present application is subject to the scope of the claims.

[0109] As used herein, the terms "having" and "including" or any variations thereof are intended to cover a non-exclusive inclusion. Thus, a process, method, article, or device that includes a list of elements is not necessarily limited to those elements, but may include elements not specified or other elements inherent to the process, method, article, or device. Unless otherwise specified, an element limited by the expression "comprising" does not exclude the situation where a process, method, article, or device that includes the listed elements also includes other similar elements. [Explanation of symbols]

[0110] 100 Image Management Chip 110 Memory 120 Address Resource Pool 130 Light Memory Module 140 Information Buffer 150 read memory module 160 Input Data Shift Module 170 Output Data Shift Module 310 1st device 320 2nd device

Claims

1. responsive to writing of an image block, allocating address granules to said image block; storing the image block in a memory area corresponding to the address granule; writing an address of the memory area corresponding to the address granule into a predetermined information buffer when the memory area corresponding to the address granule is filled with data of the stored image block; each of the address granules corresponds to a different memory area in a memory, the address granules are data recording the addresses of the corresponding memory areas, the memory includes a plurality of memory areas of a first predetermined size; The information buffer is configured to provide an acquirer of the image block with an address of a memory area corresponding to the address granule, and the acquirer is configured to acquire the image block from the memory based on the address of the memory area corresponding to the address granule. An image management method comprising:

2. Before allocating address granules to the image blocks, the image management method comprises: determining allocation parameters for the memory based on a predetermined conversion format, the allocation parameters being for allocating the memory; The predetermined transformation format is a predetermined compression format of the image block, and the predetermined transformation format includes a maximum image width of the image block and an arrangement manner of Y components and UV components of pixel points in the image block, the Y components being luminance of the pixel points, and the UV components being chrominance of the pixel points; The memory layout parameters include the number, width, and depth of memory units in the memory, the memory is configured by a plurality of the memory units, and the total memory space of the plurality of the memory units is divided into a plurality of memory regions.

2. The image management method according to claim 1.

3. After determining the memory allocation parameters based on a predetermined conversion format, the image management method includes: further comprising setting the number of address granules and the first predetermined size based on the memory layout parameters and the predetermined conversion format.

3. The image management method according to claim 2.

4. the information buffers include a plurality of information buffers corresponding to the Y component and a plurality of information buffers corresponding to the UV component; The step of writing the address of the memory area corresponding to the address granule into a predetermined information buffer includes: and writing an address corresponding to the memory area to an information buffer corresponding to the component type based on the component type of the pixel point written to the memory area, wherein the component type of the pixel point includes the Y component and the UV component.

3. The image management method according to claim 2.

5. After writing the granule information of the address granule to a predetermined information buffer, the image management method includes: providing addresses of memory areas corresponding to the address granules to the acquiring party via the information buffer, so that the acquiring party reads image blocks from the memory areas based on the addresses of the memory areas corresponding to the address granules; and in response to reading an image block in the memory region, freeing address granules corresponding to the memory region; Once an address granule is freed, a new image block can be written to the memory area corresponding to that address granule.

5. The image management method according to claim 1, wherein the image management method is a method for managing an image.

6. The image block includes a UV component, the UV component is a chrominance of a pixel point, the information buffer is plural, and before releasing the address granule, the image management method includes: The method further includes a step of determining whether or not the UV components to be read out need to be used in duplicate based on an initial format when writing the image block and a target format when writing the image block, and if it is determined that the UV components need to be used in duplicate, rewriting the address of the memory area corresponding to the address granule into the next information buffer.

6. The image management method according to claim 5.

7. When the written image block includes a plurality of image blocks, before allocating address granules to the image blocks, the image management method comprises: The method further includes a step of shifting and joining the input image blocks to form an image block of a second predetermined size; Accordingly, after providing the acquiring party with the address of the memory area corresponding to the address granule by the information buffer, the image management method includes: The method further includes a step of shifting the image blocks in the memory area corresponding to the address granule to return the arrangement order of the image blocks to the order at the time of input.

6. The image management method according to claim 5.

8. a memory, an address resource pool, a write memory module, and a plurality of information buffers; the memory includes a plurality of memory areas of a first predetermined size; a plurality of address granules are stored in the address resource pool, different address granules correspond to different memory areas, and the address granules are data recording addresses of the corresponding memory areas; the write memory module is coupled to each of the address resource pool and the memory and configured to receive written image blocks; Each of the information buffers is connected to the write memory module; the address resource pool is configured to allocate address granules to image blocks in response to writing of the image blocks; the write memory module is further configured to store the image block in a memory area corresponding to the address granule; The write memory module is further configured to write an address of the memory area corresponding to the address granule to the information buffer when the memory area corresponding to the address granule is filled with data of the stored image block, the information buffer is configured to provide the address of the memory area corresponding to the address granule to an acquirer of the image block, and the acquirer is configured to acquire the image block from the memory based on the address of the memory area corresponding to the address granule. An image management chip characterized by:

9. The memory is configured to determine allocation parameters of the memory based on a predetermined conversion format, the allocation parameters being for allocating the memory; The predetermined transformation format is a predetermined compression format of the image block, and the predetermined transformation format includes a maximum image width of the image block and an arrangement manner of Y components and UV components of pixel points in the image block, the Y components being luminance of the pixel points, and the UV components being chrominance of the pixel points; The memory layout parameters include the number, width, and depth of memory units in the memory, the memory is configured by a plurality of the memory units, and the total memory space of the plurality of the memory units is divided into a plurality of memory regions.

9. The image management chip according to claim 8.

10. The memory is further configured to set the number of address granules and the first predetermined size based on an arrangement parameter of the memory and the predetermined translation format.

10. The image management chip according to claim 9.

11. the plurality of information buffers include a plurality of information buffers corresponding to the Y component and a plurality of information buffers corresponding to the UV component, The write memory module is further configured to write an address corresponding to the memory area to an information buffer corresponding to the component type based on the component type of the pixel point written to the memory area, and the component type of the pixel point includes the Y component and the UV component.

10. The image management chip according to claim 9.

12. the image management chip further comprises a read memory module; The read memory module is connected to each of the memory, the address resource pool, and the information buffer, and is configured as the acquirer; the read memory module is further configured to obtain an address of a memory area corresponding to the address granule stored in the information buffer, and read and output an image block in the memory area corresponding to the address granule from the memory based on the address of the memory area corresponding to the address granule; The read memory module is further configured to, in response to reading an image block in the memory region, free an address granule corresponding to the memory region, such that, upon freeing the address granule, a new image block can be written to the memory region corresponding to the address granule.

12. The image management chip according to claim 8, wherein the image management chip is a chip for managing an image.

13. The image block includes a UV component, and the UV component is the chrominance of a pixel point. The memory is further configured to determine whether or not the UV component to be read out needs to be used repeatedly based on an initial format when the image block is written and a target format when the image block is written, and if it is determined that the UV component needs to be used repeatedly, write the address of the memory area corresponding to the address granule into the next information buffer.

13. The image management chip of claim 12.

14. The image management chip further includes an input data shift module and an output data shift module; the input data shift module is connected to the write memory module, and is configured to receive the written image blocks, and shift and join the input image blocks to form an image block of a second predetermined size; The output data shift module is connected to the read memory module and configured to shift the image block output by the read memory module to return the pixels in the image block to their input order.

13. The image management chip of claim 12.

15. compressing the image data into image blocks by a first device, and then storing the image blocks by an image management chip according to any one of claims 8 to 14; and sending a read command to the image management chip by a second device to read the image block from the image management chip. An image transmission method comprising:

16. The image management chip according to any one of claims 8 to 14 is provided. An electronic device characterized by:

Images