Sensor package with low aspect ratio through silicon vias

Abstract

The electronic device (100) includes a semiconductor substrate (112) having a first conductive routing structure (121) on a first side (115) of the semiconductor substrate (112) and a low aspect ratio via opening (117) extending from the first side (115) to an opposing second side (116). The electronic device (100) includes a transparent cover (124) on a portion of the first side (115) and covering the patterned first conductive routing structure (121), an insulating layer (131) on the second side (116) including a photosensitive material along a sidewall (118) of the via opening (117), and a second conductive routing structure (132) outside the insulating layer (131), extending through the via opening (117) and directly contacting a portion of the first conductive routing structure (121).

Description

[Background technology]

[0001] Ambient light sensors and CMOS image sensors are electronic devices used to detect light and often include a wafer chip-scale package (WCSP) having a semiconductor die with a sensing area facing upward on a host printed circuit board (PCB). Through-silicon vias (TSVs, also referred to as through-chip vias) route signals from the top side of the die to solder balls or other signal routing on the bottom of the device to help reduce package size. An insulating layer on the backside of the die and semiconductor sidewalls of the TSVs insulates the bottom terminal contacts and is typically made of silicon dioxide (SiO2) deposited by chemical vapor deposition (CVD). However, bottom-side processing is complex and costly due to the long processing times for etching through silicon to form the TSVs and the CVD deposition and patterning of silicon dioxide, which typically requires multiple photolithography processing steps. Summary of the Invention

[0002] In one aspect, an electronic device includes opposing first and second sides, a first conductive routing structure on the first side, and a via opening extending from the first side to the second side. A portion of the first conductive routing structure extends over the via opening, and the semiconductor substrate has a thickness distance between the first and second sides of about 20 μm to 150 μm. The electronic device includes a transparent cover, an insulating layer, and a second conductive routing structure. The transparent cover extends over a portion of the first side of the semiconductor substrate and covers the patterned first conductive routing structure. The insulating layer extends along sidewalls of the via opening on the second side of the semiconductor substrate, the insulating layer comprising a photo-imageable material. The second conductive routing structure extends through the via opening outside the insulating layer and directly contacts a portion of the first conductive routing structure.

[0003] In another aspect, an electronic device includes a semiconductor substrate having opposing first and second sides, a first conductive routing structure on the first side, and a via opening extending from the first side to the second side. A portion of the first conductive routing structure extends over the via opening. The electronic device includes a transparent cover, an insulating layer, and a second conductive routing structure. The transparent cover extends over a portion of the first side of the semiconductor substrate and covers the patterned first conductive routing structure. The insulating layer extends along sidewalls of the via opening on the second side of the semiconductor substrate, the insulating layer including a photosensitive material. The second conductive routing structure extends outside the insulating layer through the via opening and directly contacts a portion of the first conductive routing structure.

[0004] In a further aspect, a method of manufacturing an electronic device includes forming a patterned first conductive routing structure on a first side of a semiconductor substrate; attaching a transparent cover over a portion of the first side of the semiconductor substrate to cover the patterned first conductive routing structure; grinding the second side of the semiconductor substrate to reduce a thickness distance between the first side and the second side; forming a via opening extending from the first side of the semiconductor substrate to the second side of the semiconductor substrate, wherein a portion of the first conductive routing structure extends over the via opening; forming an insulating layer along a sidewall of the via opening on the second side of the semiconductor substrate; and forming a second conductive routing structure outside the insulating layer, wherein the second conductive routing structure extends through the via opening and directly contacts a portion of the first conductive routing structure. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a top perspective view of a sensor electronic device.

[0006] [Figure 1A] FIG. 2 is a bottom perspective view of the electronic device of FIG. 1.

[0007] [Figure 1B] 1B is a partial cross-sectional side view of the electronic device taken along line 1B-1B of FIG. 1.

[0008] [Figure 2] 1 is a flowchart of a method for manufacturing an electronic device.

[0009] [Figure 3] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 4] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 5] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 6] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 7] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 8] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 9] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 10] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 11] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 12] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 13] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 14] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 15] 3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2. [Figure 16]3 is a partial cross-sectional side view of the electronic device of FIGS. 1-1B undergoing fabrication processing according to the method of FIG. 2.

[0010] [Figure 17] FIG. 2 is a partial cross-sectional side view of another electronic device.

[0011] [Figure 18] 1 is a partial cross-sectional side view of a further electronic device.

[0012] [Figure 19] 1 is a cross-sectional side view of a further electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0013] In the drawings, like reference numerals refer to like elements throughout, and various features are not necessarily drawn to scale. Additionally, the term "couple" includes an indirect or direct electrical or mechanical connection, or a combination thereof. For example, when a first device couples to or is coupled to a second device, the connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections. One or more operational characteristics of various circuits, systems, and / or components are described below, in some cases, in the context of the function that results from the configuration and / or interconnection of various structures when the circuit elements are powered and operational. Unless otherwise noted, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0014] 1-1B illustrate an electronic device 100 having a small form factor. Figures 1 and 1A show top and bottom perspective views, respectively, and Figure 1B shows a cross-sectional side view of electronic device 100 taken along line 1B-1B in Figure 1.

[0015] The electronic device 100 has a generally rectangular shape including opposing first and second (e.g., bottom and top) sides 101 and 102, and third, fourth, fifth, and sixth sides 103, 104, 105, and 106, respectively. In one example, the electronic device 100 has a WCSP packaging structure. The electronic device 100 is shown in FIGS. 1-1B in an exemplary position or orientation in three-dimensional space having a first direction X, a perpendicular (orthogonal) second direction Y, and a third direction Z that is perpendicular (orthogonal) to the respective first and second directions X and Y, with features or characteristics along any two of these directions being orthogonal to each other. In the orientation shown, the respective first and second sides 101 and 102 are spaced apart from one another along a third direction Z, the respective third and fourth sides 103 and 104 are spaced apart from one another along a first direction X, and the respective fifth and sixth sides 105 and 106 are spaced apart from one another along a second direction Y.

[0016] The electronic device 100 includes a thin semiconductor substrate 112, such as a die that is or includes silicon or any other suitable semiconductor material, with low-aspect-ratio through-silicon vias to facilitate cost-effective insulator formation, e.g., in some implementations, using a photosensitive material by spin-coating. In one example, the semiconductor substrate 112 has a thickness distance 113 between respective first and second sides 115 and 116 that is less than 150 μm; larger values ​​may make subsequent TSV formation more difficult and / or more expensive. In this or another example, the semiconductor thickness distance 113 is approximately 20 μm or greater; smaller values ​​may be difficult to manufacture.

[0017] As shown in FIG. 1B , the semiconductor substrate 112 has an optional sensing area 114 exposed along an upper, first side 115 of the semiconductor substrate 112. The semiconductor substrate 112 has an opposite (e.g., lower) second side 116. In one example, the sensing area 114 is sensitive to light, and internal circuitry in the semiconductor substrate 112 provides a light sensor with external terminal connections for interfacing the light sensor to a host PCB. The sensing area 114 may be slightly elevated above the first side 115 of the semiconductor substrate 112, as shown in FIG. 1B , or in other implementations, the sensing area 114 may be approximately flush with the first side 115 of the semiconductor substrate 112. In another example, the sensing area 114 is omitted.

[0018] The semiconductor substrate 112 has low aspect ratio via openings 117 that individually extend from a first side 115 of the semiconductor substrate 112 to a second side 116 of the semiconductor substrate 112. The via openings 117 include at least one sidewall 118. In one example, the via openings 117 have a curved shape, such as circular or elliptical, although this is not a requirement for all possible implementations.

[0019] The first conductive routing structure 121 extends on the first side 115 of the semiconductor substrate 112, and the first conductive routing structure 121 is spaced laterally (e.g., along the first direction X as shown in FIG. 1B ) from the sensing area 114. A portion of each first conductive routing structure 121 extends over an associated via opening 117 to enable bottom-side electrical connection to a circuit element or component of the semiconductor substrate 112. In one example, the first conductive routing structure 121 is or includes copper.

[0020] The wafer bond material 122 extends over all or a portion of the first side 115 of the semiconductor die 112. A transparent cover 124 extends over a portion of the first side 115 of the semiconductor substrate 112, providing a top or second side 102 of the electronic device 100. The transparent cover 124 covers the sensing area 114 and the patterned first conductive routing structure 121 and allows light to pass from the second side 102 of the semiconductor substrate 112 to the sensing area 114. In one example, the transparent cover 124 is or includes glass. The transparent cover 124 has a thickness dimension 125 along a third direction Z between a lower or bottom side 126 and an upper or top side 127.

[0021] The wafer bonding material 122, in one example, is a cured adhesive that bonds the transparent cover 124 to the first side 115 of the semiconductor substrate 112. In the illustrated example of FIG. 1B , the wafer bonding material 122 is patterned to extend over the first conductive routing structure 121 and a portion of the first side 115 of the semiconductor substrate 112, but does not extend over the sensing area 114. This example allows for the use of a semi-transparent or non-transparent wafer bonding material 122 while still allowing light to enter the sensing area 114 from the transparent cover 124. In another example, the wafer bonding material 122 is at least partially transparent. In one example, the wafer bonding material 122 is unpatterned, at least partially transparent, and extends over any included sensing area 114. In the illustrated example, the wafer bonding material 122 is patterned to leave a gap 128 between the sensing area 114 and the bottom side 126 of the transparent cover 124, as shown in FIG. 1B .

[0022] 1A and 1B, the electronic device 100 includes an insulating layer 131 on the second side 116 of the semiconductor substrate 112 and along the sidewall 118 of the via opening 117. In one example, the insulating layer 131 includes a photosensitive material. In one example, the insulating layer 131 is or includes a polyimide material. In another example, the insulating layer 131 is or includes a polybenzoxazole (PBO) material. In another example, the insulating layer 131 is or includes a solder mask material. In one example, the insulating layer 131 is a single layer. In another implementation, the insulating layer 131 is a multi-layer structure, for example, including a second photosensitive material.

[0023] 1A and 1B, the electronic device 100 also includes a second conductive routing structure 132 outside the insulating layer 131. The second conductive routing structure 132 extends through the via opening 117 and directly contacts a portion of each of the first conductive routing structures 121. In one implementation, the first and second conductive routing structures 121 and 132 are or include copper. In this or another example, the first and second conductive routing structures 121 and 132 are formed by electroplating, for example, using an associated redistribution layer (RDL) or bonding on active circuit (BOAC) process. The thickness of the second conductive routing structure 132 on the insulating layer 131 sets the final device height 134 (FIG. 1B) for mounting the electronic device 100 on a host system PCB (not shown).

[0024] 1A and 1B, the electronic device 100 in one example also includes solder structures 136 attached to each of the second conductive routing structures 132 so that the electronic device 100 can be soldered to a host PCB. The solder structures 136 extend outward (e.g., downward) from the bottom side 101 of the electronic device 100 along the third direction Z. In the illustrated example, the solder structures 136 are somewhat spherical solder balls, as shown in FIGS. 1A and 1B. In another example, the solder structures 136 are printed solder features (not shown) of any suitable shape attached to each of the second conductive routing structures 132.

[0025] Referring now to FIGS. 2-16, FIG. 2 illustrates a method 200 for manufacturing an electronic device, and FIGS. 3-16 illustrate the electronic device 100 of FIGS. 1-1B undergoing a manufacturing process according to method 200. Method 200, in one example, includes front-end wafer processing at 201 in FIG. 2 to form circuit elements, such as a light-sensing circuit having a sensing area along a top or first side of each of a plurality of unit areas of a starting wafer. FIG. 3 illustrates an example in which a front-end wafer manufacturing process 300 is performed to form light-sensing circuit elements (e.g., transistors, diodes, etc., not shown) within unit areas 301 of a starting semiconductor wafer 302, also referred to herein as a semiconductor substrate. In the illustrated example, wafer 302 includes portions that will become semiconductor substrates 112 of the ultimately formed packaged electronic device 100, which are separated after some of the described process steps, and the remainder of the description will refer to wafer 302 with respect to the portions that will become semiconductor substrates 112.

[0026] The method 200 continues at 202 of FIG. 2 with forming a patterned first conductive routing structure on the first side of the wafer. FIG. 4 shows an example in which a redistribution layer (RDL) or bonding on active circuit (BOAC) process 400 is performed to form a patterned first conductive routing structure 121 in each unit area 301 on the first side 115 of the wafer 302. In one example, a titanium and copper seed layer is deposited (e.g., by sputtering or other deposition technique) on the first side 115 and patterned to extend over areas spaced from the respective sensing areas 114, followed by electroplating to form the first conductive routing structure 121 in each unit area 301 and removal of any remaining portions of the seed layer at 202 of FIG. 2.

[0027] At 204 in Figure 2, the method 200 continues with forming a wafer bonding material on the first side of the wafer. Figure 5 shows an example in which a coating process 500 is performed to coat the wafer bonding material 122 as a layer on the first side 115 of the wafer 302 to cover the patterned first conductive routing structure 121 and any included sensing areas 114 in each unit area 301.

[0028] In one implementation, the method 200 includes optionally patterning the wafer bonding material 122 at 205. Figure 6 shows an example in which the exposure step is performed using a stepper, followed by a development process 600 that removes the wafer bonding material 122 above the sensing area 114. In another implementation, for example, using a transparent wafer bonding material 122, the patterning at 205 is omitted.

[0029] At 206 in FIG. 2 , a glass carrier or other suitable transparent cover is attached. FIG. 7 illustrates an example in which an attachment process 700 is performed to attach a transparent cover 124 onto the wafer bonding material 112 on the first side 115 of the wafer 302 such that the transparent cover 112 covers the sensing area 114 and the patterned first conductive routing structure 121 within each unit area 301. As shown in FIG. 7 , in one example, the attached transparent cover 124 has a starting thickness 702 that is significantly greater than the final thickness dimension 125 along the third direction Z between the lower or bottom side 126 and the upper or top side 127 of the transparent cover 124 described above in connection with FIG. 1B . In the illustrated example, the process 700 adheres the attached transparent cover 124 to the wafer 302 with the wafer bonding material 122, which may include a gap 128 in the case of implementation of the patterned wafer bonding material 122 as shown in FIG. 7 . 7, the attachment process 700 attaches a single transparent cover 124 over the wafer bonding material 122 to cover the entire processed wafer. In another example, an automated pick-and-place machine (not shown) attaches an individual transparent cover 124 to each unit area 301 (not shown). In these or other examples, the attachment process 700 includes a curing step to harden the wafer bonding material 122, for example, using heat, UV exposure, or other suitable technique.

[0030] The method 200 continues at 208 by grinding the second (e.g., back or bottom) side of the wafer 302. FIG. 8 illustrates an example in which a grinding process 800 is performed to remove material from the second side 116 of the wafer 302, for example, by mechanical grinding, chemical-mechanical polishing (CMP), or other suitable material removal technique. In one example, the grinding process 800 reduces the thickness distance 113 between the first side 115 and the second side 116 to 150 μm or less, for example, between about 20 μm and 150 μm. This reduces the aspect ratio of the ultimately formed via opening (e.g., 117 in FIG. 1B above), which facilitates spin-coating processes and simplified patterning when forming the insulating layer 131 using a photosensitive material, helping to reduce manufacturing time, complexity, and cost. The grinding process 800 also helps reduce the overall height of the completed device (e.g., the final device height 134 shown in FIG. 1B) to accommodate high-density circuit board and system designs that utilize the completed electronic device 100.

[0031] The method 200 of FIG. 2 continues at 210, 212, and 214 with the formation of through-silicon vias (TSVs). At 210, a patterned photoresist is formed on the bottom side of the wafer. FIG. 9 illustrates an example in which a process 900 is performed to form a patterned photoresist 902 on the second side 116 of the wafer 302, including depositing a resist material, exposing selected portions of the resist, and removing the exposed portions to provide the patterned photoresist 902 shown in FIG. 9. At 212 of FIG. 2, a via opening is etched through the exposed portions of the wafer. FIG. 10 illustrates an example in which an etching process 1000 is performed using the patterned resist 902 as an etch mask. The etch process 1000 forms a via opening 117 extending from the first side 115 of the wafer 302 to the second side 116 of the wafer 302. 10, the etch process 1000 extends the via openings to expose a portion of each first conductive routing structure 121 in each via opening 117. At 214 of FIG. 2, the patterned resist is removed, for example, by a strip process 1100 shown in FIG.

[0032] At 216 of Figure 2, the method 200 continues by forming a patterned insulating layer on the via sidewalls and bottom second side 116 of the wafer. Figure 12 shows an example in which a deposition process 1200 is performed using any suitable material deposition technique and apparatus to form an insulating layer 131 on the second side 116 of the semiconductor substrate 112, along the sidewalls 118 of the via openings 117. The deposited insulating layer 131 may extend over and cover the exposed portions of the first conductive routing structure 121 in each via opening 117, although this is not required in all implementations.

[0033] Sidewall coverage is advantageous for insulating the semiconductor material of wafer 302 from subsequently formed conductive RDL or BOAC metal inside via openings 117. Continued exposure of a portion of first conductive routing structure 121 within each via opening 117 can alleviate the need for a patterning step prior to metal formation to form TSVs, in which case spin-coat deposition in 216 provides a patterned insulating layer 131 without additional processing time and cost.

[0034] In one example, the deposition process 1200 includes spin-coating a photosensitive (e.g., photosensitive definable) material on the second side 116 of the semiconductor substrate 112 along the sidewall 118 of the via opening 117. In this example or another example, the deposited photosensitive material 131 includes a polyimide material. In the above example or another example, the deposited photosensitive material 131 includes a polybenzoxazole (PBO) material. In the above example or another example, the deposited material 131 includes a solder mask material. One exemplary spin-coating process includes dispensing a photosensitive material, such as a resin fluid, onto the wafer surface, rapidly spinning or rotating the wafer to thin the fluid, and a drying step to remove excess solvent from the resulting film. Different implementations can include static dispensing or dynamic dispensing.

[0035] In one example, a patterning step is performed at 216 to expose a portion of the first conductive routing structure 121 in each via opening 117. Figure 13 shows an example in which a patterning process 1300 is performed to pattern a photosensitive material 131 to expose a portion of the patterned first conductive routing structure 121 in each via opening 117. In one implementation, the patterning process 1300 includes a light exposure or other photo exposure process. In one example, a photosensitive definable material layer 131 is deposited at 216, such as by spin coating or other formation, and the patterning process 1300 includes exposing a portion of the layer 131 to light for development. In another implementation, a coating is formed from a solution on the layer at 216, and the solvent is evaporated from the coating. In this implementation, a positive photoresist is applied over the coating and exposed to a pattern of light via a patterning process 1300, where the exposed portions of the photoresist are removed along with the exposed portions of the polyamic acid coating underneath, after which the remaining photoresist is removed and the polyamic acid coating is imidized, leaving a patterned insulating layer 131 of polyimide.

[0036] 2, patterned second conductive routing features are formed on the bottom side of the wafer and on the patterned insulating layer 131 in the via openings 117, contacting a portion of the first conductive routing structure 121 in each via opening 117. Figure 14 shows an example of an RDL implementation in which a process 1400 is performed to form second conductive routing structures 132 outside of the insulating layer 131 such that the second conductive routing structures 132 extend through each via opening 117 and directly contact exposed portions of each first conductive routing structure 121.

[0037] Method 200 optionally includes forming a patterned photosensitive material on a second side of the wafer at 219 of FIG. 2, for example, as a second layer of multi-layer insulator 131. In another example, material formation at 219 is omitted. Method 200, in one example, includes optional grinding of the transparent cover at 220 of FIG. 2. FIG. 15 shows an example in which a second grinding process 1500 is performed that removes material from the top side 127 of transparent cover 124 to reduce thickness distance 125 of transparent cover 124 from its original starting thickness (e.g., starting thickness distance 702 in FIG. 7 above). In another implementation, grinding of the transparent cover at 220 is omitted. Mounting including grinding at 220 advantageously facilitates handling of thicker transparent covers at 220 during attachment at 206, particularly for attachment of a single transparent cover at 220 over the entire wafer 302, while helping to reduce the overall height of the completed device (e.g., final device height 134 in FIG. 1B above) to accommodate high-density circuit board and system designs using the completed electronic device 100.

[0038] 2 also includes an optional solder ball drop or solder printing operation at 221. Figure 16 shows an example in which a solder ball drop process 1600 is performed to form substantially spherical solder structures 136 (e.g., solder balls) on the second conductive routing structure 132, with the solder structures 136 extending outward from the bottom or first side 101 of the electronic device 100.

[0039] At 222 of Figure 2, method 200 further includes separating the devices or dies. Figure 17 shows an example in which a sawing process 1700 is performed, for example, using a saw, laser cutting, chemical etching, or a combination thereof, to cut the starting wafer along the boundaries between the rows and columns of unit areas 301. The sawing process 1700 separates multiple instances of the completed electronic device 100 from the starting wafer.

[0040] 18 illustrates a cross-sectional side view of another exemplary electronic device 1800 including a low-aspect-ratio through-silicon via to facilitate cost-effective insulator formation, e.g., using a photosensitive material by spin-coating in some implementations. The electronic device 100 includes structures and features 112-118, 121, 124-127, 131, 132, 134, and 136 as described above in connection with FIGS. 1-1B. In this example, the electronic device 1800 includes an unpatterned, transparent, or substantially transparent wafer bonding material 1822 (e.g., the wafer bonding material patterning at 205 in FIG. 2 is omitted). In this example, the wafer bonding material 1822 extends over the sensing area 114 of the semiconductor substrate 112, as well as the first conductive routing structure 121 and a portion of the first side 115 of the semiconductor substrate 112.

[0041] FIG. 19 shows a cross-sectional side view of a further example electronic device 1900 comprising a low-aspect ratio through-silicon via. The electronic device 1900 includes structures and features 112-118, 121, 122, 126-128, 131, 132, and 136 as described above in connection with FIGS. 1-1B. In this example, the wafer bonding material 122 is patterned, which may be transparent or opaque. In another implementation, the transparent wafer bonding material (e.g., 1822 in FIG. 18) need not be patterned. The electronic device 1900 of FIG. 19 has a thicker transparent cover 1924 that extends over a portion of the first side 115 of the semiconductor substrate 112 and provides a top or second side 127 of the electronic device 1900. The device 1900 has a device height dimension 1934 that is larger than the electronic devices 100 and 1800 described above. A transparent cover 1924 covers the sensing area 114 and the patterned first conductive routing structure 121 and allows light to pass from the second side 102 of the semiconductor substrate 112 to the sensing area 114. In one example, the transparent cover 124 is or includes glass. The transparent cover 124 has a thickness dimension 125 along the third direction Z between a lower or bottom side 126 and an upper or top side 127. In this example, the transparent cover 1924 has a thickness 702 along the third direction Z between its bottom side 126 and top side 127, which corresponds to the starting thickness described above in connection with FIG. 7, for example. In one implementation, the second backgrinding operation at 219 of FIG. 2 is omitted when manufacturing the electronic device 1900 of FIG. 19 .

[0042] Unlike higher aspect ratio TVS devices, the described example electronic devices 100, 1800, and 1900 offer low-profile device geometries and smaller device height dimensions, along with manufacturing cost savings. Because the example semiconductor substrate 112 or wafer 302 is back-ground to less than 150 μm before TVS formation, the etching time to form the via opening 117 is significantly shorter than the time required to form an opening through a thicker semiconductor wafer, such as 200-300 μm. The lower aspect ratio of the via opening 117 also facilitates cost-effective spin-coating deposition of the insulating layer 131 using a photosensitive material that can be patterned without adding extra masks to the manufacturing process. This further saves cost and manufacturing time compared to CVD or other slower deposition processes used to fill higher aspect ratio TSV openings with SiO. The combination of the upward-facing light sensing area 114 in some examples with bottom-side TSVs for electrical terminal connection to the host PCB enables top-side light sensing without the need for holes through the host PCB, while providing the advantages of the compact form factor of wafer chip-scale packages using redistribution layers or BOAC signal routing and interconnection technology.

[0043] Modifications may be made to the described examples and other implementations are possible within the scope of the claims.

Claims

1. 1. An electronic device comprising: a semiconductor substrate having opposing first and second sides, a first conductive routing structure on the first side of the semiconductor substrate, and a via opening extending from the first side of the semiconductor substrate to the second side of the semiconductor substrate, wherein a portion of the first conductive routing structure extends over the via opening, and the semiconductor substrate has a thickness distance between the first side and the second side of the semiconductor substrate that is greater than or equal to about 20 μm and less than or equal to 150 μm; a transparent cover on a portion of the first side of the semiconductor substrate, the transparent cover covering the patterned first conductive routing structure; an insulating layer on the second side of the semiconductor substrate and along a sidewall of the via opening, the insulating layer comprising a photo-imageable material; a second conductive routing structure outside the insulating layer, the second conductive routing structure extending through the via opening and directly contacting the portion of the first conductive routing structure; , an electronic device.

2. 10. The electronic device of claim 1, wherein the first and second conductive routing structures comprise copper.

3. 10. The electronic device of claim 1, wherein the transparent cover comprises glass.

4. 10. The electronic device of claim 1, wherein the insulating layer comprises a polyimide material.

5. 10. The electronic device of claim 1, wherein the insulating layer comprises a polybenzoxazole (PBO) material.

6. 10. The electronic device of claim 1, wherein the insulating layer comprises a solder mask material.

7. 10. The electronic device of claim 1, further comprising a solder structure attached to the second conductive routing structure and extending outward from a bottom side of the electronic device.

8. 10. The electronic device of claim 1, wherein the semiconductor substrate includes a sensing area exposed along the first side of the semiconductor substrate and spaced from the first conductive routing structure.

9. 1. An electronic device comprising: a semiconductor substrate having opposing first and second sides, a first conductive routing structure on the first side of the semiconductor substrate, and a via opening extending from the first side of the semiconductor substrate to the second side of the semiconductor substrate, a portion of the first conductive routing structure extending over the via opening; a transparent cover on a portion of the first side of the semiconductor substrate, the transparent cover covering the patterned first conductive routing structure; an insulating layer on a second side of the semiconductor substrate and along a sidewall of the via opening, the insulating layer comprising a polyimide material; a second conductive routing structure outside the insulating layer, the second conductive routing structure extending through the via opening and directly contacting the portion of the first conductive routing structure; , an electronic device.

10. 10. The electronic device of claim 9, wherein the semiconductor substrate has a thickness distance between the first side and the second side that is between about 20 [mu]m and 150 [mu]m.

11. 10. The electronic device of claim 9, wherein the first and second conductive routing structures comprise copper.

12. 10. The electronic device of claim 9, wherein the transparent cover comprises glass.

13. 10. The electronic device of claim 9, further comprising a solder structure attached to the second conductive routing structure and extending outward from a bottom side of the electronic device.

14. 10. The electronic device of claim 9, wherein the semiconductor substrate includes a sensing area exposed along the first side of the semiconductor substrate and spaced from the first conductive routing structure.

15. 1. A method of manufacturing an electronic device, comprising: forming a patterned first conductive routing structure on a first side of a semiconductor substrate; attaching a transparent cover over a portion of the first side of the semiconductor substrate, the transparent cover covering the patterned first conductive routing structure; grinding the second side of the semiconductor substrate to reduce a thickness distance between the first side and the second side to about 20 μm or more and 150 μm or less; forming a via opening extending from the first side of the semiconductor substrate to the second side of the semiconductor substrate, a portion of the first conductive routing structure extending over the via opening; forming an insulating layer on the second side of the semiconductor substrate along sidewalls of the via opening; forming a second conductive routing structure outside the insulating layer; Including, the second conductive routing structure extends through the via opening and directly contacts the portion of the first conductive routing structure; method.

16. 16. The method of claim 15, wherein forming the insulating layer comprises spin-coating a photosensitive material on the second side of the semiconductor substrate and along the sidewalls of the via opening.

17. 17. The method of claim 16, wherein forming an insulating layer further comprises patterning the photosensitive material to expose a portion of the patterned first conductive routing structure in the via opening.

18. 17. The method of claim 16, wherein the photosensitive material comprises a polyimide material.

19. 16. The method of claim 15, wherein the insulating layer comprises a polyimide material.

20. 16. The method of claim 15, wherein the insulating layer comprises a polybenzoxazole material.

21. 16. The method of claim 15, wherein the insulating layer comprises a solder mask material.

22. 16. The method of claim 15, The method further includes forming a solder structure on the second conductive routing structure, the solder structure extending outward from a bottom side of the electronic device.

Images