Method and apparatus for operating a memory device, and memory device

Abstract

A method for operating a memory device having at least one memory unit, e.g., a memory cell, wherein the at least one memory unit has a bistable flip-flop, the method comprising the steps of providing a first current that depends on a state of the bistable flip-flop, which can be characterized, e.g., by a potential of a first circuit node of the bistable flip-flop, and optionally evaluating at least the first current.

Description

[Technical Field]

[0001] The present disclosure relates to a method for operating a memory device. The present disclosure further relates to an apparatus for operating a memory device. The present disclosure further relates to a memory device. Summary of the Invention

[0002] An exemplary embodiment relates to a method for operating a memory device having at least one memory unit, e.g., a memory cell, wherein the at least one memory unit comprises a bistable flip-flop, the method comprising providing a first current that depends on a state of the bistable flip-flop, which can be characterized, e.g., by a potential of a first circuit node of the bistable flip-flop, and optionally evaluating at least the first current.

[0003] Furthermore, combining, eg summing, the first current with at least one further first current of a further, eg similar, memory unit is contemplated. In further exemplary embodiments, this allows, for example, obtaining information about the memory contents of at least one memory unit. In further exemplary embodiments, the principles according to the above embodiments can be applied to multiple memory units, which may for example be present in a memory device, for example, information about the memory contents of multiple memory units of a memory device is obtained, for example simultaneously, which in further exemplary embodiments can be used, for example, to perform arithmetic operations based on the obtained information.

[0004] In a further exemplary embodiment, at least one memory unit is designed as or forms a static RAM (Random Access Memory) memory cell.

[0005] In a further exemplary embodiment, the bistable flip-flop comprises a plurality of field effect transistors, for example of the MOSFET type. In a further exemplary embodiment, the step of providing the first current comprises at least one of the following elements: a) providing the first current from a power source, e.g., external to the bistable flip-flop; b) providing, e.g., deriving, the first current from the bistable flip-flop, e.g., from a first circuit node of the bistable flip-flop.

[0006] In a further exemplary embodiment, the method comprises the step of using, for the providing step, at least one providing transistor, for example designed as a field effect transistor, for example of the MOSFET type.

[0007] In a further exemplary embodiment, the method comprises the steps of connecting a first terminal of a load path of the at least one provide transistor, e.g., with an external power supply; connecting a control terminal, e.g., a gate electrode, of the at least one provide transistor with one or a first circuit node of the bistable flip-flop; and optionally providing a first current to a second terminal of the load path of the at least one provide transistor.

[0008] In a further exemplary embodiment, the step of connecting the first terminal of the load path of the at least one provide transistor with, for example, an external power source is performed via a resistor, and thus, in a further exemplary embodiment, the provide transistor is operable in a voltage follower configuration.

[0009] In a further exemplary embodiment, the method comprises the steps of connecting a first terminal of a load path of the at least one provide transistor with one or a first circuit node of the bistable flip-flop, connecting a control terminal, e.g., a gate electrode, of the at least one provide transistor with, e.g., an external power supply, and optionally providing a first current to a second terminal of the load path of the at least one provide transistor, e.g., by providing a corresponding potential, e.g., by an external power supply.

[0010] In a further exemplary embodiment, the step of connecting the first terminal of the load path of the at least one provide transistor with the first circuit node of the bistable flip-flop is performed via a resistor.

[0011] In a further exemplary embodiment, it is contemplated that at least one memory unit has access transistors controllable via two second control lines associated with the at least one memory unit, e.g., a first control line for controllable connection of a bit line and a bistable flip-flop, respectively, and the step of providing the first current is performed by a current providing device different from the two access transistors. In other words, in a further exemplary embodiment, the first current is not provided by the access transistors.

[0012] However, in further exemplary embodiments, it is also contemplated that the first current is provided by at least one of the access transistors. In a further exemplary embodiment, the method includes outputting a first current onto a first output line.

[0013] A further exemplary embodiment relates to an apparatus for carrying out the method according to the above embodiment. In a further exemplary embodiment, it is contemplated that the apparatus has a current providing device, the current providing device being designed to provide a first current based on a state of the bistable flip-flop, for example based on a potential of a first circuit node of the bistable flip-flop.

[0014] In a further exemplary embodiment, it is envisaged that at least one provide transistor, e.g. designed as a field effect transistor of the MOSFET type, is provided for providing the first current, e.g. the provide transistor is designed to a) provide the first current from a power source external to the bistable flip-flop, e.g., and / or b) provide, e.g. derive, the first current from the bistable flip-flop.

[0015] A further exemplary embodiment relates to a memory device having at least one memory unit, e.g., a memory cell, wherein the at least one memory unit comprises a bistable flip-flop and at least one device according to the above embodiments.

[0016] In a further exemplary embodiment, it is contemplated that the memory device has a control line for controlling the current providing device of at least one, eg, a plurality, eg, all, of the at least one memory unit.

[0017] In a further exemplary embodiment, it is contemplated that at least one, e.g., controllable resistor is provided, and that the current providing devices of at least one, e.g., a plurality, e.g., all, of the memory units can be controlled by a control line via the resistor.

[0018] Further exemplary embodiments relate to a computing device, such as a vector matrix multiplier, having at least one apparatus according to the above embodiments and / or at least one memory device according to the above embodiments.

[0019] Further exemplary embodiments relate to the use of a method according to the above embodiments, and / or an apparatus according to the above embodiments, and / or a memory device according to the above embodiments, and / or a computing device according to the above embodiments for at least one of the following aspects: a) processing currents associated with bistable flip-flops; b) determining a sum of first currents respectively associated with the bistable flip-flops of each memory unit; c) providing a computing device for, e.g., an artificial intelligence algorithm, for performing inference, e.g., of an artificial neural network; d) enhancing, e.g., a conventional memory cell.

[0020] Further features, possible applications and advantages of the invention will become apparent from the following description of exemplary embodiments of the invention as illustrated in the figures of the drawing, wherein all features described or shown, individually or in any combination, constitute the subject of the invention, regardless of their summary or their relationship in the claims, and regardless of their formulation or expression in the text or drawings. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a simplified schematic circuit diagram according to an example embodiment. [Figure 2] 1 is a simplified schematic flowchart in accordance with an exemplary embodiment; [Figure 3] 10 is a simplified schematic flow chart according to a further exemplary embodiment; [Figure 4] FIG. 10 is a simplified schematic circuit diagram according to a further exemplary embodiment. [Figure 5] 10 is a simplified schematic flow chart according to a further exemplary embodiment; [Figure 6] FIG. 10 is a simplified schematic circuit diagram according to a further exemplary embodiment. [Figure 7] 10 is a simplified schematic flow chart according to a further exemplary embodiment; [Figure 8]FIG. 10 is a simplified schematic circuit diagram according to a further exemplary embodiment. [Figure 9] FIG. 10 is a simplified schematic circuit diagram according to a further exemplary embodiment. [Figure 10] FIG. 10 is a simplified schematic block diagram according to a further exemplary embodiment. [Figure 11] 10A-10C are schematic diagrams illustrating modes of use according to further exemplary embodiments; DETAILED DESCRIPTION OF THE INVENTION

[0022] An exemplary embodiment (FIGS. 1, 2) relates to a method for operating a memory device 100 having at least one memory unit 110, e.g., a memory cell, wherein the at least one memory unit 110 comprises a bistable flip-flop KS, the method comprising a step 200 (FIG. 2) of providing a first current I1 that depends on the state of the bistable flip-flop KS, which can be characterized, e.g., by the potential of a first circuit node N1 (FIG. 1) of the bistable flip-flop KS, and optionally a step 202 of evaluating at least the first current I1.

[0023] In further exemplary embodiments, this may, for example, allow obtaining information regarding memory contents of at least one memory unit 110. In further exemplary embodiments, the principles according to the above embodiments may, for example, be applied to multiple memory units, which may be present in a memory device (see, for example, FIG. 8), for example, whereby information regarding memory contents of multiple memory units of a memory device is, for example, obtained simultaneously, which may, in further exemplary embodiments, be usable, for example, to perform arithmetic operations based on the obtained information.

[0024] In a further exemplary embodiment (FIG. 1), at least one memory unit 110 is designed as or forms a static RAM (Random Access Memory) memory cell.

[0025] In a further exemplary embodiment (FIG. 1), a bistable flip-flop KS comprises a number of field-effect transistors T1, T2, T3, T4, for example of the MOSFET type, which are connected, for example, in the manner shown in FIG. 1. The reference symbol BP1 exemplarily denotes a first reference potential, for example, ground potential. The reference symbol BP2 exemplarily denotes a second reference potential, for example, operating voltage potential, which is different from the ground potential BP1.

[0026] Element N1 represents, by way of example, a first circuit node of the bistable flip-flop KS, at which the memory contents of the memory unit 110 are present in the form of a potential, characterizing, for example, one of two possible states, for example "1" or "0." In further exemplary embodiments, the opposite state may be present, for example, in the form of a potential at a second circuit node N2.

[0027] In a further exemplary embodiment (FIG. 1), the at least one memory unit 110 has two access transistors T5, T6, for example of the MOSFET type, which are controllable, for example, via a first control line (which may be referred to as a "word line") SL1, for example, for selective connection of a bistable flip-flop KS with two secondary control lines (which may be referred to as "bit lines") SL2a, SL2b, associated with the at least one memory unit 110.

[0028] For example, when writing to and / or reading from memory unit 100 in a conventional manner, optional access transistors T5, T6 are both activated, i.e., have a gate-source voltage applied to them, for example, which is relatively large above the threshold voltages of access transistors T5, T6, for example, via first control line SL1.

[0029] Thus, when reading, according to a further exemplary embodiment, the potential at at least one of the circuit nodes N1, N2 can be determined via at least one bit line SL2a (or, for example, via both bit lines SL2a, SL2b) and can be detected, for example, by voltage measurement.

[0030] When writing, according to a further exemplary embodiment, a corresponding value is pre-given via at least one bit line SL2a (or e.g. via both bit lines SL2a, SL2b) and can be applied at the bit lines, e.g. in the form of a respective potential.

[0031] In a further exemplary embodiment, reading data from and / or writing data to the memory unit 110 can be performed under appropriate control of the access transistors T5, T6, e.g., by the first control line SL1, while providing 200 the first current I1 (FIG. 2) can be performed, for example, by a device 300 different from the access transistors T5, T6.

[0032] In a further exemplary embodiment, an apparatus 300 for carrying out aspects of a method according to an exemplary embodiment is designed to carry out, for example, an exemplary sequence according to FIG. In a further exemplary embodiment (FIG. 1), it is contemplated that the apparatus 300 has a current providing device 302, which is designed to provide a first current I1 based on the state of a bistable flip-flop KS, for example based on the potential of a first circuit node N1 of the bistable flip-flop KS.

[0033] In a further exemplary embodiment (FIG. 2), the step 200 of providing a first current I1 comprises at least one of the following elements: a) providing 200a the first current I1, e.g., from an external power supply V-ext (FIG. 1) with respect to the bistable flip-flop KS; b) providing, e.g., deriving 200b, the first current I1 from the bistable flip-flop KS, e.g., from a first circuit node N1 of the bistable flip-flop KS.

[0034] In a further exemplary embodiment (FIG. 3), the method comprises a step 210 in which for the providing step, at least one providing transistor 304-1 is used, for example, designed as a field effect transistor, for example of the MOSFET type (see also, for example, the exemplary configuration 100a according to FIG. 4).

[0035] In a further exemplary embodiment (FIGS. 3, 4), the method comprises a step 212 of connecting a first terminal 304a of the load path of the at least one provide transistor 304-1 with, for example, an external power supply V-ext (FIG. 1), for example via a third control line SL3 (FIG. 4), a step 214 of connecting a control terminal, for example, a gate electrode 304b, of the at least one provide transistor 304-1 with one or a first circuit node N1 of the bistable flip-flop KS, and optionally a step 216 of providing a first current I1 to a second terminal 304c of the load path of the at least one provide transistor 304-1.

[0036] In a further exemplary embodiment (FIG. 4), the step 212 of connecting the first terminal 304a of the load path of the at least one provide transistor 304-1 with, for example, an external power supply V-ext is performed via a resistor 306. Thus, in a further exemplary embodiment, the provide transistor 304-1 is operable in a voltage follower configuration.

[0037] In a further exemplary embodiment (FIGS. 5, 6), the method comprises a step 220 in which, for provision, at least one provision transistor 304-2 is used, for example, designed as a field effect transistor, for example of the MOSFET type (see also, for example, the exemplary configuration 100a according to FIG. 6).

[0038] In further exemplary embodiments (FIGS. 5 and 6), the method comprises a step 222 of connecting a first terminal 304a (FIG. 6) of the load path of the at least one provide transistor 304-2 with one or a first circuit node N1 of the bistable flip-flop KS, a step 224 of connecting a control terminal, e.g., the gate electrode 304b, of the at least one provide transistor 304-2 with, e.g., an external power supply V-ext (FIG. 1), e.g., via a third control line SL3, and optionally a step 226 of providing a first current I1 to a second terminal 304c of the load path of the at least one provide transistor 304-2, for example, by providing a corresponding potential by, e.g., the external power supply V-ext, e.g., via the third control line SL3.

[0039] In a further exemplary embodiment (FIGS. 5, 6), the step 222 of connecting the first terminal 304a of the load path of the at least one provide transistor 304-2 with the first circuit node N1 of the bistable flip-flop KS is performed via a resistor 308.

[0040] In further exemplary embodiments (FIGS. 4, 6), the memory devices 100a, 100b are designed to provide a control signal for driving the provide transistors 304-1, 304-2 by a third control line SL3, for example when a first current I1 is provided.

[0041] In further exemplary embodiments (FIGS. 4, 6), memory devices 100a, 100b are designed to synchronize operation of provide transistors 304-1, 304-2 with at least one further operating mode of memory unit 110, e.g., conventional read and / or write, e.g., under corresponding control of at least one of control lines SL1, SL2a, SL2b.

[0042] In further exemplary embodiments (Figures 1, 4, 6), the memory devices 100, 100a, 100b are designed to perform temperature compensation with respect to an external power supply V-ext or with respect to a control signal (e.g., a reference voltage) that can be provided via a third control line SL3.

[0043] In a further exemplary embodiment (FIG. 4), for example, the flip-flop KS is designed to be able to provide a suitable gate-source voltage to the first circuit node N1, for example for providing a first current I1, based on a control signal for the terminal 304a of the provide transistor 304-1, which can be supplied, for example, via the third control line SL3.

[0044] In contrast, in the configuration 100b according to FIG. 6, the gate-source voltage for the provide transistor 304-2 can be provided via a third control line SL3, for example, from an external power supply V-ext (FIG. 1).

[0045] In further exemplary embodiments (Figures 4, 6), the memory devices 100a, 100b have a first output line AL1 and are capable of outputting, e.g., at least temporarily, a first current I1 to and / or via the first output line AL1.

[0046] In further exemplary embodiments (FIGS. 4, 6), the memory devices 100a, 100b may have at least one further memory unit 110′, which in further exemplary embodiments may have the same or at least a similar configuration as the configuration 110 according to FIG. 1, for example.

[0047] In further exemplary embodiments (FIGS. 4, 6), a first current I1 that can be provided by at least one memory unit 110, for example via a first output line AL1, can be combined, for example added, with a first current I1′ that can be provided by at least one further memory unit 110′.

[0048] Thus, in a further exemplary embodiment (FIG. 7), the method has at least one of the following elements: a) a step 230 of outputting a first current I1 to one or a first output line AL1; b) a step 232 of combining, e.g., adding, the first current I1 with at least one further first current I1′ of, e.g., a further, e.g., identical, similar or different, memory unit 110′.

[0049] In a further exemplary embodiment, the exemplary sequence according to FIG. 7 enables, for example, in-memory computing, i.e., aspects of calculation within the memory device, since the first currents I1, I1' of, for example, different memory units 110, 110' of memory devices 100, 100a, 100b are addable, and the first currents I1, I1' of the different memory units 110, 110' each depend on, for example, the memory contents of the associated flip-flops KS of the memory units 110, 110'.

[0050] In a further exemplary embodiment (FIG. 1), it is contemplated that at least one memory unit 110 has the aforementioned access transistors T5, T6 for controllable connection of two second control lines SL2a, SL2b, e.g., bit lines, associated with the at least one memory unit and the bistable flip-flop KS, and that the provision 200 of the first current I1 (FIG. 2) is performed by a current providing device 302 different from the two access transistors T5, T6. In other words, in the further exemplary embodiment, the first current I1 is not provided by the access transistors T5, T6, but by the current providing device 302 including, for example, at least one provide transistor 304-1 (FIG. 4), 304-2 (FIG. 6), for example.

[0051] However, in further exemplary embodiments, it is also contemplated that the first current I1 may be provided by at least one of the access transistors T5, T6. Thus, in some embodiments, for example, the current providing device 302 may be omitted (not shown). In further exemplary embodiments, it is contemplated that the provision 200 of the first current I1 may involve controlling at least one of the access transistors T5, T6 so that the load path of the at least one access transistor T5, T6 is at least partially conductive, e.g., compared to a high-resistance state of the load path of the at least one access transistor T5, T6, and less conductive, e.g., compared to a low-resistance state of the load path of the at least one access transistor T5, T6. In further exemplary embodiments, this may be achieved, for example, by applying a control voltage below a threshold voltage of the at least one access transistor T5, T6 to a control terminal (e.g., gate electrode) of at least one of the two access transistors T5, T6, e.g., via the first control line SL1, e.g., outside of a time range in which, e.g., conventional reading or writing is performed using the at least one access transistor T5, T6.

[0052] A further exemplary embodiment (FIG. 1) relates to a memory device 100 having at least one memory unit 110, e.g., a memory cell, wherein the at least one memory unit 110 has a bistable flip-flop KS and at least one device 300 according to the above embodiment.

[0053] In a further exemplary embodiment (FIG. 1), it is contemplated that the memory device 100 has a control line, e.g., a third control line SL3, for controlling the current providing device 302 of at least one, e.g., a plurality, e.g., all, of the at least one memory unit.

[0054] In other words, in a further exemplary embodiment (FIG. 8) in which the memory device 100c has a plurality of (here, e.g., four) memory units 110-1, 110-2, 110-3, 110-4, a common, e.g., third control line SL3, can be provided that powers the provide transistors 304-1 of a plurality of, e.g., all, memory units 110-1, 110-2, 110-3, 110-4 of the memory device 100c.

[0055] As an example, the memory units 110-1, 110-2, 110-3, 110-4 of the memory device 100c according to FIG. 8 each have the configuration according to FIG. 4, with the gate electrode 304b of the provide transistor 304-1 connected to the first circuit node N1 of the respective bistable flip-flop KS.

[0056] As an example, the memory units 110-1, 110-2, 110-3, 110-4 of the memory device 100c may be organized in a matrix, i.e., in rows and columns, with the memory units 110-1, 110-2, e.g., from FIG. 8, forming a first column and the memory units 110-3, 110-4, e.g., from FIG. 8, forming a second column. The memory units 110-1, 110-2 of the first column output their respective first currents I1-1, I1-2, e.g., to a common first output line AL1, and the memory units 110-3, 110-4 of the second column output their respective first currents I1-3, I1-4, e.g., to a common second output line AL2.

[0057] The element SL1-1 according to FIG. 8 represents a first word line via which the access transistors T5, T6 of a first row, for example having memory units 110-1, 110-3, can be controlled, for example for conventional reading and / or writing.

[0058] The element SL1-2 according to FIG. 8 represents a second word line via which the access transistors T5, T6 of the second row, for example having the memory units 110-2, 110-4, can be controlled, for example for conventional reading and / or writing.

[0059] The elements SL2a, SL2b according to FIG. 8 represent first bit lines via which, for example, the memory units 110-1, 110-2 can be controlled, for example, for conventional reading and / or writing.

[0060] The elements SL2c, SL2d according to FIG. 8 represent second bit lines via which, for example, the memory units 110-3, 110-4 can be controlled, for example, for conventional reading and / or writing.

[0061] In a further exemplary embodiment (FIG. 8), at least one resistor (here two resistors) R1, R2 is provided, and it is contemplated that a current providing device, e.g., provide transistor 304-1, of at least one, e.g., a plurality of, e.g., all, memory units 110-1, 110-2, 110-3, 110-4 is controllable by a third control line SL3 via the resistors R1, R2. In this case, for example, the provide transistor 304-1 of memory units 110-1, 110-2 is controllable by the third control line SL3 via the resistor R1, and the provide transistor 304-1 of memory units 110-3, 110-4 is controllable by the third control line SL3 via the resistor R2.

[0062] In a further exemplary embodiment, resistors R1, R2 may have the same resistance value. In further exemplary embodiments, resistors R1, R2 may have different resistance values.

[0063] Figure 9 shows a further configuration 100d of a memory device according to a further exemplary embodiment, similar to the configuration 100c according to Figure 8. In contrast to Figure 8, the configuration of Figure 9 has controllable resistors RS1, RS2 instead of resistors R1, R2. The controllable resistors RS1, RS2 according to Figure 9 are realized here by way of example by transistors, for example MOSFETs, whose load paths are connected to a third control line SL3 in the same way as the resistors R1, R2 (Figure 8), but whose gate electrodes are now controllable via a common fourth control line SL4, by which, for example, the resistance values ​​of the load paths of the MOSFETs RS1, RS2 can be adjusted.

[0064] FIG. 10 schematically shows a simplified block diagram of a memory device 100e according to a further exemplary embodiment, which here has, by way of example, six memory units 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, which are similar or identical to the configuration 110 according to, for example, FIG. 1 or FIG. 4 or FIG. 6, respectively.

[0065] Elements 310-1, 310-2 represent optional decision devices for the memory contents of the respective memory units, e.g., sense amplifiers, with decision device 310-1 assigned to the first column of memory units 110-1, 110-2, 110-3 and decision device 310-2 assigned to the second column of memory units 110-4, 110-5, 110-6.

[0066] Elements 312-1, 312-2 represent optional determination devices for the currents to be bled through the respective output lines AL1, AL2, which currents correspond, for example, to the sum of the respective first currents I1-1, I1-2, I1-3 or I1-4, I1-5, I1-6 of the corresponding columns of the memory units, which currents can be provided at least temporarily by the respective memory units, for example under the control of control lines SL3-1, SL3-2, SL3-3 (here, for example, each provided at least per row).

[0067] Similarly, control lines SL1-1, SL1-2, SL1-3, each provided per row (i.e., common to all memory units in the same row), can be used to activate (e.g., for conventional reading or writing of the respective memory units) or deactivate optional access transistors T5, T6, as described above, e.g., with reference to control line SL1 according to FIG. 1.

[0068] The memory contents of each memory unit, where the decision device 310-1 is assigned to the first row of memory units 110-1, 110-2, 110-3, and the decision device 310-2 is assigned to the second row of memory units 110-4, 110-5, 110-6.

[0069] Element 314 represents, for example, a central control device for at least temporarily providing at least one control signal for, for example, at least one of the control lines SL1-1, SL1-2, SL1-3, SL3-1, SL3-2, SL3-3. By way of example, control device 314 may be assigned, for example, a temperature compensated reference voltage source V1, from which, in a further exemplary embodiment, at least one control signal for at least one of memory units 110-1, ..., 110-6 can be derived or generated.

[0070] A further exemplary embodiment (FIG. 8) relates to a computing device 400, such as a vector-matrix multiplier VMM, having at least one apparatus 300 (FIG. 1) according to the above embodiments and / or at least one memory device 100, 100a, 100b, 100c, 100d, 100e according to the above embodiments.

[0071] Further exemplary embodiments (FIG. 11) relate to the use 500 of the method according to the above embodiments, and / or the apparatus 300 according to the above embodiments, and / or the memory device 100, 100a, 100b, 100c, 100d, 100e according to the above embodiments, and / or the computing device 400 according to the above embodiments for at least one aspect of: a) processing 501 of a current I1 associated with the bistable flip-flop KS; b) determining 502 the sum of first currents I1, I1′ associated respectively with the bistable flip-flops of the respective memory units; c) providing 503 the computing device 400 for, e.g., in-memory computing relating to, e.g., artificial intelligence algorithms, for performing inference, e.g., of an artificial neural network; d) extending 504, e.g., a conventional memory cell.

[0072] In a further exemplary embodiment (FIG. 10), the functions of devices 310-1, 312-1 or 310-2, 312-2 can be combined, i.e., for each column there can be one composite device, which is designed to read and write the respective memory units and to determine the total current of the first currents I1-1, I1-2, I1-3 of each column.

[0073] In further exemplary embodiments, devices 312-1, 312-2, or the composite devices described above, may be designed as, for example, current-based or current-driven analog-to-digital converter devices.

[0074] In further exemplary embodiments, instead of the analog-to-digital converter devices 312-1, 312-2, for example, one or more of the sense amplifiers or decision devices 310-1, 310-2 may also be provided.

[0075] In further exemplary embodiments, the sense amplifiers or decision devices 310-1, 310-2 may for example have a memory register, which may store a threshold value for detection, which may for example be changeable or pre-set, whereby the operating behavior of the decision devices 310-1, 310-2 may be influenced, for example with regard to reading the contents of the memory unit, and in further exemplary embodiments, for example aspects of the activation function of an artificial neuron may be realised.

[0076] In further exemplary embodiments, the activation function controls, for example, when or under what circumstances, for example, input data or values ​​of input data to one or more (artificial) neurons or their outputs are activated, e.g., comprising, for example, adding up input data and outputting a sum only when a pre-configurable threshold, which may be characterized by the activation function, is exceeded.

[0077] In a further exemplary embodiment, for example, the threshold voltages for the decision devices 310-1, 310-2 may be selected based on the values ​​of memory registers. In a further exemplary embodiment (FIG. 4), the provide transistor 304-1 can be operated in a voltage follower configuration as already described above, e.g., using a digital signal as the control signal, where the voltage at the source electrode follows, e.g., the voltage at the gate electrode.

[0078] In a further exemplary embodiment, the provide transistor 304-1 provides a voltage drop corresponding to, for example, its threshold voltage, where the regulated first current I1 is defined by, for example, the voltage drop across the load path of the provide transistor 304-1.

[0079] In a further exemplary embodiment (FIG. 4), the optional resistor 306 may be replaced, for example, by a transistor, e.g., a MOSFET, which may operate as a controllable resistor and which has, for example, a relatively small footprint for a relatively large resistance value.

[0080] In a further exemplary embodiment (FIG. 8), e.g., with respect to in-memory computing aspects, "Weight 1" for "Kernel 1" may be stored in the first row of matrix-like configuration 100c, and "Weight 2" for "Kernel 1" may be stored in the third row of matrix-like configuration 100c. For example, when a calculation is performed using "Kernel 1", e.g., only rows 1 and 3 are activated, and no resistor sharing is performed.

[0081] In further exemplary embodiments (FIGS. 8, 9), providing the first current 200 (FIG. 2) can be done, for example, by applying a "HIGH" potential to the third control line SL3.

[0082] In a further exemplary embodiment, the memory unit 110, which for example has six transistors T1, T2, T3, T4, T5, T6, can be expanded or supplemented according to the principles according to the invention.

[0083] In further exemplary embodiments, memory units with, for example, more than six transistors T1, T2, T3, T4, T5, T6 can also be extended or supplemented by the principles according to the invention.

[0084] In further exemplary embodiments, for example, at least one memory device 100, 100a, 100b, 100c, 100d according to at least one of Figures 1, 4, 6, 8, 9 may also be assigned to at least one device 310-1, 312-1, 310-2, 312-2, 314 according to Figure 10, for example, for conventional reading and / or writing and / or for determining and / or evaluating a first current of at least one memory unit.

[0085] Help and Support Information The project leading to this application was funded by the Joint Venture ECSEL (Joint Undertaking) under grant agreement No. 826655. The Joint Undertaking receives support from the European Union's Horizon 2020 research and innovation program, as well as from Belgium, France, Germany, the Netherlands and Switzerland.

Claims

1. 1. A method for operating at least one memory unit (110; 110-1, 110-2, 110-3, ...), e.g. a memory device (100; 100a; 100b; 100c; 100d; 100e) having memory cells, wherein the at least one memory unit (110; 110-1, 110-2, 110-3, ...) comprises a bistable flip-flop (KS), the method comprising the steps of: providing (200) a first current (I1) dependent on a state of the bistable flip-flop (KS), which can be characterized, e.g., by a potential of a first circuit node (N1) of the bistable flip-flop (KS); and combining, e.g., adding, (232) the first current (I1) with, e.g., at least one further first current (I1') of a further, e.g., similar, memory unit (110').

2. 2. The method of claim 1, wherein the step of providing the first current (I1) comprises at least one of the following elements: a) providing the first current (I1) from a power supply (V-ext) external to the bistable flip-flop (KS) (200a); b) providing, e.g., deriving, the first current (I1) from the bistable flip-flop (KS) (200b).

3. 3. The method according to claim 1 or 2, comprising a step (210; 220) of using, for the providing step (200), at least one providing transistor (304-1; 304-2), for example designed as a field effect transistor, for example of the MOSFET type.

4. 4. The method of claim 3 when dependent on claim 2, comprising the steps of: connecting (212) a first terminal (304a) of a load path of the at least one provide transistor (304-1) to the power supply (V-ext), e.g., external; connecting (214) a control terminal, e.g., a gate electrode (304b) of the at least one provide transistor (304-1) to one of the bistable flip-flops (KS) or the first circuit node (N1); and optionally providing (216) the first current (I1) to a second terminal (304c) of the load path of the at least one provide transistor (304-1).

5. 5. The method of claim 4, wherein the step of connecting the first terminal of the load path of the at least one provide transistor to the external power supply, for example, V-ext, is performed via a resistor.

6. 4. The method of claim 3 when dependent on claim 2, comprising the steps of: connecting (222) a first terminal (304a) of a load path of the at least one provide transistor (304-2) to one of the bistable flip-flops (KS) or the first circuit node (N1); connecting (224) a control terminal, e.g., a gate electrode (304b) of the at least one provide transistor (304-2) to, e.g., the external power supply (V-ext); and optionally providing (226) the first current (I1) to a second terminal (304c) of the load path of the at least one provide transistor (304-2).

7. 7. The method of claim 6, wherein the step of connecting the first terminal of the load path of the at least one provide transistor with the first circuit node of the bistable flip-flop is performed through a resistor.

8. 8. The method according to claim 1, wherein the at least one memory unit (110; 110-1, 110-2, 110-3, ...) has two access transistors (T5, T6) controllable via a first control line (SL1), respectively, for a controllable connection of the bistable flip-flop (KS) with two second control lines (SL2a, SL2b), e.g., bit lines, associated with the at least one memory unit (110; 110-1, 110-2, 110-3, ...), and wherein the step (200) of providing the first current (I1) is performed by a current providing device (302) different from the two access transistors (T5, T6).

9. Apparatus (300) for carrying out the method according to at least one of claims 1 to 8.

10. 10. The apparatus (300) of claim 9, wherein the apparatus (300) comprises a current providing device (302), the current providing device (302) being designed to provide the first current (I1) based on the state of the bistable flip-flop (KS), for example based on the potential of the first circuit node (N1) of the bistable flip-flop (KS).

11. The device (300) according to claim 9 or 10, wherein at least one providing transistor (304-1; 304-2), for example designed as a field effect transistor of the MOSFET type, is provided for the providing (200) of the first current (I1), for example the providing transistor (304-1) is designed to a) provide the first current (I1), for example from a power supply (V-ext) external to the bistable flip-flop (KS), and / or b) provide, for example derive (200b), the first current (I1) from the bistable flip-flop (KS).

12. A memory device (100; 100a; 100b; 100c; 100d; 100e) having at least one memory unit (110; 110-1, 110-2, 110-3, 110-4), for example a memory cell, wherein the at least one memory unit (110; 110-1, 110-2, 110-3, 110-4) comprises a bistable flip-flop (KS) and at least one device (300) according to at least one of claims 9 to 11.

13. The memory device (100; 100a; 100b; 100c; 100d; 100e) according to claim 12, comprising a control line (SL3) for controlling current providing devices (302) of at least one, e.g. a plurality, e.g. all, of the at least one memory unit (110; 110-1, 110-2, 110-3, 110-4).

14. 14. The memory device (100; 100a; 100b) according to claim 13, wherein at least one, e.g. controllable resistor (R1, R2; RS1, RS2) is provided, via which the current providing device (302) of at least one, e.g. a plurality, e.g. all, memory units (110; 110-1, 110-2, 110-3, 110-4) is controllable by the control line (SL3).

15. A computing device (400), such as a vector matrix multiplier (VMM), comprising at least one apparatus (300) according to at least one of claims 9 to 11 and / or at least one memory device (100; 100a; 100b; 100c; 100d; 100e) according to at least one of claims 12 to 14.

16. a) processing (501) currents associated with the bistable flip-flops (KS); b) determining (502) sums of first currents (I1-1, I1-2, ...) respectively associated with the bistable flip-flops (KS) of each memory unit (110-1, 110-2, 110-3, ...); c) providing a computing device for, e.g., an artificial intelligence algorithm, e.g., for performing inference of an artificial neural network (503); d) using (500) a method according to at least one of claims 1 to 8, and / or an apparatus (300) according to at least one of claims 9 to 11, and / or a memory device (100; 100a; 100b; 100c; 100d; 100e) according to at least one of claims 12 to 14, and / or a computing device (400) according to claim 15, for at least one aspect of: a) processing (501) currents associated with the bistable flip-flops (KS); b) determining (502) sums of first currents (I1-1, I1-2, ...) respectively associated with the bistable flip-flops (KS) of each memory unit (110-1, 110-2, 110-3, ...); c) providing a computing device for, e.g., an artificial intelligence algorithm, e.g., for performing inference of an artificial neural network (503); d) extending (504) e.g., a conventional memory cell.

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