Driving circuit, driving method, driving module and display device

Abstract

A driving circuit, a driving method, a driving module, and a display device are provided. The driving circuit includes a first driving signal generating circuit (110), a first output control circuit (112), a first gating circuit (111), a first first energy storage circuit (114), a first second energy storage circuit (115), and a first output circuit (113). The first gating circuit (111) controls a gating input signal to be written to a first first node (N1-1) under the control of a gating control signal. The first output circuit (113) controls the potential of the first second node (N1-2) to connect the Nth (N is a positive integer) stage output drive terminal (NO(N)) and the first voltage terminal (V1) to each other, and controls the potential of the first third control node (NC1-3) to connect the Nth stage output drive terminal (NO(N)) and the second voltage terminal (V2) to each other. The first third control node (NC1-3) and the first second control node (NC1-2) are different nodes. By controlling the gating input signal, it is possible to update a portion of the display screen and reduce power consumption.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to PCT application No. PCT / CN2022 / 140042, filed on December 19, 2022, PCT application No. PCT / CN2022 / 140046, PCT application No. PCT / CN2022 / 140044, and PCT application No. PCT / CN2022 / 140045, the entire contents of which are incorporated by reference. The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module and a display device. [Background technology]

[0002] In related technology, when updating the screen of an OLED (organic light-emitting diode) display, pixel voltages must be initialized and written to all rows of pixel circuits within one frame time. On the other hand, for some special screens (e.g., always-on display (AOD) screens (AOD screens are screens that control localized lighting of the screen without lighting the entire screen), still screens, or screens with few updates), most pixel circuits across the entire screen do not need to have their pixel voltages updated. In other words, most pixel circuits can maintain their conventional display brightness using low-leakage LTPO (low-temperature poly-oxide) TFTs (thin-film transistors). Repeated refreshing and writing to these pixel circuits results in wasted power consumption. Summary of the Invention

[0003] In one aspect, an embodiment of the present disclosure provides a drive circuit including a first drive signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit, and a first output circuit. The first drive signal generation circuit, which is electrically connected to a first first control node, a first second control node, and an Nth (N is a positive integer) stage drive signal output terminal, generates an Nth stage drive signal under the control of the potential of the first first control node and the potential of the first second control node, and outputs the Nth stage drive signal via the Nth stage drive signal output terminal. The first output control circuit, which is electrically connected to the first first node, the first first control node, and the first second node, respectively, controls the first first control node and the first second node to be conductive under control of the potential of the first first node. The first gating circuit, which is electrically connected to a first first node, a gating input terminal, and a gating control terminal, controls the gating input signal supplied from the gating input terminal to be written to the first first node under the control of a gating control signal supplied from the gating control terminal. The first first energy storage circuit, which is electrically connected to the first first node and the first second node, controls the potential of the first second node based on the potential of the first first node. The first second energy storage circuit, which is electrically connected to a first third control node and an N-stage output drive terminal, which are nodes different from the first second control node, controls the potential of the first third control node based on the N-stage drive output signal supplied from the N-stage output drive terminal. The first output circuit, which is electrically connected to the first second node, the first third control node, the first voltage terminal, the second voltage terminal, and the N-stage output drive terminal, controls the N-stage output drive terminal and the first voltage terminal to be electrically connected together under control of the potential of the first second node, and controls the N-stage output drive terminal and the second voltage terminal to be electrically connected together under control of the potential of the first third control node.

[0004] Optionally, the first gating circuit controls the gating input signal supplied from the gating input terminal to be written to the first first node when the potential of the first third node of the N-1th stage is a second voltage and the potential of the Nth stage driving signal is a second voltage.

[0005] Optionally, the first gating circuit includes a first first transistor, a gate of the first first transistor electrically connected to the gating control terminal, a first pole of the first first transistor electrically connected to the first first node, and a second pole of the first first transistor electrically connected to the gating input terminal.

[0006] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal, and the first gating circuit includes a first first transistor and a first second transistor. The gate of the first first transistor is electrically connected to a first gating control terminal, the first pole of the first first transistor is electrically connected to the first first node, and the second pole of the first first transistor is electrically connected to the first pole of the first second transistor. The gate of the first second transistor is electrically connected to a second gating control terminal, and the second electrode of the first second transistor is electrically connected to the gating input terminal. The first gating control terminal is an Nth stage driving signal output terminal, the second gating control terminal is a first third node of an N-1th stage, and the first first transistor and the first second transistor are both p-type transistors. Alternatively, the first gating control terminal is a first third node of the (N-1)th stage, the second gating control terminal is an Nth stage driving signal output terminal, and the first first transistor and the first second transistor are both p-type transistors. Alternatively, the first gating control terminal is an (N-1)th stage driving signal output terminal, the second gating control terminal is an Nth stage driving signal output terminal, the first first transistor is an n-type transistor, and the first second transistor is a p-type transistor. Alternatively, the first gating control terminal is an N-th stage driving signal output terminal, the second gating control terminal is an N-1-th stage driving signal output terminal, the first first transistor is a p-type transistor, and the first second transistor is an n-type transistor. Alternatively, an inverted signal of the N-1th stage driving signal is input to the first gating control terminal, the second gating control terminal is an Nth stage driving signal output terminal, and the first first transistor and the first second transistor are both p-type transistors. Alternatively, the first gating control terminal is an Nth stage driving signal output terminal, an inverted signal of an N-1th stage driving signal is input to the second gating control terminal, and the first first transistor and the first second transistor are both p-type transistors. Alternatively, the first gating control terminal is an (N-1)th stage driving signal terminal, an inverted signal of the (N)th stage driving signal is input to the second gating control terminal, and the first first transistor and the first second transistor are both n-type transistors. Alternatively, an inverted signal of an Nth stage driving signal is input to the first gating control terminal, the second gating control terminal is an N-1th stage driving signal terminal, and the first first transistor and the first second transistor are both n-type transistors.

[0007] Optionally, the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor. A first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node. A first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage output drive terminal.

[0008] Optionally, the first output control circuit includes a first third transistor, a gate of the first third transistor electrically connected to the first first node, a first pole of the first third transistor electrically connected to the first first control node, and a second pole of the first third transistor electrically connected to the first second node.

[0009] Optionally, the drive circuit according to at least one embodiment of the present disclosure further includes a first second node control circuit, which is electrically connected to a first third control node, a first second node, and a first voltage terminal, respectively, and controls the first second node and the first voltage terminal to be electrically connected to each other under control of the potential of the first third control node.

[0010] Optionally, the drive circuit according to at least one embodiment of the present disclosure further includes a first second node control circuit, which is electrically connected to a first third control node, the Nth stage output drive terminal, a first second node, and a first voltage terminal, and controls the first second node and the first voltage terminal to be conductive under control of the potential of the first third control node and an Nth stage drive output signal supplied from the Nth stage output drive terminal.

[0011] Optionally, the first second node control circuit includes a first fourth transistor, a gate of the first fourth transistor electrically connected to the first third control node, a first pole of the first fourth transistor electrically connected to the first second node, and a second pole of the first fourth transistor electrically connected to a first voltage terminal.

[0012] Optionally, the first second node control circuit includes a first fourth transistor and a first control transistor. A gate of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to a first voltage terminal. A gate of the first control transistor is electrically connected to the Nth stage output drive terminal, and a first electrode of the first control transistor is electrically connected to the first second node.

[0013] Optionally, the first output circuit includes a first fifth transistor, a first sixth transistor, and a first third capacitor. A gate of the first fifth transistor is electrically connected to the first second node, a first electrode of the first fifth transistor is electrically connected to a first voltage terminal, and a second electrode of the first fifth transistor is electrically connected to the Nth stage output drive terminal. A gate of the first sixth transistor is electrically connected to the first third control node, a first electrode of the first sixth transistor is electrically connected to the N-th stage output driving terminal, and a second electrode of the first sixth transistor is electrically connected to a second voltage terminal. A first terminal of the first third capacitor is electrically connected to the first second node, and a second terminal of the first third capacitor is electrically connected to the first voltage terminal.

[0014] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit, which is electrically connected to an initial control terminal, a second voltage terminal, and a first first node, and controls the first first node and the second voltage terminal to be electrically connected to each other under control of an initial control signal supplied from the initial control terminal.

[0015] Optionally, the drive circuit according to at least one embodiment of the present disclosure further includes a first first-node control circuit, which is electrically connected to a first fourth node, a second voltage terminal, and the first first node, respectively, and controls the first first node and the second voltage terminal to be electrically connected together under control of the potential of the first fourth node.

[0016] Optionally, the first initialization circuit includes a first seventh transistor, a gate of the first seventh transistor electrically connected to the initial control terminal, a first pole of the first seventh transistor electrically connected to the first first node, and a second pole of the first seventh transistor electrically connected to a second voltage terminal.

[0017] Optionally, the first first node control circuit includes a first eighth transistor, a gate of the first eighth transistor electrically connected to the first fourth node, a first pole of the first eighth transistor electrically connected to the first first node, and a second pole of the first eighth transistor electrically connected to a second voltage terminal.

[0018] Optionally, the drive circuit according to at least one embodiment of the present disclosure further includes a first third control node control circuit, which is electrically connected to a first first node, a first fifth node, a first second control node, a first third control node, and a first sixth node, respectively, and controls, under control of a potential of the first first node, to bring the first fifth node and the first third control node into conduction, and controls, under control of a potential of the first sixth node, to bring the first second control node and the first sixth node into conduction, and controls the first sixth node and the first third control node into conduction.

[0019] Optionally, the first third control node control circuit includes a first ninth transistor, a first tenth transistor, and a first eleventh transistor. A gate of the first ninth transistor is electrically connected to the first first node, a first pole of the first ninth transistor is electrically connected to the first fifth node, and a second pole of the first ninth transistor is electrically connected to the first third control node. The gate of the first tenth transistor and the second electrode of the first tenth transistor are both electrically connected to the first sixth node, and the first electrode of the first tenth transistor is electrically connected to the first second control node. The gate of the first 11th transistor and the first pole of the first 11th transistor are both electrically connected to the first sixth node, and the second pole of the first 11th transistor is electrically connected to the first third control node.

[0020] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first output pull-down circuit, which is electrically connected to the first first control node, the N-stage driving signal output terminal, and a second voltage terminal, and controls the N-stage driving signal output terminal and the second voltage terminal to be electrically connected to each other under control of the potential of the first first control node.

[0021] Optionally, the first drive signal generation circuit includes a first first drive output circuit, a first second drive output circuit, a first first control node control circuit, and a first second control node control circuit. The first first control node control circuit controls the potential of the first first control node. The first second control node control circuit controls the potential of the first second control node. The first first drive output circuit, which is electrically connected to the first first control node, a first voltage terminal, and an N-stage drive signal output terminal, respectively, controls the N-stage drive signal output terminal and the first voltage terminal to be electrically connected together under the control of the potential of the first first control node. The first second drive output circuit, which is electrically connected to the first second control node, a second voltage terminal, and an N-stage drive signal output terminal, respectively, controls the N-stage drive signal output terminal and the second voltage terminal to be electrically connected together under the control of the potential of the first second control node.

[0022] Optionally, the first first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit. The first seventh node control circuit, which is electrically connected to a seventh node, a second voltage terminal, a first clock signal terminal, and a first fifth node, respectively, controls the first seventh node and the second voltage terminal to be electrically connected together under control of a first clock signal supplied from the first clock signal terminal, and controls the first seventh node and the first clock signal terminal to be electrically connected together under control of the potential of the first fifth node. The first eighth node control circuit, which is electrically connected to the second voltage terminal, the first seventh node, and the first eighth node, respectively, controls the first seventh node and the first eighth node to be conductive under the control of a second voltage signal supplied from the second voltage terminal. The first third node control circuit, which is electrically connected to the first eighth node, the second clock signal terminal, and the first third node, respectively, controls the electrical connection between the first third node and the second clock signal terminal under control of the potential of the first eighth node, and controls the potential of the first third node based on the potential of the first eighth node. The first first control circuit, which is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node, and the first voltage terminal, respectively, controls the first third node and the first first control node to be electrically connected together under control of a second clock signal supplied from the second clock signal terminal, and controls the first first control node and the first voltage terminal to be electrically connected together under control of the potential of the first fifth node.

[0023] Optionally, the first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit. The first sixth node control circuit, which is electrically connected to the second voltage terminal, the first ninth node, the first sixth node, and the first fourth node, respectively, controls the first ninth node and the first sixth node to be conductive under the control of a second voltage signal supplied from the second voltage terminal, and controls the potential of the first sixth node based on the potential of the first fourth node. The first fifth node control circuit, which is electrically connected to the N-1th stage drive signal output terminal, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, controls the first fifth node and the N-1th stage drive signal output terminal to be electrically connected together under the control of a first clock signal supplied from the first clock signal terminal, and controls the first fifth node and the first voltage terminal to be electrically connected together under the control of an initial control signal supplied from the initial control terminal. The first 9th node control circuit, which is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal, and the first 9th node, respectively, controls the first 9th node and the N-1th stage drive signal output terminal to be electrically connected together under the control of the first clock signal supplied from the first clock signal terminal. The first fourth node control circuit, which is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal, and the first sixth node, respectively, controls the first fourth node and the first voltage terminal to be electrically connected together under control of the potential of the first seventh node, and controls the first fourth node and the second clock signal terminal to be electrically connected together under control of the potential of the first sixth node. The first second control circuit, which is electrically connected to the second voltage terminal, the first fifth node, and the first second control node, respectively, controls the first fifth node and the first second control node to be conductive under the control of a second voltage signal supplied from the second voltage terminal.

[0024] Optionally, the first seventh node control circuit includes a first twelfth transistor and a first thirteenth transistor, the first eighth node control circuit includes a first fourteenth transistor, the first third node control circuit includes a first fifteenth transistor and a first fourth capacitor, and the first first control circuit includes a first sixteenth transistor and a first seventeenth transistor. A gate of the first twelfth transistor is electrically connected to a first clock signal terminal, a first electrode of the first twelfth transistor is electrically connected to a second voltage terminal, and a second electrode of the first twelfth transistor is electrically connected to a first seventh node. A gate of the first thirteenth transistor is electrically connected to a first fifth node, a first pole of the first thirteenth transistor is electrically connected to the first seventh node, and a second pole of the first thirteenth transistor is electrically connected to a first clock signal terminal. A gate of the first fourteenth transistor is electrically connected to a second voltage terminal, a first electrode of the first fourteenth transistor is electrically connected to the first seventh node, and a second electrode of the first fourteenth transistor is electrically connected to the first eighth node. A gate of the first 15th transistor is electrically connected to the first 8th node, a first pole of the first 15th transistor is electrically connected to a second clock signal terminal, and a second pole of the first 15th transistor is electrically connected to the first 3rd node. A first terminal of the first fourth capacitor is electrically connected to a first eighth node, and a second terminal of the first fourth capacitor is electrically connected to a first third node. A gate of the first 16th transistor is electrically connected to the second clock signal terminal, a first pole of the first 16th transistor is electrically connected to the first third node, and a second pole of the first 16th transistor is electrically connected to the first first control node. A gate of the first 17th transistor is electrically connected to a first 5th node, a first electrode of the first 17th transistor is electrically connected to a first 1st control node, and a second electrode of the first 17th transistor is electrically connected to a first voltage terminal.

[0025] Optionally, the first sixth node control circuit includes a first eighteenth transistor and a first fifth capacitor, the first fifth node control circuit includes a first nineteenth transistor and a first twentieth transistor, the first ninth node control circuit includes a first twenty-first transistor, the first fourth node control circuit includes a first twenty-second transistor and a first twenty-third transistor, and the first second control circuit includes a first twenty-fourth transistor. A gate of the first 18th transistor is electrically connected to a second voltage terminal, a first electrode of the first 18th transistor is electrically connected to a first 9th node, and a second electrode of the first 18th transistor is electrically connected to a first 6th node. A first terminal of the first fifth capacitor is electrically connected to the first fourth node, and a second terminal of the first fifth capacitor is electrically connected to the first sixth node. A gate of the first 19th transistor is electrically connected to a first clock signal terminal, a first electrode of the first 19th transistor is electrically connected to an N-1th stage driving signal output terminal, and a second electrode of the first 19th transistor is electrically connected to a first 5th node. A gate of the first twentieth transistor is electrically connected to an initial control terminal, a first electrode of the first twentieth transistor is electrically connected to a first voltage terminal, and a second electrode of the first twentieth transistor is electrically connected to the first fifth node. The gate of the first 21st transistor is electrically connected to a first clock signal terminal, the first pole of the first 21st transistor is electrically connected to an N-1th stage driving signal output terminal, and the second pole of the first 21st transistor is electrically connected to a first 9th node. The gate of the first 22nd transistor is electrically connected to a first 7th node, the first electrode of the first 22nd transistor is electrically connected to a first voltage terminal, and the second electrode of the first 22nd transistor is electrically connected to a first 4th node. The gate of the first 23rd transistor is electrically connected to the first 6th node, the first pole of the first 23rd transistor is electrically connected to the first 4th node, and the second pole of the first 23rd transistor is electrically connected to a second clock signal terminal. A gate of the first 24th transistor is electrically connected to a second voltage terminal, a first electrode of the first 24th transistor is electrically connected to a first 9th node, and a second electrode of the first 24th transistor is electrically connected to a first second control node.

[0026] Optionally, the first first driving output circuit includes a first 25th transistor and a first 6th capacitor, and the first second driving output circuit includes a first 26th transistor and a first 7th capacitor. A gate of the first 25th transistor is electrically connected to the first first control node, a first electrode of the first 25th transistor is electrically connected to a first voltage terminal, and a second electrode of the first 25th transistor is electrically connected to an N-stage driving signal output terminal. A first terminal of the first sixth capacitor is electrically connected to the first first control node, and a second terminal of the first sixth capacitor is electrically connected to a first voltage terminal. The gate of the first 26th transistor is electrically connected to the first second control node, the first electrode of the first 26th transistor is electrically connected to the Nth stage driving signal output terminal, and the second electrode of the first 26th transistor is electrically connected to the second voltage terminal. A first terminal of the first seventh capacitor is electrically connected to the N-th stage drive signal output terminal, and a second terminal of the first seventh capacitor is electrically connected to a second voltage terminal.

[0027] Optionally, the first output pull-down circuit includes a 27th first transistor, a gate of the 27th first transistor electrically connected to the 1st first control node, a first pole of the 27th first transistor electrically connected to the Nth stage driving signal output terminal, and a second pole of the 27th first transistor electrically connected to the second voltage terminal.

[0028] In a second aspect, an embodiment of the present disclosure provides a driving method to be applied to the above-mentioned driving circuit, the driving method comprising: the first drive signal generation circuit generates an Nth stage drive signal (N is a positive integer) under control of the potential of the first first control node and the potential of the first second control node, and outputs the Nth stage drive signal via an Nth stage drive signal output terminal; a first output control circuit controlling the first first control node and the first second node to be electrically connected under control of a potential of the first first node; a first gating circuit controlling, under control of a gating control signal, a gating input signal to be written to a first first node; a first first energy storage circuit controlling a potential of the first second node based on a potential of the first first node; the first second energy storage circuit controls the potential of the first third control node based on an N-stage drive output signal supplied from an N-stage output drive terminal; the first output circuit controls the N-stage output drive terminal and the first voltage terminal to be electrically connected together under control of the potential of the first second node, and the first output circuit controls the N-stage output drive terminal and the second voltage terminal to be electrically connected together under control of the potential of the first third control node; The first third control node and the first second control node are different nodes.

[0029] In a third aspect, an embodiment of the present disclosure provides a driving module including a plurality of stages of the above-mentioned driving circuits, wherein an Nth (N is a positive integer) stage driving circuit is electrically connected to a driving signal output terminal included in an N-1th stage driving circuit.

[0030] In a fourth aspect, an embodiment of the present disclosure provides a display device including the driving module described above. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 2 is a configuration diagram of a drive circuit according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a circuit diagram of a related pixel circuit. [Figure 3] FIG. 3 is an operation timing diagram of the related pixel circuit shown in FIG. 2. [Figure 4] FIG. 2 is a circuit diagram of a related pixel circuit. [Figure 5] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 7] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 10] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 11] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 12] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 13] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 14] FIG. 2 is a circuit diagram of at least one embodiment of a first gating circuit in a driving circuit according to an embodiment of the present disclosure. [Figure 15] FIG. 2 is a circuit diagram of at least one embodiment of a first inverter. [Figure 16] FIG. 2 is a circuit diagram of at least one embodiment of a second inverter. [Figure 17A] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 17B] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 18A] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 18B] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 18C] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 18D] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 19A] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 19B] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 19C] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 19D] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 20A] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 20B] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 20C] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 20D] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 21A]FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 21B] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 21C] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 21D] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 22A] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 22B] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 22C] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 22D] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 23] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 24A] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 24B] FIG. 25 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 24. [Figure 25] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 26] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 27] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 28] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 29] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 30] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 31] FIG. 2 is a configuration diagram of a drive circuit according to an embodiment of the present disclosure. [Figure 32] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 33] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 34] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 35] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 36] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 37] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 38] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 39] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 40] FIG. 40 is a timing diagram of the operation of at least one embodiment of the drive circuit shown in FIG. 39. [Figure 41] FIG. 40 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 39. [Figure 42] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 43] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 44] FIG. 2 is a configuration diagram of a drive circuit according to an embodiment of the present disclosure. [Figure 45] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 46] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 47] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 48] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 49]FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 50] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 51] FIG. 51 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 50. [Figure 52] FIG. 51 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 50. [Figure 53] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 54] FIG. 54 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 53. [Figure 55] FIG. 2 is a configuration diagram of a drive circuit according to an embodiment of the present disclosure. [Figure 56] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 57] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 58] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 59] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 60] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 61] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 62] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 63] FIG. 63 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 62. [Figure 64] FIG. 63 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 62. [Figure 65] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 66] FIG. 66 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 65. [Figure 67] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 68] FIG. 68 is an operational timing diagram of at least one embodiment of the drive circuit shown in FIG. 67. [Figure 69] FIG. 2 is a configuration diagram of a drive circuit according to an embodiment of the present disclosure. [Figure 70] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 71] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 72] FIG. 1 is a block diagram of a drive circuit in accordance with at least one embodiment of the present disclosure. [Figure 73] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 74] FIG. 74 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 73. [Figure 75] FIG. 74 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 73. [Figure 76] FIG. 1 is a circuit diagram of a driver circuit in accordance with at least one embodiment of the present disclosure. [Figure 77] FIG. 77 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 76. [Figure 78] FIG. 1 is a block diagram of a drive module in accordance with at least one embodiment of the present disclosure. [Figure 79] FIG. 79 is an operational timing diagram of at least one embodiment of the drive module shown in FIG. 78. [Figure 80] 3 is a waveform diagram of a first clock signal supplied from GCK and a second clock signal supplied from GCB. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0032] The following clearly and completely describes the technical aspects of the embodiments of the present disclosure in connection with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0033] The transistors used in all the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish between the two poles other than the gate of the transistor, one pole is called the first pole and the other pole is called the second pole.

[0034] In actual operation, if the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain and the second pole may be a source, or the first pole may be a source and the second pole may be a drain.

[0035] As shown in FIG. 1, the driving circuit according to an embodiment of the present disclosure includes a first driving signal generating circuit 110, a first gating circuit 111, a first output control circuit 112, a first output circuit 113, a first first energy storage circuit 114, and a first second energy storage circuit 115. The first drive signal generating circuit 110, which is electrically connected to the first first control node NC1-1, the first second control node NC1-2, and the Nth (N is a positive integer) stage drive signal output terminal NS(N), generates an Nth stage drive signal under the control of the potential of the first first control node NC1-1 and the potential of the first second control node NC1-2, and outputs it via the Nth stage drive signal output terminal NS(N). The first gating circuit 111, which is electrically connected to the first first node N1-1, the gating input terminal VCT, and the gating control terminal CX, controls the gating input signal supplied from the gating input terminal VCT to be written to the first first node N1-1 under the control of the gating control signal supplied from the gating control terminal CX. The first output control circuit 112, which is electrically connected to the first first node N1-1, the first first control node NC1-1, and the first second node N1-2, respectively, controls the first first control node NC1-1 and the first second node N1-2 to be conductive under control of the potential of the first first node N1-1. The first first energy storage circuit 114, electrically connected to the first first node N1-1 and the first second node N1-2, controls the potential of the first second node N1-2 based on the potential of the first first node N1-1. The first second energy storage circuit 115, which is electrically connected to the first third control node NC1-3 and the Nth stage output driving terminal NO(N), controls the potential of the first third control node NC1-3 based on the Nth stage driving output signal supplied from the Nth stage output driving terminal NO(N). The first output circuit 113, which is electrically connected to the first second node N1-2, the first third control node NC1-3, the first voltage terminal V1, the second voltage terminal V2, and the Nth stage output drive terminal NO(N), respectively, controls the Nth stage output drive terminal NO(N) and the first voltage terminal V1 to be electrically connected together under control of the potential of the first second node N1-2, and controls the Nth stage output drive terminal NO(N) and the second voltage terminal V2 to be electrically connected together under control of the potential of the first third control node NC1-3. The first third control node NC1-3 is a node different from the first second control node NC1-2.

[0036] In the embodiment of the driving circuit shown in FIG. 1 of the present disclosure, during operation, the first driving signal generation circuit 110 generates an N-stage driving signal under control of the potential of the first first control node NC1-1 and the potential of the first second control node NC1-2 and outputs the N-stage driving signal via the N-stage driving signal output terminal NS(N). The first gating circuit 111 controls the gating input signal supplied from the gating input terminal VCT to be written to the first first node N1-1 under control of the gating control signal supplied from the gating control terminal CX. The first output control circuit 112 controls the first first control node NC1-1 and the first second node N1-2 to be conductive under control of the potential of the first first node N1-1. The first first energy storage circuit 114 controls the potential of the first second node N1-2 based on the potential of the first first node N1-1. The first second energy storage circuit 115 controls the potential of the first third control node NC1-3 based on the N-stage driving output signal supplied from the N-stage output driving terminal NO(N). The first output circuit 113 controls the N-stage output driving terminal NO(N) and the first voltage terminal V1 to be electrically connected under control of the potential of the first second node N1-2, and controls the N-stage output driving terminal NO(N) and the second voltage terminal V2 to be electrically connected under control of the potential of the first third control node NC1-3.

[0037] Optionally, the first voltage terminal may be, but is not limited to, a high voltage terminal.

[0038] The embodiment of the driving circuit shown in FIG. 1 of the present disclosure may be an Nth stage driving circuit.

[0039] The embodiment of the driving circuit shown in FIG. 1 of the present disclosure operates as follows within one frame time. Before the N-th stage driving signal supply step, the first gating circuit 111 writes the gating input signal supplied from the gating input terminal VCT to the first first node N1-1 under the control of the gating control signal. When the gating input signal is a high-voltage signal, in the Nth-stage driving signal supply step, a high-voltage signal is output from the Nth-stage driving signal output terminal NS(N), and the potential of the first first node N1-1 is high. The first output control circuit 112 controls the first first control node NC1-1 and the first second node N1-2 to be disconnected under control of the potential of the first first node N1-1. The first first energy storage circuit 114 controls the potential of the first second node N1-2 to be high based on the potential of the first first node N1-1. The first output circuit 113 controls the output driving terminal NO(N) to maintain a low-voltage signal output, and can control the pixel voltages of the pixel circuits in the corresponding row not to be updated. When the gating input signal is a low-voltage signal, in the N-th stage driving signal supply step, a high-voltage signal is output from the N-th stage driving signal output terminal NS(N), and the potential of the first first node N1-1 is low. The first output control circuit 112 controls the first first control node NC1-1 and the first second node N1-2 to be conductive under control of the potential of the first first node N1-1, so that the potential of the first second node N1-2 becomes low. The first output circuit 113 controls the output driving terminal NO(N) and the first voltage terminal V1 to be conductive under control of the potential of the first second node N1-2, so that a high-voltage signal is output from NO(N), thereby controlling the pixel voltages of the pixel circuits in the corresponding row to be updated.

[0040] In operation, the embodiment of the driving circuit shown in FIG. 1 of the present disclosure can pull down the potential of the first third control node NC1-3 when the potential of the N-stage driving output signal supplied from NO(N) drops from a high voltage to a low voltage, so that the gate included in the first output circuit 113 can better turn on the transistor electrically connected to the first third control node NC1-3, and the potential of the N-stage driving output signal is maintained at a low voltage.

[0041] In the embodiment of the present disclosure, by controlling the gating input signal supplied from the gating input terminal VCT, it is possible to update a part of the display screen to reduce power consumption, or to update a part of the display screen to achieve ultra-low power consumption in OLED display products such as wearable products, mobile terminals, and notebook computers (NBs).

[0042] As shown in FIG. 2, the associated pixel circuit may include a first display control transistor M1, a second display control transistor M2, a drive transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light emitting diode O1. The gate of M1 is electrically connected to the first reset terminal NR(N), the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the gate of M3. The gate of M2 is electrically connected to the first scan terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3. The gate of M4 is electrically connected to the second scan terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3. The gate of M5 is electrically connected to the light emission control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3. The gate of M6 is electrically connected to the light-emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal ELVSS. The gate of M7 is electrically connected to the second scan terminal PG(N), the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0043] In a specific implementation, the first reset terminal NR(N) may be the first scan terminal NG(N) of the (N-1)th stage, but is not limited thereto.

[0044] In the relevant pixel circuit shown in FIG. 2, M1 and M2 are n-type transistors, M3, M4, M5, M6, and M7 are all p-type transistors, M1 and M2 are IGZO TFTs with low leakage current, and M3, M4, M5, M6, and M7 are all LTPS TFTs.

[0045] In the relevant pixel circuit shown in Figure 2, M1 and M2 are IGZO TFTs. For low frequency display, the IGZO TFT can ensure that Cst can maintain the voltage on the gate of M3 for a long time.

[0046] In the related pixel circuit shown in FIG. 2, the second scanning terminal PG(N) serves to reset the voltage of the anode of O1 and write the data voltage on the data line to the source of the driving transistor, and the first scanning terminal NG(N) serves to reset Cst, extract Vth (Vth is the threshold voltage of the driving transistor), and write the data voltage to the gate of the driving transistor.

[0047] In a specific implementation, the first scan signal supplied from the first scan terminal NG(N) and the second scan signal supplied from the second scan terminal PG(N) may be mutually inverted signals, but are not limited thereto.

[0048] A driving circuit according to at least one embodiment of the present disclosure may supply the first scanning signal to the first scanning terminal NG(N) via the output driving terminal NO(N), but is not limited to this.

[0049] As shown in FIG. 3, when the associated pixel circuit shown in FIG. 2 is operating, the display period may include a first display control stage t1, a second display control stage t2, and a third display control stage t3 set in sequence. In the first display control stage t1, a high voltage signal is output from E(N), a high voltage signal is supplied from NR(N), a high voltage signal is supplied from PG(N), a low voltage signal is supplied from NG(N), M5 and M6 are turned off, M1 is turned on, and the potential of the gate of M3 is pulled down to the initial voltage Vinit. The initial voltage terminal I1 is for supplying the initial voltage Vinit. During the second display control phase t2, a high voltage signal is output from E(N), a low voltage signal is supplied from NR(N), a low voltage signal is supplied from PG(N), a high voltage signal is supplied from NG(N), M5 and M6 are turned off, M1 is turned off, M2 is turned on, and M4 is turned on. M2 and M3 form a diode structure, and Cst is charged by the data voltage Vdata supplied from the data line D1 until M3 is turned off. At this time, the gate voltage of M3 is Vdata+Vth, where Vth is the threshold voltage of M3. M7 is turned on to reset the anode voltage of O1. In the third display control stage t3, a low voltage signal is output from E(N), a low voltage signal is supplied from NR(N), a high voltage signal is supplied from PG(N), a low voltage signal is supplied from NG(N), M5 and M6 are turned on, and M3 drives O1 to emit light. O1 emits light based on the voltage setting of Vdata.

[0050] From the above operation procedures of the related pixel circuits, NG(N) can control whether to write a data voltage Vdata (the data voltage Vdata may be the pixel voltage) to the gate of M3 in the second display control stage.

[0051] FIG. 4 is a circuit diagram of a related pixel circuit.

[0052] As shown in FIG. 4, the associated pixel circuit may include a first display control transistor M1, a second display control transistor M2, a drive transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light emitting diode O1. The gate of M1 is electrically connected to the third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3. The gate of M2 is electrically connected to the first scan terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3. The gate of M4 is electrically connected to the second scan terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3. The gate of M5 is electrically connected to the light emission control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3. The gate of M6 is electrically connected to the light-emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal ELVSS. The gate of M7 is electrically connected to the fourth reset terminal RST2, the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0053] When the associated pixel circuit shown in FIG. 4 is in operation, NG(N) can control whether the data voltage Vdata on the data line D1 is written to the gate of the drive transistor M3.

[0054] In a specific implementation, the first scanning signal provided by NG(N) turns on or off the first second transistor, thereby controlling whether the data voltage on the data line is written to the gate of the driving transistor, thereby controlling whether the brightness of the pixel circuit of the current row is updated. When a high-voltage signal is output from NG(N), the first second transistor is turned on, updating the brightness of the pixel circuit of the current row. When a low-voltage signal is output from NG(N), the first second transistor is always turned off, so changes in the data voltage on the data line are not written to the gate of the driving transistor, and the brightness of the OLED remains unchanged. That is, the display brightness of the pixel circuit of the current row remains unchanged. From the above, pixel brightness can be updated by controlling the on / off of the N-type transistor. To prevent some pixels from being updated, simply ensure that the N-type transistor is turned off.

[0055] In at least one embodiment of the present disclosure, the first gating circuit controls so that the gating input signal supplied from the gating input terminal is written to the first first node when the potential of the first third node of the N-1th stage is a second voltage and the potential of the Nth stage drive signal is a second voltage.

[0056] Optionally, the second voltage may be, but is not limited to, a low voltage.

[0057] Optionally, the first gating circuit includes a first first transistor, a gate of the first first transistor electrically connected to the gating control terminal, a first pole of the first first transistor electrically connected to the first first node, and a second pole of the first first transistor electrically connected to the gating input terminal.

[0058] As shown in FIG. 5, the first gating circuit may include a first transistor T1-1. The gate of the first first transistor T1-1 is electrically connected to the gating control terminal S0, the drain of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first first transistor T1-1 is electrically connected to the gating input terminal VCT. T1-1 is a p-type transistor.

[0059] As shown in FIG. 6, the first gating circuit may include a first transistor T1-1. The gate of the first first transistor T1-1 is electrically connected to the gating control terminal S0, the source of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the drain of the first first transistor T1-1 is electrically connected to the gating input terminal VCT. T1-1 is an n-type transistor.

[0060] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal, and the first gating circuit includes a first first transistor and a first second transistor. The gate of the first first transistor is electrically connected to a first gating control terminal, the first pole of the first first transistor is electrically connected to the first first node, and the second pole of the first first transistor is electrically connected to the first pole of the first second transistor. The gate of the first second transistor is electrically connected to a second gating control terminal, and the second electrode of the first second transistor is electrically connected to the gating input terminal. The first gating control terminal is an Nth stage driving signal output terminal, the second gating control terminal is a first third node of an N-1th stage, and the first first transistor and the first second transistor are both p-type transistors. Alternatively, the first gating control terminal is a first third node of the (N-1)th stage, the second gating control terminal is an Nth stage driving signal output terminal, and the first first transistor and the first second transistor are both p-type transistors. Alternatively, the first gating control terminal is an (N-1)th stage driving signal output terminal, the second gating control terminal is an Nth stage driving signal output terminal, the first first transistor is an n-type transistor, and the first second transistor is a p-type transistor. Alternatively, the first gating control terminal is an N-th stage driving signal output terminal, the second gating control terminal is an N-1-th stage driving signal output terminal, the first first transistor is a p-type transistor, and the first second transistor is an n-type transistor. Alternatively, an inverted signal of the N-1th stage driving signal is input to the first gating control terminal, the second gating control terminal is an Nth stage driving signal output terminal, and the first first transistor and the first second transistor are both p-type transistors. Alternatively, the first gating control terminal is an Nth stage driving signal output terminal, an inverted signal of an N-1th stage driving signal is input to the second gating control terminal, and the first first transistor and the first second transistor are both p-type transistors. Alternatively, the first gating control terminal is an (N-1)th stage driving signal terminal, an inverted signal of the (N)th stage driving signal is input to the second gating control terminal, and the first first transistor and the first second transistor are both n-type transistors. Alternatively, an inverted signal of an Nth stage driving signal is input to the first gating control terminal, the second gating control terminal is an N-1th stage driving signal terminal, and the first first transistor and the first second transistor are both n-type transistors.

[0061] As shown in FIG. 7, the first gating circuit may include a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the drain of the first first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2. The gate of the first second transistor T1-2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. T1-1 is an n-type transistor and T1-2 is a p-type transistor.

[0062] As shown in FIG. 8, the first gating circuit may include a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first first transistor T1-1 is electrically connected to the source of the first second transistor T1-2. The gate of the first second transistor T1-2 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. T1-1 is a p-type transistor and T1-2 is an n-type transistor.

[0063] As shown in FIG. 9, the first gating circuit may include a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to a first third node N1-3(N-1) of the N-1th stage, the drain of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2. The gate of the first second transistor T1-2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. T1-1 is a p-type transistor and T1-2 is a p-type transistor.

[0064] In at least one embodiment of the present disclosure, the first third node N1-3(N-1) of the N-1th stage may be the first third node in the N-1th stage driving circuit.

[0065] As shown in FIG. 10, the first gating circuit may include a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2. The gate of the first second transistor T1-2 is electrically connected to the first third node N1-3(N-1) of the N-1th stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. T1-1 is a p-type transistor and T1-2 is a p-type transistor.

[0066] As shown in FIG. 11, the first gating circuit may include a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to a first inverted drive signal terminal NGI1, the drain of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2. The first inverted drive signal supplied from the first inverted drive signal terminal NGI1 and the N-1-th stage drive signal supplied from the N-1-th stage drive signal output terminal NS(N-1) are mutually inverted signals. The gate of the first second transistor T1-2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. T1-1 is a p-type transistor and T1-2 is a p-type transistor.

[0067] As shown in FIG. 12, the first gating circuit may include a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2. The gate of the first second transistor T1-2 is electrically connected to a first inverted drive signal terminal NGI1, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. The first inverted drive signal supplied from the first inverted drive signal terminal NGI1 and the N-1th stage drive signal supplied from the N-1th stage drive signal output terminal NS(N-1) are mutually inverted signals. T1-1 is a p-type transistor and T1-2 is a p-type transistor.

[0068] As shown in FIG. 13, the first gating circuit may include a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the drain of the first first transistor T1-1 is electrically connected to the source of the first second transistor T1-2. The gate of the first second transistor T1-2 is electrically connected to a second inverted drive signal terminal NGI2, and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. The second inverted drive signal supplied from the second inverted drive signal terminal NGI2 and the N-stage drive signal supplied from the N-stage drive signal output terminal NS(N) are mutually inverted signals. T1-1 is an n-type transistor and T1-2 is an n-type transistor.

[0069] As shown in FIG. 14, the first gating circuit may include a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to a second inverted drive signal terminal NGI2, the source of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the drain of the first first transistor T1-1 is electrically connected to the source of the first second transistor T1-2. The second inverted drive signal supplied from the second inverted drive signal terminal NGI2 and the N-th stage drive signal supplied from the N-th stage drive signal output terminal NS(N) are mutually inverted signals. The gate of the first second transistor T1-2 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. T1-1 is an n-type transistor and T1-2 is an n-type transistor.

[0070] As shown in Figure 15, the N-1th stage drive signal supplied from the N-1th stage drive signal output terminal NS(N-1) is inverted by a first inverter to obtain a first inverted drive signal supplied from the first inverted drive signal terminal NGI1. The first inverter includes a first inversion control transistor T01 and a second inversion control transistor T02. T01 is a p-type transistor and T02 is an n-type transistor.

[0071] As shown in FIG. 16, the Nth-stage drive signal supplied from the Nth-stage drive signal output terminal NS(N) can be inverted by a second inverter to obtain a second inverted drive signal supplied from the second inverted drive signal terminal NGI2. The second inverter includes a third inversion control transistor T03 and a fourth inversion control transistor T04. T03 is a p-type transistor and T04 is an n-type transistor.

[0072] In at least one embodiment of the present disclosure, the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor. A first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node. A first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage output drive terminal.

[0073] Optionally, the first output control circuit includes a first third transistor. A gate of the first third transistor is electrically connected to the first first node, a first pole of the first third transistor is electrically connected to the first first control node, and a second pole of the first third transistor is electrically connected to the first second node.

[0074] The driving circuit according to at least one embodiment of the present disclosure may further include a first second node control circuit. The first second node control circuit, which is electrically connected to the first third control node, the first second node, and the first voltage terminal, respectively, controls the first second node and the first voltage terminal to be electrically connected together under control of the potential of the first third control node.

[0075] In a specific implementation, the driving circuit may further include a first second node control circuit. The first second node control circuit controls the first second node to be electrically connected to a first voltage terminal under control of the potential of a first third control node.

[0076] As shown in FIG. 17A, based on the embodiment of the driving circuit shown in FIG. 1, the driving circuit further includes a first second node control circuit 120. The first second node control circuit 120, which is electrically connected to the first third control node NC1-3, the first second node N1-2, and the first voltage terminal V1, respectively, controls the first second node N1-2 and the first voltage terminal V1 to be conductive under control of the potential of the first third control node NC1-3.

[0077] In at least one embodiment of the driving circuit shown in FIG. 17A, in operation, when the potential of the first third control node NC1-3 is an effective voltage, the potential of the first second node N1-2 may be a first voltage.

[0078] Optionally, the first second node control circuit includes a first fourth transistor. A gate of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to a first voltage terminal.

[0079] The driving circuit according to at least one embodiment of the present disclosure may further include a first second node control circuit. The first second node control circuit, which is electrically connected to the first third control node, the Nth stage output drive terminal, the first second node, and the first voltage terminal, respectively, controls the first second node and the first voltage terminal to be conductive under control of the potential of the first third control node and the Nth stage drive output signal supplied from the Nth stage output drive terminal.

[0080] In a specific implementation, the driving circuit may further include a first second node control circuit. The first second node control circuit controls the first second node and the first voltage terminal to be electrically connected under control of the potential of the first third control node and the Nth stage drive output signal supplied from the Nth stage output drive terminal.

[0081] As shown in FIG. 17B, based on the embodiment of the driving circuit shown in FIG. 1, the driving circuit further includes a first second node control circuit 120. The first second node control circuit 120, which is electrically connected to the first third control node NC1-3, the Nth stage output driving terminal NO(N), the first second node N1-2, and the first voltage terminal V1, controls the first second node N1-2 and the first voltage terminal V1 to be conductive under control of the potential of the first third control node NC1-3 and the Nth stage driving output signal supplied from the Nth stage output driving terminal NO(N).

[0082] In at least one embodiment of the driving circuit shown in FIG. 17B, during operation, when the potential of the first third control node NC1-3 is an effective voltage and the potential of the Nth stage driving output signal is an effective voltage, the potential of the first second node N1-2 may be a first voltage.

[0083] Optionally, the first second node control circuit includes a first fourth transistor and a first control transistor. A gate of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to a first voltage terminal. A gate of the first control transistor is electrically connected to the Nth stage output drive terminal, and a first electrode of the first control transistor is electrically connected to the first second node.

[0084] Optionally, the first output circuit includes a first fifth transistor, a first sixth transistor, and a first third capacitor. A gate of the first fifth transistor is electrically connected to the first second node, a first electrode of the first fifth transistor is electrically connected to a first voltage terminal, and a second electrode of the first fifth transistor is electrically connected to the Nth stage output drive terminal. A gate of the first sixth transistor is electrically connected to the first third control node, a first electrode of the first sixth transistor is electrically connected to the N-th stage output driving terminal, and a second electrode of the first sixth transistor is electrically connected to a second voltage terminal. A first terminal of the first third capacitor is electrically connected to the first second node, and a second terminal of the first third capacitor is electrically connected to the first voltage terminal.

[0085] The driving circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit. The first initialization circuit, which is electrically connected to an initial control terminal, a second voltage terminal, and a first first node, controls the first first node and the second voltage terminal to be conductive under the control of an initial control signal supplied from the initial control terminal.

[0086] In a specific implementation, the driving circuit may further include a first initialization circuit. When the display device is powered on, the first initialization circuit controls the first first node and the second voltage terminal to be conductive under control of an initialization control signal, thereby controlling the potential of the first first node to the second voltage. The first output control circuit controls the first first control node and the first second node to be conductive under control of the potential of the first first node.

[0087] The driving circuit according to at least one embodiment of the present disclosure further includes a first node control circuit. The first first node control circuit, which is electrically connected to the first fourth node, the second voltage terminal, and the first first node, respectively, controls the first first node and the second voltage terminal to be electrically connected together under control of the potential of the first fourth node.

[0088] In a specific implementation, the driving circuit may further include a first first node control circuit. The first first node control circuit controls the first first node to be conductive with a second voltage terminal under control of the potential of the first fourth node. After the N-th stage driving signal supply step, when the potential of the first fourth node is an effective voltage, the first first node control circuit controls the first first node to be conductive with a second voltage terminal, so that the potential of the first first node becomes a second voltage. The first output control circuit controls the first first control node to be conductive with the first second node under control of the potential of the first first node.

[0089] In at least one embodiment of the present disclosure, when the transistor included in the first first node control circuit is a p-type transistor, the effective voltage may be a low voltage, and when the transistor included in the first first node control circuit is an n-type transistor, the effective voltage may be a high voltage.

[0090] As shown in FIG. 18A, based on at least one embodiment of the driving circuit shown in FIG. 17A, the driving circuit may further include a first node control circuit 122. The first first node control circuit 122, which is electrically connected to the first fourth node N1-4, the first first node N1-1, and the second voltage terminal V2, respectively, controls the first first node N1-1 and the second voltage terminal V2 to be electrically connected to each other under control of the potential of the first fourth node N1-4.

[0091] As shown in FIG. 18B, based on at least one embodiment of the driving circuit shown in FIG. 17B, the driving circuit may further include a first node control circuit 122. The first first node control circuit 122, which is electrically connected to the first fourth node N1-4, the first first node N1-1, and the second voltage terminal V2, respectively, controls the first first node N1-1 and the second voltage terminal V2 to be electrically connected to each other under control of the potential of the first fourth node N1-4.

[0092] As shown in FIG. 18C, based on at least one embodiment of the driving circuit shown in FIG. 17A, the driving circuit may further include a first initialization circuit 121 and a first first node control circuit 122. The first initialization circuit 121, which is electrically connected to the initial control terminal NCX, the first first node N1-1, and the second voltage terminal V2, respectively, controls the first first node N1-1 and the second voltage terminal V2 to be conductive under the control of an initial control signal supplied from the initial control terminal NCX. The first first node control circuit 122, which is electrically connected to the first fourth node N1-4, the first first node N1-1, and the second voltage terminal V2, respectively, controls the first first node N1-1 and the second voltage terminal V2 to be electrically connected to each other under control of the potential of the first fourth node N1-4.

[0093] As shown in FIG. 18D, based on at least one embodiment of the driving circuit shown in FIG. 17B, the driving circuit may further include a first initialization circuit 121 and a first first node control circuit 122. The first initialization circuit 121, which is electrically connected to the initial control terminal NCX, the first first node N1-1, and the second voltage terminal V2, respectively, controls the first first node N1-1 and the second voltage terminal V2 to be conductive under the control of an initial control signal supplied from the initial control terminal NCX. The first first node control circuit 122, which is electrically connected to the first fourth node N1-4, the first first node N1-1, and the second voltage terminal V2, respectively, controls the first first node N1-1 and the second voltage terminal V2 to be electrically connected to each other under control of the potential of the first fourth node N1-4.

[0094] Optionally, the first initialization circuit includes a first seventh transistor. A gate of the first seventh transistor is electrically connected to the initial control terminal, a first electrode of the first seventh transistor is electrically connected to the first first node, and a second electrode of the first seventh transistor is electrically connected to a second voltage terminal.

[0095] Optionally, the first first node control circuit includes a first eighth transistor. A gate of the first eighth transistor is electrically connected to the first fourth node, a first electrode of the first eighth transistor is electrically connected to the first first node, and a second electrode of the first eighth transistor is electrically connected to a second voltage terminal.

[0096] The driving circuit according to at least one embodiment of the present disclosure further includes a first third control node control circuit. The first third control node control circuit, which is electrically connected to the first first node, the first fifth node, the first second control node, the first third control node, and the first sixth node, respectively, controls the first fifth node and the first third control node to be electrically connected together under control of the potential of the first first node, controls the first second control node and the first sixth node to be electrically connected together under control of the potential of the first sixth node, and controls the first sixth node and the first third control node to be electrically connected together.

[0097] In a specific implementation, the driving circuit may include a first third control node control circuit, which controls the potential of the first third control node under control of the potential of the first first node and the potential of the first sixth node.

[0098] As shown in FIG. 19A, based on at least one embodiment of the driving circuit shown in FIG. 18A, the driving circuit further includes a first third control node control circuit 130. The first third control node control circuit 130, which is electrically connected to the first first node N1-1, the first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3, and the first sixth node N1-6, respectively, controls the first fifth node N1-5 and the first third control node NC1-3 to be conductive under control of the potential of the first first node N1-1, controls the first second control node NC1-2 and the first sixth node N1-6 to be conductive under control of the potential of the first sixth node N1-6, and controls the first sixth node N1-6 to be conductive and the first third control node NC1-3 to be conductive.

[0099] As shown in FIG. 19B, based on at least one embodiment of the driving circuit shown in FIG. 18B, the driving circuit further includes a first third control node control circuit 130. The first third control node control circuit 130, which is electrically connected to the first first node N1-1, the first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3, and the first sixth node N1-6, respectively, controls the first fifth node N1-5 and the first third control node NC1-3 to be conductive under control of the potential of the first first node N1-1, controls the first second control node NC1-2 and the first sixth node N1-6 to be conductive under control of the potential of the first sixth node N1-6, and controls the first sixth node N1-6 to be conductive and the first third control node NC1-3 to be conductive.

[0100] As shown in FIG. 19C, based on at least one embodiment of the driving circuit shown in FIG. 18C, the driving circuit further includes a first third control node control circuit 130. The first third control node control circuit 130, which is electrically connected to the first first node N1-1, the first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3, and the first sixth node N1-6, respectively, controls the first fifth node N1-5 and the first third control node NC1-3 to be conductive under control of the potential of the first first node N1-1, controls the first second control node NC1-2 and the first sixth node N1-6 to be conductive under control of the potential of the first sixth node N1-6, and controls the first sixth node N1-6 to be conductive and the first third control node NC1-3 to be conductive.

[0101] As shown in FIG. 19D, based on at least one embodiment of the driving circuit shown in FIG. 18D, the driving circuit further includes a first third control node control circuit 130. The first third control node control circuit 130, which is electrically connected to the first first node N1-1, the first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3, and the first sixth node N1-6, respectively, controls the first fifth node N1-5 and the first third control node NC1-3 to be conductive under control of the potential of the first first node N1-1, controls the first second control node NC1-2 and the first sixth node N1-6 to be conductive under control of the potential of the first sixth node N1-6, and controls the first sixth node N1-6 to be conductive and the first third control node NC1-3 to be conductive.

[0102] Optionally, the first third control node control circuit includes a first ninth transistor, a first tenth transistor, and a first eleventh transistor. A gate of the first ninth transistor is electrically connected to the first first node, a first pole of the first ninth transistor is electrically connected to the first fifth node, and a second pole of the first ninth transistor is electrically connected to the first third control node. The gate of the first tenth transistor and the second electrode of the first tenth transistor are both electrically connected to the first sixth node, and the first electrode of the first tenth transistor is electrically connected to the first second control node. The gate of the first 11th transistor and the first pole of the first 11th transistor are both electrically connected to the first sixth node, and the second pole of the first 11th transistor is electrically connected to the first third control node.

[0103] In at least one embodiment of the present disclosure, the first drive signal generation circuit includes a first first drive output circuit, a first second drive output circuit, a first first control node control circuit, and a first second control node control circuit. The first first control node control circuit controls the potential of the first control node. The first second control node control circuit controls the potential of the second control node. The first first drive output circuit, which is electrically connected to the first first control node, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, controls the Nth stage drive signal output terminal and the first voltage terminal to be electrically connected together under control of the potential of the first first control node. The first second drive output circuit, which is electrically connected to the first second control node, the second voltage terminal, and the Nth stage drive signal output terminal, respectively, controls the Nth stage drive signal output terminal and the second voltage terminal to be electrically connected together under control of the potential of the first second control node.

[0104] As shown in FIG. 20A, based on at least one embodiment of the driving circuit shown in FIG. 19A, the driving circuit further includes a first first control node control circuit 131, a first second control node control circuit 132, a first first drive output circuit 133, and a first second drive output circuit 134. The first first control node control circuit 131, which is electrically connected to the first first control node NC1-1, controls the potential of the first first control node NC1-1. The first second control node control circuit 132, which is electrically connected to the first second control node NC1-2, controls the potential of the first second control node NC1-2. The first first drive output circuit 133, which is electrically connected to the first first control node NC1-1, the first voltage terminal V1, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 to be conductive under the control of the potential of the first first control node NC1-1. The first second drive output circuit 134, which is electrically connected to the first second control node NC1-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 to be conductive under the control of the potential of the first second control node NC1-2.

[0105] As shown in FIG. 20B, based on at least one embodiment of the driving circuit shown in FIG. 19B, the driving circuit further includes a first first control node control circuit 131, a first second control node control circuit 132, a first first drive output circuit 133, and a first second drive output circuit 134. The first first control node control circuit 131, which is electrically connected to the first first control node NC1-1, controls the potential of the first first control node NC1-1. The first second control node control circuit 132, which is electrically connected to the first second control node NC1-2, controls the potential of the first second control node NC1-2. The first first drive output circuit 133, which is electrically connected to the first first control node NC1-1, the first voltage terminal V1, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) to be conductive with the first voltage terminal V1 under control of the potential of the first first control node NC1-1. The first second drive output circuit 134, which is electrically connected to the first second control node NC1-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 to be conductive under the control of the potential of the first second control node NC1-2.

[0106] As shown in Figure 20C, based on at least one embodiment of the driving circuit shown in Figure 19C, the driving circuit further includes a first first control node control circuit 131, a first second control node control circuit 132, a first first drive output circuit 133, and a first second drive output circuit 134. The first first control node control circuit 131, which is electrically connected to the first first control node NC1-1, controls the potential of the first first control node NC1-1. The first second control node control circuit 132, which is electrically connected to the first second control node NC1-2, controls the potential of the first second control node NC1-2. The first first drive output circuit 133, which is electrically connected to the first first control node NC1-1, the first voltage terminal V1, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) to be conductive with the first voltage terminal V1 under control of the potential of the first first control node NC1-1. The first second drive output circuit 134, which is electrically connected to the first second control node NC1-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 to be conductive under the control of the potential of the first second control node NC1-2.

[0107] As shown in FIG. 20D, based on at least one embodiment of the driving circuit shown in FIG. 19D, the driving circuit further includes a first first control node control circuit 131, a first second control node control circuit 132, a first first drive output circuit 133, and a first second drive output circuit 134. The first first control node control circuit 131, which is electrically connected to the first first control node NC1-1, controls the potential of the first first control node NC1-1. The first second control node control circuit 132, which is electrically connected to the first second control node NC1-2, controls the potential of the first second control node NC1-2. The first first drive output circuit 133, which is electrically connected to the first first control node NC1-1, the first voltage terminal V1, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) to be conductive with the first voltage terminal V1 under control of the potential of the first first control node NC1-1. The first second drive output circuit 134, which is electrically connected to the first second control node NC1-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 to be conductive under the control of the potential of the first second control node NC1-2.

[0108] In at least one embodiment of the present disclosure, the first first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit. The first seventh node control circuit, which is electrically connected to the first seventh node, the second voltage terminal, the first clock signal terminal, and the first fifth node, respectively, controls the first seventh node and the second voltage terminal to be electrically connected together under control of a first clock signal supplied from the first clock signal terminal, and controls the first seventh node and the first clock signal terminal to be electrically connected together under control of the potential of the first fifth node. The first eighth node control circuit, which is electrically connected to the second voltage terminal, the first seventh node, and the first eighth node, respectively, controls the first seventh node and the first eighth node to be conductive under the control of a second voltage signal supplied from the second voltage terminal. The first third node control circuit, which is electrically connected to the first eighth node, the second clock signal terminal, and the first third node, respectively, controls the electrical connection between the first third node and the second clock signal terminal under control of the potential of the first eighth node, and controls the potential of the first third node based on the potential of the first eighth node. The first first control circuit, which is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node, and the first voltage terminal, respectively, controls the first third node and the first first control node to be electrically connected together under control of a second clock signal supplied from the second clock signal terminal, and controls the first first control node and the first voltage terminal to be electrically connected together under control of the potential of the first fifth node.

[0109] In a specific implementation, the first first control node control circuit may include a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit. The first seventh node control circuit controls the potential of the first seventh node under control of a first clock signal and the potential of the first fifth node. The first eighth node control circuit controls the first seventh node and the first eighth node to be conductively connected under control of a second voltage signal. The first third node control circuit controls the electrical connection between the first third node and the second clock signal terminal under control of the potential of the first eighth node, and controls the potential of the first third node based on the potential of the first eighth node. The first first control circuit controls the first third node and the first first control node to be conductively connected under control of the second clock signal, and controls the first first control node and the first voltage terminal to be conductively connected under control of the potential of the first fifth node.

[0110] In at least one embodiment of the present disclosure, the first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit. The first sixth node control circuit, which is electrically connected to the second voltage terminal, the first ninth node, the first sixth node, and the first fourth node, respectively, controls the first ninth node and the first sixth node to be conductive under the control of a second voltage signal supplied from the second voltage terminal, and controls the potential of the first sixth node based on the potential of the first fourth node. The first fifth node control circuit, which is electrically connected to the N-1th stage drive signal output terminal, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, controls the first fifth node and the N-1th stage drive signal output terminal to be electrically connected together under the control of a first clock signal supplied from the first clock signal terminal, and controls the first fifth node and the first voltage terminal to be electrically connected together under the control of an initial control signal supplied from the initial control terminal. The first 9th node control circuit, which is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal, and the first 9th node, respectively, controls the first 9th node and the N-1th stage drive signal output terminal to be electrically connected together under the control of the first clock signal supplied from the first clock signal terminal. The first fourth node control circuit, which is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal, and the first sixth node, respectively, controls the first fourth node and the first voltage terminal to be electrically connected together under control of the potential of the first seventh node, and controls the first fourth node and the second clock signal terminal to be electrically connected together under control of the potential of the first sixth node. The first second control circuit, which is electrically connected to the second voltage terminal, the first fifth node, and the first second control node, respectively, controls the first fifth node and the first second control node to be conductive under the control of a second voltage signal supplied from the second voltage terminal.

[0111] In a specific implementation, the first second control node control circuit may include a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit. The first fourth node control circuit controls the potential of the first fourth node under control of the potential of the first seventh node and the potential of the first sixth node. The first sixth node control circuit controls the first ninth node and the first sixth node to be conductive under control of a second voltage signal, and controls the potential of the first sixth node based on the potential of the first fourth node. The first fifth node control circuit controls the first fifth node and the (N-1)th stage driving signal output terminal to be conductive under control of a first clock signal, and controls the first fifth node and the first voltage terminal to be conductive under control of an initial control signal. The first ninth node control circuit controls, under control of a first clock signal, to bring the first ninth node and the (N-1)th stage drive signal output into conduction. The first fourth node control circuit controls, under control of a potential of the first seventh node, to bring the first fourth node and the first voltage terminal into conduction, and controls, under control of a potential of the first sixth node, to bring the first fourth node and the second clock signal terminal into conduction. The first second control circuit controls, under control of a second voltage signal, to bring the first fifth node and the first second control node into conduction.

[0112] As shown in FIG. 21A, based on at least one embodiment of the driving circuit shown in FIG. 20A, the first first control node control circuit includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143, and a first first control circuit 144. The first seventh node control circuit 141, which is electrically connected to the first seventh node N1-7, the second voltage terminal V2, the first clock signal terminal GCK, and the first fifth node N1-5, respectively, controls the first seventh node N1-7 and the second voltage terminal V2 to be electrically connected together under control of the first clock signal supplied from the first clock signal terminal GCK, and controls the first seventh node N1-7 and the first clock signal terminal GCK to be electrically connected together under control of the potential of the first fifth node N1-5. The first eighth node control circuit 142, which is electrically connected to the second voltage terminal V2, the seventh node N1-7, and the first eighth node N1-8, respectively, controls the first seventh node N1-7 and the first eighth node N1-8 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2. The first third node control circuit 143, which is electrically connected to the first eighth node N1-8, the second clock signal terminal GCB, and the first third node N1-3, controls the electrical connection between the first third node N1-3 and the second clock signal terminal GCB under control of the potential of the first eighth node N1-8, and controls the potential of the first third node N1-3 based on the potential of the first eighth node N1-8. The first first control circuit 144, which is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5, and the first voltage terminal V1, controls the first third node N1-3 and the first first control node NC1-1 to be conductive under the control of the second clock signal supplied from the second clock signal terminal GCB, and controls the first first control node NC1-1 and the first voltage terminal V1 to be conductive under the control of the potential of the first fifth node N1-5. The first second control node control circuit includes a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154, and a first second control circuit 155. The first sixth node control circuit 151, which is electrically connected to the second voltage terminal V2, the ninth node N1-9, the sixth node N1-6, and the fourth node N1-4, respectively, controls the ninth node N1-9 and the sixth node N1-6 to be conductive under control of a second voltage signal supplied from the second voltage terminal V2, and controls the potential of the sixth node N1-6 based on the potential of the fourth node N1-4. The first fifth node control circuit 152, which is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX, and the first voltage terminal V1, controls the first fifth node N1-5 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK, and controls the first fifth node N1-5 and the first voltage terminal V1 to be conductive under the control of the initial control signal supplied from the initial control terminal NCX. The first 9th node control circuit 153, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the first 9th node N1-9, controls the first 9th node N1-9 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK. The first fourth node control circuit 154, which is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4, and the second clock signal terminal GCB, controls the electrical connection between the first fourth node N1-4 and the first voltage terminal V1 under control of the potential of the first seventh node N1-7, and controls the first fourth node N1-4 and the second clock signal terminal GCB to be electrically connected to each other under control of the potential of the first sixth node N1-6. The first second control circuit 155, which is electrically connected to the second voltage terminal V2, the first fifth node N1-5, and the first second control node NC1-2, respectively, controls the first fifth node N1-5 and the first second control node NC1-2 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2.

[0113] As shown in FIG. 21B, based on at least one embodiment of the driving circuit shown in FIG. 20B, the first first control node control circuit includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143, and a first first control circuit 144. The first seventh node control circuit 141, which is electrically connected to the first seventh node N1-7, the second voltage terminal V2, the first clock signal terminal GCK, and the first fifth node N1-5, respectively, controls the first seventh node N1-7 and the second voltage terminal V2 to be electrically connected together under control of the first clock signal supplied from the first clock signal terminal GCK, and controls the first seventh node N1-7 and the first clock signal terminal GCK to be electrically connected together under control of the potential of the first fifth node N1-5. The first eighth node control circuit 142, which is electrically connected to the second voltage terminal V2, the first seventh node N1-7, and the first eighth node N1-8, respectively, controls the first seventh node N1-7 and the first eighth node N1-8 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2. The first third node control circuit 143, which is electrically connected to the first eighth node N1-8, the second clock signal terminal GCB, and the first third node N1-3, controls the electrical connection between the first third node N1-3 and the second clock signal terminal GCB under control of the potential of the first eighth node N1-8, and controls the potential of the first third node N1-3 based on the potential of the first eighth node N1-8. The first first control circuit 144, which is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5, and the first voltage terminal V1, controls the first third node N1-3 and the first first control node NC1-1 to be conductive under the control of the second clock signal supplied from the second clock signal terminal GCB, and controls the first first control node NC1-1 and the first voltage terminal V1 to be conductive under the control of the potential of the first fifth node N1-5. The first second control node control circuit includes a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154, and a first second control circuit 155. The first sixth node control circuit 151, which is electrically connected to the second voltage terminal V2, the ninth node N1-9, the sixth node N1-6, and the fourth node N1-4, respectively, controls the ninth node N1-9 and the sixth node N1-6 to be conductive under control of a second voltage signal supplied from the second voltage terminal V2, and controls the potential of the sixth node N1-6 based on the potential of the fourth node N1-4. The first fifth node control circuit 152, which is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX, and the first voltage terminal V1, controls the first fifth node N1-5 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK, and controls the first fifth node N1-5 and the first voltage terminal V1 to be conductive under the control of the initial control signal supplied from the initial control terminal NCX. The first 9th node control circuit 153, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the first 9th node N1-9, controls the first 9th node N1-9 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK. The first fourth node control circuit 154, which is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4, and the second clock signal terminal GCB, controls the electrical connection between the first fourth node N1-4 and the first voltage terminal V1 under control of the potential of the first seventh node N1-7, and controls the first fourth node N1-4 and the second clock signal terminal GCB to be electrically connected to each other under control of the potential of the first sixth node N1-6. The first second control circuit 155, which is electrically connected to the second voltage terminal V2, the first fifth node N1-5, and the first second control node NC1-2, respectively, controls the first fifth node N1-5 and the first second control node NC1-2 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2.

[0114] As shown in FIG. 21C, based on at least one embodiment of the driving circuit shown in FIG. 20C, the first first control node control circuit includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143, and a first first control circuit 144. The first seventh node control circuit 141, which is electrically connected to the first seventh node N1-7, the second voltage terminal V2, the first clock signal terminal GCK, and the first fifth node N1-5, controls the first seventh node N1-7 and the second voltage terminal V2 to be electrically connected together under control of the first clock signal supplied from the first clock signal terminal GCK, and controls the first seventh node N1-7 and the first clock signal terminal GCK to be electrically connected together under control of the potential of the first fifth node N1-5. The first eighth node control circuit 142, which is electrically connected to the second voltage terminal V2, the first seventh node N1-7, and the first eighth node N1-8, respectively, controls the first seventh node N1-7 and the first eighth node N1-8 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2. The first third node control circuit 143, which is electrically connected to the first eighth node N1-8, the second clock signal terminal GCB, and the first third node N1-3, controls the electrical connection between the first third node N1-3 and the second clock signal terminal GCB under control of the potential of the first eighth node N1-8, and controls the potential of the first third node N1-3 based on the potential of the first eighth node N1-8. The first first control circuit 144, which is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5, and the first voltage terminal V1, controls the first third node N1-3 and the first first control node NC1-1 to be conductive under the control of the second clock signal supplied from the second clock signal terminal GCB, and controls the first first control node NC1-1 and the first voltage terminal V1 to be conductive under the control of the potential of the first fifth node N1-5. The first second control node control circuit includes a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154, and a first second control circuit 155. The first sixth node control circuit 151, which is electrically connected to the second voltage terminal V2, the ninth node N1-9, the sixth node N1-6, and the fourth node N1-4, respectively, controls the ninth node N1-9 and the sixth node N1-6 to be conductive under control of a second voltage signal supplied from the second voltage terminal V2, and controls the potential of the sixth node N1-6 based on the potential of the fourth node N1-4. The first fifth node control circuit 152, which is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX, and the first voltage terminal V1, controls the first fifth node N1-5 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK, and controls the first fifth node N1-5 and the first voltage terminal V1 to be conductive under the control of the initial control signal supplied from the initial control terminal NCX. The first 9th node control circuit 153, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the first 9th node N1-9, controls the first 9th node N1-9 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK. The first fourth node control circuit 154, which is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4, and the second clock signal terminal GCB, controls the electrical connection between the first fourth node N1-4 and the first voltage terminal V1 under control of the potential of the first seventh node N1-7, and controls the first fourth node N1-4 and the second clock signal terminal GCB to be electrically connected to each other under control of the potential of the first sixth node N1-6. The first second control circuit 155, which is electrically connected to the second voltage terminal V2, the first fifth node N1-5, and the first second control node NC1-2, respectively, controls the first fifth node N1-5 and the first second control node NC1-2 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2.

[0115] As shown in FIG. 21D, based on at least one embodiment of the driving circuit shown in FIG. 20D, the first first control node control circuit includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143, and a first first control circuit 144. The first seventh node control circuit 141, which is electrically connected to the first seventh node N1-7, the second voltage terminal V2, the first clock signal terminal GCK, and the first fifth node N1-5, controls the first seventh node N1-7 and the second voltage terminal V2 to be electrically connected together under control of the first clock signal supplied from the first clock signal terminal GCK, and controls the first seventh node N1-7 and the first clock signal terminal GCK to be electrically connected together under control of the potential of the first fifth node N1-5. The first eighth node control circuit 142, which is electrically connected to the second voltage terminal V2, the first seventh node N1-7, and the first eighth node N1-8, respectively, controls the first seventh node N1-7 and the first eighth node N1-8 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2. The first third node control circuit 143, which is electrically connected to the first eighth node N1-8, the second clock signal terminal GCB, and the first third node N1-3, controls the electrical connection between the first third node N1-3 and the second clock signal terminal GCB under control of the potential of the first eighth node N1-8, and controls the potential of the first third node N1-3 based on the potential of the first eighth node N1-8. The first first control circuit 144, which is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5, and the first voltage terminal V1, controls the first third node N1-3 and the first first control node NC1-1 to be conductive under control of the second clock signal supplied from the second clock signal terminal GCB, and controls the first first control node NC1-1 and the first voltage terminal V1 to be conductive under control of the potential of the first fifth node N1-5. The first second control node control circuit includes a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154, and a first second control circuit 155. The first sixth node control circuit 151, which is electrically connected to the second voltage terminal V2, the ninth node N1-9, the sixth node N1-6, and the fourth node N1-4, respectively, controls the ninth node N1-9 and the sixth node N1-6 to be conductive under control of a second voltage signal supplied from the second voltage terminal V2, and controls the potential of the sixth node N1-6 based on the potential of the fourth node N1-4. The first fifth node control circuit 152, which is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the first fifth node N5, the initial control terminal NCX, and the first voltage terminal V1, controls the first fifth node N1-5 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK, and controls the first fifth node N1-5 and the first voltage terminal V1 to be conductive under the control of the initial control signal supplied from the initial control terminal NCX. The first 9th node control circuit 153, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the first 9th node N1-9, controls the first 9th node N1-9 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK. The first fourth node control circuit 154, which is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4, and the second clock signal terminal GCB, controls the electrical connection between the first fourth node N1-4 and the first voltage terminal V1 under control of the potential of the first seventh node N1-7, and controls the first fourth node N1-4 and the second clock signal terminal GCB to be electrically connected to each other under control of the potential of the first sixth node N1-6. The first second control circuit 155, which is electrically connected to the second voltage terminal V2, the first fifth node N1-5, and the first second control node NC1-2, respectively, controls the first fifth node N1-5 and the first second control node NC1-2 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2.

[0116] Optionally, the first seventh node control circuit includes a first twelfth transistor and a first thirteenth transistor, the first eighth node control circuit includes a first fourteenth transistor, the first third node control circuit includes a first fifteenth transistor and a first fourth capacitor, and the first first control circuit includes a first sixteenth transistor and a first seventeenth transistor. A gate of the first twelfth transistor is electrically connected to a first clock signal terminal, a first electrode of the first twelfth transistor is electrically connected to a second voltage terminal, and a second electrode of the first twelfth transistor is electrically connected to a first seventh node. A gate of the first thirteenth transistor is electrically connected to a first fifth node, a first pole of the first thirteenth transistor is electrically connected to the first seventh node, and a second pole of the first thirteenth transistor is electrically connected to a first clock signal terminal. A gate of the first fourteenth transistor is electrically connected to a second voltage terminal, a first electrode of the first fourteenth transistor is electrically connected to the first seventh node, and a second electrode of the first fourteenth transistor is electrically connected to the first eighth node. A gate of the first 15th transistor is electrically connected to the first 8th node, a first pole of the first 15th transistor is electrically connected to a second clock signal terminal, and a second pole of the first 15th transistor is electrically connected to the first 3rd node. A first terminal of the first fourth capacitor is electrically connected to a first eighth node, and a second terminal of the first fourth capacitor is electrically connected to a first third node. A gate of the first 16th transistor is electrically connected to the second clock signal terminal, a first pole of the first 16th transistor is electrically connected to the first third node, and a second pole of the first 16th transistor is electrically connected to the first first control node. A gate of the first 17th transistor is electrically connected to a first 5th node, a first electrode of the first 17th transistor is electrically connected to a first 1st control node, and a second electrode of the first 17th transistor is electrically connected to a first voltage terminal.

[0117] Optionally, the first sixth node control circuit includes a first eighteenth transistor and a first fifth capacitor, the first fifth node control circuit includes a first nineteenth transistor and a first twentieth transistor, the first ninth node control circuit includes a first twenty-first transistor, the first fourth node control circuit includes a first twenty-second transistor and a first twenty-third transistor, and the first second control circuit includes a first twenty-fourth transistor. A gate of the first 18th transistor is electrically connected to a second voltage terminal, a first electrode of the first 18th transistor is electrically connected to a first 9th node, and a second electrode of the first 18th transistor is electrically connected to a first 6th node. A first terminal of the first fifth capacitor is electrically connected to the first fourth node, and a second terminal of the first fifth capacitor is electrically connected to the first sixth node. A gate of the first 19th transistor is electrically connected to a first clock signal terminal, a first electrode of the first 19th transistor is electrically connected to an N-1th stage driving signal output terminal, and a second electrode of the first 19th transistor is electrically connected to a first 5th node. A gate of the first twentieth transistor is electrically connected to an initial control terminal, a first electrode of the first twentieth transistor is electrically connected to a first voltage terminal, and a second electrode of the first twentieth transistor is electrically connected to the first fifth node. The gate of the first 21st transistor is electrically connected to a first clock signal terminal, the first pole of the first 21st transistor is electrically connected to an N-1th stage driving signal output terminal, and the second pole of the first 21st transistor is electrically connected to a first 9th node. The gate of the first 22nd transistor is electrically connected to a first 7th node, the first electrode of the first 22nd transistor is electrically connected to a first voltage terminal, and the second electrode of the first 22nd transistor is electrically connected to a first 4th node. The gate of the first 23rd transistor is electrically connected to the first 6th node, the first pole of the first 23rd transistor is electrically connected to the first 4th node, and the second pole of the first 23rd transistor is electrically connected to a second clock signal terminal. A gate of the first 24th transistor is electrically connected to a second voltage terminal, a first electrode of the first 24th transistor is electrically connected to a first 9th node, and a second electrode of the first 24th transistor is electrically connected to a first second control node.

[0118] Optionally, the first first driving output circuit includes a first 25th transistor and a first 6th capacitor, and the first second driving output circuit includes a first 26th transistor and a first 7th capacitor. A gate of the first 25th transistor is electrically connected to the first first control node, a first electrode of the first 25th transistor is electrically connected to a first voltage terminal, and a second electrode of the first 25th transistor is electrically connected to an N-stage driving signal output terminal. A first terminal of the first sixth capacitor is electrically connected to the first first control node, and a second terminal of the first sixth capacitor is electrically connected to a first voltage terminal. The gate of the first 26th transistor is electrically connected to the first second control node, the first electrode of the first 26th transistor is electrically connected to the Nth stage driving signal output terminal, and the second electrode of the first 26th transistor is electrically connected to the second voltage terminal. A first terminal of the first seventh capacitor is electrically connected to the N-th stage drive signal output terminal, and a second terminal of the first seventh capacitor is electrically connected to a second voltage terminal.

[0119] The driver circuit according to at least one embodiment of the present disclosure further includes a first output pull-down circuit. The first output pull-down circuit, which is electrically connected to the first first control node, the Nth stage drive signal output terminal, and the second voltage terminal, respectively, controls the Nth stage drive signal output terminal and the second voltage terminal to be electrically connected together under control of the potential of the first first control node.

[0120] In a specific implementation, the driving circuit may further include a first output pull-down circuit, which can control the N-stage driving signal output terminal and the second voltage terminal to be conductive under control of the potential of the first first control node, thereby increasing the second voltage signal output capability of the N-stage driving signal output terminal.

[0121] As shown in FIG. 22A, based on at least one embodiment of the driving circuit shown in FIG. 21A, the driving circuit according to at least one embodiment of the present disclosure further includes a first output pull-down circuit 1220. The first output pull-down circuit 1220, which is electrically connected to the first first control node NC1-1, the Nth stage driving signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage driving signal output terminal NS(N) and the second voltage terminal V2 to be conductive under the control of the potential of the first first control node NC1-1.

[0122] As shown in FIG. 22B, based on at least one embodiment of the driving circuit shown in FIG. 21B, the driving circuit according to at least one embodiment of the present disclosure further includes a first output pull-down circuit 1220. The first output pull-down circuit 1220, which is electrically connected to the first first control node NC1-1, the Nth stage driving signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage driving signal output terminal NS and the second voltage terminal V2 to be conductive under the control of the potential of the first first control node NC1-1.

[0123] As shown in FIG. 22C, based on at least one embodiment of the driving circuit shown in FIG. 21C, the driving circuit according to at least one embodiment of the present disclosure further includes a first output pull-down circuit 1220. The first output pull-down circuit 1220, which is electrically connected to the first first control node NC1-1, the Nth stage driving signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage driving signal output terminal NS and the second voltage terminal V2 to be conductive under the control of the potential of the first first control node NC1-1.

[0124] As shown in FIG. 22D, based on at least one embodiment of the driving circuit shown in FIG. 21D, the driving circuit according to at least one embodiment of the present disclosure further includes a first output pull-down circuit 1220. The first output pull-down circuit 1220, which is electrically connected to the first first control node NC1-1, the Nth stage driving signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage driving signal output terminal NS and the second voltage terminal V2 to be conductive under the control of the potential of the first first control node NC1-1.

[0125] As shown in FIG. 23, based on at least one embodiment of the driving circuit shown in FIG. 21A, the first gating circuit includes a first first transistor T1-1 and a first second transistor T1-2. The gate of the first first transistor T1-1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2. The gate of the first second transistor T1-2 is electrically connected to the first third node N1-3(N-1) of the N-1th stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT. The first output control circuit includes a first third transistor T1-3. The gate of the first third transistor T1-3 is electrically connected to the first first node N1-1, the source of the first third transistor T1-3 is electrically connected to the first first control node NC1-1, and the drain of the first third transistor T1-3 is electrically connected to the first second node N1-2. The first first energy storage circuit includes a first first capacitor C1-1. A first terminal of the first first capacitor C1-1 is electrically connected to the first first node N1-1, and a second terminal of the first first capacitor C1-1 is electrically connected to the first second node N1-2. The first second energy storage circuit includes a first second capacitor C1-2. A first terminal of the first second capacitor C1-2 is electrically connected to the first third control node NC1-3, and a second terminal of the first second capacitor C1-2 is electrically connected to the Nth stage output driving terminal NO(N). The first second node control circuit includes a first fourth transistor T1-4. The gate of the first fourth transistor T1-4 is electrically connected to the first third control node NC1-3, the source of the first fourth transistor T1-4 is electrically connected to the first second node N1-2, and the drain of the first fourth transistor T1-4 is electrically connected to the high voltage terminal VGH. The first output circuit includes a first fifth transistor T1-5, a first sixth transistor, and a first third capacitor C1-3. The gate of the first fifth transistor T1-5 is electrically connected to the first second node N1-2, the source of the first fifth transistor T1-5 is electrically connected to the high voltage terminal VGH, and the drain of the first fifth transistor T1-5 is electrically connected to the output driving terminal NO(N). The gate of the first sixth transistor T1-6 is electrically connected to the first third control node NC1-3, the source of the first sixth transistor T1-6 is electrically connected to the output driving terminal NO(N), and the drain of the first sixth transistor T1-6 is electrically connected to the low voltage terminal VGL. A first terminal of the first third capacitor C1-3 is electrically connected to the first second node N1-2, and a second terminal of the first third capacitor C1-3 is electrically connected to the high voltage terminal VGH. The first first node control circuit includes a first eighth transistor T1-8. The gate of the first eighth transistor T1-8 is electrically connected to the first fourth node N1-4, the source of the first eighth transistor T1-8 is electrically connected to the first first node N1-1, and the drain of the first eighth transistor T8 is electrically connected to the low voltage terminal VGL. The first third control node control circuit includes a first ninth transistor T1-9, a first tenth transistor T1-10, and a first eleventh transistor T1-11. The gate of the first ninth transistor T1-9 is electrically connected to the first first node N1-1, the drain of the first ninth transistor T1-9 is electrically connected to the first fifth node N1-5, and the source of the first ninth transistor T1-9 is electrically connected to the first third control node NC1-3. The gate of the first tenth transistor T1-10 and the source of the first tenth transistor T1-10 are both electrically connected to the first sixth node N1-6, and the drain of the first tenth transistor T1-10 is electrically connected to the first second control node NC1-2. The gate of the first eleventh transistor T1-11 and the source of the first eleventh transistor T1-11 are both electrically connected to the first sixth node N1-6, and the drain of the first eleventh transistor T1-11 is electrically connected to the first third control node NC1-3. The first seventh node control circuit includes a first twelfth transistor T1-12 and a first thirteenth transistor T1-13, the first eighth node control circuit includes a first fourteenth transistor T1-14, the first third node control circuit includes a first fifteenth transistor T1-15 and a first fourth capacitor C1-4, and the first first control circuit includes a first sixteenth transistor T1-16 and a first seventeenth transistor T1-17. The gate of the first twelfth transistor T1-12 is electrically connected to the first clock signal terminal GCK, the source of the first twelfth transistor T1-12 is electrically connected to the low voltage terminal VGL, and the drain of the first twelfth transistor T1-12 is electrically connected to the first seventh node N1-7. The gate of the first thirteenth transistor T1-13 is electrically connected to the first fifth node N1-5, the source of the first thirteenth transistor T1-13 is electrically connected to the first seventh node N1-7, and the drain of the first thirteenth transistor T1-13 is electrically connected to the first clock signal terminal GCK. The gate of the first fourteenth transistor T1-14 is electrically connected to the low voltage terminal VGL, the source of the first fourteenth transistor T1-14 is electrically connected to the first seventh node N1-7, and the drain of the first fourteenth transistor T1-14 is electrically connected to the first eighth node N1-8. The gate of the first fifteenth transistor T1-15 is electrically connected to the first eighth node N1-8, the source of the first fifteenth transistor T1-15 is electrically connected to the second clock signal terminal GCB, and the drain of the first fifteenth transistor T1-15 is electrically connected to the first third node N1-3. A first terminal of the first fourth capacitor C1-4 is electrically connected to a first eighth node N1-8, and a second terminal of the first fourth capacitor C1-4 is electrically connected to a first third node N1-3. The gate of the first sixteenth transistor T1-16 is electrically connected to the second clock signal terminal GCB, the source of the first sixteenth transistor T1-16 is electrically connected to the first third node N1-3, and the drain of the first sixteenth transistor T1-16 is electrically connected to the first first control node NC1-1. The gate of the first seventeenth transistor T1-17 is electrically connected to the first fifth node N1-5, the source of the first seventeenth transistor T1-17 is electrically connected to the first first control node NC1-1, and the drain of the first seventeenth transistor T1-17 is electrically connected to the high voltage terminal VGH. The first sixth node control circuit includes a first eighteenth transistor T1-18 and a first fifth capacitor C1-5, the first fifth node control circuit includes a first nineteenth transistor T1-19 and a first twentieth transistor T1-20, the first ninth node control circuit includes a first twenty-first transistor T1-21, the first fourth node control circuit includes a first twenty-second transistor T1-22 and a first twenty-third transistor T1-23, and the first second control circuit includes a first twenty-fourth transistor T1-24. The gate of the first transistor T1-18 is electrically connected to the low voltage terminal VGL, the source of the first transistor T1-18 is electrically connected to the first ninth node N1-9, and the drain of the first transistor T1-18 is electrically connected to the first sixth node N1-6. A first terminal of the first fifth capacitor C1-5 is electrically connected to the first fourth node N1-4, and a second terminal of the first fifth capacitor C1-5 is electrically connected to the first sixth node N1-6. The gate of the first 19th transistor T1-19 is electrically connected to the first clock signal terminal GCK, the source of the first 19th transistor T1-19 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first 19th transistor T1-19 is electrically connected to the first 5th node N1-5. The gate of the first twentieth transistor T1-20 is electrically connected to the initial control terminal NCX, the source of the first twentieth transistor T1-20 is electrically connected to the high voltage terminal VGH, and the drain of the first twentieth transistor T1-20 is electrically connected to the first fifth node N1-5. The gate of the first 21st transistor T1-21 is electrically connected to the first clock signal terminal GCK, the source of the first 21st transistor T1-21 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first 21st transistor T1-21 is electrically connected to the first 9th node N1-9. The gate of the first 22nd transistor T1-22 is electrically connected to the first seventh node N1-7, the source of the first 22nd transistor T1-22 is electrically connected to the high voltage terminal VGH, and the drain of the first 22nd transistor T1-22 is electrically connected to the first fourth node N1-4. The gate of the first 23rd transistor T1-23 is electrically connected to the first 6th node N1-6, the source of the first 23rd transistor T1-23 is electrically connected to the first 4th node N1-4, and the drain of the first 23rd transistor T1-23 is electrically connected to the second clock signal terminal GCB. The gate of the first 24th transistor T1-24 is electrically connected to the low voltage terminal VGL, the source of the first 24th transistor T1-24 is electrically connected to the first 9th node N1-9, and the drain of the first 24th transistor T1-24 is electrically connected to the first second control node NC1-2. The first first drive output circuit includes a first 25th transistor T1-25 and a first 6th capacitor C1-6, and the first second drive output circuit includes a first 26th transistor T1-26 and a first 7th capacitor C1-7. The gate of the first 25th transistor T1-25 is electrically connected to the first first control node NC1-1, the source of the first 25th transistor T1-25 is electrically connected to the high voltage terminal VGH, and the drain of the first 25th transistor T1-25 is electrically connected to the Nth stage driving signal output terminal NS(N). A first terminal of the first sixth capacitor C1-6 is electrically connected to the first first control node NC1-1, and a second terminal of the first sixth capacitor C1-6 is electrically connected to the high voltage terminal VGH. The gate of the first 26th transistor T1-26 is electrically connected to the first second control node NC1-2, the source of the first 26th transistor T1-26 is electrically connected to the Nth stage driving signal output terminal NS(N), and the drain of the first 26th transistor T1-26 is electrically connected to the low voltage terminal VGL. A first terminal of the first seventh capacitor C1-7 is electrically connected to the Nth stage drive signal output terminal NS(N), and a second terminal of the first seventh capacitor C1-7 is electrically connected to the low voltage terminal VGL.

[0126] 23, T1-3 are dual-gate transistors, but are not limited to such. In specific implementations, T1-3 may be replaced with single-gate transistors.

[0127] In FIG. 23, the first node, the tenth node, is given the symbol N1-10.

[0128] In at least one embodiment of the driver circuit shown in FIG. 23, all of the transistors are p-type transistors, but this is not limiting.

[0129] In at least one embodiment of the drive circuit shown in FIG. 23, the first voltage terminal is a high voltage terminal and the second voltage terminal is a low voltage terminal, but is not limited to this.

[0130] In at least one embodiment of the driver circuit shown in FIG. 23, all of the transistors are p-type transistors, but this is not limiting.

[0131] In at least one embodiment of the driver circuit shown in FIG. 23, N1-10 is the first tenth node.

[0132] In at least one embodiment of the present disclosure, the configuration of the first drive signal generation circuit is not limited to that shown in FIG. 22, and the first drive signal generation circuit may be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.

[0133] In at least one embodiment of the driving circuit shown in FIG. 23 of the present disclosure, during operation, when the potential of the N-stage driving output signal supplied from NO(N) drops from a high voltage to a low voltage, the potential of the first third control node NC1-3 can be pulled down, so that T1-6 can be better turned on, and the potential of the N-stage driving output signal is maintained at a low voltage.

[0134] At least one embodiment of the driver circuit shown in FIG. 23 of the present disclosure operates as follows. In the first stage, when NS(N-1) outputs a low voltage signal, GCK outputs a low voltage signal, and GCB outputs a high voltage signal, T1-19 and T1-21 turn on to pull down the potential of N1-5 and N1-9, T1-24 and T1-18 turn on to pull down the potential of NC1-2 and N1-6, and T1-26 turns on. The potential of N1-6 is low, ensuring that T1-23 is on, the potential of N1-5 is low, T1-13 is turned on, a low voltage signal is supplied from GCK, T1-12 is turned on, T1-14 is turned on, the potentials of N1-7 and N1-8 are low, T1-15 is turned on to control the potential of N1-3 to high, the potential of N1-5 is low, T1-17 is turned on, and the potential of NC1-1 is high. T1-10 and T1-11 are turned on, and the potentials of NC1-2 and NC1-3 are both low voltages. In the second stage, a low voltage signal is output from NS(N-1), the potential of the first clock signal output from GCK jumps from low voltage to high voltage, a low voltage signal is output from GCB, T1-19 and T1-21 are turned off, the potential of N1-5 is low voltage, T1-12 is turned off and the potential of N1-5 is maintained at low voltage, T1-13 is turned on, T1-14 is turned on, the potential of N1-7 and the potential of N1-8 are high voltage, T1-15 is turned off and the potential of N1-3 is maintained at the high voltage of the previous stage, T1-16 is turned on and the potential of NC1-1 is maintained at high voltage, and T1-25 is turned off. At the same time, the potential of N1-6 is low, turning on T1-23, and the GCB writes a low-voltage signal to N1-4. C1-4 pulls down the potential of N1-6 to a lower voltage (5V to 10V lower than the voltage of the low-voltage signal supplied by the GCB). T1-10 and T1-11 turn on, writing a low-voltage signal to NC1-2 and N1-6 (the potential of NC1-2 is 3V to 8V lower than the voltage of the low-voltage signal supplied by the GCB). T1-26 turns on sufficiently, outputting a low-voltage signal from NS(N). The potential of NC1-3 is low, turning on T1-6, outputting a low-voltage signal from NO(N). The potential of N1-4 is low, turning on T1-8, pulling down the potential of N1-1. T1-9 turns on, controlling the potential of NC1-3 to a low voltage, turning on T1-6, outputting a low-voltage signal from NO(N). Since the potential of N1-4 is low voltage, T1-8 turns on and controls the potential of N1-1 to low voltage, T1-3 turns on and controls to make NC1-1 and N1-2 conductive, and the potential of N1-2 is high voltage, so T1-5 turns off. In the third stage, a high voltage signal is output from NS(N-1), a low voltage signal is output from GCK, a high voltage signal is output from GCB, T1-19 and T1-21 turn on to pull up the potential of N1-5 and the potential of N1-9, T1-24 and T1-18 turn on, the potential of NC1-2 and the potential of N1-6 are high voltage, and T1-26 turns off. The potential of N1-6 is high voltage, T1-23 is off, the potential of N1-5 is high voltage, T1-13 is off, a low voltage signal is output from GCK, T1-12 is on, T1-14 is on and pulls down the potential of N1-7 and N1-8, T1-15 is on, GCB writes a high voltage signal to N1-3, T1-16 is off, the potential of N1-5 is high voltage, T1-17 is off, and the potential of NC1-1 is high voltage. This ensures that T1-25 is off. T1-22 is on, the potential of N1-4 is high voltage, and T1-8 is off. The potentials of NC1-1 and NC1-2 are both high voltage, and a low voltage signal continues to be output from NS(N). T1-10 and T1-11 are off. In the third stage, a low voltage signal is output from N1-3(N-1) and NS(N), T1-1 and T1-2 turn on, and conduction occurs between VCT and N1-1. In the third stage, when a high voltage signal is supplied from VCT, the potential of N1-1 is high, T1-9 is turned off, T1-3 is turned off, and the potential of N1-2 is maintained at high voltage. T1-9 is turned off, NC1-3 and N1-5 are disconnected, the potential of N1-6 is high, T1-10 and T1-11 are turned off, the potential of NC1-3 is maintained at low voltage, T1-6 is turned on, and a low voltage signal is output from NO(N). In the third stage, when a low voltage signal is supplied from VCT, the potential of N1-1 is low voltage, T1-9 is turned on, T1-3 is turned on, conduction occurs between NC1-1 and N1-2, the potential of N1-2 is high voltage, T1-5 is turned off, T1-9 is turned on, control is performed to conduct NC1-3 and N1-5, the potential of NC1-3 is high voltage, and a low voltage signal continues to be output from NO(N). In the fourth stage, NS(N-1) outputs a high-voltage signal, the potential of the first clock signal output from GCK jumps from low to high, GCB outputs a low-voltage signal, T1-19 and T1-21 turn off, N1-7 is maintained at a low voltage, T1-14 turns on, N1-8 is maintained at a low voltage, T1-15 turns on, T1-16 turns on and writes a low-voltage signal to N1-3 and NC1-1, T1-25 turns on, and NS(N) outputs a high-voltage signal. At the same time, N1-6 is maintained at a high voltage, T1-23 turns off, N1-4 is maintained at a high voltage, and N1-6 is maintained at a high voltage. T1-10 and T1-11 turn off. In the fourth stage, a high voltage signal is output from N1-3 (N-1), T1-2 is turned off, and T1-8 is turned off. When the potential of N1-1 is low, T1-9 is turned on to connect N1-5 and NC1-3, the potential of N1-5 is high, the potential of NC1-3 is high, and T1-6 is turned off. T1-3 is turned on to connect NC1-1 and N1-2, the potential of N1-2 is low, T1-5 is turned on, T1-6 is turned off, and a high voltage signal is output from NO(N). When the potential of N1-1 is high, T1-9 is turned off to cut off N1-5 and NC1-3, the potential of NC1-3 is maintained at high voltage, the potential of NC1-3 is maintained at the third stage low voltage, T1-6 is maintained on, T1-3 is turned off to cut off NC1-1 and N1-2, the potential of N1-2 is maintained at high voltage, T1-5 is turned off, and a low voltage signal continues to be output from NO(N). In the fifth stage, the potential of the N-1th stage driving signal output from NS(N-1) jumps from high voltage to low voltage, a high voltage signal is output from GCK, a low voltage signal is output from GCB, T1-19 and T1-21 are turned off, the potential of N1-5 and the potential of N1-9 are maintained at high voltage, and the potentials of the remaining nodes are maintained as they are, ensuring the output of a high voltage signal from NS(N). In the sixth stage, NS(N-1) outputs a low voltage signal, the potential of the first clock signal output from GCK jumps from high voltage to low voltage, GCB outputs a high voltage signal, T1-19 and T1-21 turn on, the potential of N1-5 and the potential of N1-9 are controlled to low voltage, T1-24 and T1-18 turn on, the potential of NC1-2 and N1-6 are low voltage, T1-26 is turned on, and N1-6 The potential is low, ensuring that T1-23 is on; the potential of N1-5 is low, turning on T1-13; T1-12 turns on, pulling down the potential of N1-7 and N1-8, turning on T1-5; GCB writes a high voltage signal to N1-3; the potential of N1-5 is low, turning on T1-17, pulling up the potential of NC1-1 to high voltage, ensuring that T1-25 is off.

[0135] At least one embodiment of the drive circuit shown in FIG. 24A differs from at least one embodiment of the drive circuit shown in FIG. 23 in the following respects. The first second node control circuit includes a first fourth transistor T1-4 and a first control transistor TC1. The gate of the first fourth transistor T1-4 is electrically connected to the first third control node NC1-3, the source of the first fourth transistor T1-4 is electrically connected to the drain of the first control transistor TC1, and the drain of the first fourth transistor T1-4 is electrically connected to the high voltage terminal VGH. The gate of the first control transistor TC1 is electrically connected to the Nth stage output driving terminal NO(N), and the source of the first control transistor TC1 is electrically connected to the first second node N1-2.

[0136] In at least one embodiment of the driving circuit shown in FIG. 24A of the present disclosure, during operation, when a low voltage signal is output from NO(N) and the potential of NC1-3 is low voltage, T1-4 and TC1 turn on to connect N1-2 to VGH, making the potential of N1-2 high voltage, ensuring that T1-5 is off, and ensuring the output of a low voltage signal from NO(N).

[0137] In FIG. 24A, the node marked with the symbol N1-11 is the first 11th node.

[0138] FIG. 24B is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG. 24A of the present disclosure.

[0139] At least one embodiment of the drive circuit shown in FIG. 25 differs from at least one embodiment of the drive circuit shown in FIG. 24 in the following respects. At least one embodiment of the driver circuit shown in FIG. 25 of the present disclosure further includes a first initialization circuit. The first initialization circuit includes a first seventh transistor T1-7. The gate of the first seventh transistor T1-7 is electrically connected to the initial control terminal NCX, the source of the first seventh transistor T1-7 is electrically connected to the first first node N1-1, and the drain of the first seventh transistor T1-7 is electrically connected to the low voltage terminal VGL.

[0140] In at least one embodiment of the driver circuit shown in FIG. 25, T1-7 are p-type transistors.

[0141] At least one embodiment of the driver circuit shown in FIG. 25 of the present disclosure operates as follows. At the start of display (i.e., when the display device is powered on), in the reset stage before the first stage, NCX outputs a low-voltage signal, T1-7 turns on to control the potential of N1-1 to a low voltage, and T1-3 turns on to control NC1-1 and N1-2 to be conductive. T1-9 turns on to control NC1-3 and N1-5 to be conductive. T1-20 turns on to control the potential of N1-5 and NC1-3 to be high. At this time, NC1-1 and N1-2 are at low potential, T1-25 turns on, T1-5 turns on, and high-voltage signals are output from NS(N) and NO(N), turning on all second display control transistors M2 included in all pixel circuits in the effective display area, emptying any charge remaining in the storage capacitor Cst and improving the screen flash defect when power is turned on. Thereafter, when a low voltage signal is output from both NS(N) and N1-3(N-1), T1-1 and T1-2 become conductive, and control is performed so that VCT and N1-1 become conductive. When a low-voltage signal is supplied from VCT, the potential of N1-1 is low, and C1-1 maintains the potential of N1-1. T1-3 turns on and controls NC1-1 and N1-2 to be conductive, at which time the potential of NC1-1 is high, the potential of N1-2 is high, T1-5 turns off, T1-9 turns on and controls NC1-3 and N1-5 to be conductive, the potential of NC1-3 is high, and a low-voltage signal continues to be output from NO(N). When a high voltage signal is supplied from VCT, the potential of N1-1 is high, T1-3 is off, NC1-1 and N1-2 are disconnected, C1-1 controls the potential of N1-2 to high voltage, T1-9 is off, NC1-3 and N1-5 are disconnected, the potential of N1-6 is high, T1-10 and T1-11 are off, the potential of NC1-3 is maintained at low voltage, T1-6 is on, and a low voltage signal is output from NO(N). Then, in the Nth stage drive signal supply stage, a high voltage signal is output from NS(N). At this time, the potential of NC1-1 is low voltage and the potential of NC1-2 is high voltage. When the potential of N1-1 is low voltage, T1-3 is turned on, causing conduction between NC1-1 and N1-2, the potential of N1-2 is low voltage, T1-9 is turned on, controlling N1-5 to conduct between NC1-3, the potential of N1-5 is high voltage, the potential of NC1-3 is high voltage, and T1-6 is turned off. T1-5 is turned on, T1-6 is turned off, and a high voltage signal is output from NO(N). When the potential of N1-1 is high, T1-3 turns off, NC1-1 and N1-2 are disconnected, the potential of N1-2 is maintained at high voltage, T1-9 turns off, N1-5 is controlled to be disconnected from NC1-3, the potential of NC1-3 is maintained at low voltage, T1-6 turns on, T1-5 turns off, and a low voltage signal continues to be output from NO(N). After the N-th stage driving signal supply step, when the potential of N1-4 is low, T1-8 is turned on to control N1-1 to be conductive with VGL, and when N1-1 is low, T1-3 is turned on to control NC1-1 to be conductive with N1-2. At this time, when NC1-1 is high, NC1-2 is low, and N1-2 is high, T1-9 is turned on to control NC1-3 to be conductive with N1-5. When the potentials of N1-5 and N1-6 are both low, T1-10 and T1-11 are turned on, NC1-3 is low, and a low-voltage signal is output from NO(N).

[0142] 25 of the present disclosure, when a low-voltage signal is output from N1-3(N-1) and a low-voltage signal is output from NS(N), T1-1 and T1-2 turn on, and the simultaneous gating of these two signals obtains the gating input signal state within one high-low frequency switching period and writes it to N1-1. T1-1 and T1-2 are not turned on simultaneously at other times, preventing the potential of N1-1 from being affected by the gating input signal supplied from VCT.

[0143] In at least one embodiment of the drive circuit shown in FIG. 25 of the present disclosure, during operation, when low voltage signals are output from both NS(N) and N3(N-1) and a low voltage signal is output from VCT, the potential of N1-1 is low, T1-3 is turned on, the potential of N1-2 is the same as the potential of NC1-1, NC1-3 turns off T1-6, and N1-2 turns on T1-5, thereby ensuring normal output of NO(N). When NS(N) and N1-3(N-1) both output low voltage signals and VCT outputs high voltage signals, N1-1 potential is high voltage, T1-3 is off, T1-9 is off, N1-2 potential is high voltage, T1-5 is off, N1-6 potential is high voltage, T1-11 is in reverse off state, NC1-3 potential is maintained at low voltage, T1-6 is turned on, and NO(N) can always output low voltage signals. NC1-3 potential is low voltage, T1-4 is turned on, N1-2 potential is maintained at high voltage, preventing T1-5 leakage. After NO(N) output is completed, N1-4 potential is low voltage, T1-8 is turned on, and N1-1 potential is pulled down to low voltage.

[0144] At least one embodiment of the driving circuit shown in FIG. 26 of the present disclosure differs from at least one embodiment of the driving circuit shown in FIG. 24 in the following respects. At least one embodiment of the driver circuit shown in FIG. 26 of the present disclosure further includes a first output pull-down circuit. The first output pull-down circuit includes a first transistor T1-27. The gate of the first 27th transistor T1-27 is electrically connected to the first first control node NC1-1, the source of the first 27th transistor T1-27 is electrically connected to the Nth stage driving signal output terminal NS(N), and the drain of the first 27th transistor T1-27 is electrically connected to the low voltage terminal VGL.

[0145] In at least one embodiment of the driver circuit shown in FIG. 26, T1-27 is an n-type transistor.

[0146] In at least one embodiment of the drive circuit shown in FIG. 26, during operation, when the potential of NC1-1 is a high voltage, T1-27 turns on, causing conduction between NS(N) and VGL, and a low voltage signal is output from NS(N).

[0147] At least one embodiment of the drive circuit shown in FIG. 27 differs from at least one embodiment of the drive circuit shown in FIG. 23 in that it does not include the first fourth transistor T1-4.

[0148] At least one embodiment of the driving circuit shown in FIG. 28 differs from at least one embodiment of the driving circuit shown in FIG. 23 in that it does not include the first eighth transistor T1-8.

[0149] At least one embodiment of the driving circuit shown in FIG. 29 differs from at least one embodiment of the driving circuit shown in FIG. 24 in that it does not include the first eighth transistor T1-8.

[0150] At least one embodiment of the drive circuit shown in FIG. 30 differs from at least one embodiment of the drive circuit shown in FIG. 23 in that T1-3 are single-gate transistors.

[0151] As shown in FIG. 31, the drive circuit according to the embodiment of the present disclosure includes a second drive signal generation circuit 210, a second gating circuit 211, a second output control circuit 212, and a second output circuit 213. The second drive signal generation circuit 210, which is electrically connected to the Nth (N is a positive integer) stage drive signal output terminal NS(N), generates an Nth stage drive signal and outputs it via the Nth stage drive signal output terminal NS(N). The second gating circuit 211, which is electrically connected to the second first node N2-1, the gating input terminal VCT, and the gating control terminal CX, controls the gating input signal supplied from the gating input terminal VCT to be written to the second first node N2-1 under the control of the gating control signal supplied from the gating control terminal CX. The first terminal of the second output control circuit 212 is electrically connected to the Nth stage driving signal output terminal NS(N), and the second terminal of the second output control circuit 212 is electrically connected to the second first node N2-1, and a first output signal is obtained by performing a NAND operation on the potential of the Nth stage driving signal and the second terminal of the second output control circuit 212. The second output circuit 213, electrically connected to the second output control circuit 212 and the output drive terminal NO(N), inverts the first output signal to obtain an output drive signal, which is supplied via the output drive terminal NO(N).

[0152] In the embodiment of the drive circuit shown in FIG. 31 of the present disclosure, during operation, the second drive signal generation circuit 210 generates an N-stage drive signal and outputs it via the N-stage drive signal output terminal NS(N), the second gating circuit 211 writes a gating input signal to the second first node N2-1 under the control of a gating control signal, the second output control circuit 212 performs a NAND operation on the N-stage drive signal and the potential of the second terminal of the second output control circuit 212 to obtain a first output signal, and the second output circuit 213 inverts the first output signal to obtain an output drive signal and supplies it via the output drive terminal NO(N).

[0153] The embodiment of the driving circuit shown in FIG. 31 of the present disclosure may be an Nth stage driving circuit.

[0154] The embodiment of the driving circuit shown in FIG. 31 of the present disclosure operates as follows within one frame time. Before the N-th stage driving signal supply step, the second gating circuit 211 writes the gating input signal supplied from the gating input terminal VCT to the second first node N2-1 under the control of the gating control signal. When the gating input signal is a high voltage signal, in the Nth stage driving signal supply step, when a high voltage signal is output from the Nth stage driving signal output terminal NS(N), the first output signal output from the second output control circuit 212 is a low voltage signal, and the second output circuit 213 supplies a high voltage signal through the output driving terminal NO(N), thereby controlling the pixel voltage of the pixel circuit in the corresponding row to be updated. When the gating input signal is a low voltage signal, in the Nth stage driving signal supply step, when a high voltage signal is output from the Nth stage driving signal output terminal NS(N), the first output signal output from the second output control circuit 212 is a high voltage signal, and the second output circuit 213 supplies a low voltage signal through the output driving terminal NO(N), thereby controlling so that the pixel voltages of the pixel circuits in the corresponding row are not updated.

[0155] In the embodiment of the present disclosure, by controlling the gating input signal supplied from the gating input terminal VCT, it is possible to update a part of the display screen to reduce power consumption, or to update a part of the display screen to achieve ultra-low power consumption in OLED display products such as wearable products, mobile terminals, and notebook computers (NBs).

[0156] The driving circuit according to at least one embodiment of the present disclosure may further include a second initialization circuit and a second first voltage maintenance circuit. The second initialization circuit, which is electrically connected to the initial control terminal, the first voltage terminal, and the second first node, respectively, controls the second first node and the first voltage terminal to be conductive under the control of an initial control signal supplied from the initial control terminal. A first terminal of the second first voltage maintenance circuit is electrically connected to the second first node, and a second terminal of the second first voltage maintenance circuit is electrically connected to a DC voltage terminal or a second third node, and the second first voltage maintenance circuit maintains the potential of the second first node.

[0157] In a specific implementation, the driving circuit may include a second initialization circuit and a second first voltage maintaining circuit, wherein the second initialization circuit controls the second first node to be conductive with the first voltage terminal under control of an initialization control signal, and the first potential maintaining circuit maintains the potential of the second first node.

[0158] As shown in FIG. 32, based on at least one embodiment of the driving circuit shown in FIG. 31, the driving circuit according to at least one embodiment of the present disclosure may further include a second initialization circuit 221 and a second first voltage maintenance circuit 222. The second initialization circuit 221, which is electrically connected to the initial control terminal NCX, the first voltage terminal V1, and the second first node N2-1, controls the second first node N2-1 and the first voltage terminal V1 to be conductive under the control of the initial control signal supplied from the initial control terminal NCX. A first terminal of the second first voltage maintenance circuit 222 is electrically connected to the second first node N2-1, and a second terminal of the second first voltage maintenance circuit 222 is electrically connected to a first voltage terminal V1, and the second first voltage maintenance circuit 222 maintains the potential of the second first node N2-1.

[0159] At least one embodiment of the driving circuit shown in FIG. 32, in operation, supplies an effective voltage signal from NCX at the start of one frame time, and controls the second initialization circuit 221 to connect the second first node N2-1 and the first voltage terminal V1.

[0160] In at least one embodiment of the present disclosure, the first voltage terminal may be, but is not limited to, a high voltage terminal.

[0161] The driving circuit according to at least one embodiment of the present disclosure may further include a second second voltage maintaining circuit, which includes a second first inverter, a second second inverter, and a second maintaining control circuit. An input terminal of the second first inverter is electrically connected to the second first node, an output terminal of the second first inverter is electrically connected to a second third node, an input terminal of the second second inverter is electrically connected to the second third node, and an output terminal of the second second inverter is electrically connected to a second fourth node. The second first inverter inverts the potential of the second first node, and outputs the inverted potential of the second first node via the output terminal of the second first inverter. The second second inverter inverts the potential of its input terminal and outputs the inverted potential via the output terminal of the second second inverter. The second sustain control circuit, which is electrically connected to a sustain control terminal, the second fourth node, and the second first node, respectively, controls conduction or interruption between the second fourth node and the second first node under control of a sustain control signal supplied from the sustain control terminal.

[0162] In a specific implementation, the driving circuit may further include a second second voltage maintenance circuit including a second first inverter, a second second inverter, and a second maintenance control circuit, where the second first inverter inverts the potential of the second first node, the second second inverter inverts the potential of its input terminal, and the second maintenance control circuit controls conduction or cutoff between the second fourth node and the second first node under the control of a maintenance control signal. When the second gating circuit controls to write the gating input signal to the second first node, the second sustain control circuit controls to disconnect the second fourth node from the second first node so as not to affect the potential of the second first node.

[0163] In operation, the drive circuit according to at least one embodiment of the present disclosure may further include a second second voltage maintenance circuit, and the second first inverter and the second second inverter included in the second second voltage maintenance circuit may be controlled to connect the output terminal of the second second inverter to the high voltage terminal when the potential of the second first node is high, so that the potential of the output terminal of the second second inverter is higher than the potential of the second first node. When the potential of the second first node is low, the drive circuit may be controlled to connect the output terminal of the second second inverter to the low voltage terminal, so that the potential of the output terminal of the second second inverter is lower than the potential of the second first node. The second sustain control circuit included in the second second voltage sustain circuit controls the output terminal of the second second inverter and the second first node to be conductive at the Nth stage driving signal output stage, and can further increase the absolute value of the potential of the second first node, so that the second first node can better control the transistor included in the second output control circuit, whose gate is electrically connected to the second first node.

[0164] 33, based on at least one embodiment of the driving circuit shown in FIG. 32, the driving circuit according to at least one embodiment of the present disclosure may further include a second second voltage sustain circuit. The second second voltage sustain circuit includes a second first inverter F21, a second second inverter F22, and a second sustain control circuit W21. The sustain control terminal includes an (N-1)th stage driving signal output terminal NS(N-1) and a first clock signal terminal GCK. An input terminal of the second first inverter F21 is electrically connected to the second first node N2-1, and an output terminal of the second first inverter F21 is electrically connected to a second third node N2-3. An input terminal of the second second inverter F22 is electrically connected to the second third node N2-3, and an output terminal of the second second inverter F22 is electrically connected to a second fourth node N2-4. The second first inverter F21 inverts the potential of the second first node N2-1 and outputs the inverted potential of the second first node N2-1 via the output terminal of the second first inverter F21. The second second inverter F22 inverts the potential of its input terminal and outputs the inverted potential via the output terminal of the second second inverter F22. The second sustain control circuit W21, which is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the second-fourth node N2-4, and the second-first node N2-1, respectively, controls the conduction or cut-off between the second-fourth node N2-4 and the second-first node N2-1 under control of the N-1th stage drive signal supplied from the N-1th stage drive signal output terminal NS(N-1), and controls the conduction or cut-off between the second-fourth node N2-4 and the second-first node N2-1 under control of the first clock signal supplied from the first clock signal terminal GCK.

[0165] In at least one embodiment shown in FIG. 33, the N-1th stage drive signal output terminal may be replaced with a second clock signal terminal, but is not limited to this.

[0166] In at least one embodiment of the present disclosure, the driving circuit may further include a second voltage maintaining circuit. The second first node is electrically connected to a second terminal of the second output control circuit via the second second voltage maintenance circuit. The second second voltage maintaining circuit includes a second first inverter, a second second inverter, and a second maintaining control circuit. An input terminal of the second first inverter is electrically connected to the second first node, an output terminal of the second first inverter is electrically connected to a second third node, an input terminal of the second second inverter is electrically connected to the second third node, and an output terminal of the second second inverter is electrically connected to a second fourth node and a second terminal of the second output control circuit. The second first inverter inverts the potential of the second first node and outputs the inverted potential of the second first node via the output terminal of the second first inverter, and the second second inverter inverts the potential of its input terminal and outputs the inverted potential via the output terminal of the second second inverter. The second sustain control circuit, which is electrically connected to a sustain control terminal, the second fourth node, and the second first node, respectively, controls conduction or interruption between the second fourth node and the second first node under control of a sustain control signal supplied from the sustain control terminal.

[0167] In a specific implementation, the driving circuit may further include a second second voltage maintenance circuit. The second first node may be electrically connected to the second terminal of the second output control circuit via the second second voltage maintenance circuit. The second second voltage maintenance circuit may include a second first inverter, a second second inverter, and a second maintenance control circuit. The second first inverter inverts the potential of the second first node, and the second second inverter inverts the potential of its input terminal. The second maintenance control circuit controls conduction or cutoff between the second fourth node and the second first node under control of a sustain control signal supplied from the sustain control terminal. The second sustain control circuit controls to disconnect the second fourth node from the second first node when the second gating circuit controls to write the gating input signal to the second first node.

[0168] In operation, the drive circuit according to at least one embodiment of the present disclosure further includes a second second voltage maintenance circuit, and the second first inverter and the second second inverter included in the second second voltage maintenance circuit are controlled to connect the second fourth node and the high voltage terminal when the potential of the second first node is a high voltage, so that the potential of the second fourth node is higher than the potential of the second first node. When the potential of the second first node is a low voltage, the second fourth node and the low voltage terminal are controlled to connect the second fourth node and the low voltage terminal, so that the potential of the second fourth node is lower than the potential of the second first node. The second fourth node can better control a transistor included in the second output control circuit, whose gate is electrically connected to the second fourth node.

[0169] As shown in Figure 34, based on at least one embodiment of the driving circuit shown in Figure 32, the driving circuit may further include a second second voltage sustain circuit, and the sustain control terminal includes an N-1th stage driving signal output terminal NS(N-1) and a first clock signal terminal GCK. The second first node N2-1 is electrically connected to the second terminal of the second output control circuit 212 via the second second voltage maintenance circuit. The second second voltage maintaining circuit includes a second first inverter F21, a second second inverter F22, and a second maintaining control circuit W21. An input terminal of the second first inverter F21 is electrically connected to the second first node N2-1, and an output terminal of the second first inverter F21 is electrically connected to a second third node N2-3. The input terminal of the second second inverter F22 is electrically connected to the second third node N2-3, and the output terminal of the second second inverter F22 is electrically connected to the second fourth node N2-4 and the second terminal of the second output control circuit 12. The second first inverter F21 inverts the potential of the second first node N2-1 and outputs the inverted potential of the second first node N2-1 via the output terminal of the second first inverter F21. The second second inverter F22 inverts the potential of its input terminal and outputs the inverted potential via the output terminal of the second second inverter F22. The second sustain control circuit W21, which is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the second-fourth node N2-4, and the second-first node N2-1, respectively, controls the conduction or cut-off between the second-fourth node N2-4 and the second-first node N2-1 under control of the N-1th stage drive signal supplied from the N-1th stage drive signal output terminal NS(N-1), and controls the conduction or cut-off between the second-fourth node N2-4 and the second-first node N2-1 under control of the first clock signal supplied from the first clock signal terminal GCK.

[0170] In at least one embodiment shown in FIG. 34, the N-1th stage drive signal output terminal may be replaced with a second clock signal terminal, but is not limited to this.

[0171] Optionally, the sustain control terminal includes a first sustain control terminal and a second sustain control terminal. The second sustain control circuit includes a second third transistor and a second fourth transistor. A gate of the second third transistor is electrically connected to the first maintenance control terminal, a first electrode of the second third transistor is electrically connected to the second first node, and a second electrode of the second third transistor is electrically connected to the second fourth node. A gate of the second fourth transistor is electrically connected to a second maintenance control terminal, a first electrode of the second fourth transistor is electrically connected to the second fourth node, and a second electrode of the second fourth transistor is electrically connected to the second first node. The second third transistor is a p-type transistor, and the second fourth transistor is an n-type transistor. The first sustain control terminal is an (N-1)th stage driving signal terminal, and the second sustain control terminal is a first clock signal terminal. Alternatively, the first sustain control terminal is a second clock signal terminal, and the second sustain control terminal is a first clock signal terminal.

[0172] Optionally, the second first inverter includes a second fifth transistor and a second sixth transistor, and the second second inverter includes a second seventh transistor and a second eighth transistor. A gate of the second fifth transistor is electrically connected to the second first node, a first electrode of the second fifth transistor is electrically connected to a first voltage terminal, and a second electrode of the second fifth transistor is electrically connected to a second third node. A gate of the second sixth transistor is electrically connected to the second first node, a first electrode of the second sixth transistor is electrically connected to the second third node, and a second electrode of the second sixth transistor is electrically connected to a second voltage terminal. The second fifth transistor is a p-type transistor, and the second sixth transistor is an n-type transistor. A gate of the second seventh transistor is electrically connected to the second third node, a first electrode of the second seventh transistor is electrically connected to the first voltage terminal, and a second electrode of the second seventh transistor is electrically connected to the second fourth node. A gate of the second eighth transistor is electrically connected to the second third node, a first electrode of the second eighth transistor is electrically connected to the second fourth node, and a second electrode of the second eighth transistor is electrically connected to a second voltage terminal. The second seventh transistor is a p-type transistor, and the second eighth transistor is an n-type transistor.

[0173] Optionally, the second initialization circuit includes a second ninth transistor, and the second first voltage maintenance circuit includes a second first capacitor. A gate of the second ninth transistor is electrically connected to the initial control terminal, a first electrode of the second ninth transistor is electrically connected to a first voltage terminal, and a second electrode of the second ninth transistor is electrically connected to a second first node. A first terminal of the second first capacitor is electrically connected to the second first node, and a second terminal of the second first capacitor is electrically connected to the DC voltage terminal or a second third node.

[0174] Optionally, the second output control circuit includes a second tenth transistor, a second eleventh transistor, a second twelfth transistor, and a second thirteenth transistor. A gate of the second tenth transistor is electrically connected to the N-stage driving signal output terminal, a first electrode of the second tenth transistor is electrically connected to a first voltage terminal, and a second electrode of the second tenth transistor is electrically connected to a second fifth node. A gate of the second eleventh transistor is electrically connected to the second first node, a first pole of the second eleventh transistor is electrically connected to the first voltage terminal, and a second pole of the second eleventh transistor is electrically connected to the second fifth node. A gate of the second twelfth transistor is electrically connected to the N-th stage driving signal output terminal, a first electrode of the second twelfth transistor is electrically connected to the second fifth node, and a second electrode of the second twelfth transistor is electrically connected to the second sixth node. A gate of the second thirteenth transistor is electrically connected to the second first node, a first pole of the second thirteenth transistor is electrically connected to the second sixth node, and a second pole of the second thirteenth transistor is electrically connected to the second voltage terminal. The second tenth transistor and the second eleventh transistor are p-type transistors, and the second twelfth transistor and the second thirteenth transistor are n-type transistors.

[0175] Optionally, the second output control circuit includes a second tenth transistor, a second eleventh transistor, a second twelfth transistor, and a second thirteenth transistor. A gate of the second tenth transistor is electrically connected to the N-stage driving signal output terminal, a first electrode of the second tenth transistor is electrically connected to a first voltage terminal, and a second electrode of the second tenth transistor is electrically connected to a second fifth node. A gate of the second eleventh transistor is electrically connected to the second fourth node, a first electrode of the second eleventh transistor is electrically connected to the first voltage terminal, and a second electrode of the second eleventh transistor is electrically connected to the second fifth node. A gate of the second twelfth transistor is electrically connected to the N-th stage driving signal output terminal, a first electrode of the second twelfth transistor is electrically connected to the second fifth node, and a second electrode of the second twelfth transistor is electrically connected to the second sixth node. A gate of the second thirteenth transistor is electrically connected to the second fourth node, a first electrode of the second thirteenth transistor is electrically connected to the second sixth node, and a second electrode of the second thirteenth transistor is electrically connected to the second voltage terminal. The second tenth transistor and the second eleventh transistor are p-type transistors, and the second twelfth transistor and the second thirteenth transistor are n-type transistors.

[0176] Optionally, the second output circuit includes a second fourteenth transistor and a second fifteenth transistor. A gate of the second fourteenth transistor is electrically connected to the second fifth node, a first electrode of the second fourteenth transistor is electrically connected to a first voltage terminal, and a second electrode of the second fourteenth transistor is electrically connected to an output drive terminal. A gate of the second fifteenth transistor is electrically connected to the second fifth node, a first electrode of the second fifteenth transistor is electrically connected to the output driving terminal, and a second electrode of the second fifteenth transistor is electrically connected to a second voltage terminal.

[0177] In at least one embodiment of the present disclosure, the second drive signal generation circuit may include a second first control node control circuit, a second second control node control circuit, a second first drive output circuit, and a second second drive output circuit. The second first control node control circuit controls the potential of the first control node. The second second control node control circuit controls the potential of the second control node. The second first drive output circuit, which is electrically connected to a first control node, a first voltage terminal, and an N-stage drive signal output terminal, controls the N-stage drive signal output terminal and the first voltage terminal to be electrically connected together under control of the potential of the first control node. The second second drive output circuit, which is electrically connected to a second control node, a second voltage terminal, and the N-stage drive signal output terminal, respectively, controls the N-stage drive signal output terminal and the second voltage terminal to be electrically connected together under control of the potential of the second control node.

[0178] In a specific implementation, the second drive signal generation circuit may include a second first control node control circuit, a second second control node control circuit, a second first drive output circuit, and a second second drive output circuit. The second first control node control circuit controls the potential of the first control node. The second second control node control circuit controls the potential of the second control node. The second first drive output circuit controls the Nth stage drive signal output terminal and the first voltage terminal to be electrically connected under the control of the potential of the first control node. The second second drive output circuit controls the Nth stage drive signal output terminal and the second voltage terminal to be electrically connected under the control of the potential of the second control node.

[0179] Optionally, the first voltage terminal may be a high voltage terminal and the second voltage terminal may be a low voltage terminal, but is not limited thereto.

[0180] As shown in Figure 35, based on at least one embodiment of the drive circuit shown in Figure 33, the second drive signal generation circuit may include a second first control node control circuit 231, a second second control node control circuit 232, a second first drive output circuit 233, and a second second drive output circuit 234. The second first control node control circuit 231, which is electrically connected to the first control node NC2-1, controls the potential of the first control node NC2-1. The second second control node control circuit 232, which is electrically connected to the second control node NC2-2, controls the potential of the second control node NC2-2. The second first drive output circuit 233, which is electrically connected to the first control node NC2-1, the first voltage terminal V1, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) and the first voltage terminal V12 to be conductive under the control of the potential of the first control node NC2-1. The second second drive output circuit 234, which is electrically connected to the second control node NC2-2, the second voltage terminal V2, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 to be conductive under the control of the potential of the second control node NC2-2.

[0181] As shown in Figure 36, based on at least one embodiment of the drive circuit shown in Figure 34, the second drive signal generation circuit may include a second first control node control circuit 231, a second second control node control circuit 232, a second first drive output circuit 233, and a second second drive output circuit 234. The second first control node control circuit 231, which is electrically connected to the first control node NC2-1, controls the potential of the first control node NC2-1. The second second control node control circuit 232, which is electrically connected to the second control node NC2-2, controls the potential of the second control node NC2-2. The second first drive output circuit 233, which is electrically connected to the first control node NC2-1, the first voltage terminal V1, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) and the first voltage terminal V12 to be conductive under the control of the potential of the first control node NC2-1. The second second drive output circuit 234, which is electrically connected to the second control node NC2-2, the second voltage terminal V2, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 to be conductive under the control of the potential of the second control node NC2-2.

[0182] In at least one embodiment of the present disclosure, the second first control node control circuit includes a second seventh node control circuit, a second eighth node control circuit, and a second first control circuit. The second seventh node control circuit, which is electrically connected to the first clock signal terminal, the first voltage terminal, the second seventh node, and the second ninth node, respectively, controls the second seventh node and the first voltage terminal to be electrically connected together under control of the first clock signal supplied from the first clock signal terminal, and controls the second seventh node and the first clock signal terminal to be electrically connected together under control of the potential of the second ninth node. The second-eighth-node control circuit, which is electrically connected to the second voltage terminal, the second seventh node, and the second eighth node, respectively, controls the second seventh node and the second eighth node to be conductive under the control of a second voltage signal supplied from the second voltage terminal. The second first control circuit, which is electrically connected to the second eighth node, the second second node, the second clock signal terminal, the second ninth node, the first voltage terminal, and the first control node, respectively, controls the second second node and the second clock signal terminal to be electrically connected together under control of the potential of the second eighth node, controls the potential of the second second node based on the potential of the second eighth node, controls the second second node and the first control node to be electrically connected together under control of the second clock signal supplied from the second clock signal terminal, and controls the first control node and the first voltage terminal to be electrically connected together under control of the potential of the second ninth node.

[0183] In a specific implementation, the second first control node control circuit may include a second seventh node control circuit, a second eighth node control circuit, and a second first control circuit. The second seventh node control circuit controls the potential of the second seventh node. The second eighth node control circuit controls the potential of the second eighth node. The second first control circuit controls the potential of the first control node.

[0184] In at least one embodiment of the present disclosure, the second second control node control circuit includes a second ninth node control circuit, a second tenth node control circuit, a second eleventh node control circuit, and a second second control circuit. The second ninth node control circuit, which is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal, the initial control terminal, the first voltage terminal, and the second ninth node, respectively, controls the N-1th stage drive signal output terminal and the second ninth node to be conductive under the control of a first clock signal supplied from the first clock signal terminal, and controls the second ninth node and the first voltage terminal to be conductive under the control of an initial control signal supplied from the initial control terminal. The second-tenth node control circuit, which is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal, and the second-tenth node, respectively, controls the N-1th stage drive signal output terminal and the second-tenth node to be electrically connected under the control of the first clock signal. The second-11th node control circuit, which is electrically connected to the second voltage terminal, the second-10th node, the second-11th node, the second-7th node, the first voltage terminal, the second-12th node, and the second clock signal terminal, respectively, controls the second-10th node and the second-11th node to be electrically connected together under control of a second voltage signal supplied from the second voltage terminal, controls the electrical connection between the second-12th node and the first voltage terminal under control of the potential of the second-7th node, controls the second-12th node and the second clock signal terminal to be electrically connected together under control of the potential of the second-11th node, and controls the potential of the second-11th node based on the potential of the second-12th node. The second second control circuit, which is electrically connected to the second control node, the second eleventh node, the second voltage terminal, and the second ninth node, respectively, controls the potential of the second control node under control of the potential of the second eleventh node, and controls the second ninth node and the second control node to be conductive under control of a second voltage signal supplied from the second voltage terminal.

[0185] In a specific implementation, the second second control node control circuit may include a second ninth node control circuit, a second tenth node control circuit, a second eleventh node control circuit, and a second second control circuit. The second ninth node control circuit controls the potential of the second ninth node. The second tenth node control circuit controls the potential of the second tenth node. The second eleventh node control circuit controls the potential of the second eleventh node. The second second control circuit controls the potential of the second control node.

[0186] As shown in FIG. 37, based on at least one embodiment of the driving circuit shown in FIG. 35, the second first control node control circuit includes a second seventh node control circuit 241, a second eighth node control circuit 242, and a second first control circuit 243. The second seventh node control circuit 241, which is electrically connected to the first clock signal terminal GCK, the second voltage terminal V2, the second seventh node N2-7, and the second ninth node N2-9, respectively, controls the second seventh node N2-7 and the second voltage terminal V2 to be electrically connected together under control of the first clock signal supplied from the first clock signal terminal GCK, and controls the second seventh node N2-7 and the first clock signal terminal GCK to be electrically connected together under control of the potential of the second ninth node N2-9. The second-eighth node control circuit 242, which is electrically connected to the second voltage terminal V2, the second seventh node N2-7, and the second eighth node N2-8, respectively, controls the second seventh node N2-7 and the second eighth node N2-8 to be conductive under the control of a second voltage signal supplied from the second voltage terminal V2. The second first control circuit 243, which is electrically connected to the second eighth node N2-8, the second second node N2-2, the second clock signal terminal GCB, the second ninth node N2-9, the first voltage terminal V1, and the first control node NC2-1, controls the second second node N2-2 and the second clock signal terminal GCB to be electrically connected together under control of the potential of the second eighth node N2-8, controls the potential of the second second node N2-2 based on the potential of the second eighth node N2-8, controls the second second node N2-2 and the first control node NC2-1 to be electrically connected together under control of the second clock signal supplied from the second clock signal terminal GCB, and controls the first control node NC2-1 and the first voltage terminal V1 to be electrically connected together under control of the potential of the second ninth node N2-9. The second second control node control circuit includes a second ninth node control circuit 251 , a second tenth node control circuit 252 , a second eleventh node control circuit 253 , and a second second control circuit 254 . The second-ninth node control circuit 251, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), the initial control terminal NCX, the first voltage terminal V1, and the second-ninth node N2-9, controls the N-1th stage drive signal output terminal NS(N-1) and the second-ninth node N2-9 to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK, and controls the second-ninth node N2-9 and the first voltage terminal V1 to be conductive under the control of the initial control signal supplied from the initial control terminal NCX. The second tenth node control circuit 252, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output NS(N-1), and the second tenth node N2-10, controls the N-1th stage drive signal output NS(N-1) and the second tenth node N2-10 to be electrically connected to each other under the control of the first clock signal. The second-eleventh node control circuit 253, which is electrically connected to the second voltage terminal V2, the second tenth node N2-10, the second eleventh node N2-11, the second seventh node N2-7, the first voltage terminal V1, the second twelfth node N2-12, and the second clock signal terminal GCB, respectively, conducts the second tenth node N2-10 and the second eleventh node N2-11 under the control of the second voltage signal supplied from the second voltage terminal V2. under control of the potential of the second seventh node N2-7, the second twelfth node N2-12 and the first voltage terminal V1 are controlled to be electrically connected to each other, under control of the potential of the second eleventh node N2-11, the second twelfth node N2-12 and the second clock signal terminal GCB are controlled to be electrically connected to each other, and the potential of the second eleventh node N2-11 is controlled based on the potential of the second twelfth node N2-12. The second control circuit 254, which is electrically connected to the second control node NC2-2, the second eleventh node N2-11, the second voltage terminal V2, and the second ninth node N2-9, controls the potential of the second control node NC2-2 under control of the potential of the second eleventh node N2-11, and controls the second ninth node N2-9 and the second control node NC2-2 to be conductive under control of a second voltage signal supplied from the second voltage terminal V2.

[0187] As shown in FIG. 38, based on at least one embodiment of the driving circuit shown in FIG. 36, the second first control node control circuit includes a second seventh node control circuit 241, a second eighth node control circuit 242, and a second first control circuit 243. The second seventh node control circuit 241, which is electrically connected to the first clock signal terminal GCK, the second voltage terminal V2, the second seventh node N2-7, and the second ninth node N2-9, respectively, controls the second seventh node N2-7 and the second voltage terminal V2 to be electrically connected together under control of the first clock signal supplied from the first clock signal terminal GCK, and controls the second seventh node N2-7 and the first clock signal terminal GCK to be electrically connected together under control of the potential of the second ninth node N2-9. The second-eighth node control circuit 242, which is electrically connected to the second voltage terminal V2, the second seventh node N2-7, and the second eighth node N2-8, respectively, controls the second seventh node N2-7 and the second eighth node N2-8 to be conductive under the control of a second voltage signal supplied from the second voltage terminal V2. The second first control circuit 243, which is electrically connected to the second eighth node N2-8, the second second node N2-2, the second clock signal terminal GCB, the second ninth node N2-9, the first voltage terminal V1, and the first control node NC2-1, controls the second second node N2-2 and the second clock signal terminal GCB to be electrically connected together under control of the potential of the second eighth node N2-8, controls the potential of the second second node N2-2 based on the potential of the second eighth node N2-8, controls the second second node N2-2 and the first control node NC2-1 to be electrically connected together under control of the second clock signal supplied from the second clock signal terminal GCB, and controls the first control node NC2-1 and the first voltage terminal V1 to be electrically connected together under control of the potential of the second ninth node N2-9. The second second control node control circuit includes a second ninth node control circuit 251 , a second tenth node control circuit 252 , a second eleventh node control circuit 253 , and a second second control circuit 254 . The second-ninth node control circuit 251, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), the initial control terminal NCX, the first voltage terminal V1, and the second-ninth node N2-9, controls the N-1th stage drive signal output terminal NS(N-1) and the second-ninth node N2-9 to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK, and controls the second-ninth node N2-9 and the first voltage terminal V1 to be conductive under the control of the initial control signal supplied from the initial control terminal NCX. The second tenth node control circuit 252, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output NS(N-1), and the second tenth node N2-10, controls the N-1th stage drive signal output NS(N-1) and the second tenth node N2-10 to be electrically connected to each other under the control of the first clock signal. The second-eleventh node control circuit 253, which is electrically connected to the second voltage terminal V2, the second tenth node N2-10, the second eleventh node N2-11, the second seventh node N2-7, the first voltage terminal V1, the second twelfth node N2-12, and the second clock signal terminal GCB, respectively, conducts the second tenth node N2-10 and the second eleventh node N2-11 under the control of the second voltage signal supplied from the second voltage terminal V2. under control of the potential of the second seventh node N2-7, the second twelfth node N2-12 and the first voltage terminal V1 are controlled to be electrically connected to each other, under control of the potential of the second eleventh node N2-11, the second twelfth node N2-12 and the second clock signal terminal GCB are controlled to be electrically connected to each other, and the potential of the second eleventh node N2-11 is controlled based on the potential of the second twelfth node N2-12. The second control circuit 254, which is electrically connected to the second control node NC2-2, the second eleventh node N2-11, the second voltage terminal V2, and the second ninth node N2-9, controls the potential of the second control node NC2-2 under control of the potential of the second eleventh node N2-11, and controls the second ninth node N2-9 and the second control node NC2-2 to be conductive under control of a second voltage signal supplied from the second voltage terminal V2.

[0188] Optionally, the second first driving output circuit includes a second sixteenth transistor and a second second capacitor. The gate of the second 16th transistor is electrically connected to the first control node, the first electrode of the second 16th transistor is electrically connected to a first voltage terminal, and the second electrode of the second 16th transistor is electrically connected to the Nth stage driving signal output terminal. A first terminal of the second second capacitor is electrically connected to the first control node, and a second terminal of the second second capacitor is electrically connected to the first voltage terminal. The second second driving output circuit includes a second seventeenth transistor and a second third capacitor. The gate of the second 17th transistor is electrically connected to the second control node, the first electrode of the second 17th transistor is electrically connected to the Nth stage driving signal output terminal, and the second electrode of the second 17th transistor is electrically connected to a second voltage terminal. A first terminal of the second third capacitor is electrically connected to the N-stage driving signal output terminal, and a second terminal of the second third capacitor is electrically connected to a second voltage terminal.

[0189] Optionally, the second seventh node control circuit includes a second eighteenth transistor and a second nineteenth transistor. A gate of the second 18th transistor is electrically connected to the first clock signal terminal, a first electrode of the second 18th transistor is electrically connected to a second voltage terminal, and a second electrode of the second 18th transistor is electrically connected to a second seventh node. A gate of the second 19th transistor is electrically connected to the second 9th node, a first pole of the second 19th transistor is electrically connected to the second 7th node, and a second pole of the second 19th transistor is electrically connected to a first clock signal terminal. The second eighth node control circuit includes a second twentieth transistor. A gate of the second twentieth transistor is electrically connected to the second voltage terminal, a first electrode of the second twentieth transistor is electrically connected to the second seventh node, and a second electrode of the second twentieth transistor is electrically connected to the second eighth node. The second first control circuit includes a second 21st transistor, a second 4th capacitor, a second 22nd transistor, and a second 23rd transistor. The gate of the second 21st transistor is electrically connected to the second 8th node, the first pole of the second 21st transistor is electrically connected to the second clock signal terminal, and the second pole of the second 21st transistor is electrically connected to the second 2nd node. A first terminal of the second fourth capacitor is electrically connected to the second eighth node, and a second terminal of the second fourth capacitor is electrically connected to the second second node. A gate of the second 22nd transistor is electrically connected to the second clock signal terminal, a first pole of the second 22nd transistor is electrically connected to a second second node, and a second pole of the second 22nd transistor is electrically connected to the first control node. A gate of the second 23rd transistor is electrically connected to a second 9th node, a first electrode of the second 23rd transistor is electrically connected to the first control node, and a second electrode of the second 23rd transistor is electrically connected to a first voltage terminal.

[0190] Optionally, the second ninth node control circuit includes a second twenty-fourth transistor and a second twenty-fifth transistor. A gate of the second 24th transistor is electrically connected to a first clock signal terminal, a first pole of the second 24th transistor is electrically connected to the N-1th stage driving signal output terminal, and a second pole of the second 24th transistor is electrically connected to the second 9th node. A gate of the second 25th transistor is electrically connected to the initial control terminal, a first electrode of the second 25th transistor is electrically connected to the first voltage terminal, and a second electrode of the second 25th transistor is electrically connected to a second 9th node. The second tenth node control circuit includes a second twenty-sixth transistor. A gate of the second 26th transistor is electrically connected to a first clock signal terminal, a first electrode of the second 26th transistor is electrically connected to the N-1th stage driving signal output terminal, and a second electrode of the second 26th transistor is electrically connected to the second 10th node. The second eleventh node control circuit includes a second twenty-seventh transistor, a second twenty-eighth transistor, a second twenty-ninth transistor, and a second fifth capacitor. A gate of the second 27th transistor is electrically connected to a second voltage terminal, a first electrode of the second 27th transistor is electrically connected to a second 10th node, and a second electrode of the second 27th transistor is electrically connected to a second 11th node. The gate of the second 28th transistor is electrically connected to a second 7th node, the first electrode of the second 28th transistor is electrically connected to a first voltage terminal, and the second electrode of the second 28th transistor is electrically connected to a second 12th node. A gate of the second 29th transistor is electrically connected to a second 11th node, a first pole of the second 29th transistor is electrically connected to a second 12th node, and a second pole of the second 29th transistor is electrically connected to a second clock signal terminal. A first terminal of the second fifth capacitor is electrically connected to the second twelfth node, and a second terminal of the second fifth capacitor is electrically connected to the second eleventh node. The second second control circuit includes a second 30th transistor and a second 31st transistor. The gate of the second 30th transistor and the first pole of the second 30th transistor are both electrically connected to the second 11th node, and the second pole of the second 30th transistor is electrically connected to the second control node. A gate of the second 31st transistor is electrically connected to a second voltage terminal, a first electrode of the second 31st transistor is electrically connected to the second 9th node, and a second electrode of the second 31st transistor is electrically connected to a second control node.

[0191] As shown in FIG. 39, based on at least one embodiment of the driving circuit shown in FIG. 37, the second gating circuit includes a second first transistor T2-1 and a second second transistor T2-2. The gate of the second first transistor T2-1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the second first transistor T2-1 is electrically connected to the second first node N2-1, and the drain of the second first transistor T2-1 is electrically connected to the drain of the second second transistor T2-2. The gate of the second second transistor T2-2 is electrically connected to the N-stage driving signal output terminal NS(N), and the source of the second second transistor T2-2 is electrically connected to the gating input terminal VCT. The second sustain control circuit includes a second third transistor T2-3 and a second fourth transistor T2-4. The gate of the second third transistor T2-3 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the second third transistor T2-3 is electrically connected to the second first node N2-1, and the drain of the second third transistor T2-3 is electrically connected to the second fourth node N2-4. The gate of the second fourth transistor T2-4 is electrically connected to the first clock signal terminal GCK, the source of the second fourth transistor T2-4 is electrically connected to the second fourth node N2-4, and the drain of the second fourth transistor T2-4 is electrically connected to the second first node N2-1. The second first inverter includes a second fifth transistor T2-5 and a second sixth transistor T2-6, and the second second inverter includes a second seventh transistor T2-7 and a second eighth transistor T2-8. The gate of the second fifth transistor T2-5 is electrically connected to the second first node N2-1, the source of the second fifth transistor T2-5 is electrically connected to the high voltage terminal VGH, and the drain of the second fifth transistor T2-5 is electrically connected to the second third node N2-3. The gate of the second-sixth transistor T2-6 is electrically connected to the second-first node N2-1, the source of the second-sixth transistor T2-6 is electrically connected to the second-third node N2-3, and the drain of the second-sixth transistor T2-6 is electrically connected to the low voltage terminal VGL. The gate of the second seventh transistor T2-7 is electrically connected to the second third node N2-3, the source of the second seventh transistor T2-7 is electrically connected to the high voltage terminal VGH, and the drain of the second seventh transistor T2-7 is electrically connected to the second fourth node N2-4. The gate of the second eighth transistor T2-8 is electrically connected to the second third node N2-3, the source of the second eighth transistor T2-8 is electrically connected to the second fourth node N2-4, and the drain of the second eighth transistor T2-8 is electrically connected to the low voltage terminal VGL. The second initialization circuit includes a second ninth transistor T2-9, and the second first voltage maintenance circuit includes a second first capacitor C2-1. The gate of the second ninth transistor T2-9 is electrically connected to the initial control terminal NCX, the source of the second ninth transistor T2-9 is electrically connected to the high voltage terminal VGH, and the drain of the second ninth transistor T2-9 is electrically connected to the second first node N2-1. A first terminal of the second first capacitor C2-1 is electrically connected to the second first node N2-1, and a second terminal of the second first capacitor C2-1 is electrically connected to a low voltage terminal VGL. The second output control circuit includes a second tenth transistor T2-10, a second eleventh transistor T2-11, a second twelfth transistor T2-12, and a second thirteenth transistor T2-13. The gate of the second tenth transistor T2-10 is electrically connected to the N-stage driving signal output terminal NS(N), the source of the second tenth transistor T2-10 is electrically connected to the high voltage terminal VGH, and the drain of the second tenth transistor T2-10 is electrically connected to the second fifth node N2-5. The gate of the second eleventh transistor T2-11 is electrically connected to the second first node N2-1, the source of the second eleventh transistor T2-11 is electrically connected to the high voltage terminal VGH, and the drain of the second eleventh transistor T2-11 is electrically connected to the second fifth node N2-5. The gate of the second twelfth transistor T2-12 is electrically connected to the N-th stage driving signal output terminal NS(N), the source of the second twelfth transistor T2-12 is electrically connected to the second fifth node N2-5, and the drain of the second twelfth transistor T2-12 is electrically connected to the second sixth node N2-6. The gate of the second thirteenth transistor T2-13 is electrically connected to the second first node N2-1, the source of the second thirteenth transistor T2-13 is electrically connected to the second sixth node N2-6, and the drain of the second thirteenth transistor T2-13 is electrically connected to the low voltage terminal VGL. The second output circuit includes a second fourteenth transistor T2-14 and a second fifteenth transistor T2-15. The gate of the second transistor T2-14 is electrically connected to the second fifth node N2-5, the source of the second transistor T2-14 is electrically connected to the high voltage terminal VGH, and the drain of the second transistor T2-14 is electrically connected to the output driving terminal NO(N). The gate of the second fifteenth transistor T2-15 is electrically connected to the second fifth node N2-5, the source of the second fifteenth transistor T2-15 is electrically connected to the output driving terminal NO(N), and the drain of the second fifteenth transistor T2-15 is electrically connected to the low voltage terminal VGL. The second first driving output circuit includes a second sixteenth transistor T2-16 and a second second capacitor C2-2. The gate of the second sixteenth transistor T2-16 is electrically connected to the first control node NC2-1, the source of the second sixteenth transistor T2-16 is electrically connected to the high voltage terminal VGH, and the drain of the second sixteenth transistor T2-16 is electrically connected to the N-th stage driving signal output terminal NS(N). A first terminal of the second second capacitor C2-2 is electrically connected to the first control node NC2-1, and a second terminal of the second second capacitor C2-2 is electrically connected to the high voltage terminal VGH. The second second driving output circuit includes a second seventeenth transistor T2-17 and a second third capacitor C2-3. The gate of the second seventeenth transistor T2-17 is electrically connected to the second control node NC2-2, the source of the second seventeenth transistor T2-17 is electrically connected to the N-th stage driving signal output terminal NS(N), and the drain of the second seventeenth transistor T2-17 is electrically connected to the low voltage terminal VGL. A first terminal of the second third capacitor C2-3 is electrically connected to the Nth stage drive signal output terminal NS(N), and a second terminal of the second third capacitor C2-3 is electrically connected to the low voltage terminal VGL. The second seventh node control circuit includes a second eighteenth transistor T2-18 and a second nineteenth transistor T2-19. The gate of the second transistor T2-18 is electrically connected to the first clock signal terminal GCK, the source of the second transistor T2-18 is electrically connected to the low voltage terminal VGL, and the drain of the second transistor T2-18 is electrically connected to the second seventh node N2-7. The gate of the second transistor T2-19 is electrically connected to the second ninth node N2-9, the source of the second transistor T2-19 is electrically connected to the second seventh node N2-7, and the drain of the second transistor T2-19 is electrically connected to the first clock signal terminal GCK. The second eighth node control circuit includes a second twentieth transistor T2-20. The gate of the second twentieth transistor T2-20 is electrically connected to the low voltage terminal VGL, the source of the second twentieth transistor T2-20 is electrically connected to the second seventh node N2-7, and the drain of the second twentieth transistor T2-20 is electrically connected to the second eighth node N2-8. The second first control circuit includes a second twenty-first transistor T2-21, a second fourth capacitor C2-4, a second twenty-second transistor T2-22, and a second twenty-third transistor T2-23. The gate of the second 21st transistor T2-21 is electrically connected to the second 8th node N2-8, the source of the second 21st transistor T2-21 is electrically connected to the second clock signal terminal GCB, and the drain of the second 21st transistor T2-21 is electrically connected to the second 2nd node N2-2. A first terminal of the second fourth capacitor C2-4 is electrically connected to the second eighth node N2-8, and a second terminal of the second fourth capacitor C2-4 is electrically connected to the second second node N2-2. The gate of the second 22nd transistor T2-22 is electrically connected to the second clock signal terminal GCB, the source of the second 22nd transistor T2-22 is electrically connected to the second second node N2-2, and the drain of the second 22nd transistor T2-22 is electrically connected to the first control node NC2-1. The gate of the second transistor T2-23 is electrically connected to the second ninth node N2-9, the source of the second transistor T2-23 is electrically connected to the first control node NC2-1, and the drain of the second transistor T2-23 is electrically connected to the high voltage terminal VGH. The second ninth node control circuit includes a second twenty-fourth transistor T2-24 and a second twenty-fifth transistor T2-25. The gate of the second 24th transistor T2-24 is electrically connected to the first clock signal terminal GCK, the source of the second 24th transistor T2-24 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second 24th transistor T2-24 is electrically connected to the second 9th node N2-9. The gate of the second 25th transistor T2-25 is electrically connected to the initial control terminal NCX, the source of the second 25th transistor T2-25 is electrically connected to the high voltage terminal VGH, and the drain of the second 25th transistor T2-25 is electrically connected to the second 9th node N2-9. The second tenth node control circuit includes a second twenty-sixth transistor T2-26. The gate of the second 26th transistor T2-26 is electrically connected to the first clock signal terminal GCK, the source of the second 26th transistor T2-26 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second 26th transistor T2-26 is electrically connected to the second 10th node N2-10. The second eleventh node control circuit includes a twenty-seventh second transistor T2-27, a twenty-eighth second transistor T2-28, a twenty-ninth second transistor T2-29, and a fifth second capacitor C2-5. The gate of the second 27th transistor T2-27 is electrically connected to the low voltage terminal VGL, the source of the second 27th transistor T2-27 is electrically connected to the second 10th node N2-10, and the drain of the second 27th transistor T2-27 is electrically connected to the second 11th node N2-11. The gate of the second transistor T2-28 is electrically connected to the second seventh node N2-7, the source of the second transistor T2-28 is electrically connected to the high voltage terminal VGH, and the drain of the second transistor T2-28 is electrically connected to the second twelfth node N2-12. The gate of the second 29th transistor T2-29 is electrically connected to the second 11th node N2-11, the source of the second 29th transistor T2-29 is electrically connected to the second 12th node N2-12, and the drain of the second 29th transistor T2-29 is electrically connected to the second clock signal terminal GCB. A first terminal of the second fifth capacitor C2-5 is electrically connected to the second twelfth node N2-12, and a second terminal of the second fifth capacitor C2-5 is electrically connected to the second eleventh node N2-11. The second second control circuit includes a second 30th transistor and a second 31st transistor. The gate of the second 30th transistor T2-30 and the source of the second 30th transistor T2-31 are both electrically connected to the second 11th node N2-11, and the drain of the second 30th transistor T2-31 is electrically connected to the second control node NC2-2. The gate of the second 31st transistor T2-31 is electrically connected to the low voltage terminal VGL, the source of the second 31st transistor T2-31 is electrically connected to the second ninth node N2-9, and the drain of the second 31st transistor T2-31 is electrically connected to the second control node NC2-2.

[0192] In FIG. 39, the second thirteenth node is designated by the symbol N2-13.

[0193] In at least one embodiment of the driving circuit shown in FIG. 39, T2-1 is an n-type transistor, T2-2 is a p-type transistor, T2-3 is a p-type transistor, T2-4 is an n-type transistor, T2-5 is a p-type transistor, T2-6 is an n-type transistor, T2-7 is a p-type transistor, T2-8 is an n-type transistor, T2-9 is a p-type transistor, T2-10 and T2-11 are n-type transistors, T2-12 and T2-13 are n-type transistors, T2-14 is a p-type transistor, T2-15 is an n-type transistor, and T2-16 to T2-31 are all p-type transistors.

[0194] In at least one embodiment of the present disclosure, the configuration of the second drive signal generation circuit is not limited to that shown in FIG. 39, and the second drive signal generation circuit may be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.

[0195] At least one embodiment of the driver circuit shown in FIG. 39 of the present disclosure operates as follows. In the first stage, when a low voltage signal is output from NS(N-1), a low voltage signal is output from GCK, and a high voltage signal is supplied from GCB, T2-24 and T2-26 turn on, the potential of N2-9 and the potential of N2-10 are low voltage, T2-27 and T2-31 become conductive, it is ensured that the potential of NC2-2 and the potential of N2-11 become low voltage, T2-17 turns on, and a low voltage signal is output from NS(N). The potential of N2-11 is low voltage, ensuring that T2-29 is on, the potential of N2-9 is low voltage, turning on T2-19, T2-18 is on, pulling down the potential of N2-7 and N2-8, turning on T2-21, the GCB writes a high voltage signal to N2-2, the potential of N2-9 is low voltage, turning on T2-23, pulling up the potential of NC2-1 to high voltage, and ensuring that T2-16 is off. In the second stage, a low voltage signal is output from NS(N-1), the potential of the first clock signal output from GCK jumps from low voltage to high voltage, T2-24 and T2-26 are turned off, the potential of N2-9 is low voltage, T2-19 is turned on, T2-18 is turned off, T2-20 is turned on, the potential of N2-7 and the potential of N2-8 are high voltage, T2-21 is turned off, the potential of N2-2 is maintained at high voltage, a low voltage signal is output from GCB, T2-22 is turned on, the potential of NC2-1 is maintained at high voltage, and T2-16 is turned off. At the same time, the potential of N2-11 is maintained at a low voltage, T2-29 turns on, the GCB writes a low voltage signal to N2-12, the potential of N2-11 is pulled down to a lower voltage (5V to 10V lower than the voltage value of the low voltage signal supplied from the GCB) via C2-5, T2-30 turns on, the low voltage signal is written to NC2-2 (the potential of NC2-2 is 3V to 8V lower than the voltage value of the low voltage signal supplied from the GCB), T2-17 is turned on sufficiently, and the output of a low voltage signal from NS (N) is guaranteed. In the third stage, a high voltage signal is output from NS(N-1), a low voltage signal is output from GCK, a high voltage signal is output from GCB, T2-24 and T2-26 are turned on, the potentials of N2-9 and N2-10 are controlled to high voltages, T2-27 and T2-31 are turned on, the potentials of NC2-2 and N2-11 are high voltages, and T2-17 is turned off. The potential of N2-11 is high voltage, T2-29 is turned off, the potential of N2-9 is high voltage, T2-19 is turned off, T2-18 is turned on, T2-20 is turned on, the potential of N2-7 and the potential of N2-8 are pulled down, T2-21 is turned on, GCB writes a high voltage signal to N2-2, T2-22 is turned off, the potential of N2-9 is high voltage, T2-23 is turned off, the potential of NC2-1 is maintained at high voltage, and T2-16 is ensured to be off. In the fourth stage, NS(N-1) outputs a high voltage signal, the potential of the first clock signal output from GCK jumps from low to high, GCB outputs a low voltage signal, T2-24 and T2-26 are turned off, N2-9 is at a high voltage, T2-19 is turned off, T2-18 is turned off, T2-20 is turned on, N2-7 and N2-8 are kept at a low voltage, T2-21 is turned on, T2-22 is turned on, N2-2 and NC2-1 are kept at a low voltage, T2-16 is turned on, and NS(N) outputs a high voltage signal. At the same time, N2-11 is at a high voltage, T2-29 is turned off, N2-12 is kept at a high voltage, and N2-11 is kept at a high voltage. In the fifth stage, the potential of the N-1th stage driving signal output from NS(N-1) jumps from high voltage to low voltage, a high voltage signal is output from GCK, a low voltage signal is output from GCB, T2-24 and T2-26 are turned off, the potentials of N2-9 and N2-10 are maintained at high voltage, and the potentials of the remaining nodes are maintained as they are, ensuring the output of a high voltage signal from NS(N). In the sixth stage, a low voltage signal is output from NS(N-1), the potential of the first clock signal output from GCK jumps from high voltage to low voltage, a high voltage signal is output from GCB, T2-24 and T2-26 turn on, the potential of N2-9 and the potential of N2-10 are low voltage, T2-27 and T2-31 turn on, ensuring that the potential of NC2-2 and the potential of N2-11 are low voltage, T2-17 is turned on, and a low voltage signal is output from NS(N). The potential of N2-11 is low voltage, ensuring that T2-29 is on, the potential of N2-9 is low voltage, turning on T2-19, T2-18 is on, T2-20 is on, pulling down the potential of N2-7 and N2-8, turning on T2-21, the GCB writes a high voltage signal to N2-2, the potential of N2-9 is low voltage, turning on T2-23, pulling up the potential of NC2-1 to high voltage, and ensuring that T2-16 is off. Optionally, at the start of display (i.e., when the display device is powered on), in the power-on stage before the first stage, NCX outputs a low-voltage signal, T2-9 turns on to control the potential of N2-1 to a high voltage, T2-25 turns on, the potential of N2-9 is high, T2-19 turns off, and when a low-voltage signal is supplied from GCK, the potential of N2-7 is low, T2-20 turns on, the potential of N2-8 is low, and T2-21 turns on to control N2-2 and GCB to be conductive.When a low-voltage signal is supplied from GCB, T2-22 turns on, the potential of NC2-1 is low, T2-16 turns on, and a high-voltage signal is output from NS(N). T2-12 is turned on, T2-13 is turned on, the potential of N2-5 is low, T2-14 is turned on, a high voltage signal is output from NO(N), all second display control transistors M2 included in all pixel circuits in the effective display area are turned on, the charge remaining in the storage capacitor Cst is emptied, and the screen flash defect at power-on can be improved. After that, when a high voltage signal is output from NS(N-1) and a low voltage signal is output from NS(N), T2-1 and T2-2 turn on. When a low voltage signal is supplied from VCT, the potential of N2-1 is a low voltage signal, C2-1 maintains the potential of N2-1, T2-11 conducts, T2-10 conducts, the potential of N2-5 is a high voltage, T2-15 turns on, and a low voltage signal is output from NO(N). When a high voltage signal is supplied from VCT, the potential of N2-1 is the high voltage signal, C2-1 maintains the potential of N2-1, T2-11 turns off, T2-10 conducts, the potential of N2-5 is high voltage, T2-15 turns on, and a low voltage signal is output from NO(N). Thereafter, at the Nth stage drive signal supply stage, a high voltage signal is output from NS(N). When the potential of N2-1 is low voltage, T2-10 is turned off, T2-11 is turned on, the potential of N2-5 is high voltage, T2-15 is turned on, and a low voltage signal is output from NO(N). When the potential of N2-1 is high voltage, T2-10 is off, T2-11 is off, T2-12 and T2-13 are conductive, the potential of N2-5 is low voltage, T2-14 is on, and a high voltage signal is output from NO(N). After the Nth stage drive signal supply stage, a low voltage signal is output from NS(N). When the potential of N2-1 is a low voltage signal, T2-10 is conductive, T2-11 is conductive, the potential of N2-5 is high voltage, and a low voltage signal is output from NO(N). When the potential of N2-1 is a high voltage signal, T2-10 is conductive, T2-11 is turned off, the potential of N2-5 is high voltage, and a low voltage signal is output from NO(N).

[0196] In at least one embodiment of the driving circuit shown in FIG. 39 of the present disclosure, when a high voltage signal is output from NS(N-1) and a low voltage signal is output from NS(N), T2-1 and T2-2 turn on, and by simultaneously gating these two signals, the gating input signal state within one high / low frequency switching period can be obtained.

[0197] 39 of the present disclosure, p-type transistors have a threshold voltage loss when transmitting low voltages, while n-type transistors have a threshold voltage loss when transmitting high voltages, so the absolute value of the potential of N2-1 is low, and the second first inverter and the second second inverter can control the increase in the absolute value of the potential of N2-1, thereby better controlling the on / off of the corresponding transistor in the second output circuit. The second sustain control circuit controls N2-1 and N2-4 to be cut off when T2-1 and T2-2-2 are on, so as not to affect the writing of the potential of N2-1.

[0198] FIG. 40 is a timing diagram illustrating the operation of at least one embodiment of the driver circuit shown in FIG.

[0199] FIG. 41 is a simulated operational timing diagram of at least one embodiment of the driver circuit shown in FIG.

[0200] At least one embodiment of the driving circuit shown in FIG. 42 of the present disclosure differs from at least one embodiment of the driving circuit shown in FIG. 39 of the present disclosure in that it does not have a second second voltage maintenance circuit (i.e., it does not have T2-3 to T2-8).

[0201] At least one embodiment of the drive circuit shown in FIG. 43 of the present disclosure differs from at least one embodiment of the drive circuit shown in FIG. 39 of the present disclosure in that N2-4 is electrically connected to the gate of T2-11 and the gate of T2-13.

[0202] 43 of the present disclosure, during operation, p-type transistors have threshold voltage losses when transmitting low voltages, and n-type transistors have threshold voltage losses when transmitting high voltages, so the absolute value of the potential of N2-1 is low, and the second first inverter and second second inverter can control the increase in the absolute value of the potential of N2-4, thereby better controlling the on / off of the corresponding transistor in the second output circuit. The second sustain control circuit controls N2-1 and N2-4 to be cut off when T2-1 and T2-2-2 are on, so as not to affect the writing of the potential of N2-1.

[0203] As shown in FIG. 44, the drive circuit according to an embodiment of the present disclosure includes a third drive signal generation circuit 310, a third gating circuit 311, a third output control circuit 312, a third output circuit 313, and a third voltage control circuit 314. The third drive signal generation circuit 310, which is electrically connected to the third first control node NC3-1, the third second control node NC3-2, and the Nth stage drive signal output terminal NS(N), generates an Nth stage drive signal under the control of the potential of the third first control node NC3-1 and the potential of the third second control node NC3-2, and outputs it via the Nth stage drive signal output terminal NS(N). The third gating circuit 311, which is electrically connected to the third first node N3-1, the gating input terminal VCT, and the gating control terminal CX, controls the gating input signal supplied from the gating input terminal VCT to be written to the third first node N3-1 under the control of the gating control signal supplied from the gating control terminal CX. The third output control circuit 312, which is electrically connected to the third first node N3-1, the third first control node NC3-1, and the third second node N3-2, respectively, controls the third first control node NC3-1 and the third second node N3-2 to be conductive under control of the potential of the third first node N3-1. The third voltage control circuit 314, electrically connected to the third first node N3-1 and the third second node N3-2, controls the potential of the third second node N3-2 based on the potential of the third first node N3-1. The third output circuit 313, which is electrically connected to the third second node N3-2, the third third control node NC3-3, the first voltage terminal V1, the second voltage terminal V2, and the output drive terminal NO(N), respectively, controls the output drive terminal NO(N) and the first voltage terminal V1 to be conductive under control of the potential of the third second node N3-2, and controls the output drive terminal NO(N) and the second voltage terminal V2 to be conductive under control of the potential of the third third control node NC3-3. The third second control node NC3-2 and the third third control node NC3-3 are different nodes, and N is a positive integer.

[0204] In the embodiment of the drive circuit shown in FIG. 44 of the present disclosure, during operation, the third drive signal generation circuit 310 generates an N-stage drive signal and outputs it via the N-stage drive signal output terminal NS(N), the third gating circuit 311 writes a gating input signal to the third first node N3-1 under the control of a gating control signal, and the third output control circuit 312 connects the third first control node NC3-1 and the third second node N3-2 under the control of the potential of the third first node N3-1. a third voltage control circuit 314 controls the potential of the third second node N3-2 based on the potential of the third first node N3-1; a third output circuit 313 controls the output drive terminal NO(N) and the first voltage terminal V1 to be conductive under the control of the potential of the third second node N3-2, and controls the output drive terminal NO(N) and the second voltage terminal V2 to be conductive under the control of the potential of the third third control node NC3-3.

[0205] Optionally, the first voltage terminal may be, but is not limited to, a high voltage terminal.

[0206] The embodiment of the driver circuit shown in FIG. 44 of the present disclosure may be an Nth stage driver circuit.

[0207] In the embodiment of the driving circuit shown in FIG. 44 of the present disclosure, the following operation is performed within one frame time. Before the N-th stage driving signal supplying step, the third gating circuit 311 writes the gating input signal supplied from the gating input terminal VCT to the third first node N3-1 under the control of the gating control signal. When the gating input signal is a high-voltage signal, in the Nth-stage driving signal supply step, a high-voltage signal is output from the Nth-stage driving signal output terminal NS(N), and the potential of the third first node N3-1 is high. The third output control circuit 312 controls the third first control node NC3-1 to be disconnected from the third second node N3-2 under control of the potential of the third first node N3-1. The third voltage control circuit 314 controls the potential of the third second node N3-2 to be high based on the potential of the third first node N3-1. The third output circuit controls the output driving terminal NO(N) to maintain a low-voltage signal output, and can control the pixel voltages of the pixel circuits in the corresponding row not to be updated. When the gating input signal is a low-voltage signal, in the N-stage driving signal supply step, a high-voltage signal is output from the N-stage driving signal output terminal NS(N), and the potential of the third first node N3-1 is low. The third output control circuit 312 controls the third first control node NC3-1 and the third second node N3-2 to be conductive under control of the potential of the third first node N3-1, so that the potential of the third second node N3-2 is low. The third output circuit 313 controls the output driving terminal NO(N) and the first voltage terminal V1 to be conductive under control of the potential of the third second node N3-2, so that a high-voltage signal is output from NO(N), thereby controlling the pixel voltages of the pixel circuits in the corresponding row to be updated.

[0208] In the embodiment of the present disclosure, by controlling the gating input signal supplied from the gating input terminal VCT, it is possible to update a part of the display screen to reduce power consumption, or to update a part of the display screen to achieve ultra-low power consumption in OLED display products such as wearable products, mobile terminals, and notebook computers (NBs).

[0209] Optionally, the third output control circuit includes a third third transistor. A gate of the third third transistor is electrically connected to the third first node, a first pole of the third third transistor is electrically connected to the third first control node, and a second pole of the third third transistor is electrically connected to the third second node.

[0210] Optionally, the third voltage control circuit includes a third first capacitor. A first terminal of the third first capacitor is electrically connected to the third first node, and a second terminal of the third first capacitor is electrically connected to the third second node.

[0211] The driving circuit according to at least one embodiment of the present disclosure further includes a third second node control circuit. The third second node control circuit, which is electrically connected to the third third control node, the third second node, and the first voltage terminal, respectively, controls the third second node and the first voltage terminal to be electrically connected together under control of the potential of the third third control node.

[0212] In a specific implementation, the driving circuit may further include a third second node control circuit. The third second node control circuit controls the third second node to be electrically connected to a first voltage terminal under control of the potential of a third third control node.

[0213] As shown in FIG. 45, based on the embodiment of the driving circuit shown in FIG. 44, the driving circuit further includes a third second node control circuit 320. The third second node control circuit 320, which is electrically connected to the third third control node NC3-3, the third second node N3-2, and the first voltage terminal V1, respectively, controls the third second node N3-2 and the first voltage terminal V1 to be conductive under control of the potential of the third third control node NC3-3.

[0214] In at least one embodiment of the driver circuit shown in FIG. 45, in operation, when the potential of the third third control node NC3-3 is at an effective voltage, the potential of the third second node N3-2 may be at a first voltage.

[0215] Optionally, the third second node control circuit includes a third fourth transistor. A gate of the third fourth transistor is electrically connected to the third third control node, a first electrode of the third fourth transistor is electrically connected to the third second node, and a second electrode of the third fourth transistor is electrically connected to a first voltage terminal.

[0216] Optionally, the third output circuit includes a third fifth transistor, a third sixth transistor, and a third second capacitor. A gate of the third fifth transistor is electrically connected to the third second node, a first pole of the third fifth transistor is electrically connected to a first voltage terminal, and a second pole of the third fifth transistor is electrically connected to the output drive terminal. A gate of the third sixth transistor is electrically connected to the third third control node, a first electrode of the third sixth transistor is electrically connected to the output drive terminal, and a second electrode of the third sixth transistor is electrically connected to a second voltage terminal. A first terminal of the third second capacitor is electrically connected to the third second node, and a second terminal of the third second capacitor is electrically connected to the first voltage terminal.

[0217] The driving circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit. The third initialization circuit, which is electrically connected to the initial control terminal, the second voltage terminal, and the third first node, respectively, controls the third first node and the second voltage terminal to be conductive under the control of an initial control signal supplied from the initial control terminal.

[0218] In a specific implementation, the driving circuit may further include a third initialization circuit. When the display device is powered on, the third initialization circuit controls the third first node and the second voltage terminal to be conductive under control of an initialization control signal, thereby controlling the potential of the third first node to the second voltage. The third output control circuit controls the third first control node and the third second node to be conductive under control of the potential of the third first node.

[0219] In at least one embodiment of the present disclosure, the driving circuit further includes a third first node control circuit. The third first node control circuit, which is electrically connected to the third fourth node, the second voltage terminal, and the third first node, respectively, controls the third first node and the second voltage terminal to be electrically connected together under control of the potential of the third fourth node.

[0220] In a specific implementation, the driving circuit may further include a third first node control circuit. The third first node control circuit controls the third first node to be electrically connected to the second voltage terminal under control of the potential of the third fourth node. After the N-stage driving signal supply stage, when the potential of the third fourth node is an effective voltage, the third first node control circuit controls the third first node to be electrically connected to the second voltage terminal, so that the potential of the third first node becomes the second voltage. The third output control circuit controls the third first control node to be electrically connected to the third second node under control of the potential of the third first node.

[0221] In at least one embodiment of the present disclosure, when the transistor included in the third first node control circuit is a p-type transistor, the effective voltage may be a low voltage, and when the transistor included in the third first node control circuit is an n-type transistor, the effective voltage may be a high voltage.

[0222] As shown in FIG. 46, based on at least one embodiment of the driving circuit shown in FIG. 45, the driving circuit may further include a third initialization circuit 321 and a third first node control circuit 322. The third initialization circuit 321, which is electrically connected to the initial control terminal NCX, the third first node N3-1, and the second voltage terminal V2, respectively, controls the third first node N3-1 and the second voltage terminal V2 to be conductive under the control of an initial control signal supplied from the initial control terminal NCX. The third first node control circuit 322, which is electrically connected to the third fourth node N3-4, the third first node N3-1, and the second voltage terminal V2, respectively, controls the third first node N3-1 and the second voltage terminal V2 to be conductive under control of the potential of the third fourth node N3-4.

[0223] Optionally, the third initialization circuit includes a third seventh transistor. A gate of the third seventh transistor is electrically connected to the initial control terminal, a first electrode of the third seventh transistor is electrically connected to the third first node, and a second electrode of the third seventh transistor is electrically connected to a second voltage terminal.

[0224] Optionally, the third first node control circuit includes a third eighth transistor. A gate of the third eighth transistor is electrically connected to the third fourth node, a first electrode of the third eighth transistor is electrically connected to the third first node, and a second electrode of the third eighth transistor is electrically connected to a second voltage terminal.

[0225] The driving circuit according to at least one embodiment of the present disclosure further includes a third control node control circuit. The third-third control node control circuit, which is electrically connected to the third-first node, the third-fifth node, the third-second control node, the third-third control node, and the third-sixth node, respectively, controls the third-fifth node and the third-third control node to be electrically connected together under control of the potential of the third-first node, controls the third-second control node and the third-sixth node to be electrically connected together under control of the potential of the third-sixth node, and controls the third-sixth node and the third-third control node to be electrically connected together.

[0226] In a specific implementation, the driving circuit may include a third third control node control circuit, which controls the potential of the third third control node under the control of the potential of the third first node and the potential of the third sixth node.

[0227] As shown in FIG. 47, based on at least one embodiment of the driving circuit shown in FIG. 46, the driving circuit further includes a third control node control circuit 330. The third-third control node control circuit 330, which is electrically connected to the third-first node N3-1, the third-fifth node N3-5, the third-second control node NC3-2, the third-third control node NC3-3, and the third-sixth node N3-6, respectively, controls the third-fifth node N3-5 and the third-third control node NC3-3 to be conductive under control of the potential of the third-first node N3-1, controls the third-second control node NC3-2 and the third-sixth node N3-6 to be conductive under control of the potential of the third-sixth node N3-6, and controls the third-sixth node N3-6 and the third-third control node NC3-3 to be conductive.

[0228] Optionally, the third third control node control circuit includes a third ninth transistor, a third tenth transistor, and a third eleventh transistor. A gate of the third ninth transistor is electrically connected to the third first node, a first pole of the third ninth transistor is electrically connected to the third fifth node, and a second pole of the third ninth transistor is electrically connected to the third third control node. The gate of the third tenth transistor and the second pole of the third tenth transistor are both electrically connected to the third sixth node, and the first pole of the third tenth transistor is electrically connected to the third second control node. The gate of the third eleventh transistor and the first pole of the third eleventh transistor are both electrically connected to the third sixth node, and the second pole of the third eleventh transistor is electrically connected to the third third control node.

[0229] In at least one embodiment of the present disclosure, the third drive signal generation circuit includes a third first drive output circuit, a third second drive output circuit, a third first control node control circuit, and a third second control node control circuit. The third first control node control circuit controls the potential of the third first control node. The third second control node control circuit controls the potential of the third second control node. The third first drive output circuit, which is electrically connected to the third first control node, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, controls the Nth stage drive signal output terminal and the first voltage terminal to be electrically connected together under control of the potential of the third first control node. The third second drive output circuit, which is electrically connected to the third second control node, the second voltage terminal, and the Nth stage drive signal output terminal, respectively, controls the Nth stage drive signal output terminal and the second voltage terminal to be electrically connected together under control of the potential of the third second control node.

[0230] As shown in FIG. 48, based on at least one embodiment of the driving circuit shown in FIG. 47, the driving circuit further includes a third first control node control circuit 331, a third second control node control circuit 332, a third first driving output circuit 333, and a third second driving output circuit 334. The third first control node control circuit 331, which is electrically connected to the third first control node NC3-1, controls the potential of the third first control node NC3-1. The third second control node control circuit 332, which is electrically connected to the third second control node NC3-2, controls the potential of the third second control node NC3-2. The third first drive output circuit 333, which is electrically connected to the third first control node NC3-1, the first voltage terminal V1, and the Nth stage drive signal output terminal NS(N), respectively, controls the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 to be conductive under the control of the potential of the third first control node NC3-1. The third second drive output circuit 334, which is electrically connected to the third second control node NC3-2, the Nth stage drive signal output terminal NS(N), and the second voltage terminal V2, respectively, controls the Nth stage drive signal output terminal NS(N) and the second voltage terminal V2 to be conductive under the control of the potential of the third second control node NC3-2.

[0231] In at least one embodiment of the present disclosure, the third first control node control circuit includes a third seventh node control circuit, a third eighth node control circuit, a third third node control circuit, and a third first control circuit. The third seventh node control circuit, which is electrically connected to the third seventh node, the second voltage terminal, the first clock signal terminal, and the third fifth node, respectively, controls the third seventh node and the second voltage terminal to be electrically connected together under control of a first clock signal supplied from the first clock signal terminal, and controls the third seventh node and the first clock signal terminal to be electrically connected together under control of the potential of the third fifth node. The third-eighth-node control circuit, which is electrically connected to the second voltage terminal, the third seventh node, and the third eighth node, respectively, controls the third seventh node and the third eighth node to be conductive under the control of a second voltage signal supplied from the second voltage terminal. The third-third-node control circuit, which is electrically connected to the third-eighth node, the second clock signal terminal, and the third-third node, respectively, controls the electrical connection between the third node and the second clock signal terminal under control of the potential of the third-eighth node, and controls the potential of the third-third node based on the potential of the third-eighth node. The third first control circuit, which is electrically connected to the second clock signal terminal, the third third node, the third first control node, the third fifth node, and the first voltage terminal, respectively, controls the third third node and the third first control node to be electrically connected together under control of a second clock signal supplied from the second clock signal terminal, and controls the third first control node and the first voltage terminal to be electrically connected together under control of the potential of the third fifth node.

[0232] In a specific implementation, the third-first control node control circuit may include a third-seventh node control circuit, a third-eighth node control circuit, a third-third node control circuit, and a third-first control circuit. The third-seventh node control circuit controls the potential of the third-seventh node under control of a first clock signal and the potential of the third-fifth node. The third-eighth node control circuit controls the third-seventh node and the third-eighth node to be electrically connected together under control of a second voltage signal. The third-third node control circuit controls the electrical connection between the third-third node and the second clock signal terminal under control of the potential of the third-eighth node, and controls the potential of the third-third node based on the potential of the third-eighth node. The third-first control circuit controls the third-third node and the third-first control node to be electrically connected together under control of the second clock signal, and controls the third-first control node and the first voltage terminal to be electrically connected together under control of the potential of the third-fifth node.

[0233] In at least one embodiment of the present disclosure, the third second control node control circuit includes a third sixth node control circuit, a third fifth node control circuit, a third ninth node control circuit, a third fourth node control circuit, and a third second control circuit. The third-sixth-node control circuit, which is electrically connected to the second voltage terminal, the third-ninth node, the third-sixth node, and the third-fourth node, respectively, controls the third-ninth node and the third-sixth node to be conductive under the control of a second voltage signal supplied from the second voltage terminal, and controls the potential of the third-sixth node based on the potential of the third-fourth node. The third-fifth node control circuit, which is electrically connected to the N-1th stage drive signal output terminal, the first clock signal terminal, the third-fifth node, the initial control terminal, and the first voltage terminal, respectively, controls the third-fifth node and the N-1th stage drive signal output terminal to be electrically connected under the control of a first clock signal supplied from the first clock signal terminal, and controls the third-fifth node and the first voltage terminal to be electrically connected under the control of an initial control signal supplied from the initial control terminal. The third ninth node control circuit, which is electrically connected to the first clock signal terminal, the N-1th stage drive signal output terminal, and the third ninth node, respectively, controls the third ninth node and the N-1th stage drive signal output terminal to be electrically connected together under the control of the first clock signal supplied from the first clock signal terminal. The third-fourth node control circuit, which is electrically connected to the third-seventh node, the first voltage terminal, the third-fourth node, the second clock signal terminal, and the third-sixth node, respectively, controls the third-fourth node and the first voltage terminal to be electrically connected together under control of the potential of the third-seventh node, and controls the third-fourth node and the second clock signal terminal to be electrically connected together under control of the potential of the third-sixth node. The third second control circuit, which is electrically connected to the second voltage terminal, the third fifth node, and the third second control node, respectively, controls the third fifth node and the third second control node to be conductive under the control of a second voltage signal supplied from the second voltage terminal.

[0234] In a specific implementation, the third second control node control circuit may include a third sixth node control circuit, a third fifth node control circuit, a third ninth node control circuit, a third fourth node control circuit, and a third second control circuit. The third fourth node control circuit controls the potential of the third fourth node under control of the potential of the third seventh node and the potential of the third sixth node. The third sixth node control circuit controls the third ninth node and the third sixth node to be conductive under control of a second voltage signal, and controls the potential of the third sixth node based on the potential of the third fourth node. The third fifth node control circuit controls the third fifth node and the (N-1)th stage driving signal output terminal to be conductive under control of a first clock signal, and controls the third fifth node and the first voltage terminal to be conductive under control of an initial control signal. The third ninth node control circuit controls, under control of the first clock signal, to bring the third ninth node and the (N-1)th stage drive signal output into conduction. The third fourth node control circuit controls, under control of the potential of the third seventh node, to bring the third fourth node into conduction with the first voltage terminal, and controls, under control of the potential of the third sixth node, to bring the third fourth node into conduction with the second clock signal terminal. The third second control circuit controls, under control of the second voltage signal, to bring the third fifth node and the third second control node into conduction.

[0235] As shown in FIG. 49, based on at least one embodiment of the driving circuit shown in FIG. 48, the third first control node control circuit includes a third seventh node control circuit 341, a third eighth node control circuit 342, a third third node control circuit 343, and a third first control circuit 344. The third seventh node control circuit 341, which is electrically connected to the third seventh node N3-7, the second voltage terminal V2, the first clock signal terminal GCK, and the third fifth node N3-5, respectively, controls the third seventh node N3-7 and the second voltage terminal V2 to be electrically connected together under control of the first clock signal supplied from the first clock signal terminal GCK, and controls the third seventh node N3-7 and the first clock signal terminal GCK to be electrically connected together under control of the potential of the third fifth node N3-5. The third and eighth node control circuit 342, which is electrically connected to the second voltage terminal V2, the seventh third node N3-7, and the eighth third node N3-8, respectively, controls the seventh third node N3-7 and the eighth third node N3-8 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2. The third third node control circuit 343, which is electrically connected to the third eighth node N3-8, the second clock signal terminal GCB, and the third third node N3-3, respectively, controls the electrical connection between the third third node N3-3 and the second clock signal terminal GCB under control of the potential of the third eighth node N3-8, and controls the potential of the third third node N3-3 based on the potential of the third eighth node N3-8. The third first control circuit 344, which is electrically connected to the second clock signal terminal GCB, the third third node N3-3, the third first control node NC3-1, the third fifth node N3-5, and the first voltage terminal V1, controls the third third node N3-3 and the third first control node NC3-1 to be conductive under the control of the second clock signal supplied from the second clock signal terminal GCB, and controls the third first control node NC3-1 and the first voltage terminal V1 to be conductive under the control of the potential of the third fifth node N3-5. The third second control node control circuit includes a third sixth node control circuit 351, a third fifth node control circuit 352, a third ninth node control circuit 353, a third fourth node control circuit 354, and a third second control circuit 355. The third-sixth node control circuit 351, which is electrically connected to the second voltage terminal V2, the ninth-third node N3-9, the sixth-third node N3-6, and the fourth-third node N3-4, respectively, controls the ninth-third node N3-9 and the sixth-third node N3-6 to be conductive under the control of a second voltage signal supplied from the second voltage terminal V2, and controls the potential of the sixth-third node N3-6 based on the potential of the fourth-third node N3-4. The third-fifth node control circuit 352, which is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the first clock signal terminal GCK, the third-fifth node N3-5, the initial control terminal NCX, and the first voltage terminal V1, respectively, controls the third-fifth node N3-5 and the N-1th stage drive signal output terminal NS(N-1) to be conductive under the control of the first clock signal supplied from the first clock signal terminal GCK, and controls the third-fifth node N3-5 and the first voltage terminal V1 to be conductive under the control of the initial control signal supplied from the initial control terminal NCX. The third ninth node control circuit 353, which is electrically connected to the first clock signal terminal GCK, the N-1th stage drive signal output terminal NS(N-1), and the third ninth node N3-9, controls the third ninth node N3-9 and the N-1th stage drive signal output terminal NS(N-1) to be electrically connected to each other under the control of the first clock signal supplied from the first clock signal terminal GCK. The third-fourth node control circuit 354, which is electrically connected to the seventh third node N3-7, the first voltage terminal V1, the sixth third node N3-6, the fourth third node N3-4, and the second clock signal terminal GCB, controls the electrical connection between the fourth third node N3-4 and the first voltage terminal V1 under control of the potential of the seventh third node N3-7, and controls the electrical connection between the fourth third node N3-4 and the second clock signal terminal GCB under control of the potential of the sixth third node N3-6. The third second control circuit 355, which is electrically connected to the second voltage terminal V2, the third fifth node N3-5, and the third second control node NC3-2, respectively, controls the third fifth node N3-5 and the third second control node NC3-2 to be conductive under the control of the second voltage signal supplied from the second voltage terminal V2.

[0236] Optionally, the third seventh node control circuit includes a third twelfth transistor and a third thirteenth transistor, the third eighth node control circuit includes a third fourteenth transistor, the third third node control circuit includes a third fifteenth transistor and a third third capacitor, and the third first control circuit includes a third sixteenth transistor and a third seventeenth transistor. A gate of the third twelfth transistor is electrically connected to a first clock signal terminal, a first pole of the third twelfth transistor is electrically connected to a second voltage terminal, and a second pole of the third twelfth transistor is electrically connected to a third seventh node. A gate of the third thirteenth transistor is electrically connected to the third fifth node, a first pole of the third thirteenth transistor is electrically connected to the third seventh node, and a second pole of the third thirteenth transistor is electrically connected to a first clock signal terminal. A gate of the third transistor is electrically connected to a second voltage terminal, a first electrode of the third transistor is electrically connected to the third node, and a second electrode of the third transistor is electrically connected to the third node. A gate of the third fifteenth transistor is electrically connected to the third eighth node, a first pole of the third fifteenth transistor is electrically connected to a second clock signal terminal, and a second pole of the third fifteenth transistor is electrically connected to the third third node. A gate of the third sixteenth transistor is electrically connected to the second clock signal terminal, a first pole of the third sixteenth transistor is electrically connected to the third third node, and a second pole of the third sixteenth transistor is electrically connected to the third first control node. A gate of the third seventeenth transistor is electrically connected to a third fifth node, a first electrode of the third seventeenth transistor is electrically connected to a third first control node, and a second electrode of the third seventeenth transistor is electrically connected to a first voltage terminal.

[0237] Optionally, the third sixth node control circuit includes a third eighteenth transistor and a third fourth capacitor, the third fifth node control circuit includes a third nineteenth transistor and a third twentieth transistor, the third ninth node control circuit includes a third twenty-first transistor, the third fourth node control circuit includes a third twenty-second transistor and a third twenty-third transistor, and the third second control circuit includes a third twenty-fourth transistor. A gate of the third transistor is electrically connected to a second voltage terminal, a first electrode of the third transistor is electrically connected to a third ninth node, and a second electrode of the third transistor is electrically connected to a third sixth node. A first terminal of the third fourth capacitor is electrically connected to the third fourth node, and a second terminal of the third fourth capacitor is electrically connected to the third sixth node. A gate of the third 19th transistor is electrically connected to the first clock signal terminal, a first electrode of the third 19th transistor is electrically connected to the (N-1)th stage driving signal output terminal, and a second electrode of the third 19th transistor is electrically connected to the third 5th node. A gate of the twentieth transistor is electrically connected to an initial control terminal, a first pole of the twentieth transistor is electrically connected to a first voltage terminal, and a second pole of the twentieth transistor is electrically connected to the third fifth node. The gate of the third 21st transistor is electrically connected to the first clock signal terminal, the first pole of the third 21st transistor is electrically connected to the N-1th stage driving signal output terminal, and the second pole of the third 21st transistor is electrically connected to the third 9th node. A gate of the third 22nd transistor is electrically connected to a third 7th node, a first electrode of the third 22nd transistor is electrically connected to a first voltage terminal, and a second electrode of the third 22nd transistor is electrically connected to a third 4th node. A gate of the third 23rd transistor is electrically connected to a third 6th node, a first pole of the third 23rd transistor is electrically connected to a third 4th node, and a second pole of the third 23rd transistor is electrically connected to a second clock signal terminal. A gate of the third 24th transistor is electrically connected to a second voltage terminal, a first electrode of the third 24th transistor is electrically connected to a third 9th node, and a second electrode of the third 24th transistor is electrically connected to a third second control node.

[0238] Optionally, the third first driving output circuit includes a 25th transistor and a 5th capacitor, and the third second driving output circuit includes a 26th transistor and a 6th capacitor. The gate of the 25th transistor is electrically connected to the third first control node, the first electrode of the 25th transistor is electrically connected to a first voltage terminal, and the second electrode of the 25th transistor is electrically connected to an Nth stage driving signal output terminal. A first terminal of the third fifth capacitor is electrically connected to the third first control node, and a second terminal of the third fifth capacitor is electrically connected to a first voltage terminal. The gate of the third 26th transistor is electrically connected to the third second control node, the first electrode of the third 26th transistor is electrically connected to the N-th stage driving signal output terminal, and the second electrode of the third 26th transistor is electrically connected to the second voltage terminal. A first terminal of the third sixth capacitor is electrically connected to the N-stage driving signal output terminal, and a second terminal of the third sixth capacitor is electrically connected to a second voltage terminal.

[0239] As shown in FIG. 50, based on at least one embodiment of the driving circuit shown in FIG. 49, the third gating circuit includes a third first transistor T3-1 and a third second transistor T3-2. The gate of the third first transistor T3-1 is electrically connected to the N-stage driving signal output terminal NS(N), the drain of the third first transistor T3-1 is electrically connected to the third first node N3-1, and the source of the third first transistor T3-1 is electrically connected to the drain of the third second transistor T3-2. The gate of the third second transistor T3-2 is electrically connected to the third third node N3(N-1) of the N-1th stage, and the source of the third second transistor T3-2 is electrically connected to the gating input terminal VCT. The third output control circuit includes a third third transistor T3-3. The gate of the third third transistor T3-3 is electrically connected to the third first node N3-1, the source of the third third transistor T3-3 is electrically connected to the third first control node NC3-1, and the drain of the third third transistor T3-3 is electrically connected to the third second node N3-2. The third voltage control circuit includes a third first capacitor C3-1. A first terminal of the third first capacitor C3-1 is electrically connected to the third first node N3-1, and a second terminal of the third first capacitor C3-1 is electrically connected to the third second node N3-2. The third second node control circuit includes a third fourth transistor T3-4. The gate of the third fourth transistor T3-4 is electrically connected to the third third control node NC3-3, the source of the third fourth transistor T3-4 is electrically connected to the third second node N3-2, and the drain of the third fourth transistor T3-4 is electrically connected to the high voltage terminal VGH. The third output circuit includes a third fifth transistor T3-5, a third sixth transistor, and a third second capacitor C3-2. The gate of the third fifth transistor T3-5 is electrically connected to the third second node N2, the source of the third fifth transistor T3-5 is electrically connected to the high voltage terminal VGH, and the drain of the third fifth transistor T3-5 is electrically connected to the output driving terminal NO(N). The gate of the third sixth transistor T3-6 is electrically connected to the third third control node NC3-3, the source of the third sixth transistor T3-6 is electrically connected to the output driving terminal NO(N), and the drain of the third sixth transistor T3-6 is electrically connected to the low voltage terminal VGL. A first terminal of the third second capacitor C3-2 is electrically connected to the third second node N3-2, and a second terminal of the third second capacitor C3-2 is electrically connected to the high voltage terminal VGH. The third initialization circuit includes a third seventh transistor T3-7. The gate of the third seventh transistor T3-7 is electrically connected to the initial control terminal NCX, the source of the third seventh transistor T3-7 is electrically connected to the third first node N3-1, and the drain of the third seventh transistor T3-7 is electrically connected to the low voltage terminal VGL. The third first node control circuit includes a third eighth transistor T3-8. The gate of the third eighth transistor T3-8 is electrically connected to the third fourth node N3-4, the source of the third eighth transistor T3-8 is electrically connected to the third first node N3-1, and the drain of the third eighth transistor T3-8 is electrically connected to the low voltage terminal VGL. The third third control node control circuit includes a ninth third transistor T3-9, a tenth third transistor T3-10, and an eleventh third transistor T3-11. The gate of the third ninth transistor T3-9 is electrically connected to the third first node N3-1, the drain of the third ninth transistor T3-9 is electrically connected to the third fifth node N3-5, and the source of the third ninth transistor T3-9 is electrically connected to the third third control node NC3-3. The gate of the third tenth transistor T3-10 and the source of the third tenth transistor T3-10 are both electrically connected to the third sixth node N3-6, and the drain of the third tenth transistor T3-10 is electrically connected to the third second control node NC3-2. The gate of the third transistor T3-11 and the source of the third transistor T3-11 are both electrically connected to the third node N3-6, and the drain of the third transistor T3-11 is electrically connected to the third control node NC3-3. The third seventh node control circuit includes a third twelfth transistor T3-12 and a third thirteenth transistor T3-13, the third eighth node control circuit includes a third fourteenth transistor T3-14, the third third node control circuit includes a third fifteenth transistor T3-15 and a third third capacitor C3-3, and the third first control circuit includes a third sixteenth transistor T3-16 and a third seventeenth transistor T3-17. The gate of the third twelfth transistor T3-12 is electrically connected to the first clock signal terminal GCK, the source of the third twelfth transistor T3-12 is electrically connected to the low voltage terminal VGL, and the drain of the third twelfth transistor T3-12 is electrically connected to the third seventh node N3-7. The gate of the third transistor T3-13 is electrically connected to the third node N3-5, the source of the third transistor T3-13 is electrically connected to the third node N3-7, and the drain of the third transistor T3-13 is electrically connected to the first clock signal terminal GCK. The gate of the third transistor T3-14 is electrically connected to the low voltage terminal VGL, the source of the third transistor T3-14 is electrically connected to the third node N3-7, and the drain of the third transistor T3-14 is electrically connected to the third node N3-8. The gate of the third fifteenth transistor T3-15 is electrically connected to the third eighth node N3-8, the source of the third fifteenth transistor T3-15 is electrically connected to the second clock signal terminal GCB, and the drain of the third fifteenth transistor T3-15 is electrically connected to the third third node N3-3. The gate of the third sixteenth transistor T3-16 is electrically connected to the second clock signal terminal GCB, the source of the third sixteenth transistor T3-16 is electrically connected to the third third node N3-3, and the drain of the third sixteenth transistor T3-16 is electrically connected to the third first control node NC3-1. The gate of the third seventeenth transistor T3-17 is electrically connected to the third fifth node N5, the source of the third seventeenth transistor T3-17 is electrically connected to the third first control node NC3-1, and the drain of the third seventeenth transistor T3-17 is electrically connected to the high voltage terminal VGH. The third sixth node control circuit includes a third eighteenth transistor T3-18 and a third fourth capacitor C3-4, the third fifth node control circuit includes a third nineteenth transistor T3-19 and a third twentieth transistor T3-20, the third ninth node control circuit includes a third twenty-first transistor T3-21, the third fourth node control circuit includes a third twenty-second transistor T3-22 and a third twenty-third transistor T3-23, and the third second control circuit includes a third twenty-fourth transistor T3-24. The gate of the third transistor T3-18 is electrically connected to the low voltage terminal VGL, the source of the third transistor T3-18 is electrically connected to the third ninth node N3-9, and the drain of the third transistor T3-18 is electrically connected to the third sixth node N3-6. A first terminal of the third fourth capacitor C3-4 is electrically connected to the third fourth node N3-4, and a second terminal of the third fourth capacitor C3-4 is electrically connected to the third sixth node N3-6. The gate of the third transistor T3-19 is electrically connected to the first clock signal terminal GCK, the source of the third transistor T3-19 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the third transistor T3-19 is electrically connected to the third fifth node N3-5. The gate of the third twentieth transistor T3-20 is electrically connected to the initial control terminal NCX, the source of the third twentieth transistor T3-20 is electrically connected to the high voltage terminal VGH, and the drain of the third twentieth transistor T3-20 is electrically connected to the third fifth node N3-5. The gate of the third transistor T3-21 is electrically connected to the first clock signal terminal GCK, the source of the third transistor T3-21 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the third transistor T3-21 is electrically connected to the third ninth node N3-9. The gate of the third 22nd transistor T3-22 is electrically connected to the third seventh node N3-7, the source of the third 22nd transistor T3-22 is electrically connected to the high voltage terminal VGH, and the drain of the third 22nd transistor T3-22 is electrically connected to the third fourth node N3-4. The gate of the third transistor T3-23 is electrically connected to the third node N3-6, the source of the third transistor T3-23 is electrically connected to the third node N3-4, and the drain of the third transistor T3-23 is electrically connected to the second clock signal terminal GCB. The gate of the third 24th transistor T3-24 is electrically connected to the low voltage terminal VGL, the source of the third 24th transistor T3-24 is electrically connected to the third 9th node N3-9, and the drain of the third 24th transistor T3-24 is electrically connected to the third second control node NC3-2. The third first driving output circuit includes a third twenty-fifth transistor T3-25 and a third fifth capacitor C3-5, and the third second driving output circuit includes a third twenty-sixth transistor T3-26 and a third sixth capacitor C3-6. The gate of the third 25th transistor T3-25 is electrically connected to the third first control node NC3-1, the source of the third 25th transistor T3-25 is electrically connected to the high voltage terminal VGH, and the drain of the third 25th transistor T3-25 is electrically connected to the Nth stage driving signal output terminal NS(N). A first terminal of the third fifth capacitor C3-5 is electrically connected to the third first control node NC3-1, and a second terminal of the third fifth capacitor C3-5 is electrically connected to the high voltage terminal VGH. The gate of the third 26th transistor T3-26 is electrically connected to the third second control node NC3-2, the source of the third 26th transistor T3-26 is electrically connected to the Nth stage driving signal output terminal NS(N), and the drain of the third 26th transistor T3-26 is electrically connected to the low voltage terminal VGL. A first terminal of the third sixth capacitor C3-6 is electrically connected to the Nth stage drive signal output terminal NS(N), and a second terminal of the third sixth capacitor C3-6 is electrically connected to the low voltage terminal VGL.

[0240] In at least one embodiment of the driver circuit shown in FIG. 50, all transistors are p-type transistors, but this is not a limitation.

[0241] In at least one embodiment of the drive circuit shown in FIG. 50, the first voltage terminal is a high voltage terminal and the second voltage terminal is a low voltage terminal, but is not limited to this.

[0242] In at least one embodiment of the driver circuit shown in FIG. 50, all transistors are p-type transistors, but this is not a limitation.

[0243] In at least one embodiment of the driver circuit shown in FIG. 50, N3-10 is the third tenth node.

[0244] In at least one embodiment of the present disclosure, the configuration of the third drive signal generation circuit is not limited to that shown in FIG. 22, and the third drive signal generation circuit may be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.

[0245] At least one embodiment of the driver circuit shown in FIG. 50 of the present disclosure operates as follows. In the first stage, when NS(N-1) outputs a low voltage signal, GCK outputs a low voltage signal, and GCB outputs a high voltage signal, T3-19 and T3-21 turn on to pull down the potential of N3-5 and N3-9, T3-24 and T3-18 turn on to pull down the potential of NC3-2 and N3-6, and T3-26 turns on. The potential of N3-6 is low, ensuring that T3-23 is on, the potential of N3-5 is low, T3-13 is turned on, a low voltage signal is supplied from GCK, T3-12 is turned on, T3-14 is turned on, the potentials of N3-7 and N3-8 are low, T3-15 is turned on to control the potential of N3-3 to high, the potential of N3-5 is low, T3-17 is turned on, and the potential of NC3-1 is high. T3-10 and T3-11 are turned on, and the potentials of NC3-2 and NC3-3 are both low voltages. In the second stage, a low voltage signal is output from NS(N-1), the potential of the first clock signal output from GCK jumps from low voltage to high voltage, a low voltage signal is output from GCB, T3-19 and T3-21 are turned off, the potential of N3-5 is low voltage, T3-12 is turned off and the potential of N3-5 is maintained at low voltage, T3-13 is turned on, T3-14 is turned on, the potentials of N3-7 and N3-8 are high voltage, T3-15 is turned off and the potential of N3-3 is maintained at the high voltage of the previous stage, T3-16 is turned on and the potential of NC3-1 is maintained at high voltage, and T3-25 is turned off. At the same time, the potential of N3-6 is low, turning on T3-23, and the GCB writes a low-voltage signal to N3-4. C3-4 pulls down the potential of N3-6 to a lower voltage (5V to 10V lower than the low-voltage signal supplied by the GCB). T3-10 and T3-11 turn on, writing a low-voltage signal to NC3-2 and N3-6 (NC3-2's potential is 3V to 8V lower than the low-voltage signal supplied by the GCB), fully turning on T3-26 and outputting a low-voltage signal from NS(N). The potential of NC3-3 is low, turning on T3-6 and outputting a low-voltage signal from NO(N). The potential of N3-4 is low, turning on T3-8 and pulling down the potential of N3-1. T3-9 turns on, controlling the potential of NC3-3 to a low voltage, turning on T3-6 and outputting a low-voltage signal from NO(N). Since the potential of N3-4 is low voltage, T3-8 turns on and controls the potential of N3-1 to low voltage, T3-3 turns on and controls NC3-1 and N3-2 to be conductive, and the potential of N3-2 is high voltage, so T3-5 turns off. In the third stage, a high voltage signal is output from NS(N-1), a low voltage signal is output from GCK, a high voltage signal is output from GCB, T3-19 and T3...

Claims

1. A drive circuit including a first drive signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit, and a first output circuit, the first drive signal generation circuit, which is electrically connected to a first first control node, a first second control node, and an Nth (N is a positive integer) stage drive signal output terminal, generates an Nth stage drive signal under control of the potential of the first first control node and the potential of the first second control node, and outputs the Nth stage drive signal via the Nth stage drive signal output terminal; the first output control circuit electrically connected to the first first node, the first first control node, and the first second node, respectively, controls the first first control node and the first second node to be electrically connected together under control of the potential of the first first node; the first gating circuit electrically connected to a first first node, a gating input terminal, and a gating control terminal, respectively, controls, under control of a gating control signal supplied from the gating control terminal, such that a gating input signal supplied from the gating input terminal is written to the first first node; the first first energy storage circuit electrically connected to the first first node and the first second node, respectively, controls a potential of the first second node based on a potential of the first first node; the first second energy storage circuit, which is electrically connected to a first third control node and an N-stage output drive terminal, which are nodes different from the first second control node, controls the potential of the first third control node based on an N-stage drive output signal supplied from the N-stage output drive terminal; the first output circuit, which is electrically connected to a first second node, the first third control node, a first voltage terminal, a second voltage terminal, and the N-stage output drive terminal, controls the N-stage output drive terminal and the first voltage terminal to be electrically connected together under control of the potential of the first second node, and controls the N-stage output drive terminal and the second voltage terminal to be electrically connected together under control of the potential of the first third control node.

2. The drive circuit of claim 1, wherein the first gating circuit controls the gating input signal supplied from the gating input terminal to be written to the first first node when the potential of the first third node of the N-1th stage is a second voltage and the potential of the Nth stage drive signal is a second voltage.

3. the first gating circuit includes a first transistor; 2. The drive circuit of claim 1, wherein a gate of the first first transistor is electrically connected to the gating control terminal, a first pole of the first first transistor is electrically connected to the first first node, and a second pole of the first first transistor is electrically connected to the gating input terminal.

4. the gating control terminal includes a first gating control terminal and a second gating control terminal, the first gating circuit includes a first first transistor and a first second transistor, a gate of the first first transistor is electrically connected to a first gating control terminal, a first pole of the first first transistor is electrically connected to the first first node, and a second pole of the first first transistor is electrically connected to a first pole of the first second transistor; a gate of the first second transistor electrically connected to a second gating control terminal, and a second electrode of the first second transistor electrically connected to the gating input terminal; The first gating control terminal is an N-th stage drive signal output terminal, the second gating control terminal is a first third node of an N-1-th stage, and the first first transistor and the first second transistor are both p-type transistors, or The first gating control terminal is a first third node of the (N-1)th stage, the second gating control terminal is an Nth stage drive signal output terminal, and the first first transistor and the first second transistor are both p-type transistors, or The first gating control terminal is an (N-1)th stage drive signal output terminal, the second gating control terminal is an Nth stage drive signal output terminal, the first first transistor is an n-type transistor, and the first second transistor is a p-type transistor, or The first gating control terminal is an N-th stage drive signal output terminal, the second gating control terminal is an (N-1)th stage drive signal output terminal, the first first transistor is a p-type transistor, and the first second transistor is an n-type transistor, or An inverted signal of an N-1th stage drive signal is input to the first gating control terminal, the second gating control terminal is an Nth stage drive signal output terminal, and the first first transistor and the first second transistor are both p-type transistors, or the first gating control terminal is an N-th stage drive signal output terminal, an inverted signal of an N-1-th stage drive signal is input to the second gating control terminal, and the first first transistor and the first second transistor are both p-type transistors, or the first gating control terminal is an (N-1)th stage drive signal terminal, an inverted signal of an Nth stage drive signal is input to the second gating control terminal, and the first first transistor and the first second transistor are both n-type transistors, or 2. The drive circuit according to claim 1, wherein an inverted signal of an N-th stage drive signal is input to the first gating control terminal, the second gating control terminal is an N-1-th stage drive signal terminal, and the first first transistor and the first second transistor are both n-type transistors.

5. the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor; a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node; The drive circuit according to any one of claims 1 to 4, wherein a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage output drive terminal.

6. the first output control circuit includes a first third transistor; 5. The drive circuit according to claim 1, wherein a gate of the first third transistor is electrically connected to the first first node, a first pole of the first third transistor is electrically connected to the first first control node, and a second pole of the first third transistor is electrically connected to the first second node.

7. a first second node control circuit; The drive circuit according to any one of claims 1 to 4, wherein the first second node control circuit, which is electrically connected to a first third control node, a first second node, and a first voltage terminal, controls the first second node and the first voltage terminal to be electrically connected together under control of the potential of the first third control node.

8. a first second node control circuit; The drive circuit according to any one of claims 1 to 4, wherein the first second node control circuit, which is electrically connected to a first third control node, the Nth stage output drive terminal, a first second node, and a first voltage terminal, controls the first second node and the first voltage terminal to be electrically connected together under control of the potential of the first third control node and an Nth stage drive output signal supplied from the Nth stage output drive terminal.

9. the first second node control circuit includes a first fourth transistor; 8. The drive circuit of claim 7, wherein a gate of the first fourth transistor is electrically connected to the first third control node, a first pole of the first fourth transistor is electrically connected to the first second node, and a second pole of the first fourth transistor is electrically connected to a first voltage terminal.

10. the first second node control circuit includes a first fourth transistor and a first control transistor; a gate of the first fourth transistor is electrically connected to the first third control node, a first pole of the first fourth transistor is electrically connected to a second pole of the first control transistor, and a second pole of the first fourth transistor is electrically connected to a first voltage terminal; 9. The drive circuit according to claim 8, wherein a gate of the first control transistor is electrically connected to the Nth stage output drive terminal, and a first pole of the first control transistor is electrically connected to the first second node.

11. the first output circuit includes a first fifth transistor, a first sixth transistor, and a first third capacitor; a gate of the first fifth transistor is electrically connected to the first second node, a first electrode of the first fifth transistor is electrically connected to a first voltage terminal, and a second electrode of the first fifth transistor is electrically connected to the N-th stage output drive terminal; a gate of the first sixth transistor is electrically connected to the first third control node, a first electrode of the first sixth transistor is electrically connected to the N-th stage output drive terminal, and a second electrode of the first sixth transistor is electrically connected to a second voltage terminal; 5. The drive circuit according to claim 1, wherein a first terminal of the first third capacitor is electrically connected to the first second node, and a second terminal of the first third capacitor is electrically connected to the first voltage terminal.

12. further comprising a first initialization circuit; The drive circuit according to any one of claims 1 to 4, wherein the first initialization circuit, which is electrically connected to an initial control terminal, a second voltage terminal, and a first first node, controls the first first node and the second voltage terminal to be electrically connected under the control of an initial control signal supplied from the initial control terminal.

13. a first node control circuit; 5. The drive circuit according to claim 1, wherein the first first node control circuit, which is electrically connected to a first fourth node, a second voltage terminal, and the first first node, respectively, controls the first first node and the second voltage terminal to be electrically connected together under control of the potential of the first fourth node.

14. the first initialization circuit includes a first seventh transistor; 13. The driving circuit of claim 12, wherein a gate of the first seventh transistor is electrically connected to the initial control terminal, a first pole of the first seventh transistor is electrically connected to the first first node, and a second pole of the first seventh transistor is electrically connected to a second voltage terminal.

15. the first first node control circuit includes a first eighth transistor; 14. The drive circuit of claim 13, wherein a gate of the first eighth transistor is electrically connected to the first fourth node, a first pole of the first eighth transistor is electrically connected to the first first node, and a second pole of the first eighth transistor is electrically connected to a second voltage terminal.

16. a first third control node control circuit; 5. The drive circuit according to claim 1, wherein the first third control node control circuit electrically connected to a first first node, a first fifth node, a first second control node, a first third control node, and a first sixth node, respectively, controls the first fifth node and the first third control node to be electrically connected together under control of the potential of the first first node, controls the first second control node and the first sixth node to be electrically connected together under control of the potential of the first sixth node, and controls the first sixth node and the first third control node to be electrically connected together.

17. the first third control node control circuit includes a first ninth transistor, a first tenth transistor, and a first eleventh transistor; a gate of the first ninth transistor is electrically connected to the first first node, a first pole of the first ninth transistor is electrically connected to the first fifth node, and a second pole of the first ninth transistor is electrically connected to the first third control node; a gate of the first tenth transistor and a second electrode of the first tenth transistor are both electrically connected to the first sixth node, and a first electrode of the first tenth transistor is electrically connected to the first second control node; 17. The drive circuit of claim 16, wherein a gate of the first eleventh transistor and a first pole of the first eleventh transistor are both electrically connected to the first sixth node, and a second pole of the first eleventh transistor is electrically connected to a first third control node.

18. further comprising a first output pull-down circuit; The drive circuit according to any one of claims 1 to 4, wherein the first output pull-down circuit electrically connected to the first first control node, the N-stage drive signal output terminal, and the second voltage terminal respectively controls the N-stage drive signal output terminal and the second voltage terminal to be electrically connected under control of the potential of the first first control node.

19. the first drive signal generation circuit includes a first first drive output circuit, a first second drive output circuit, a first first control node control circuit, and a first second control node control circuit; the first first control node control circuit controls the potential of the first first control node; the first second control node control circuit controls the potential of the first second control node; the first first drive output circuit, which is electrically connected to the first first control node, the first voltage terminal, and the N-stage drive signal output terminal, respectively, controls the N-stage drive signal output terminal and the first voltage terminal to be electrically connected together under control of the potential of the first first control node; The drive circuit according to any one of claims 1 to 4, wherein the first second drive output circuit electrically connected to the first second control node, the second voltage terminal, and the N-stage drive signal output terminal respectively controls the N-stage drive signal output terminal and the second voltage terminal to be electrically connected under control of the potential of the first second control node.

20. the first first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit; the first seventh node control circuit, which is electrically connected to a first seventh node, a second voltage terminal, a first clock signal terminal, and a first fifth node, controls the first seventh node and the second voltage terminal to be electrically connected together under control of a first clock signal supplied from the first clock signal terminal, and controls the first seventh node and the first clock signal terminal to be electrically connected together under control of a potential of the first fifth node; the first eighth-node control circuit, which is electrically connected to the second voltage terminal, the first seventh node, and the first eighth node, respectively, controls the first seventh node and the first eighth node to be electrically connected to each other under control of a second voltage signal supplied from the second voltage terminal; the first third node control circuit, which is electrically connected to a first eighth node, a second clock signal terminal, and a first third node, respectively, controls the electrical connection between the first third node and the second clock signal terminal under control of the potential of the first eighth node, and controls the potential of the first third node based on the potential of the first eighth node; 20. The drive circuit of claim 19, wherein the first control circuit, which is electrically connected to a second clock signal terminal, a first third node, a first first control node, a first fifth node, and a first voltage terminal, controls the first third node and the first first control node to be electrically connected together under control of a second clock signal supplied from the second clock signal terminal, and controls the first first control node and the first voltage terminal to be electrically connected together under control of a potential of the first fifth node.

21. the first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit; the first sixth node control circuit, which is electrically connected to a second voltage terminal, a first ninth node, the first sixth node, and the first fourth node, respectively, controls the first ninth node and the first sixth node to be electrically connected together under control of a second voltage signal supplied from the second voltage terminal, and controls the potential of the first sixth node based on the potential of the first fourth node; the first fifth node control circuit, which is electrically connected to the N-1 stage drive signal output terminal, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, controls the first fifth node and the N-1 stage drive signal output terminal to be electrically connected together under control of a first clock signal supplied from the first clock signal terminal, and controls the first fifth node and the first voltage terminal to be electrically connected together under control of an initial control signal supplied from the initial control terminal; the first ninth node control circuit, which is electrically connected to a first clock signal terminal, an N-1th stage drive signal output terminal, and a first ninth node, controls the first ninth node and the N-1th stage drive signal output terminal to be electrically connected to each other under control of a first clock signal supplied from the first clock signal terminal; the first fourth node control circuit, which is electrically connected to a first seventh node, a first voltage terminal, a first fourth node, a second clock signal terminal, and a first sixth node, respectively, controls the first fourth node and the first voltage terminal to be electrically connected together under control of the potential of the first seventh node, and controls the first fourth node and the second clock signal terminal to be electrically connected together under control of the potential of the first sixth node; 20. The drive circuit of claim 19, wherein the first second control circuit, which is electrically connected to a second voltage terminal, a first fifth node, and a first second control node, respectively, controls the first fifth node and the first second control node to be conductive under control of a second voltage signal supplied from the second voltage terminal.

22. the first seventh node control circuit includes a first twelfth transistor and a first thirteenth transistor, the first eighth node control circuit includes a first fourteenth transistor, the first third node control circuit includes a first fifteenth transistor and a first fourth capacitor, and the first first control circuit includes a first sixteenth transistor and a first seventeenth transistor; a gate of the first twelfth transistor is electrically connected to a first clock signal terminal, a first pole of the first twelfth transistor is electrically connected to a second voltage terminal, and a second pole of the first twelfth transistor is electrically connected to a first seventh node; a gate of the first thirteenth transistor is electrically connected to a first fifth node, a first pole of the first thirteenth transistor is electrically connected to the first seventh node, and a second pole of the first thirteenth transistor is electrically connected to a first clock signal terminal; a gate of the first fourteenth transistor is electrically connected to a second voltage terminal, a first electrode of the first fourteenth transistor is electrically connected to the first seventh node, and a second electrode of the first fourteenth transistor is electrically connected to the first eighth node; a gate of the first fifteenth transistor is electrically connected to the first eighth node, a first pole of the first fifteenth transistor is electrically connected to a second clock signal terminal, and a second pole of the first fifteenth transistor is electrically connected to the first third node; a first terminal of the first fourth capacitor is electrically connected to a first eighth node, and a second terminal of the first fourth capacitor is electrically connected to a first third node; a gate of the first sixteenth transistor is electrically connected to the second clock signal terminal, a first pole of the first sixteenth transistor is electrically connected to the first third node, and a second pole of the first sixteenth transistor is electrically connected to a first first control node; 21. The drive circuit of claim 20, wherein a gate of the first seventeenth transistor is electrically connected to a first fifth node, a first pole of the first seventeenth transistor is electrically connected to a first first control node, and a second pole of the first seventeenth transistor is electrically connected to a first voltage terminal.

23. the first sixth node control circuit includes a first eighteenth transistor and a first fifth capacitor, the first fifth node control circuit includes a first nineteenth transistor and a first twentieth transistor, the first ninth node control circuit includes a first twenty-first transistor, the first fourth node control circuit includes a first twenty-second transistor and a first twenty-third transistor, and the first second control circuit includes a first twenty-fourth transistor; a gate of the first 18th transistor is electrically connected to a second voltage terminal, a first electrode of the first 18th transistor is electrically connected to a first 9th node, and a second electrode of the first 18th transistor is electrically connected to a first 6th node; a first terminal of the first fifth capacitor is electrically connected to the first fourth node, and a second terminal of the first fifth capacitor is electrically connected to the first sixth node; a gate of the first 19th transistor is electrically connected to a first clock signal terminal, a first pole of the first 19th transistor is electrically connected to an (N-1)th stage drive signal output terminal, and a second pole of the first 19th transistor is electrically connected to a first fifth node; a gate of the first twentieth transistor is electrically connected to an initial control terminal, a first pole of the first twentieth transistor is electrically connected to a first voltage terminal, and a second pole of the first twentieth transistor is electrically connected to the first fifth node; a gate of the first 21st transistor is electrically connected to a first clock signal terminal, a first pole of the first 21st transistor is electrically connected to an (N-1)th stage drive signal output terminal, and a second pole of the first 21st transistor is electrically connected to a first ninth node; a gate of the first 22nd transistor is electrically connected to a first seventh node, a first pole of the first 22nd transistor is electrically connected to a first voltage terminal, and a second pole of the first 22nd transistor is electrically connected to a first fourth node; a gate of the first 23rd transistor is electrically connected to a first sixth node, a first pole of the first 23rd transistor is electrically connected to a first fourth node, and a second pole of the first 23rd transistor is electrically connected to a second clock signal terminal; 22. The drive circuit of claim 21, wherein a gate of the first 24th transistor is electrically connected to a second voltage terminal, a first pole of the first 24th transistor is electrically connected to a first 9th node, and a second pole of the first 24th transistor is electrically connected to a first second control node.

24. the first first drive output circuit includes a first 25th transistor and a first 6th capacitor, the first second drive output circuit includes a first 26th transistor and a first 7th capacitor, a gate of the first 25th transistor is electrically connected to the first first control node, a first electrode of the first 25th transistor is electrically connected to a first voltage terminal, and a second electrode of the first 25th transistor is electrically connected to an N-stage drive signal output terminal; a first terminal of the first sixth capacitor is electrically connected to the first first control node, and a second terminal of the first sixth capacitor is electrically connected to a first voltage terminal; a gate of the first 26th transistor is electrically connected to a first second control node, a first electrode of the first 26th transistor is electrically connected to an N-stage drive signal output terminal, and a second electrode of the first 26th transistor is electrically connected to a second voltage terminal; 20. The drive circuit of claim 19, wherein a first terminal of the first seventh capacitor is electrically connected to the Nth stage drive signal output terminal, and a second terminal of the first seventh capacitor is electrically connected to a second voltage terminal.

25. the first output pull-down circuit includes a first 27th transistor; 19. The drive circuit of claim 18, wherein a gate of the first 27th transistor is electrically connected to the first first control node, a first pole of the first 27th transistor is electrically connected to the N-th stage drive signal output terminal, and a second pole of the first 27th transistor is electrically connected to the second voltage terminal.

26. A driving method applied to the driving circuit according to any one of claims 1 to 25, comprising: The driving method includes: a first drive signal generating circuit generates an Nth stage drive signal (N is a positive integer) under control of the potential of the first first control node and the potential of the first second control node, and outputs the Nth stage drive signal via an Nth stage drive signal output terminal; a first output control circuit controlling the first first control node and the first second node to be electrically connected under control of a potential of the first first node; a first gating circuit controlling, under control of a gating control signal, a gating input signal to be written to a first first node; a first first energy storage circuit controlling a potential of the first second node based on a potential of the first first node; the first second energy storage circuit controls the potential of the first third control node based on an N-th stage drive output signal supplied from an N-th stage output drive terminal; the first output circuit controls the N-stage output drive terminal and the first voltage terminal to be electrically connected together under control of the potential of the first second node, and the first output circuit controls the N-stage output drive terminal and the second voltage terminal to be electrically connected together under control of the potential of the first third control node; A driving method, wherein the first third control node and the first second control node are different nodes.

27. A driving module including a plurality of stages of the driving circuit according to any one of claims 1 to 25, A driving module in which an Nth (N is a positive integer) stage driving circuit is electrically connected to a driving signal output terminal included in an N-1th stage driving circuit.

28. A display device comprising a driving module according to claim 27.

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