Solid-state switch-based high-speed pulser with plasma IEDF correction via multi-level output capability

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating waveforms for plasma processing of substrates in a processing chamber. One embodiment includes a waveform generator having three MOSFETs and three series-connected capacitors. The capacitors are connected to a direct current (DC) power supply, and the voltage of each of the capacitors can be changed according to the value of the capacitor. A diode is connected after each of the top two capacitors. The bottom capacitor is connected to ground. The drain terminal of each MOSFET is connected to the higher potential end of the series-connected capacitors. A diode is connected after each MOSFET, and the cathode terminals of the diodes are connected together. An electrode is connected between the common cathode and ground.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to systems used in the manufacture of semiconductor devices, and more particularly to plasma processing systems used to process substrates. [Background technology]

[0002] Low-temperature, non-equilibrium glow discharge plasmas are powerful tools for semiconductor device fabrication, primarily used for thin film etching and deposition and ion implantation, among other applications. High-aspect-ratio features are increasingly desirable in the semiconductor industry as it ventures into the sub-10 nm regime. One common method for achieving high aspect ratios with reliable throughput is reactive ion etching (RIE). In this process, a plasma is formed, traditionally using a radio-frequency (RF) source, and ions in the plasma are accelerated toward the substrate surface under the influence of a bias voltage applied to a metal plate known as the cathode. The cathode can be coupled to the plasma using capacitive coupling through a dielectric layer.

[0003] An RF voltage bias applied to the chamber's cathode creates an electron-repellent plasma sheath above the substrate surface, which acts like a nonlinear diode, resulting in a negative cathode potential relative to the positive plasma potential. The RF cathode bias results in an ion energy distribution function (IEDF) that contains two peaks. Lower-energy ions contribute to the isotropic behavior, resulting in sidewall bowing of high-aspect-ratio features, while higher-energy ions reach the bottom of the feature with greater sputtering. Increased sputtering levels can impair etch selectivity and cause unwanted etching of mask layers. Therefore, additional control knobs are needed on the bias source to fine-tune selectivity while producing high-aspect-ratio features.

[0004] Therefore, some modern chamber designs incorporate multiple RF bias sources to enable additional levels of etch control. However, multiple RF bias sources can introduce arcing and crosstalk issues. Pulsed plasma sources present a unique platform that can mitigate the aforementioned issues associated with RF bias sources and help improve etch selectivity, throughput, and uniformity.

[0005] Traditionally, pulsed power supplies provide a pulsed DC bias to the cathode. The design must consider switching frequency and power dissipation capabilities. As device dimensions shrink, the complexity of semiconductor tools increases exponentially. Of critical importance for semiconductor manufacturing tools employing plasma etch processes, DC bias supplies are undergoing changes, including increased peak amplitude and switching frequency, multi-level pulsing, and robust cooling mechanisms. The two main types of direct current (DC) power supplies suitable for semiconductor tools are inductive adder-based DC power supplies and metal-oxide semiconductor field-effect transistor (MOSFET)-based DC power supplies. However, inductive adder-based DC power supplies are limited in their operating switching frequency due to the limited range of magnetic flux density variation in the magnetic core. Furthermore, the weight of the magnetic core results in a large footprint and bulky power supply. However, MOSFET-based power supplies, especially silicon carbide (SiC) MOSFETs and gallium nitride (GaN) MOSFETs, offer superior switching capabilities. Furthermore, these solid-state switch-based sources can provide similar or better performance in a smaller footprint due to the compact size of the MOSFETs. However, as the switching frequency increases, switching losses increase proportionally and cooling mechanisms become more complex.

[0006] Therefore, there is a need for a pulsed DC bias source with a switching frequency high enough to control the critical high aspect ratio features, etch selectivity, and uniformity of RIE. Summary of the Invention

[0007] FIELD OF THE INVENTION The embodiments described herein relate generally to systems used in the manufacture of semiconductor devices. More particularly, embodiments of the present disclosure relate to plasma processing systems used to process substrates using bias pulse regimes to generate micropulses.

[0008] In one embodiment, a system for reactive ion etching includes a chamber body, a substrate support within the chamber body, a bias electrode within the substrate support, and a bias voltage source configured to supply a pulsed bias voltage to the bias electrode, the bias voltage source including a direct current (DC) voltage source, a first capacitor connected to the DC voltage source, ground, a first diode connected in series between the first capacitor and ground, a first resistor connected to the DC voltage source, a first metal oxide semiconductor field effect transistor (MOSFET) connected in series with the first resistor, a first gate voltage source connected to a gate of the first MOSFET, a first blocking diode connected to a source of the first MOSFET, a second capacitor connected in series between the first diode and ground, a second diode connected in series between the second capacitor and ground, a second resistor connected between the first diode and the second capacitor, the second MOSFET connected in series with the second resistor, a second gate voltage source connected to a gate of the second MOSFET, and a second blocking diode connected to a source of the second MOSFET.

[0009] In another embodiment, a method for etching using a pulsed waveform is provided. The method includes generating a plasma in a chamber body, applying a pulsed direct current (DC) voltage to the plasma using a bias electrode capacitively coupled to the plasma through a dielectric layer, the pulsed DC voltage including a plurality of pulses, each of the plurality of pulses further including a plurality of signals, each of the plurality of signals having an off time, a pulse width, and an amplitude, and etching a substrate in the chamber body using the pulsed DC voltage applied to the plasma. The DC voltage source is connected in series to a second capacitor connected between a first diode and ground, a second resistor connected in parallel with the second capacitor, a second MOSFET connected in series with the second resistor, a second gate voltage source connected to a gate terminal of the second MOSFET, and a second blocking diode connected to a source terminal of the second MOSFET. A direct current (DC) voltage source is connected in series with a second capacitor connected in series between the first diode and ground, a second diode connected in series between the second capacitor and ground, a second resistor connected in parallel with the second capacitor, a second MOSFET connected in series with the second resistor, a second gate voltage source connected to a gate terminal of the second MOSFET, and a second blocking diode connected to a source terminal of the second MOSFET. The first MOSFET receives a first gating signal having a first pulse width from the first gate voltage source, and the second MOSFET receives a second gating signal having a second pulse width from the second gate voltage source.

[0010] In yet another embodiment, a pulsed signal source apparatus for etching is presented, comprising: a controller; a bias electrode; and a bias voltage source configured to provide a pulsed bias voltage to the bias electrode. The bias voltage source includes a direct current (DC) voltage source, a first capacitor connected in series with the direct current (DC) voltage source, a first diode connected to the first capacitor, ground connected in series with the first diode, a first resistor connected in parallel with the first capacitor, a first MOSFET connected in series with the first resistor, a first gate voltage source connected to a gate terminal of the first MOSFET, a second capacitor connected in series between the first diode and ground, a second diode connected in series between the second capacitor and ground, a second resistor connected in parallel with the second capacitor, the second MOSFET connected in series with the second resistor, a second gate voltage source connected to a gate terminal of the second MOSFET, a second blocking diode connected to a source terminal of the second MOSFET, a third capacitor connected in series between the second diode and ground, a third resistor connected in parallel with the third capacitor, the third MOSFET connected in series with the third resistor, a third gate voltage source connected to a gate terminal of the third MOSFET, and a third blocking diode connected to a source terminal of the third MOSFET.

[0011] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above will be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and therefore should not be considered limiting of its scope, as the present disclosure may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic cross-sectional view of a processing system configured to perform methods described herein, according to one or more embodiments. [Figure 2A]FIG. 1 illustrates a solid-state switch-based high-speed pulser according to an embodiment of the present disclosure. [Figure 2B] FIG. 1 illustrates a solid-state switch-based high-speed pulser according to an embodiment of the present disclosure. [Figure 3] 1 is a schematic cross-sectional view of an apparatus configured to perform the methods described herein, according to one or more embodiments. [Figure 4] 3 shows a voltage waveform formed on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 5] 3 shows a voltage waveform formed on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 6A] 3 shows a voltage waveform formed on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 6B] 3 shows a voltage waveform formed on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 7] 3 shows a voltage waveform formed on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 8A] 3 shows a voltage waveform formed on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 8B] 3 shows a voltage waveform formed on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 9] FIG. 1 is a process flow diagram illustrating a waveform generation method. DETAILED DESCRIPTION OF THE INVENTION

[0013] For ease of understanding, wherever possible, like reference numerals have been used to designate like elements common to the figures. It is believed that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0014] FIELD OF THE INVENTION The embodiments described herein are directed generally to electronic device manufacturing, and more particularly to systems and methods for forming low resistivity tungsten features in semiconductor device manufacturing schemes.

[0015] The present disclosure includes a metal-oxide-semiconductor field-effect transistor (MOSFET)-based three-stage topology configured to generate customizable multi-level output waveforms and increase effective output frequencies while mitigating the switching frequency limitations of current-generation MOSFETs. In embodiments of the present disclosure, customizable voltage output waveforms for dynamic ion energy distribution functions (IEDFs) are generated to add unique tuning knobs to plasma etch recipes. Furthermore, the effective output efficiency of the pulser is increased based on the number of stages and gating signal patterns. Furthermore, embodiments of the present disclosure also generate pulses of various widths in a single output burst while mitigating the switching frequency limitations of current-generation MOSFETs and correspondingly reducing cooling requirements, creating a lighter, faster alternative to inductive adder-based pulsers.

[0016] 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma process. However, it should be noted that the embodiments described herein can also be used in processing systems configured for use with other plasma-assisted processes, such as plasma-enhanced deposition processes, e.g., plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma processing, or plasma-based ion implantation processes, e.g., plasma doping (PLAD) processes.

[0017] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP) and includes a processing chamber 100. The processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) disposed near a processing space 129, the upper electrode facing a lower electrode (e.g., a substrate support assembly 136) disposed within the processing space 129 on the opposite side of the upper electrode. In a typical CCP processing system, a radio frequency (RF) source (e.g., an RF generator 118) is electrically coupled to one of the upper or lower electrodes (the lower electrode in FIG. 1 ) and provides an RF signal configured to generate and sustain a plasma (e.g., plasma 101). In this configuration, the plasma is capacitively coupled to each of the upper and lower electrodes and is disposed within the processing space 129 between the upper and lower electrodes. Typically, the opposite upper or lower electrode (the upper electrode in FIG. 1 ) is coupled to ground or a second RF power source. 1, one or more components of the substrate support assembly 136, such as the support base 107, are electrically coupled to a plasma generating assembly 163 that includes an RF generator 118, and the chamber lid 123 is electrically coupled to ground. As shown, the processing system 10 includes a processing chamber 100, the support assembly 136, and a system controller 126.

[0018] The processing chamber 100 typically includes a chamber body 113, which includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which collectively define a processing volume 129. The one or more sidewalls 122 and the chamber base 124 generally comprise a material sized and shaped to provide structural support for the elements of the processing chamber 100 and configured to withstand the pressure and additional energy applied thereto while a plasma 101 is generated in a vacuum environment maintained within the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or stainless steel.

[0019] A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases to the process space 129 from a process gas source 119 in fluid communication with the gas inlet 128. The substrate 103 is loaded into and removed from the process space 129 through an opening (not shown) in one of the sidewalls 122, which is sealed by a slit valve (not shown) during plasma processing of the substrate 103. The substrate 103 is supported by a substrate support assembly 136. The substrate support assembly 136 includes a substrate support 105 configured to support the substrate 103 thereon, a support base 107 disposed below the substrate support 105, an insulating plate 111 disposed below the support base 107, and a ground plate 112 disposed below the insulating plate 111.

[0020] In some embodiments, the processing chamber 100 further includes a quartz pipe 110, or collar, that at least partially surrounds a portion of the substrate support assembly 136 to prevent the substrate support 105 and support base 107 from contacting corrosive process gases or plasmas, cleaning gases or plasmas, or by-products thereof. Typically, the quartz pipe 110, the insulating plate 111, and the ground plate 112 are surrounded by a liner 108. In some embodiments, a plasma screen 109 is disposed between the liner 108 and one or more sidewalls 122 to prevent plasma from forming in the space below the plasma screen 109 between the liner 108 and the one or more sidewalls 122.

[0021] The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate biasing methods described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial environment to control the processing chamber and its associated sub-processors. The memory 134 described herein is generally non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of local or remote digital storage. The support circuits 135 are conventionally connected to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data for instructing the processor in the CPU 133 may be coded and stored in the memory 134. The software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks are executable by the components in the processing chamber 10.

[0022] Typically, a program readable by CPU 133 in system controller 126 includes code that, when executed by the processor (CPU 133), performs tasks related to the plasma processing schemes described herein. The program may include instructions used to control various hardware and electrical components within processing chamber 10 to perform various process tasks and various process sequences used to carry out the methods described herein.

[0023] The processing system may include a plasma generation assembly 163 and a first pulsed voltage (PV) source assembly 196, described in more detail herein with respect to FIGS. 4-8B , for forming a first PV waveform at a bias electrode 104 disposed within the substrate support 105. In some embodiments, the plasma generation assembly 163 supplies an RF signal to the support base 107 (e.g., a power electrode or cathode) that may be used to generate (sustain or ignite) a plasma 101 within a process space 129 disposed between the substrate support assembly 136 and the chamber lid 123. The bias electrode 104 is capacitively coupled to the plasma 101 through a dielectric layer 105B of the substrate support 105. In some embodiments, the RF generator 118 is configured to supply an RF signal having a frequency of 1 MHz or greater, or about 2 MHz or greater, for example, a frequency of about 13.56 MHz or greater.

[0024] As described above, in some embodiments, the plasma generating assembly 163, including the RF generator 118 and the RF generating assembly 160, is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal waveform frequency to the support base 107 of the substrate support assembly 136 based on control signals provided from the system controller 126. During processing, the plasma generating assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107, which is positioned proximate the substrate support 105 within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to generate and sustain a processing plasma 101 using a process gas disposed within the process space 129 and an electric field generated by the RF power (RF signal) supplied to the support base 107 by the RF generator 118.

[0025] In some embodiments, the support base 107 is an RF electrode that is electrically coupled to the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161 (both disposed within the RF generating assembly 160).

[0026] The processing space 129 is fluidly coupled via a vacuum outlet 120 to one or more dedicated vacuum pumps that maintain the processing space 129 at sub-atmospheric pressure and evacuate processing and / or other gases therefrom. In some embodiments, a substrate support assembly 136 disposed within the processing space 129 is disposed on a support shaft 138 that is grounded and extends through the chamber base 124.

[0027] The substrate support assembly 136 generally includes a substrate support 105 (e.g., an electrostatic chuck substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may additionally include an insulating plate 111 and a grounded plate 112, as described further below. The support base 107 is electrically isolated from the chamber base 124 by the insulating plate 111 and the grounded plate 112, which is interposed between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and rests on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing.

[0028] Typically, the substrate support 105 is formed of a dielectric material such as a bulk-sintered ceramic material, e.g., a corrosion-resistant metal oxide or metal nitride material, e.g., aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (YO3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material of the substrate support 105.

[0029] In one configuration, the bias electrode 104 is a chucking pole used to secure (i.e., chuck) the substrate 103 to the substrate receiving surface 105A of the substrate support 105 and bias the substrate 103 with respect to the processing plasma 101 using one or more pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components, such as one or more metallic meshes, foils, plates, or combinations thereof.

[0030] In some embodiments, the bias electrode 104 is electrically coupled to a bias voltage source 150, which supplies a chucking voltage or pulsed bias voltage 153, such as a pulsed DC voltage between about -5000V and about 5000V, to the bias electrode 104 using a conductor such as a coaxial power supply 106 (e.g., a coaxial cable).

[0031] Power supply line 157 electrically connects the output of bias voltage source 150 of first bias voltage supply assembly 196 to optional filter assembly 151 and bias electrode 104. The conductors in the various components of power supply line 157 may include one or a combination of (a) coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable, (b) insulated high-voltage corona-resistant hook-up wires, (c) bare wires, (d) metal rods, (e) electrical connectors, or (f) any combination of the electrical elements (a)-(e). Optional filter assembly 151 includes one or more electrical elements configured to substantially prevent current generated by the output of RF generator 118 from flowing through power supply line 157 and damaging bias voltage source 150. Optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by RF generator 118, thereby inhibiting current flow to bias voltage source 150.

[0032] 2A is a schematic diagram of a bias voltage source 150. As shown in FIG. 2A, the bias voltage source 150 includes a DC voltage source 210, a first capacitor 220 connected to the positive terminal of the DC voltage source 210, and a first diode 230 connected to the first capacitor 220. The bias voltage source 150 further includes a first resistor 240 connected to the positive terminal of the DC voltage source 210, a first MOSFET 250 connected in series with the first resistor 240, a first gate voltage source 260 connected to the gate terminal of the first MOSFET 250, and a first blocking diode 270 connected to the source terminal 251 of the first MOSFET 250. The bias voltage source 150 may also include a second capacitor 222 connected in series between the first diode 230 and ground 228 and a second diode 232 connected in series between the second capacitor 222 and ground 228. As shown, the second capacitor 222 is connected in series between the first diode 230 and the second diode 232. A second resistor 242 may be connected to the common node of the first diode 230 and the second capacitor 222. A second MOSFET 252, a second gate voltage source 262, and a second blocking diode 272 may also be connected in series with the second resistor 242, where the cathode of the second blocking diode 272 is connected to the cathode of the first blocking diode 270. As shown, the bias voltage source 150 may also include a third capacitor 224 connected in series between the second diode 232 and ground 228. Additionally, a third resistor 244 may be connected to the common node of the second diode 232 and the third capacitor 224. A third MOSFET 254, a third gate voltage source 264, and a third blocking diode 274 may also be connected in series with the third resistor 244, where the cathode of the third blocking diode 274 is connected to the bias electrode 104. When all MOSFETs are gated ON simultaneously and the width of the gating signals is the same, the full supply voltage will be applied to the load.

[0033] By turning on the MOSFETs (e.g., 250, 252, and 254) at different timestamps, the effective output frequency can be tripled. While this approach increases the effective output frequency, each MOSFET operates at a switching frequency that is one-third of the effective output switching frequency. Furthermore, using a combination of gate signal widths and delays, a wide range of multi-level output voltage waveforms can be generated, each corresponding to a unique IEDF that can be a unique addition to a plasma etch recipe. By utilizing the above features provided by the present disclosure, the selectivity, uniformity, and throughput of RIE can be significantly improved.

[0034] 2B , the bias voltage source 150 may include a first resistor 240 connected to the positive terminal of the DC voltage source 210, a first MOSFET 250 connected in series with the first resistor 240, a first gate voltage source 260 connected to a gate terminal of the first MOSFET 250, and a first blocking diode 270 connected to a source terminal 251 of the first MOSFET 250. Furthermore, a second capacitor 222 may be connected in series between the first diode 230 and ground 228. The bias voltage source 152 may also include a second resistor 242 connected to a common node of the first diode 230 and the second capacitor 222. The second MOSFET 252 may be connected in series with the second resistor 242, a second gate voltage source 262 may be connected to a gate terminal of the second MOSFET 252, and a second blocking diode 272 may be connected to a source terminal 253 of the second MOSFET 252. In this embodiment, the electrode 140 is electrically coupled to a second blocking diode 272 of the bias voltage source 152 .

[0035] 3 is a schematic diagram of a pulsed signal source apparatus 300. The pulsed signal source apparatus 300 includes a substrate support (e.g., an electrostatic chuck) 305 made of a dielectric material and configured to support a substrate 303 on a substrate support surface 305a, a support base 307, an insulating plate, a ground plate 312, and a support shaft 338. The pulsed signal source apparatus 300 further includes an electrode 304 disposed within the substrate support 305 and configured to capacitively couple to a plasma through a dielectric layer 305b, and a bias voltage source 301 configured to supply a pulsed bias voltage to the electrode 304. The bias voltage source 301 includes a DC voltage source 310, a first capacitor 320 connected in series with the DC voltage source 310, a first diode 330 connected to the first capacitor 320, a first resistor 340 having one end connected to the positive terminal of the DC voltage source 310, a first MOSFET 350 connected in series with the first resistor 340, a first gate voltage source 360 ​​connected to the gate terminal of the first MOSFET 350, and a first blocking diode 370 connected to the source terminal 351 of the first MOSFET 350. The bias voltage source 301 further includes a second capacitor 322 connected in series between the first diode 330 and the second diode 332 connected in series between the second capacitor 322 and ground 328, a second resistor 342 connected to a common connection point between the first diode 330 and the second capacitor 322, a second MOSFET 352 connected in series with the second resistor 342, a second gate voltage source 362 connected to a gate terminal of the second MOSFET 352, and a second blocking diode 372 connected to a source terminal 353 of the second MOSFET 352. Furthermore, a third capacitor 324 is connected in series between the second diode 332 and ground 328, and a third resistor 344 is connected to the common connection point between the second diode 332 and the third capacitor 324. In addition, a third MOSFET 354 is connected in series with the third resistor 344, a third gate voltage source 364 is connected to the gate terminal of the third MOSFET 354, and a third blocking diode 374 is connected to the source terminal of the third MOSFET 354.The memory 334, CPU 333, and support circuits 335 of system controller 326 (similar to system controller 126) can vary the pulse width, duration, and amplitude in accordance with the present disclosure, as further described below.

[0036] 4 illustrates a pulsed voltage bias scheme using a waveform 400, in accordance with certain embodiments of the present disclosure. As shown, waveform 400 includes a plurality of pulses 410. Each of the plurality of pulses 410 includes a total pulse width 412. Within each of the plurality of pulses 410, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 420 having a first pulse width 421, a second signal 422 having a second pulse width 423, and a third signal 424 having a third pulse width 425. Each signal also has an off-time (T off ), for example, for the first signal 420, the first T off 430, and for the second signal 422, the second T off 432, and for the third signal 434, a third T off 434 and so on. off 430 is the period between pulses or the period before the start of the initial pulse, during which at least the first MOSFET is gated OFF, and typically all MOSFETs are gated OFF. Furthermore, each signal has its own respective amplitude, for example, first amplitude 440, second amplitude 442, and third amplitude 444, etc.

[0037] In FIG. 4, each of the MOSFETs is gated on at the same time and supplies the same voltage, so that the first signal 420, the second signal 422, and the third signal 424 have the same amplitude (e.g., 440, 442, and 444 are equal), T off (e.g., 430, 432, and 434 are equal), and pulse width (e.g., 421, 423, and 425 are equal).

[0038] 5 illustrates a pulsed voltage bias scheme using a waveform 500, in accordance with certain embodiments of the present disclosure. As shown, waveform 500 includes a plurality of pulses 510. The plurality of pulses 510 includes a total pulse width 512. Within the plurality of pulses 510, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 520 having a first pulse width 521, a second signal 522 having a second pulse width 523, and a third signal 524 having a third pulse width 525. Each signal has a T off For example, for the first signal 520, the first T off 530, and for the second signal 522, a second T off 532, and a third T for the third signal 534. off 534, etc. Furthermore, each signal has its own respective amplitude, for example, first amplitude 540, second amplitude 542, and third amplitude 544, etc.

[0039] 5, each of the MOSFETs is sequentially gated on and then gated off, but each MOSFET supplies the same voltage with the same pulse width. This results in first signal 520, second signal 522, and third signal 524 having the same amplitude (e.g., 540, 542, and 544 are equal) and pulse width (e.g., 521, 523, and 525 are equal), but each T off are progressively larger (e.g., 534 is larger than 532, which is larger than 530). off The second T off 532 is the first T off 530 and the first pulse width 521. off 534 is the first T off 530, the first pulse width 521, and the second T off 532 and the second pulse width 523.

[0040] 6A illustrates a pulsed voltage bias scheme using a waveform 600, in accordance with certain embodiments of the present disclosure. As shown, waveform 600 includes a plurality of pulses 610. The plurality of pulses 610 includes a total pulse width 612. Within the plurality of pulses 610, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 620 having a first pulse width 621, a second signal 622 having a second pulse width 623, and a third signal 624 having a third pulse width 625. Each signal is a T off For example, for the first signal 620, the first T off 630, and for the second signal 622, a second T off 632, and a third T for the third signal 634. off 634, etc. Furthermore, each signal has its own respective amplitude, for example, first amplitude 640, second amplitude 642, and third amplitude 644, etc.

[0041] 6A, each of the MOSFETs is sequentially gated on and then gated off, with each MOSFET providing a different voltage with the same pulse width. This results in a first signal 620, a second signal 622, and a third signal 624 having the same pulse width (e.g., 621, 623, and 625 are equal), but each T off are progressively larger (e.g., 634 is larger than 632, which is larger than 630), and in this embodiment, each amplitude is progressively smaller (e.g., 640 is larger than 642, which is larger than 644). Each successive Toff is also larger than the previous pulse width. For example, the second T off 632 is the first T off 630 and the first pulse width 621. off 634 is the first T off 630, the first pulse width 621, and the second T off 632 and the second pulse width 623.

[0042] 6B illustrates a pulsed voltage bias scheme using a waveform 650, in accordance with certain embodiments of the present disclosure. As shown, waveform 650 includes a plurality of pulses 660. The plurality of pulses 660 includes a total pulse width 662. Within the plurality of pulses 660, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 670 having a first pulse width 671, a second signal 672 having a second pulse width 673, and a third signal 674 having a third pulse width 675. Each signal is a T off For example, for the first signal 670, the first T off 680, and for the second signal 672, a second T off 682, and a third T for the third signal 684. off 684, etc. Furthermore, each signal has its own respective amplitude, for example, first amplitude 690, second amplitude 692, and third amplitude 694, etc.

[0043] 6B, each of the MOSFETs is sequentially gated on and then gated off, with each MOSFET providing a different voltage with a different pulse width. This results in a first signal 670, a second signal 672, and a third signal 674 having different pulse widths (e.g., 671, 673, and 675 are not equal), and each T off are progressively larger (e.g., 684 is larger than 682, which is larger than 680), and in this embodiment, each amplitude is progressively smaller (e.g., 690 is larger than 692, which is larger than 694). off The second T off 682 is the first T off 680 and the first pulse width 671. off 684 is the first T off 680, the first pulse width 671, and the second T off 682 and the second pulse width 673.

[0044] 7 illustrates a pulsed voltage bias scheme using a waveform 700, in accordance with certain embodiments of the present disclosure. As shown, waveform 700 includes a plurality of pulses 710. Each of the plurality of pulses 710 includes a total pulse width 712. Within the plurality of pulses 710, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 720 having a first pulse width 721 (e.g., the first MOSFET is gated ON for the duration of the pulse) that may be equal to the total pulse width 712, a second signal 722 having a second pulse width 723, and a third signal 724 having a third pulse width 725. As shown, the second pulse width 723 and the third pulse width 725 may be equal. Each signal is a T off For example, for the first signal 720, the first T off 730, and for the second signal 722, a second T off 732, and for the third signal 724, a third T off 734, etc. Furthermore, each signal has its own respective amplitude, for example, first amplitude 740, second amplitude 742, and third amplitude 744, etc.

[0045] In FIG. 7 , the first MOSFET is gated on before the second and third MOSFETs. As shown, the first MOSFET is gated on at the beginning of the pulse. The second and third MOSFETs are gated on simultaneously after the first MOSFET and then gated off before the first MOSFET, so that their total pulse widths 723, 725 are within the first pulse width 721 of the first signal 720. In this embodiment, while the second and third MOSFETs are gated on, the first amplitude 740, the second amplitude 742, and the third amplitude 744 generate an output signal 726 having an amplitude 746 equal to the sum of the first amplitude 740, the second amplitude 742, and the third amplitude 744. In this embodiment, the second pulse width 723 and the third pulse width 725 are equal to their respective T off 732, T off 734 is the first T offEqual to 730 and the first T off As a result, it is larger than 730 and overlaps.

[0046] 8A illustrates a pulsed voltage bias scheme using a waveform 800, in accordance with certain embodiments of the present disclosure. As shown, waveform 800 includes a plurality of pulses 810. The plurality of pulses 810 includes a total pulse width 812. Within the plurality of pulses 810, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 820 having a first pulse width 821, a second signal 822 having a second pulse width 823, and a third signal 824 having a third pulse width 825. Each signal has a T off For example, for the first signal 820, the first T off 830, and for the second signal 822, a second T off 832, and for the third signal 824, a third T off 834, etc. Furthermore, each signal has its own respective amplitude, for example, first amplitude 840, second amplitude 842, and third amplitude 844, etc.

[0047] In Figure 8A, each of the MOSFETs is gated on sequentially and then gated off simultaneously at the end of the pulse. As shown, the first signal 820, the second signal 822, and the third signal 824 have different pulse widths (e.g., 821, 823, and 825 are not equal). off becomes gradually larger (e.g., 834 is larger than 832, which is larger than 830), and in this embodiment, the output voltage swing (e.g., the combination of 840, 842, and 844) increases in a step-like manner as the second and third MOSFETs are gated on. offWhen the second MOSFET is gated on after 832, the first signal 820 and the second signal 822 combine to produce a first output voltage signal 826. The first output voltage signal 826 has an amplitude 843 equal to the sum of the first amplitude 840 and the second amplitude 842. Similarly, when the third MOSFET is gated on, the first signal 820, the second signal 822, and the third signal 824 combine to produce a second output voltage signal 828 having an amplitude 845 equal to the sum of the first amplitude 840, the second amplitude 842, and the third amplitude 844.

[0048] 8B illustrates a pulsed voltage bias scheme using a waveform 850, in accordance with certain embodiments of the present disclosure. As shown, waveform 850 includes a plurality of pulses 860. The plurality of pulses 860 includes a total pulse width 862. Within the plurality of pulses 860, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal 870 having a first pulse width 871, a second signal 872 having a second pulse width 873, and a third signal 874 having a third pulse width 875. Each signal is a T off For example, for the first signal 870, the first T off 880, and for the second signal 872, a second T off 882, and a third T for the third signal 884. off 884, etc. Furthermore, each signal has its own respective amplitude, for example, first amplitude 890, second amplitude 892, and third amplitude 894, etc.

[0049] 8B, each MOSFET is gated on simultaneously and then sequentially gated off. In this embodiment, first signal 870, second signal 872, and third signal 874 have different pulse widths (e.g., 871, 873, and 875 are not equal), and in this embodiment, the output voltage amplitude (e.g., the combination of 890, 892, and 894) gradually decreases. For example, all three MOSFETs are gated on at the beginning of pulse generation, and first signal 870, second signal 872, and third signal 874 combine to generate first output voltage signal 878. The first output voltage signal has an amplitude 895 equal to the sum of first amplitude 890, second amplitude 892, and third amplitude 894. Because the first output voltage signal is a combination of all three signals 870, 872, and 873, the pulse width of the first output voltage signal is equal to the shortest pulse width of the three signals (e.g., third pulse width 875). When the third MOSFET is gated off, the combination of the first signal 870 and the second signal 874 generates a second output voltage signal 876. The second output voltage signal has an amplitude 893 equal to the sum of the first amplitude 890 and the second amplitude 892. Because the second output voltage 876 is a combination of the first signal 870 and the second signal 872, the second output voltage 876 has a pulse width equal to the shortest pulse width between the first signal 870 and the second signal 872 (e.g., second pulse width 873).

[0050] 9 is a process flow diagram illustrating an etching method 900 using a pulsed waveform. In step 910, a plasma 101 is generated in the chamber body 124. In step 920, a pulsed direct current (DC) voltage 153 is applied to the plasma 101 using a bias electrode 104 that is capacitively coupled to the plasma 101 through a dielectric layer 105B.

[0051] Applying the pulsed DC voltage in step 920 includes using a DC voltage source (e.g., DC voltage source 210) connected via its positive terminal to a first capacitor (e.g., first capacitor 220) and further connected to a first diode (e.g., first diode 230), the positive terminal of the DC voltage source (e.g., DC voltage source 210) further connected to a first resistor (e.g., first resistor 240), a first MOSFET (e.g., first MOSFET 250), and a first blocking diode (e.g., first blocking diode 270). A second capacitor (e.g., second capacitor 222) may be connected in series between the first diode (e.g., first diode 230) and ground (e.g., ground 228). The DC voltage source (e.g., DC voltage source 210) may also be coupled to a second diode (e.g., second diode 232) connected in series between a second capacitor (e.g., second capacitor 222) and ground (e.g., ground 228). A second resistor (e.g., second resistor 242) may be connected to a common point between the first diode (e.g., first diode 230) and the second capacitor (e.g., second capacitor 222). A second MOSFET (e.g., second MOSFET 252) may be connected in series with the second resistor (e.g., second resistor 242), a second gate voltage source 262 connected to a gate terminal of the second MOSFET (e.g., second MOSFET 252), and a second blocking diode (e.g., second blocking diode 272) connected to a source terminal (e.g., 253) of the second MOSFET (e.g., second MOSFET 252). Furthermore, a third resistor (e.g., third resistor 244) may be connected between the second diode (e.g., second diode 232) and the third capacitor (e.g., third capacitor 224) and to the common point of the second diode (e.g., second diode 232) and the third capacitor (e.g., third capacitor 224).A third MOSFET (e.g., third MOSFET 254), a third gate voltage source (e.g., third gate voltage source 264), and a third blocking diode (e.g., third blocking diode 274) may also be connected in series with a third resistor (e.g., third resistor 244), where the cathode of the third blocking diode (e.g., third blocking diode 274) may be connected to a bias electrode (e.g., bias electrode 104). When all MOSFETs are gated ON simultaneously and the widths of the gating signals are the same, the full supply voltage will be applied to the load.

[0052] In step 920, applying a pulsed DC voltage source (e.g., DC voltage source 210) includes switching on a first MOSFET (e.g., first MOSFET 250) for a first time period (e.g., first time period 620), switching on a second MOSFET (e.g., second MOSFET 252) for a second time period (e.g., second time period 622), and switching on a third MOSFET (e.g., third MOSFET 254) for a third time period (e.g., third time period 624). In some embodiments, the first time period (e.g., first time period 420), the second time period (e.g., second time period 622), the third time period (e.g., third time period 624), or combinations thereof may overlap. Alternatively, the first period (e.g., first period 620), the second period (e.g., second period 422), and the third period (e.g., third period 624) may not overlap. In step 920, the first gate voltage source (e.g., first gate voltage source 260) applies a first T off (For example, the first Toff 630), and a second gate voltage source (e.g., second gate voltage source 262) can provide a second T off (e.g., the second T off 632), and a third gate voltage source (e.g., third gate voltage source 264) can provide a third T off (e.g., the third T off634). In step 920, the first MOSFET (e.g., first MOSFET 250) may receive a first gating signal from a first gate voltage source (e.g., first gate voltage source 260), where the first gating signal has a first pulse width (e.g., first pulse width 620). Further, the second MOSFET (e.g., second MOSFET 252) may receive a second gating signal from a second gate voltage source (e.g., second gate voltage source 262), where the second gating signal has a second pulse width (e.g., second pulse width 622). Further, the third MOSFET (e.g., third MOSFET 254) may receive a third gating signal from a third gate voltage source (e.g., third gate voltage source 264), where the third gating signal has a third pulse width (e.g., third pulse width 624). In some embodiments, the first pulse width (e.g., first pulse width 620), the second pulse width (e.g., second pulse width 622), and the third pulse width (e.g., third pulse width 624) are different. The memory 134, CPU 133, and support circuits 135 of the system controller 126 can perform the method 900 in one embodiment of the present disclosure. In step 930, the substrate 103 in the chamber body 124 is etched using the pulsed DC voltage 153 applied to the plasma 101.

[0053] As used herein, the term "coupled" refers to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B physically contacts object C, objects A and C may be considered coupled to each other even though they are not in direct physical contact. For example, a first object may be coupled to a second object even though the first object is not in direct physical contact with the second object.

[0054] While the foregoing specification is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is defined by the claims that follow.

Claims

1. 1. A system for reactive ion etching, comprising: a chamber body; a substrate support within the chamber body; a bias electrode within the substrate support; a bias voltage source configured to supply a pulsed bias voltage to the bias electrode; wherein the bias voltage source comprises: a direct current (DC) voltage source; a first capacitor connected to the direct current (DC) voltage source; ground, a first diode connected in series between the first capacitor and ground; a first resistor connected to the direct current (DC) voltage source; a first metal oxide semiconductor field effect transistor connected in series with the first resistor; a first gate voltage source connected to the gate of the first metal oxide semiconductor field effect transistor; a first blocking diode connected to the source of the first metal oxide semiconductor field effect transistor; a second capacitor connected in series between the first diode and ground; a second diode connected in series between the second capacitor and ground; a second resistor connected between the first diode and the second capacitor; a second metal oxide semiconductor field effect transistor connected in series with the second resistor; a second gate voltage source connected to the gate of the second metal oxide semiconductor field effect transistor; and a second blocking diode connected to the source of the second first metal oxide semiconductor field effect transistor; 1. A system for reactive ion etching, comprising:

2. The system of claim 1 , wherein the bias voltage source further comprises a third capacitor connected in series between the second diode and ground.

3. 3. The system of claim 2, wherein the bias voltage source further comprises: a third resistor connected in parallel with the third capacitor; a third metal oxide semiconductor field effect transistor connected in series with the third resistor; a third gate voltage source connected to a gate terminal of the third metal oxide semiconductor field effect transistor; and a third blocking diode connected to a source terminal of the third metal oxide semiconductor field effect transistor.

4. The system of claim 1 , wherein the bias electrode is electrically coupled to the second blocking diode of the bias voltage source.

5. 3. The system of claim 2, wherein an anode of the first blocking diode is connected to the source of the first metal oxide semiconductor field effect transistor.

6. 4. The system of claim 3, wherein the cathode of the first blocking diode is connected to the cathode of the second blocking diode.

7. 7. The system of claim 6, wherein a cathode of the third blocking diode is connected to the cathode of the first blocking diode and to the cathode of the second blocking diode.

8. The system of claim 7 , wherein the cathode of the third blocking diode, the cathode of the second blocking diode, and the cathode of the third blocking diode are connected to the bias electrode.

9. 10. The system of claim 1, further comprising a controller configured to cause the bias voltage source to deliver pulses to the bias electrode, the pulses comprising a plurality of signals, the plurality of signals comprising different pulse widths or different amplitudes.

10. The system of claim 9 , wherein the plurality of signals further include different off times.

11. 1. A method of etching using a pulse waveform, comprising: generating a plasma in the chamber body; applying a pulsed direct current (DC) voltage to the plasma using a bias electrode capacitively coupled to the plasma through a dielectric layer, the pulsed DC voltage comprising a plurality of pulses, each of the plurality of pulses further comprising a plurality of signals, each of the plurality of signals having an off time, a pulse width, and an amplitude; Etching a substrate in the chamber body using the pulsed direct current (DC) voltage applied to the plasma; A method comprising:

12. The method of claim 11 , wherein two or more of each of the off-times, the pulse widths, and the amplitudes of the plurality of signals are different.

13. 13. The method of claim 12, wherein applying the pulsed direct current (DC) voltage includes using a DC voltage source connected to a first capacitor and a first diode, the direct current (DC) voltage source further connected in parallel to a first resistor, a first metal oxide semiconductor field effect transistor, a first gate voltage source connected to a gate of the first metal oxide semiconductor field effect transistor, and a first blocking diode.

14. 14. The method of claim 13, wherein the direct current (DC) voltage source is connected in series to a second capacitor connected in series between the first diode and ground, a second diode connected in series between the second capacitor and ground, a second resistor connected in parallel with the second capacitor, a second metal oxide semiconductor field effect transistor connected in series with the second resistor, a second gate voltage source connected to a gate terminal of the second metal oxide semiconductor field effect transistor, and a second blocking diode connected to a source terminal of the second metal oxide semiconductor field effect transistor.

15. 15. The method of claim 14, wherein applying a pulsed direct current (DC) voltage source further comprises switching on the first metal oxide semiconductor field effect transistor for a first period of time and switching on the second metal oxide semiconductor field effect transistor for a second period of time.

16. The method of claim 15 , wherein the first time period and the second time period do not overlap.

17. 15. The method of claim 14, wherein the first gate voltage source comprises a first off-time and the second gate voltage source comprises a second off-time.

18. 15. The method of claim 14, wherein the first metal-oxide-semiconductor field-effect transistor receives a first gating signal having a first pulse width from the first gate voltage source, and the second metal-oxide-semiconductor field-effect transistor receives a second gating signal having a second pulse width from the second gate voltage source.

19. 1. A pulsed signal source apparatus for etching, comprising: A controller; a bias electrode; a bias voltage source configured to supply a pulsed bias voltage to the bias electrode; wherein the bias voltage source comprises: a direct current (DC) voltage source; a first capacitor connected in series with the direct current (DC) voltage source; a first diode connected to the first capacitor; a ground connected in series with the first diode; a first resistor connected in parallel with the first capacitor; a first metal oxide semiconductor field effect transistor connected in series with the first resistor; a first gate voltage source connected to a gate terminal of the first metal oxide semiconductor field effect transistor; a second capacitor connected in series between the first diode and ground; a second diode connected in series between the second capacitor and ground; a second resistor connected in parallel with the second capacitor; a second metal oxide semiconductor field effect transistor connected in series with the second resistor; a second gate voltage source connected to the gate terminal of the second metal oxide semiconductor field effect transistor; a second blocking diode connected to the source terminal of the second metal-oxide-semiconductor field effect transistor; a third capacitor connected in series between the second diode and ground; a third resistor connected in parallel with the third capacitor; a third metal oxide semiconductor field effect transistor connected in series with the third resistor; a third gate voltage source connected to the gate terminal of the third metal-oxide-semiconductor field-effect transistor; and a third blocking diode connected to the source terminal of the third metal oxide semiconductor field effect transistor; A pulsed signal source apparatus for etching, comprising:

20. 20. The pulse signal source apparatus of claim 19, wherein the controller causes the first metal oxide semiconductor field effect transistor to receive a first gating signal having a first pulse width from the first gate voltage source, the controller causes the second metal oxide semiconductor field effect transistor to receive a second gating signal having a second pulse width from the second gate voltage source, and the controller causes the third metal oxide semiconductor field effect transistor to receive a third gating signal having a third pulse width from the third gate voltage source, the first pulse width, the second pulse width, and the third pulse width being different.

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