Polarization locker and related methods for fiber splices

Abstract

A photonic interconnect system is described. A fiber connects a first photonic integrated circuit (PIC) to a second PIC. The fiber is non-polarization-maintaining, which results in polarization drift. As a result, the polarization appearing at the output of the fiber may differ from the polarization launched at the input of the fiber. To reduce the adverse effects of polarization drift, each PIC may be equipped with a polarization locker. A control circuit is configured to control the first and second polarization lockers by setting one of the first and second polarization lockers in an active configuration and setting the other of the first and second polarization lockers in a passive configuration. Controlling the polarization lockers in this manner prevents polarization mismatch without having to expend additional resources that would otherwise be required to communicate a phase shift across the fiber.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to polarization lockers for fiber splices and related methods. [Background technology]

[0002] Computer systems include random access memory (RAM) for storing data and machine code. RAM is typically volatile memory, meaning that stored information is lost when power is removed. In modern implementations, the memory takes the form of integrated circuits. Each integrated circuit contains multiple memory cells. To allow access to the stored data and machine code, the memory is placed in electrical communication with the processor. Typically, these electrical communications are implemented as metal traces formed on a substrate on which the memory and processor are placed. Summary of the Invention

[0003] Some embodiments relate to a photonic interconnection system comprising: a first photonic integrated circuit (PIC) comprising a first polarization locker; a second PIC comprising a second polarization locker; an optical fiber configured to bidirectionally optically couple the first PIC and the second PIC to each other; and a control circuit configured to control the first polarization locker and the second polarization locker, wherein controlling the first polarization locker and the second polarization locker comprises setting one of the first polarization locker and the second polarization locker to an active configuration and setting the other of the first polarization locker and the second polarization locker to a passive configuration.

[0004] Some embodiments relate to a method for photonic interconnection of photonic integrated circuits (PICs), the method including transmitting an optical signal between a first PIC having a first polarization locker and a second PIC having a second polarization locker through an optical fiber, and controlling the first polarization locker and the second polarization locker using a control circuit by setting one of the first polarization locker and the second polarization locker to an active configuration and setting the other of the first polarization locker and the second polarization locker to a passive configuration.

[0005] Various aspects and embodiments are described with reference to the following figures. It should be understood that the figures are not necessarily drawn to scale. Items that appear in more than one figure are designated by the same reference numeral in all figures in which they appear. [Brief explanation of the drawings]

[0006] [Figure 1] 1 illustrates a photonic interconnect system according to some embodiments. [Figure 2] 1 illustrates a photonic integrated circuit (PIC) of a photonic interconnect system, according to some embodiments. [Figure 3] 1 illustrates an application specific integrated circuit (ASIC) with an Advanced Interface Bus (AIB) interface implementing a photonic interconnect system, according to some embodiments. [Figure 4] 1 illustrates inter-ASIC connections using an AIB interface and a photonic interconnect system according to some embodiments. [Figure 5] 1 illustrates a photonic interposer hosting multiple ASICs communicating with each other via an AIB interface, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0007] The inventors recognize and understand several challenges that limit the scalability of modern digital computing. First, current designs are power-limited. Trends in modern computing lead to ever-increasing power consumption, which limits its scalability. Additionally, the highly power-hungry nature of modern chips results in high-temperature hot spots, often exceeding 100°C. High temperatures significantly limit computer performance. Second, modern computing architectures are bandwidth-limited. These architectures rely on multiple memory chips to provide the hundreds of gigabytes or terabytes of capacity required by modern applications. Unfortunately, providing connectivity between several memory chips is challenging. The physical space available on a board or rack to accommodate interconnects is limited, thus limiting overall bandwidth. Additionally, maintaining coherence and consistency across several memory chips (e.g., memory-to-memory and processor-to-memory) is difficult to achieve. Some architectures rely on Peripheral Component Interconnect (PCI), Compute Express Link (CXL), or Ethernet for chip-to-chip communication. However, these interfaces involve board-level or rack-level communication, which increases power usage and reduces bandwidth. Wafer-scale telecommunications has also been considered, but this approach suffers from reliability issues and power inefficiencies.

[0008] The inventors have developed a photonic interposer that enables low-power, high-bandwidth chip-to-chip (e.g., board-level and / or rack-level) and intra-chip communication. The photonic interposer can be used to interconnect application-specific integrated circuits (ASICs) in ways that would otherwise be impractical (e.g., too costly or energy-inefficient) using conventional interfaces. Conventional electronic interposers are designed for high bandwidth between electronic ASICs located in relatively close proximity, e.g., a few millimeters apart. The relatively close proximity imposed by these conventional die-to-die (D2D) interfaces imposes practical limitations on the types of computing architectures achievable using these interfaces. The maximum die-to-die distance imposed by these interfaces, at most a few millimeters, guarantees high bandwidth and reliability, given the constraints of electrical interconnects. The photonic interposer can extend the applicability of conventional D2D interfaces to ASIC-to-ASIC distances greater than those possible with conventional electronic interposers.

[0009] Some architectures include several interposers connected to each other via optical fiber, with each interposer capable of hosting various types of ASICs (e.g., controllers, processors, memory, etc.). Multi-interposer architectures enable computer networks that exceed (in terms of computational power) what can be achieved with a single interposer. However, the inventors recognize and understand the challenges associated with implementing multi-interposer architectures. The optical fibers used to facilitate optical connections between interposers are non-polarization-maintaining and generate polarization drift. Optical fibers connected to photonic interposers can experience different stresses, bends, and twists as the optical signal propagates through the fiber. The stresses and bends can change over time as environmental conditions change. The longer the fiber, the greater the stresses and bends can be or the more susceptible it can be to environmental conditions. As the optical signal propagates through the fiber, stresses, bends, twists, and imperfections in the optical fiber can change the polarization of the optical signal. As a result, the polarization appearing at the output of the fiber may differ from the polarization launched at the input of the fiber. Additionally, the polarization may be unpredictable. This presents a challenge in that different polarizations behave differently when propagating within the photonic integrated substrate of an interposer of the type described herein, as described below.

[0010] An optical signal can be viewed as a superposition of multiple polarization modes. For example, in a single-mode optical fiber, the TEM 00A mode may have two orthogonal polarization components. Coupling a signal linearly polarized in one axis into a single-mode fiber does not guarantee that the polarization will be maintained as the signal travels along the fiber. Similarly, optical signals propagating inside photonic integrated circuits can also be viewed as a superposition of multiple polarization modes. For example, silicon-based optical waveguides can exhibit transverse electric (TE) modes (where the electric field is substantially perpendicular to the direction of propagation) and transverse magnetic (TM) modes (where the magnetic field is substantially perpendicular to the direction of propagation).

[0011] When an optical signal is coupled from an optical fiber into an integrated optical waveguide (e.g., a waveguide in a photonic interposer), the fiber's non-polarization-maintaining properties result in the signal in the waveguide being a combination of TE and TM modes with unpredictable ratios. This can adversely affect the performance of the PIC, since TM modes generally have substantially higher loss than TE modes. This is due to the fact that TE modes are more spatially confined than TM modes, resulting in less optical loss due to sidewall scattering. As a result, more optical loss occurs than would occur if only TE modes were excited. In addition, because the ratio between the power coupled into TE and TM modes is unpredictable, optical loss is also unpredictable, making it more difficult to allocate a reasonable amount of power to meet the system's power budget. Finally, the presence of TM modes can result in undesirable resonance peaks. Resonant structures (e.g., microrings) are often used in photonic integrated circuits as building blocks for forming modulators, filters, and other types of devices. These devices are typically designed to operate in TE modes and avoid TM modes. This is because the low-loss characteristics of TE modes result in narrower resonance peaks than would be possible with TM modes. Narrower resonance peaks are generally preferable in that they allow for finer spectral resolution (e.g., finer wavelength division multiplexing or WDM). The occurrence of TM resonances can adversely affect the ability of the resonant structure to perform fine spectral manipulation.

[0012] The present inventors have developed photonic interconnect systems and related methods that minimize power loss and other undesirable effects caused by polarization drift. The photonic interconnect systems and related methods described herein include polarization locking, a technique aimed at converting the TM component of an input optical signal to TE, regardless of the TE / TM composition of that input signal. For example, an input signal that has 50% power in TE mode and 50% power in TM mode as a result of polarization drift, when polarization locked, is converted to an input signal with 100% power in the TE mode (or as close to 100% as possible, depending on other system constraints).

[0013] The polarization locker may include, among other components, a polarization splitter and a mode converter. The polarization splitter may split the input optical signal into a TE mode and a TM mode. The TM mode may follow a first path, and the TE mode may follow a second path. The TM mode may be converted to a converted TE mode within the mode converter along the first path. In some embodiments, the TE mode may be delayed by a delay unit along the second path of the polarization locker to maintain temporal alignment between the TE mode and the converted TE mode.

[0014] In some embodiments, the polarization locker may include a phase shifter along one or both of the first and second paths. Controlling the polarization locker may include controlling one or more phase shifters of the polarization locker to align the TE mode and the converted TE mode to the same phase. The phase shifters may utilize several different physical properties: thermo-optics, microelectromechanical / nanoelectromechanical, carrier effects using pn or pn junctions, and chi(2) or chi(3) in media with optical nonlinearity. The polarization locker may further include an optical coupler that couples the TE mode and the converted TE mode and provides an output optical signal. The control circuit may control the phase shifters to maximize the output optical signal.

[0015] In some embodiments, the PIC receiving the optical signal may include a receiver to receive the output optical signal. The output optical signal may generate a photocurrent at the receiver. Maximizing the output light may include maximizing the photocurrent at the receiver. In some embodiments, the receiver may provide a feedback signal to a control circuit indicative of the photocurrent at the receiver. The control circuit may adjust the phase shifter in response to the feedback signal until the photocurrent at the receiver is maximized.

[0016] In another embodiment, if a PIC receiving an optical signal aims to maximize the optical signal of one polarization, e.g., the TE mode, the PIC may use a monitor photodetector on the optical signal to measure a signal representing an orthogonal polarization, e.g., the rotated TM mode power of a polarization splitter rotator. The PIC may use this signal as a feedback signal to minimize the TM mode power and maximize the TE mode power.

[0017] The present inventors further recognize and understand the challenges in implementing a photonic interconnect system for applications requiring bidirectional signal transmission between two PICs. In these applications, a fiber attached to two PICs can support signal propagation in either direction, depending on which PIC acts as a transmitter and which PIC acts as a receiver. Designing an optical network such that a fiber can support propagation in either direction is desirable in terms of reducing the total number of fibers in the network. Given the non-polarization-maintaining properties of fiber, polarization locking must be performed at both ends of the fiber.

[0018] In some embodiments, the two PICs may each include an edge coupler or other suitable chip-to-fiber coupler (e.g., a vertical grating coupler, an evanescent coupler, etc.) to connect each PIC to the fiber. The edge coupler may have unbalanced loss. For example, TM mode has higher loss than TE mode. Furthermore, long optical fibers also have polarization-dependent loss, with some polarization modes having higher loss than others. It may be advantageous to use two polarization lockers, one on the transmitter chip and one on the receiver chip. The transmitter chip may ensure that the polarization of the light, after accounting for the edge coupler and travel along the long optical fiber, is optimized to minimize loss. The receiver chip may then convert the polarization to a guided polarization mode within its chip. In some embodiments, the guided polarization mode may be TE mode.

[0019] However, the inventors realize that simultaneously controlling both polarization lockers at opposite ends of the fiber can lead to mismatches between the polarization state of one PIC and the polarization state of the other PIC, which can lead to additional optical power losses. These mismatches can be limited by allowing each polarization controller to communicate its polarization state to the other controller so that the polarization lockers can be intentionally aligned with each other. However, allowing the polarization lockers to do this would result in a significant expenditure of computational resources.

[0020] To reduce polarization mismatch without having to communicate the polarization state across the entire fiber, we propose setting the polarization locker at one end of the fiber in an active configuration and the polarization locker at the other end of the fiber in a passive configuration. For example, only the polarization locker at the receiving end of the fiber may be activated, while the polarization locker at the transmitting end may remain passive.

[0021] In some embodiments, the photonic interconnect system may enable wavelength division multiplexed bidirectional communication. In some embodiments, both communication chips may simultaneously transmit and receive data at different wavelengths using the same output arm of the polarization locker. One chip may transmit and receive data at wavelength set A(λ1, λ3, ..., λ 2N+1 ) to transmit data to the other communications chip. The other chip can use wavelength set B(λ, λ, . . , λ) 2N ) may be used to transmit data to the former chip. A polarization locker may be used to ensure that data encoded in the TE mode of one chip will arrive from that chip to the TE mode of the other chip. Wavelength sets A and B may be even and odd wavelengths, with adjacent wavelengths sufficiently separated by 100 GHz, 200 GHz, or 400 GHz. In other embodiments, wavelength set A may be a first N wavelengths, and wavelength set B may be a second N wavelengths. In some embodiments, wavelength multiplexing may be performed with the aid of a wavelength interleaver, which may be a series of asymmetric Mach-Zehnder interferometers (MZIs), ring-assisted MZIs, or wavelength resonant structures such as rings, disks, or resonators.

[0022] In some embodiments, an active configuration involves controlling the polarization locker as described herein to increase (e.g., maximize) the output optical signal. This may be done using a feedback loop. In contrast, a passive configuration may pass the optical signal as if the polarization locker were a passive waveguide or optical fiber. For example, the phase shifters of the polarization locker may not be driven when the polarization locker is set in the passive configuration, or may be driven but not driven to increase (e.g., maximize) the output power.

[0023] While polarization-maintaining fibers exist and are commercially available, it should be noted that these types of fibers are significantly more expensive than their non-polarization-maintaining counterparts. The increased cost of polarization-maintaining fibers is primarily due to the additional manufacturing processes and materials required to create fibers capable of maintaining the polarization state of light. The production of polarization-maintaining fibers involves precise design and manufacturing techniques to induce birefringence, which is essential for maintaining polarization. These techniques can include non-circular core designs, stress-inducing elements, and specialized coatings. Furthermore, quality control and testing processes for polarization-maintaining fibers have become more rigorous to ensure they meet polarization-maintaining specifications.

[0024] The inventors recognize and understand that it is more economical to handle polarization on-chip using the techniques described herein than to use polarization-maintaining fiber. FIG. 1 illustrates a photonic interconnect system according to some embodiments. The photonic interconnect system may include a first PIC 100 and a second PIC 101. The PIC 100 may include a transmitter 110, a receiver 120, and a polarization locker 130. In some embodiments, the PIC 100 may include an edge coupler 140 for coupling the PIC 100 to an optical fiber 160. The PIC 101 may include a transmitter 111, a receiver 121, and a polarization locker 131. In some embodiments, the PIC 101 may include an edge coupler 141 for coupling the PIC 101 to the optical fiber 160. The optical fiber may include two channels, one configured to support propagation of an optical signal in a first direction and the other configured to support propagation of an optical signal in a second direction opposite the first direction. In some embodiments, the optical fiber 160 may be a single-mode optical fiber. In some embodiments, the optical fiber 160 may be replaced with an optical waveguide or other suitable component. In some embodiments, the optical fiber 160 may be coupled to the PIC100, PIC101 through other suitable chip-to-fiber couplers (eg, vertical grating couplers, evanescent couplers, etc.) rather than through edge couplers 140, 141.

[0025] The photonic interconnect system may further include control circuitry. The control circuitry may include controllers 150, 151 coupled to their respective PICs, as shown in FIG. 1 . Note that the controllers 150, 151 may be part of the same device (e.g., a common ASIC) or may be separate devices. The controller 150 may be configured to control the polarization locker 130. The controller 150 may set the polarization locker 130 to a passive configuration when the optical signal is transmitted in a first direction from the transmitter 110 to the receiver 121. The controller 150 may further set the polarization locker 130 to an active configuration when the optical signal is transmitted in a second direction from the transmitter 111 to the receiver 120. The controller 150 may further be configured to receive a feedback signal from the receiver 120 to adjust the control of the polarization locker 130 to increase (e.g., maximize) the output optical signal to the receiver 120.

[0026] Similarly, controller 151 may be configured to control polarization locker 131. Controller 151 may set polarization locker 131 in an active configuration when PIC 101 operates as a receiver and in a passive configuration when PIC 101 operates as a transmitter. With respect to controller 150, controller 151 may be further configured to receive a feedback signal from receiver 121 to adjust the control of polarization locker 131 to maximize the output optical signal to receiver 121. In some embodiments, the feedback signal received from receiver 120, 121 may indicate the polarization of the signal coupled from the fiber to that PIC. For example, an RX generating a higher photocurrent may indicate that the signal has a larger TE component (compared to the TM component) than an RX generating a lower photocurrent.

[0027] The inventors have recognized that by configuring one of the polarization lockers 130 and 131 in an active configuration while simultaneously configuring the other of the polarization lockers 130 and 131 in a passive configuration, control of the photonic interconnect system can be simplified in that it avoids the need to communicate the phase shift applied to each polarization locker to the other polarization locker. Centralizing control to only one of the polarization lockers 130, 131 is advantageous in that it prevents mismatches between the polarization lockers without the need to expend additional resources that would otherwise be required to communicate the phase shift throughout the fiber. Activating both polarization lockers simultaneously requires the polarization lockers to be coordinated with each other, which would otherwise result in power loss. Power loss due to polarization mismatches between the polarization lockers can be prevented by leaving one polarization locker in a passive configuration while activating the other. In some embodiments, only the polarization locker on the receiving end of the fiber is activated.

[0028] FIG. 2 illustrates the PIC 101 in more detail, according to some embodiments. Although not shown in FIG. 2, the PIC 100 may be similarly arranged. FIG. 2 illustrates the polarization locker 131, which includes a polarization splitter 200, a TM-TE converter 210, a delay unit 211, phase shifters 220 and 221, and an optical coupler 230. The polarization splitter 200 splits an optical input signal received from the fiber 160 into a first mode and a second mode, e.g., a TE mode and a TM mode. The first mode may pass through a first arm of the polarization locker 131 to the delay unit 211, and the second mode may pass through a second arm of the polarization locker 131 to the mode converter 210. The mode converter 210 converts the TM mode of the optical signal to the TM mode. The delay unit 211 may be configured to time-align the TE mode with the converted TE mode by matching the delay introduced by the converter 210.

[0029] In some embodiments, both the first arm and the second arm of the polarization locker may include a phase shifter 220 or 221. It should be understood that in some embodiments, only one of the phase shifters 220 and 221 may be present. The phase shifters 220 and 221 may be configured to adjust the phase of the first mode and the phase of the converted first mode to match each other. The optical coupler 230 may be configured to couple the first mode and the converted first mode to generate an output optical signal including a combination of the first mode and the converted first mode. In some embodiments, the optical coupler 230 may be a directional coupler or a MZI. In some embodiments, the MZI may utilize pn or pn junctions, thermo-optical heaters, MEMS / NOEMS, or a combination of these phase shifter technologies to handle different bandwidths of the polarization scrambling aggressor. For example, faster phase shifters, such as pn junctions or pn junctions, can be used to correct polarization scrambling that occurs up to GHz bandwidths, and slower phase shifters can be used to adjust polarization in the kHz to MHz range. In an active configuration, the controller 151 drives the phase shifters (one or both) based on a feedback signal to increase (e.g., maximize) the output power.

[0030] The receiver 121 receives the output optical signal from the polarization locker 131 and generates a photocurrent. The controller 151 may be further configured to receive a feedback signal indicative of the photocurrent (e.g., a digitized version of the photocurrent) from the receiver 121. Controlling the phase shifters 220, 221 to maximize the output signal may include adjusting the phase shifters 220, 221 in response to the feedback signal received from the receiver 121 to maximize the photocurrent.

[0031] In contrast, when the polarization locker 131 is in the passive configuration, the controller 151 does not drive either phase shifter. In other words, the phase shifters behave as passive waveguides. Alternatively, in the passive configuration, the controller 151 drives one of the phase shifters but does not drive it to increase (e.g., maximize) its output power.

[0032] It should be understood that the photonic interconnect system and associated methods described herein can be used to optically interconnect ASICs. FIG. 3 illustrates an exemplary ASIC implementing the photonic interconnect system described herein. The ASIC 300 can include multiple die-to-die (D2D) interfaces 310-313. In some embodiments, the D2D interfaces 310-313 can be AIB interfaces. In some embodiments, the D2D interfaces can be UCIe interfaces. In some embodiments, the D2D interfaces can be BoW interfaces. The D2D interfaces 310-313 can be configured to support multiple channels. Each D2D interface can be coupled to multiple photonic interconnect systems. For clarity, only the PIC 100 and optical fiber 160 are shown in FIG. 3. The PIC 100 can be implemented in the same manner as in any of the embodiments described herein. It should be understood that the ASIC 300 can be optically coupled to a second ASIC at various distances. In some embodiments, the second ASIC can be on the same chip. In other embodiments, the second ASIC may be on the same circuit board.

[0033] FIG. 4 illustrates an ASIC-to-ASIC connection using an AIB interface and a photonic interconnect system, according to some embodiments. The ASIC 300 may be coupled to an AIB 310. The AIB 310 may include multiple wires connecting to multiple SerDes. The multiple SerDes may be coupled to multiple PICs 100, each including a polarization locker 130. Each PIC 100 may further include a transmitter 110 configured to convert an electrical signal from the SerDes to an optical signal and transmit the optical signal in a first direction. Each PIC 100 may further include a receiver 120 configured to receive an optical signal from a second direction and convert the optical signal to an electrical signal. In some embodiments, the transmitter 110 may be an optical modulator, and the receiver 120 may be a photodetector.

[0034] ASIC 300 may be optically coupled to ASIC 301 by optical fiber 160. ASIC 301 may be implemented in the same manner as ASIC 300. ASIC 301 may be coupled to multiple PICs 101, each including a polarization locker 131. PIC 101 may further include a transmitter 111 configured to convert electrical signals from the multiple SerDes into optical signals and transmit the optical signals in a second direction, and a receiver 121 configured to receive the optical signals from a first direction and convert the optical signals into electrical signals. In some embodiments, transmitter 111 may be an optical modulator, and receiver 121 may be an optical detector.

[0035] Unlike conventional electronic interposer and interconnect systems, photonic interconnect systems can optically interconnect ASICs over a wide range of distances. As such, it should be understood that ASIC 300 can be optically coupled to a second ASIC at various distances. In some embodiments, the second ASIC may be on the same chip. In other embodiments, the second ASIC may be on the same circuit board. In some embodiments, the inter-ASIC distance may be greater than 2.5 cm.

[0036] FIG. 5 illustrates a photonic interposer hosting multiple ASICs implementing an AIB interface, according to some embodiments. The photonic interposer 500 hosts multiple ASICs 300-303. Each ASIC 300-303 implements multiple D2D interfaces 310. It should be understood that the photonic interconnect ASICs 300-304 may be implemented according to any of the embodiments described herein, for example, according to the embodiment shown in FIG. 4. Furthermore, it should be understood that the ASICs 300-303 may be connected to ASICs on separate photonic interposers, separate chips, separate circuit boards, or at a certain distance, e.g., greater than 2.5 cm, using the photonic interconnect system described herein.

[0037] Having thus described several aspects and embodiments of the technology of the present application, it should be understood that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described herein. Accordingly, the foregoing embodiments are presented by way of example only, and it should be understood that, within the scope of the appended claims and their equivalents, the embodiments of the present invention may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, and / or methods described herein is within the scope of the present disclosure, provided that such features, systems, articles, materials, and / or methods are not mutually inconsistent.

[0038] Also, as described, some aspects may be embodied as one or more methods. The actions performed as part of a method may be ordered in any suitable manner. Thus, embodiments may be constructed that perform actions in an order different from that described, and example embodiments may include performing some actions simultaneously, even though they are shown as sequential actions.

[0039] All definitions defined and used herein should be understood to take precedence over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0040] As used in this specification and the claims, the indefinite articles "a" and "an" should be understood to mean "at least one," unless clearly indicated to the contrary. As used in this specification and claims, the term "and / or" should be understood to mean "either or both" of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases.

[0041] As used in this specification and claims, the phrase "at least one," when referring to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed in the list of elements, or excluding any combination of elements in the list of elements. This definition also allows for elements other than those specifically identified in the list of elements to which the phrase "at least one" refers, whether related or unrelated to the specifically identified elements, may optionally be present.

[0042] The terms "approximately" and "about" can be used in some embodiments to mean within ±20% of a target value, in some embodiments within ±10% of a target value, in some embodiments within ±5% of a target value, and even in some embodiments within ±2% of a target value. The terms "approximately" and "about" can include the target value.

Claims

1. a first photonic integrated circuit (PIC) comprising a first polarization locker; a second PIC with a second polarization locker; an optical fiber configured to bidirectionally optically couple the first PIC and the second PIC to one another; a control circuit configured to control the first polarization locker and the second polarization locker, controlling the first polarization locker and the second polarization locker; a control circuit that configures one of the first polarization locker and the second polarization locker in an active configuration and the other of the first polarization locker and the second polarization locker in a passive configuration; A photonic interconnection system comprising:

2. the first polarization locker and the second polarization locker each comprise a polarization splitter, a mode converter, and a phase shifter; setting one of the first polarization locker and the second polarization locker in an active configuration; configuring each said polarization splitter to split an optical signal into a first mode and a second mode; configuring the mode converter to convert the second mode to a converted first mode; 10. The photonic interconnect system of claim 1, comprising:

3. controlling one of the first polarization locker and the second polarization locker in the active configuration controls the phase shifter to align the first mode with the converted first mode, and generates an output optical signal including a combination of the first mode and the converted first mode; The photonic interconnect system of claim 2 , comprising:

4. the first PIC and the second PIC each comprise a receiver configured to receive the output optical signal and generate a feedback signal; controlling the phase shifter to align the first mode with the converted first mode maximizes the output optical signal using the feedback signal; 4. The photonic interconnect system of claim 3, comprising:

5. the first mode is a transverse electric (TE) mode of the optical signal; the second mode is a transverse magnetic (TM) mode of the optical signal; the mode converter is a TM-TE converter configured to convert the TM mode into a converted TE mode; The photonic interconnect system of claim 3.

6. the optical fiber comprises a first channel and a second channel, the first channel configured to transmit the optical signal in a first direction, and the second channel configured to transmit the optical signal in a second direction; The photonic interconnect system of claim 1 .

7. controlling the first polarization locker and the second polarization locker includes determining whether the optical signal is propagating in the first direction or the second direction. The photonic interconnect system of claim 6.

8. the first polarization locker is set to the active configuration when the optical signal is transmitted in the first direction; the second polarization locker is set to the active configuration when the optical signal is transmitted in the second direction. The photonic interconnect system of claim 7.

9. each of the first PIC and the second PIC being coupled to a respective application specific integrated circuit (ASIC); The photonic interconnect system of claim 1 .

10. each of said respective ASICs: a die-to-die (D2D) interface comprising a plurality of wires; a plurality of SerDes coupled to the plurality of wires; a plurality of optical modulators coupled to a first subset of the plurality of SerDes; a plurality of photodetectors coupled to a second subset of the plurality of SerDes; the first PIC and the second PIC are coupled to the respective ASICs by coupling each of the first polarization locker and the second polarization locker to one of the plurality of optical modulators and one of the plurality of optical detectors on the respective ASICs; The photonic interconnect system of claim 9.

11. the D2D interface of each ASIC includes an Advanced Interface Bus (AIB) interface; The photonic interconnect system of claim 10.

12. the D2D interface of each ASIC includes a Universal Chiplet Interconnect Express (UCIe) interface; The photonic interconnect system of claim 10.

13. the distance between the D2D interfaces of the respective ASICs is greater than 2.5 cm; The photonic interconnect system of claim 10.

14. 1. A method for photonic interconnection of a photonic integrated circuit (PIC), said method comprising: transmitting an optical signal over an optical fiber between a first PIC having a first polarization locker and a second PIC having a second polarization locker; and using a control circuit to control the first polarization locker and the second polarization locker by setting one of the first polarization locker and the second polarization locker in an active configuration and setting the other of the first polarization locker and the second polarization locker in a passive configuration.

15. With the polarization locker set in the active configuration, splitting the optical signal into a first mode and a second mode using a polarization locker; converting the second mode into a converted first mode using a mode converter; using a phase shifter to match the first mode with the converted first mode; The method of claim 14 further comprising:

16. controlling the first polarization locker and the second polarization locker includes controlling the phase shifter of the polarization locker set in the active configuration to maximize an output optical signal.

16. The method of claim 15.

17. the first mode is a transverse electric (TE) mode; the second mode is a transverse magnetic (TM) mode; the mode converter is a TM-TE converter for converting the TM mode into a converted TE mode; 16. The method of claim 15.

18. controlling the phase shifter to maximize the output optical signal; measuring a receiver photocurrent caused by the output optical signal; receiving a feedback signal indicative of the photocurrent; adjusting the phase shifter using the feedback signal; 17. The method of claim 16, comprising:

19. setting one of the first polarization locker and the second polarization locker in an active configuration; determining a direction of the optical signal; setting the first polarization locker to the active configuration when the direction of the optical signal is the first direction, and setting the second polarization locker to the active configuration when the direction of the optical signal is the second direction; 15. The method of claim 14, comprising:

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