Multi-die non-blocking crossbar switch

Abstract

A non-blocking crossbar switch architecture is disclosed that avoids a problem present in prior art crossbar switches where input signals may oversubscribe the available inter-die bandwidth. The novel non-blocking crossbar switch architecture is partitioned across multiple semiconductor dies containing multiple interleaved crossbar switch segments. Only one crossbar switch segment is implemented on each semiconductor die. Multiple input ports and multiple output ports are coupled to the crossbar switch. The crossbar switch is non-blocking; that is, any one output port that is not currently receiving data can receive data from any one input port.

Description

[Technical Field]

[0001] Examples of the present disclosure relate generally to crossbar switches in packaged devices, and more particularly to multi-die non-blocking crossbar switches. [Background technology]

[0002] Crossbar switches implemented across multiple semiconductor dies within a packaged device can subvert inter-die interconnections. These crossbar switches are not slow to configure the interconnections on field-gate programmable gate arrays (FPGAs). Rather, crossbar switches support changing the connection configuration of all ports on one or more semiconductor dies, typically every few hundred megahertz (MHz) clock cycles. Conventional techniques generally split the switches among the semiconductor dies within the package. In crossbar switches that include non-blocking characteristics, received signals on each semiconductor die are broadcast to all other semiconductor dies. However, broadcasting incoming signals typically oversubscribes the available inter-die bandwidth. Summary of the Invention

[0003] These and other examples can be understood with reference to the detailed description below.

[0004] A non-blocking crossbar switch architecture is disclosed that avoids a problem present in prior art crossbar switches where input signals may oversubscribe the available inter-die bandwidth. The novel non-blocking crossbar switch architecture is partitioned across multiple semiconductor dies containing multiple interleaved crossbar switch segments. Only one crossbar switch segment is implemented on each semiconductor die. Multiple input ports and multiple output ports are coupled to the crossbar switch. The crossbar switch is non-blocking; that is, any one output port that is not currently receiving data can receive data from any one input port.

[0005] In one example, a crossbar switch system is provided that includes a plurality of semiconductor dies, one or more data interleavers coupled to the crossbar switch, one or more data deinterleavers coupled to the crossbar switch, and a plurality of interleaved crossbar switch segments. Each data interleaver of the one or more data interleavers includes a plurality of input ports. Each data deinterleaver of the one or more data deinterleavers further includes a plurality of output ports. One of the plurality of interleaved crossbar switch segments is implemented on one of the plurality of semiconductor dies. Any one of the plurality of output ports is configured to receive data from any one of the input ports.

[0006] In another example, a crossbar switch system is provided that includes one or more data deinterleavers, an integrated circuit device, and one or more data interleavers. The one or more data deinterleavers are configured to receive data from the crossbar switch. The integrated circuit device is coupled to the one or more data deinterleavers. The one or more data interleavers are coupled to the integrated circuit device. The one or more data interleavers are configured to transmit data to the crossbar switch.

[0007] In yet another example, a method for implementing a crossbar switch is provided, the method including the steps of providing one or more device packages, providing a plurality of semiconductor dies, one or more data interleavers coupled to the crossbar switch, each data interleaver of the one or more data interleavers including a plurality of input ports, one or more data deinterleavers coupled to the crossbar switch, each data deinterleaver of the one or more data deinterleavers including a plurality of output ports, and providing a plurality of interleaved crossbar switch segments, one crossbar switch segment of the plurality of interleaved crossbar switch segments implemented on one semiconductor die of the plurality of semiconductor dies, wherein no data connections are configured between the semiconductor dies, and wherein any one output port is configured to receive data from any one input port. [Brief explanation of the drawings]

[0008] In a manner in which the above-recited features may be understood in detail, a more particular description briefly summarized above may be made by reference to exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical example implementations and therefore should not be considered limiting of the scope thereof. [Figure 1] 1 illustrates an example of a two-die, two-way interleaved crossbar switch, according to one embodiment. [Figure 2] 1 illustrates an example of an agent that supports two-way data interleaving, according to one embodiment. [Figure 3] 1 illustrates an example of an agent that supports four-way data interleaving, according to one embodiment. [Figure 4]1 illustrates an example of two, two-die, four-way interleaved switches implementing a 256×256×256 non-blocking switch, according to one embodiment. [Figure 5] 1 illustrates an example of a logical wiring diagram for an agent-multi-die crossbar switch, according to one embodiment.

[0009] For ease of understanding, wherever possible, identical reference numbers have been used to indicate identical elements common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] Disclosed herein is a novel non-blocking crossbar switch system that avoids inter-die bandwidth bottlenecks and enables the implementation of large-scale non-blocking crossbar switches that exceed the throughput of prior art. Today's prior art switches typically have 128 serial transceivers, exceeding 100 Gb / s per transceiver. As described in more detail below, non-blocking crossbar switches are split across multiple semiconductor dies to improve manufacturing yields and correspondingly reduce costs. For example, the transceivers of a non-blocking crossbar switch are split across multiple semiconductor dies. The multi-die implementation also allows per-die power binning to ensure optimal power consumption of the packaged device. In one or more examples, the multi-die implementation of a non-blocking crossbar switch can be used in networking applications where line cards communicate with each other at Tb / s rates. In another example, a multi-die implementation of a non-blocking crossbar switch may be used in neural network training, where multiple accelerator devices (such as graphics processing units (GPUs) and application-specific integrated controllers (ASICs)) exchange training results in a non-blocking manner so that the accelerators appear as one large training computing device.

[0011] Advantages of the disclosed system over the prior art include: 1. Scalable non-blocking switching with throughput exceeding that of conventional technologies. 2. Reduced costs due to improved yield. 3. Ability to control maximum power consumption using power binning. 4. It appears as a large monolithic switch to the application.

[0012] In one or more examples, if a crossbar switch having N input ports and M output ports (an N×M crossbar switch) is non-blocking, any idle output port, i.e., an output port not receiving useful data, can receive useful data from any one of the N input ports. Such a crossbar switch is non-blocking because it is a set of M instances of N-to-1 multiplexers, which are themselves non-blocking. Consider a multiplexer with N input ports, where each input port is a W-bit bus operating at a clock frequency F. This multiplexer requires at least one bus for each output port to receive data from one of the N input ports.

[0013]

number

[0014] The whole crossbar switch has three types of interfaces: input, output, and address. Table 1 shows the number of wires and bandwidth of each interface.

[0015] [Table 1]

[0016] As an example, consider a 128x128 crossbar switch where each input port is a 128 Gb / s serial receiver and each output port is a 128 Gb / s serial transmitter. The crossbar switch does not operate in the serial domain, but instead operates in the parallel domain with a 500 MHz clock, i.e., the switch's connection configuration can change every 500 MHz clock cycle. Therefore, the crossbar switch bus width is 128 Gb / s ÷ 500 MHz = 256 bits. A 1-to-256 deserializer between each serial receiver and the corresponding crossbar switch input port, and a 256-to-1 serializer between each crossbar switch output port and the corresponding serial transmitter, function as data width adapters between the serial and parallel domains.

[0017] Table 2 summarizes the number of wires and bandwidth of each interface in the parallel domain. For the address interface, dense coding is assumed.

[0018] [Table 2]

[0019] In prior art devices, such a crossbar switch on a two-die semiconductor device may be configured such that each semiconductor die holds half of the input and output interfaces. Serial receivers 0-63 and serial transmitters 0-63 reside on the first die, while serial receivers 64-127 and serial transmitters 63-127 reside on the second die. Current crossbar switch solutions split this crossbar switch into two halves, one on each die. Each half switch implements half of the outputs but receives all inputs to preserve non-blocking properties. Specifically, each half switch is an N×M / 2 crossbar switch that receives half of its inputs from the same die and the other half from the other die.

[0020] Today's advanced multi-die devices typically have fewer than 18,000 wires between two semiconductor dies, with each die capable of 64 serial transceivers (transmitters and receivers). A prior art crossbar architecture in a two-die device, as shown in Table 2, can use 32,768 die-to-die wires, half of which go from die 1 to die 2 and the other half from die 2 to die 1. This results in oversubscription, i.e., a situation where an insufficient number of die-to-die wires are available. For example, serializing inter-die signals by doubling the die-to-die interface clock to 1 GHz theoretically doubles the available die-to-die bandwidth, but a 500 MHz clock cycle in the parallel domain is a practical limitation, especially for multi-die devices that use passive silicon interposers to implement die-to-die connections.

[0021] The new crossbar switch architecture disclosed herein comprises a large, non-blocking crossbar switch configured across multiple semiconductor dies within a package, reducing silicon costs by not oversubscribing die-to-die interfaces while still maintaining non-blocking characteristics.

[0022] This disclosure proposes a method to preserve the package pinout of existing monolithic crossbar switches.

[0023] The present disclosure includes a standalone interleaving device to support legacy agents (devices that exchange data through a switch).

[0024] This disclosure indicates that an add-on device for data interleaving can be integrated into the agent's semiconductor die or can be on a separate semiconductor die within the device package. This disclosure further proposes the use of an FPGA die with programmable logic and a transceiver to support different degrees of data interleaving.

[0025] Multi-die implementations can support larger aggregate switching bandwidths than monolithic implementations because multi-die devices have more silicon area. For example, a multi-die 192x192x256 switch can be the same cost as a monolithic 128x128x256 switch but has 50% more aggregate bandwidth. It is possible to scale to larger aggregate switch bandwidths using multiple multi-die switching devices.

[0026] FIG. 1 illustrates an example of a two-die, two-way interleaved crossbar switch 100 according to one embodiment.

[0027] A crossbar switch is a set of multiplexers. Bandwidth issues in prior art crossbar switches arise from the fact that each multiplexer must receive at least half of its input data from the die-to-die interface. Specifically, when the switch is distributed across Q dies, each multiplexer receives Q-1 / Q of its inputs from the die-to-die interface. The disclosed architecture moves these die-to-die connections from the die-to-die interface to the package or board, maintaining non-blocking properties and lowering the cost of the switch.

[0028] A preferred embodiment distributes N×M crossbar switches with W-bit data buses evenly across Q dies, with each die implementing an N×M / Q crossbar switch with a W / Q-bit data bus. All Q switches operate in parallel using the same connection configuration, but switch 1 / Q of the total bandwidth T. This switch is referred to as a Q-way interleaved crossbar switch. Each of the Q switches can also be described as a crossbar switch segment. For simplicity, the N×M crossbar switch with a W-bit data bus will be described as an N×M×W crossbar switch.

[0029] 1 illustrates a monolithic N×M×W=128×128×256 crossbar switch 100 on Q=2 dies (i.e., two crossbar switch segments) as two 2-way interleaved crossbar switch segments 108, 112 on two dies A, B, each constituting an N×M×W / Q=128×128×128 crossbar switch. Each crossbar switch segment 108, 112 is implemented on only one semiconductor die. In this example, each die A and die B block represents 128 bits of data. The chip packages and their pins are visible in the diagram of die A and die B.

[0030] Column 104 shows the data interleaver input pairs (eg, 0.A and 0.B) that are inputs to the crossbar switch transmitters that are switched to output pairs coupled to the crossbar switch receivers in column 116 .

[0031] Column 104 represents an example group (i.e., for Q=2) of two-way data interleavers receiving data from various agents (FIG. 2, 208). A "group" of data interleavers can include one or more data interleavers. Each two-way data interleaver in column 104 is called a two-way interleaver because it splits the data from each input port into two halves. Each two-way data interleaver supports two parallel crossbar switches 108, 112, so Q=2. A minimal data interleaver contains two input ports, each with two halves. For example, data from port 1 has two halves labeled "1.A" and "1.B." Data from "1.A" goes to a first transmitter and enters the first port of crossbar switch A 108. The other half of the data from port 1, i.e., "1.B," goes to a second transmitter and enters the first port of crossbar switch B 112.

[0032] Column 116 represents an example group (i.e., for Q=2) of two-way data deinterleavers transmitting data to various agents (FIG. 2, item 208). A "group" of data deinterleavers can comprise one or more two-way data deinterleavers. The configuration of each two-way data deinterleaver in column 116 mirrors the configuration of the data interleavers in column 104, except that data is received by each data deinterleaver instead of transmitted.

[0033] The data bus is split into upper and lower halves, i.e., the lower 128 bits and the upper 128 bits. Each bus is switched on a different die using the exact same control lines. In this example, each data deinterleaver in column 116 has four input ports labeled Rx, and each data interleaver in column 104 has four output ports labeled Tx.

[0034] Although the data wires or data connections do not cross the die-to-die interface between the interleaved crossbar switches, the routing of the transceivers is different. This change in transceiver signal routing can occur as follows: 1. Interleaved switches occur in the package routing between the pins of the package and on the bumps on the die if the package pinout remains the same as in the monolithic implementation, or 2. Occurs on boards where pin compatibility with another switch is not required.

[0035] To avoid using die-to-die interconnects, the present disclosure divides a W-bit data word destined for a switch port into Q equal portions, with each portion destined for one of the Q interleaved switches. For Q=2, FIG. 1 labels each half of a data word for port P in the format PX, where X is the letter "A" or "B." The first half of the data word (bits 0 through W / 2-1, i.e., 0 through 127) is labeled "A" in one box. The second half of the data word (bits 128 through 255) is labeled "B" in a different box.

[0036] Figure 1 uses two-way data interleaving. The purpose of this data interleaving is to move all Part A traffic to one die ("die A") and all Part B traffic to another die ("die B"). This interleaving allows two identical two-way interleaved crossbar switch segments to switch only half the bandwidth (but still have the same number of ports, i.e., the switch is still N x M). Each interleaved switch is still a fully non-blocking switch, except that it only switches half the traffic on half of the buses, rather than half the inputs.

[0037] Data interleaving at the switch ingress and deinterleaving at the switch egress occur outside the crossbar switch package. The data interleaving pattern repeats for every Q=2 switch ports. For port P, the monolithic switch's 〈[PA,PB],[(P+1).A,(P+1).B]〉 data pattern becomes 〈[PA,(P+1).A],[PB,(P+1).B]〉, where the two half data words within the square brackets are destined for the same transceiver. Unlike monolithic switches, in this design only data words destined for the same switch die are serialized and deserialized together.

[0038] 2 illustrates an example of an agent that supports two-way data interleaving, according to one embodiment. FIG. 2 depicts a data deinterleaver-interleaver system 200 that enables an "agent" to communicate with the interleaved crossbar switch of FIG. 1.

[0039] In this manner, data deinterleaver 204 and data interleaver 212 may be added to existing devices or "agents" to enable the agents to communicate with the crossbar switch. In this example, data deinterleaver 204 has four input ports labeled Rx, and data interleaver 212 has four output ports labeled Tx.

[0040] A data interleaver and a data deinterleaver are used to connect conventional agents (eg, CPUs, GPUs, etc.) to the interleaved switch.

[0041] In one or more examples, data deinterleaver 204 and data interleaver 212 may use cooperation from external devices, i.e., agents 208. Consider 32 agents 208, such as networking line card ASICs, GPUs, CPUs, or machine learning accelerators, connected to a 128x128x256 two-way interleaved non-blocking crossbar switch. Each agent provides 128 / 32=4 ports' worth of traffic to the switch in both directions. The output of each agent 208 (connected to the switch ingress) interleaves the outgoing traffic. Similarly, the input of each agent 208 (connected to the switch egress) deinterleaves the incoming traffic.

[0042] A device that supports 2-way interleaving has an even number of ports. Data deinterleaver-interleaver system 200 has four input ports and four output ports, providing an even number of ports. In general, a device that supports Q-way interleaving has multiple Q ports.

[0043] FIG. 3 illustrates an example of an agent that supports four-way data interleaving, according to one embodiment.

[0044] The previous examples in this disclosure describe a 2-way interleaved switch (Q=2). The degree of interleaving can be any positive integer. Figure 3 shows a 4-way data interleaver system 300 (Q=4), i.e., four crossbar switch segments. The 4-way data interleaver 300 has four input ports and four output ports, which is the minimum number of ports for 4-way interleaving.

[0045] The data deinterleaver 304 and data interleaver 312 are configured to cooperate with external devices, or agents 308. In some examples, the external agents 308 can be networking line card ASICs, GPUs, CPUs, or machine learning accelerators connected to a 4-way interleaved non-blocking crossbar switch. Each agent provides 128 / 32 = 4 ports' worth of traffic to the switch in both directions. The output of each agent 308 (connected to the switch ingress) interleaves the outgoing traffic. Similarly, the input of each agent 308 (connected to the switch egress) deinterleaves the incoming traffic.

[0046] The boxes around the data interleaver 312 and the data deinterleaver 304 in Figure 3 indicate that, in one example, they may be in the same device package as the agent die, or, in another example, they may be in separate device packages and located on the board between the interleaved crossbar switch and the conventional agent chip. Specifically, the data deinterleaver 304 and data interleaver 312 in Figure 3 (with the same number of interleaver and deinterleaver groups) may be packaged on a single chip. The former is preferable because it requires less energy to move data within the package than adding transceivers (half on the agent chip and half on the interleaver and deinterleaver chips) to drive electrons through printed circuit board traces.

[0047] Examples in this disclosure focus on avoiding all inter-die data communication. It is possible to create a hybrid switch with several legacy, non-interleaved input ports. The legacy input ports broadcast data to all other interleaved switches using the inter-die interconnect. The output remains interleaved and requires external equipment for de-interleaving. (The legacy input ports can send traffic to any output port. Note that there are multiple ports for multicasting. De-interleaving the egress traffic would be prohibitively expensive and would defeat the purpose of this disclosure.) In one or more examples, limiting the number of legacy input ports ensures that corresponding data does not cloak the inter-die interface.

[0048] 4 illustrates an example of two two-die, four-way interleaved switches 408, 412 implementing a 256x256x256 non-blocking switch, according to one embodiment. The crossbar scheme 400 shows four crossbar switch segments implemented on a total of four semiconductor dies and two device packages, with two semiconductor dies implemented on each package.

[0049] Several agents 300 are shown supporting four-way data interleaving. These agents 300 communicate with several interleaved non-blocking crossbar switch packages 408, 412. Each crossbar switch package 408, 412 may comprise multiple semiconductor dies. The example of Figure 4 illustrates how the partitioning of the crossbar switch need not be entirely within one package, but may occur across multiple packages.

[0050] 3, includes data interleaving of data from the agent to the switch and data deinterleaving of data from the switch to the agent, where agents represent conventional (non-interleaved) logical entities communicating with other agents via a crossbar switch. In one example, the crossbar switch here is interleaved, so data interleaver 312 and data deinterleaver 304 are tagged to make conventional agents compatible with the (new) interleaved crossbar switch.

[0051] 5 illustrates an example logical wiring diagram of an agent-multi-die crossbar switch according to one embodiment. FIG. 5 is a logical wiring diagram and not necessarily an actual layout.

[0052] Conventional intercommunicating agents (e.g., networking ASICs, CPUs, GPUs, accelerators) do not interleave output data (toward the switch) and do not interleave input data (from the crossbar switch). The data interleaver 212 and deinterleaver 204 may be packaged components inserted between the interleaving switch and conventional agents 208. To reduce the power consumed by these additional links on the circuit board (i.e., data traveling from conventional agents 208 to data interleaver 212 and from data deinterleaver 204 to conventional agents 208), the data interleaver and deinterleaver may be on the same silicon as the agents. In other words, conventional agent 208, one or more data interleavers 212, and one or more data deinterleavers 204 may be on the same die to reduce power consumption.

[0053] Alternatively, the existing agent die may reside in a single device package (i.e., (1) a package substrate as a multi-chip module, or (2) the same device package with one or more data interleavers and deinterleavers connected via a passive silicon interposer on which the conventional agent die and the data interleavers and deinterleavers reside). As yet another alternative, an active silicon interposer containing the data interleavers and deinterleavers may communicate with the conventional agent die on the active interposer.

[0054] Figure 5 illustrates a data deinterleaver-interleaver system that allows "agents" to communicate with the interleaved crossbar switch of Figure 5. Agents 208 are external components. Multiple agents 208 communicate with each other through the interleaved switch.

[0055] In this manner, data deinterleaver 204 and data interleaver 212 may be added to existing devices or "agents" to enable the agents to communicate with the crossbar switch.

[0056] In one or more examples, data deinterleaver 204 and data interleaver 212 use cooperation from external devices, i.e., agents 208. Consider 32 agents 208, such as networking line card ASICs, GPUs, CPUs, or machine learning accelerators, connected to a 128x128x256 two-way interleaved non-blocking crossbar switch. Each agent provides 128 / 32=4 ports' worth of traffic to the switch in both directions. The output of each agent 208 (connected to the switch ingress) interleaves the outgoing traffic. Similarly, the input of each agent 208 (connected to the switch egress) deinterleaves the incoming traffic.

[0057] The degree of interleaving is configurable at system boot-up. The primary example of this disclosure describes two 2-way interleaved 128x128x128 switches in the same device package operating in parallel as one 128x128x256 non-blocking crossbar switch. By designing the multi-die switch to support both 2-way and 4-way interleaving (Q∈{2, 4}), using two such multi-die devices can scale the total non-blocking switching bandwidth to 256x256x256 when Q=4. In other words, the four semiconductor dies in two packaged 2-die devices operate in parallel as four 256x256x64 switches. The switch designer must determine the number of configurations in advance. For example, configurations can have Q∈{2, 4, 8, 16}. The higher the degree of interleaving, the more switch select signals there are and the more interleaving configurations the data interleaver and data deinterleaver support.

[0058] Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by like reference numerals throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the specification or as limitations on the scope of the claims. In addition, the illustrated example need not have all the aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be implemented in any other embodiment, even if not so illustrated or explicitly described.

[0059] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to encompass a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c).

[0060] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or another data structure), ascertaining, etc. Furthermore, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Furthermore, "determining" may include resolving, selecting, choosing, establishing, etc.

[0061] The above description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles described herein may be applied to other aspects. Reference to an element in the singular is not intended to mean "one and only one," but rather "one or more," unless otherwise specified. The term "some" refers to one or more, unless otherwise specified. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure, both already known or later known to those skilled in the art, are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is expressly recited in the claims. No claim element shall be construed under the provisions of 35 U.S.C. § 112(f) unless the element is expressly recited using the phrase "means for," or, in the case of a method claim, unless the element is recited using the phrase "step for."

[0062] The various operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including, but not limited to, circuits, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or processors (e.g., general-purpose or specially programmed processors). Generally, where there are operations illustrated in figures, those operations may have corresponding means-plus-function components with similar numbering.

[0063] The various example logic blocks, modules, and circuits described in connection with this disclosure may be implemented or performed using general-purpose processors, DSPs, ASICs, field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0064] If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. A processor may be responsible for general processing, including managing a bus and executing software modules stored on a machine-readable storage medium. A computer-readable storage medium may be coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. By way of example, machine-readable media may include a transmission line, a data-modulated carrier wave, and / or a computer-readable storage medium having instructions stored thereon that is separate from a wireless node, all of which may be accessed by a processor via a bus interface. Alternatively, or additionally, the machine-readable medium, or any portion thereof, may be integrated into the processor, such as in the case of a cache and / or general-purpose register file. Examples of machine-readable storage media may include, by way of example, RAM (random access memory), flash memory, ROM (read-only memory), PROM (programmable read-only memory), EPROM (erasable programmable read-only memory), EEPROM (electrically erasable programmable read-only memory), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product.

[0065] A software module may comprise a single instruction or many instructions, but may be distributed across several different code segments, in different programs, and across multiple storage media. A computer-readable medium may comprise several software modules. A software module contains instructions that, when executed by a device such as a processor, cause a processing system to perform various functions. A software module may include a transmitting module and a receiving module. Each software module may reside in a single storage device or may be distributed across multiple storage devices. As an example, a software module may be loaded into RAM from a hard drive when a trigger event occurs. During execution of a software module, a processor may load some of the instructions into a cache to increase access speed. One or more cache lines may then be loaded into a general-purpose register file for execution by the processor. When referring below to the functionality of a software module, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.

[0066] Accordingly, some aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and / or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein, e.g., instructions for performing the operations described herein.

[0067] Furthermore, it should be understood that modules and / or other suitable means for performing the methods and techniques described herein may be downloaded and / or otherwise obtained by a user terminal and / or base station, where applicable. For example, such devices may be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, the various methods described herein may be provided via storage means (e.g., RAM, ROM, physical storage media such as a compact disk (CD) or floppy disk, etc.) such that the user terminal and / or base station may obtain the various methods upon coupling or providing the storage means to the device. Furthermore, any other suitable technique may be utilized to provide the methods and techniques described herein to a device.

[0068] While the above is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. A crossbar switch system, comprising: a plurality of semiconductor dies; one or more data interleavers coupled to the crossbar switch, each data interleaver of the one or more data interleavers including a plurality of input ports; one or more data deinterleavers coupled to the crossbar switch, each data deinterleaver of the one or more data deinterleavers including a plurality of output ports; a plurality of interleaved crossbar switch segments, one of the plurality of interleaved crossbar switch segments implemented on one of the plurality of semiconductor dies, and any one of the plurality of output ports configured to receive data from any one of the input ports.

2. The crossbar switch system of claim 1 , wherein no data connections are configured between the semiconductor dies.

3. The crossbar switch system of claim 1 , wherein the one or more data interleavers are coupled to a transmitter.

4. The crossbar switch system of claim 1 , wherein the one or more data deinterleavers are coupled to a receiver.

5. 2. The crossbar switch system of claim 1, wherein the plurality of interleaved crossbar switch segments includes a total of Q crossbar switch segments, where T is a total bandwidth, and each crossbar switch segment of the plurality of interleaved crossbar switch segments is configured to switch a portion of the total bandwidth equal to T / Q.

6. The crossbar switch system of claim 1 further comprising a plurality of device packages.

7. The crossbar switch system of claim 1 , wherein the degree of interleaving in the interleaved crossbar switch segments is configurable at system boot-up.

8. 1. A crossbar switch system, comprising: one or more data deinterleavers configured to receive data from the crossbar switch; an integrated circuit device coupled to the one or more data deinterleavers; one or more data interleavers coupled to the integrated circuit device, the one or more data interleavers configured to transmit data to the crossbar switch.

9. The crossbar switch system of claim 8 , wherein the one or more data deinterleavers and the one or more data interleavers are configured on a semiconductor die different from the integrated circuit device.

10. The crossbar switch system of claim 8 , wherein the one or more data deinterleavers and the one or more data interleavers are configured on a device package separate from the integrated circuit device.

11. 1. A method of implementing a crossbar switch, the method comprising: providing one or more device packages; providing a plurality of semiconductor dies; providing one or more data interleavers coupled to a crossbar switch, each data interleaver of the one or more data interleavers including a plurality of input ports; providing one or more data deinterleavers coupled to the crossbar switch, each data deinterleaver of the one or more data deinterleavers including a plurality of output ports; providing a plurality of interleaved crossbar switch segments, a crossbar switch segment of the plurality of interleaved crossbar switch segments implemented on a semiconductor die of the plurality of semiconductor dies; A method wherein no data connections are configured between the semiconductor dies, and any one output port is configured to receive data from any one input port.

12. The method of claim 11 , wherein the one or more data interleavers are coupled to a transmitter.

13. The method of claim 11 , wherein the one or more data deinterleavers further comprise a receiver.

14. 12. The method of claim 11, wherein the plurality of interleaved crossbar switch segments comprises Q crossbar switch segments, where T is a total bandwidth, and each crossbar switch segment is configured to switch a portion of the data equal to T / Q of the total bandwidth.

15. The method of claim 11 , wherein the degree of interleaving in the interleaved crossbar switch segments is configurable at system boot-up.

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