High-density static random access memory

Abstract

A high-density static random access memory (HRAM) semiconductor memory cell comprising six vertical transport field effect transistors (VTFETs) on a wafer, the six VTFETs being in a first layer, and the six VTFETs being in a first column.

Description

[Background technology]

[0001] The present invention relates generally to the field of semiconductor device manufacturing, and more particularly to high density static random access memories using vertical-transport field-effect transistors (VTFETs).

[0002] Semiconductor devices are fabricated by sequentially depositing insulating (dielectric), conductive, and semiconducting layers of material on a semiconductor substrate and using lithography to pattern the various layers to form circuit components and elements thereon. Generally, these semiconductor devices include multiple circuits that form integrated circuits (ICs) fabricated on the semiconductor substrate.

[0003] Static random access memory (SRAM) may be formed as a semiconductor device. SRAM is a random access memory that uses latch circuits (flip-flops) to store each bit. A conventional SRAM is formed from six transistors. Two groups of two of the six transistors form two cross-coupled inverters that store the bit in the cell. The storage cell has two stable states, which are used to represent "0" or VSS and "1" or VDD. The fifth and sixth transistors are access transistors for read / write operations. Alternative SRAM configurations can be realized that may use four, eight, or ten transistors.

[0004] Current SRAM circuits can occupy a large amount of space on an integrated circuit. There is a need for higher density SRAM cells that reduce size requirements and therefore increase the density of SRAM circuits on an integrated circuit. Due to the vertical current flow, VTFETs have smaller widths and heights compared to conventional planar field-effect transistors. Summary of the Invention

[0005] In a first embodiment, a semiconductor memory cell is provided on a wafer, the semiconductor memory cell comprising six vertical transport field effect transistors (VTFETs). In the first embodiment, the six VTFETs are in a first layer. In the first embodiment, the six VTFETs are in a first column. In the first embodiment, a power supply for two of the six VTFETs is connected to a power supply network on the backside of the wafer. In the first embodiment, a ground for two of the six VTFETs is connected to a power supply network on the backside of the wafer. In the first embodiment, a bit line and a bit line bar for two of the six VTFETs are connected to a power supply network on the backside of the wafer, and a word line for two of the six VTFETs is connected to a power supply network on the frontside of the wafer. In the first embodiment, a bit line and a bit line bar for two of the six VTFETs are connected to a power supply network on the frontside of the wafer, and a word line for two of the six VTFETs is connected to a power supply network on the backside of the wafer. In a first embodiment, a first metal wire electrically connects the source / drain region of a first VTFET, the source / drain region of a second VTFET, the source / drain region of a third VTFET, the gate region of a fourth VTFET, and the gate region of a fifth VTFET. In a first embodiment, a second metal wire electrically connects the gate region of the second VTFET, the gate region of the third VTFET, the source / drain region of the fourth VTFET, the source / drain region of the fifth VTFET, and the source / drain region of a sixth VTFET. In a first embodiment, the first metal wire is within the semiconductor memory cell. In a first embodiment, the second metal wire is within the semiconductor memory cell. In a first embodiment, a fin edge and a gate edge of one or more VTFETs of the plurality of VTFETs are aligned with an RX edge.

[0006] In a second embodiment, a wafer includes a plurality of vertical transport field effect transistors (VTFETs). In the second embodiment, each VTFET of the plurality of VTFETs is in a first layer. In the second embodiment, six VTFETs of the plurality of VTFETs form memory cells. In the second embodiment, at least one memory cell is in a column adjacent to at least one other memory cell. In the second embodiment, a power supply for two of the six VTFETs is connected to a power supply network on the backside of the wafer. In the second embodiment, a ground for two of the six VTFETs is connected to a power supply network on the backside of the wafer. In the second embodiment, a bit line and a bit line bar for two of the six VTFETs are connected to a power supply network on the backside of the wafer, and a word line for two of the six VTFETs is connected to a power supply network on the frontside of the wafer. In a second embodiment, bit lines and bit line bars for two of the six VTFETs are connected to a power distribution network on the front side of the wafer, and word lines for two of the six VTFETs are connected to a power distribution network on the back side of the wafer. In a second embodiment, a first metal wire electrically connects the source / drain region of the first VTFET, the source / drain region of the second VTFET, the source / drain region of the third VTFET, the gate region of the fourth VTFET, and the gate region of the fifth VTFET. In a second embodiment, a second metal wire electrically connects the gate region of the second VTFET, the gate region of the third VTFET, the source / drain region of the fourth VTFET, the source / drain region of the fifth VTFET, and the source / drain region of the sixth VTFET. In a second embodiment, the first metal wire is within the semiconductor memory cell. In a second embodiment, the second metal wire is within the semiconductor memory cell.

[0007] In a third embodiment, a semiconductor SRAM includes six vertical transport field effect transistors (VTFETs) in a wafer. In the third embodiment, the six VTFETs are in a first layer. In the third embodiment, the six VTFETs are in a first column.

[0008] In a fourth embodiment, a semiconductor memory array includes a plurality of vertical transport field effect transistors (VTFETs) on a wafer. In the fourth embodiment, six VTFETs of the plurality of VTFETs are arranged in a memory cell of one or more memory cells in a first layer on the wafer. In the fourth embodiment, each memory cell of the one or more memory cells is arranged in a column. In the fourth embodiment, each memory cell of the one or more memory cells shares a first contiguous lower source / drain region for a first VTFET and a second VTFET of the respective memory cell. In the fourth embodiment, the first contiguous lower source / drain region is connected to a power supply network on the backside of the wafer. In the fourth embodiment, each memory cell of the one or more memory cells shares a second contiguous lower source / drain region for a third VTFET and a fourth VTFET of the respective memory cell. In the fourth embodiment, the second contiguous lower source / drain region is connected to a power supply network on the backside of the wafer. In a fourth embodiment, each memory cell of the one or more memory cells shares a third contiguous lower source / drain region for the fifth VTFET and a fourth contiguous lower source / drain region for the sixth VTFET of the respective memory cell. In the fourth embodiment, the third contiguous lower source / drain region is connected to a power supply network on the backside of the wafer. In the fourth embodiment, the fourth contiguous lower source / drain region is connected to a power supply network on the backside of the wafer.

[0009] In a fifth embodiment, the semiconductor memory array includes one or more vertical transistors in a wafer. In the fifth embodiment, the one or more vertical transistors are arranged in one or more memory cells in a first layer. In the fifth embodiment, each memory cell of the one or more memory cells is in one column.

[0010] Embodiments of the present invention provide a high density cell layout for SRAM technology utilizing VTFETs. Embodiments of the present invention provide an SRAM including six VTFETs in a column. Embodiments of the present invention provide a bit line connection for a first side of the SRAM and a word line connection for a second side of the SRAM. Embodiments of the present invention provide one line connecting a pull down, pass gate, pull up, and cross couple. Embodiments of the present invention provide fin edge and gate edge alignment. Embodiments of the present invention provide any number of signals (e.g., clock, bus, I / O, power, ground, etc.) distributed or fed to the source / drain / gate regions of the VTFETs through a backside power delivery network. [Brief explanation of the drawings]

[0011] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0012] [Figure 1] 1 shows a cross-sectional view of a VTFET semiconductor structure having front contacts for the upper source / drain regions, the lower source / drain regions, and the gate region according to a first embodiment of the present invention.

[0013] [Figure 2] 1 shows a cross-sectional view of a VTFET semiconductor structure having front contacts for the upper source / drain and gate regions and back contacts for the lower source / drain regions according to a first embodiment of the present invention.

[0014] [Figure 3]1 shows a cross-sectional view of a VTFET semiconductor structure having front contacts for the upper source / drain and back contacts for the lower source / drain and gate regions according to a first embodiment of the present invention.

[0015] [Figure 4] 1 shows a circuit schematic diagram of an SRAM according to one embodiment of the present invention.

[0016] [Figure 5] 1 illustrates a top view of two adjacent SRAMs according to one embodiment of the present invention.

[0017] [Figure 6] 1 shows a top view of an SRAM cell according to a first embodiment of the present invention;

[0018] [Figure 7] 2 shows a cross-sectional view of a SRAM cell at section X according to one embodiment of the present invention.

[0019] [Figure 8] 1 shows a cross-sectional view of a SRAM cell at section Y according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] Embodiments of the present invention recognize that a vertical transport field effect transistor (VTFET) has vertical current flow. Embodiments of the present invention recognize that a VTFET includes a lower source / drain region and an upper source / drain region. Embodiments of the present invention recognize that the lower source / drain region is closer to the backside of the VTFET (closer to the wafer) and the upper source / drain region is closer to the front side of the VTFET (closer to conventional interconnect wiring). Embodiments of the present invention recognize that an input is to one source / drain region and an output is to one source / drain region, and thus either the input or the output is on the backside of the device and either the input or the output is on the front side of the device. Thus, embodiments of the present invention recognize that VTFET transistors are suitable for use in SRAM technology.

[0021] Embodiments of the present invention provide a high-density cell layout for SRAM technology utilizing VTFETs. Embodiments of the present invention provide an SRAM including six VTFETs in a column. Embodiments of the present invention provide a bitline connection on a first side of the SRAM and a wordline connection on a second side of the SRAM. Embodiments of the present invention provide one line connecting a pulldown, passgate, pullup, and cross-couple. Embodiments of the present invention provide fin edge and gate edge alignment. Embodiments of the present invention provide any number of signals (e.g., clock, bus, I / O, power, ground, etc.) distributed or fed to the source / drain / gate regions of the VTFETs through a backside power delivery network.

[0022] Some embodiments will be described in more detail with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in various ways and therefore should not be construed as limited to the embodiments disclosed herein. Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.

[0023] The following presents a summary to provide a basic understanding of one or more embodiments of the present disclosure. This summary is not intended to identify key or critical elements or to delineate the scope of any particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. Aspects of the invention are described with reference to given example architectures; however, it should be understood that other architectures, structures, substrate materials, process features, and steps may be modified within the scope of the aspects of the invention.

[0024] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as semiconductor devices. The embodiments can be practiced in conjunction with integrated circuit manufacturing techniques currently used in the art for advanced semiconductor devices, and only those commonly practiced process steps necessary for understanding the described embodiments are included. The figures represent cross-sectional portions of portions of advanced semiconductor devices after fabrication and are not drawn to scale, but are instead drawn to illustrate features of the described embodiments. Specific structural and functional details disclosed herein should not be construed as limiting, but merely as representative for the purpose of teaching those skilled in the art how to variously utilize the disclosed methods and structures. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0025] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that it can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0026] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the disclosed structures and methods as oriented in the drawing figures. The terms "over," "atop," "on top of," "on," "disposed on," or "disposed on" mean that a first element is above a second element, and that intervening elements, such as interface structures, may be present between the first and second elements. The term "direct contact" means that a first element and a second element are connected without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0027] In the following detailed description, some of the processing steps, materials, or operations known in the art may be combined for purposes of presentation and illustration, and in some cases may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. Moreover, for the sake of brevity and to maintain focus on the unique features of the elements of the present invention, descriptions of materials, processes, and structures previously discussed may not be repeated with respect to subsequent figures. In other instances, some processing steps or operations that are known may not be described. It should be understood that the following description instead focuses on the unique features or elements of various embodiments of the present invention.

[0028] This embodiment can include a design for an integrated circuit chip, where the design can be created in a graphical computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive in a storage access network, etc.). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer can directly or indirectly transmit the resulting design to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., over the Internet). The stored design is then converted into an appropriate format (e.g., GDSII) for the manufacture of photolithography masks, which typically contain multiple copies of the chip design to be formed on a wafer. The photolithography masks are utilized to define the areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0029] The methods described herein may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be provided by the manufacturer in raw wafer (i.e., as a single wafer with multiple unpackaged chips), bare die form, or packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads affixed to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-cost applications to advanced computer products with displays, keyboards or other input devices, and central processors.

[0030] It should also be understood that material compounds are described in terms of the listed elements, e.g., SiGe. These compounds may include different ratios of elements within the compound, e.g., SiGe includes SiGe, where x is less than or equal to 1. Additionally, other elements may be included in the compound and still function according to the present principles. Compounds with additional elements are referred to herein as alloys.

[0031] References herein to "one embodiment" or "an embodiment," as well as other variations thereof, mean that a particular feature, structure, characteristic, etc. described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," and any other variations thereof, in various places throughout this specification are not necessarily all referring to the same embodiment.

[0032] References herein to "one embodiment," "another embodiment," "another embodiment," "an embodiment," and the like indicate that the described embodiment may include particular features, structures, or characteristics, but that not all embodiments necessarily include these particular features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is understood that one of ordinary skill in the art knows to use such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0033] It should be understood that the use of any of the following terms, " / ," "and / or," and "at least one of," for example, "A / B," "A and / or B," and "at least one of A and B," is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B). As a further example, for "A, B, and / or C" and "at least one of A, B, and C," such language is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first listed alternative and the second listed alternative (A and B), or the selection of only the first listed alternative and the third listed alternative (A and C), or the selection of only the second listed alternative and the third listed alternative (B and C), or the selection of all three alternatives (A, B, and C). This can be extended for as many items as are listed, as would be readily apparent to one skilled in the art.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and does not tend to limit example embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, it will be understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups.

[0035] Spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another, as shown in the figures, for ease of description. It will be understood that spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is inverted, an element described as "below" or "below" another element or feature would then be oriented "above" the other element or feature. Thus, the term "below" can encompass both an upper and lower orientation. A device can be otherwise rotated 90 degrees or oriented in other orientations, and the spatially relative descriptors used herein can be interpreted accordingly. Additionally, when a layer is referred to as being "between" two layers, it is understood that it may be the only layer between the two layers, or that one or more intervening layers may be present.

[0036] Terms such as "first," "second," etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element without departing from the scope of the present concepts.

[0037] Broadly speaking, the various processes used to form semiconductor chips fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process in which material is grown, coated, or otherwise transferred onto a wafer. Available techniques include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Another deposition technique is plasma-enhanced chemical vapor deposition (PECVD), a process that uses energy in a plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0038] Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate, which is then transferred to the substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called a photoresist. The pattern created by lithography or photolithography is typically used to define or protect selected surfaces and portions of a semiconductor structure during subsequent etching processes.

[0039] Removal is any process, such as etching or chemical-mechanical planarization (CMP), that removes material from a wafer. Examples of etching processes include either wet (e.g., chemical) or dry etching processes. One example of a removal or dry etching process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a remote, wide-beam ion / plasma source to remove substrate material by means of physically inert and / or chemically reactive gases. Like other dry plasma etching techniques, IBE offers advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal substrate damage. Another example of a dry etching process is reactive ion etching (RIE). Generally, RIE uses a chemically reactive plasma to remove material deposited on a wafer. High-energy ions from the RIE plasma bombard the wafer surface and react with the surface material, resulting in its removal.

[0040] Deposition processes for metal liners and sacrificial materials include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which deposition species are formed as a result of a chemical reaction between gaseous reactants at temperatures above room temperature (e.g., from about 25°C to about 900°C). A solid product of the reaction is deposited on a surface, whereupon a film, coating, or layer of the solid product is formed. Variations in CVD processes include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and metal-organic CVD (MOCVD), and combinations thereof may also be utilized. In alternative embodiments using PVD, the sputtering equipment may include a direct current diode system, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In an alternative embodiment using ALD, chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface. In an alternative embodiment using GCIB deposition, a high-pressure gas is expanded in a vacuum and then condensed into clusters. The clusters can be ionized and directed onto the surface to provide a highly anisotropic deposition.

[0041] Vertical transport field-effect transistors (VTFETs) have become a viable device option for scaling semiconductor devices (e.g., complementary metal oxide semiconductor (CMOS) devices) down to and beyond the 5-nanometer (nm) node. VTFET devices include one or more fin channels with source / drain regions at the ends of the fin channel on the top and bottom sides of the fin. Current flows vertically (e.g., perpendicular to the substrate) through the fin channel, e.g., from the lower source / drain region to the upper source / drain region. Vertical transport architecture devices are designed to address limitations of horizontal device architectures, e.g., regarding density, performance, power consumption, and integration, by, e.g., decoupling gate length from contact gate pitch to provide density equivalent to FinFETs at larger contacted poly pitch (CPP) and lower middle-of-line (MOL) resistance.

[0042] In a first embodiment, Figure 1 shows VTFET 100 with contacts 114, 124, and 134 directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 100. In a second embodiment, Figure 2 shows VTFET 200 with contacts 214 and 234 directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 200, and contact 224 directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 200. In a third embodiment, Figure 3 shows VTFET 300 with contact 314 directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 300.

[0043] 1 is a cross-sectional view of a VTFET 100 formed on a bulk substrate 102. The substrate 102 may be formed from any suitable semiconductor structure, including various silicon-containing materials, including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayer structures thereof. While silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be utilized as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like. In one exemplary embodiment, the substrate 102 is silicon.

[0044] VTFET 100 includes an STI region 104 composed of a dielectric material, such as silicon oxide or silicon oxynitride, and formed by methods known in the art. For example, in one exemplary embodiment, STI region 104 is a shallow trench isolation oxide layer.

[0045] The VTFET 100 includes upper and lower source / drain regions 110, 120 on opposite sides of a fin 130. In one embodiment, the upper source / drain region 110 is formed between dielectric layers 170. In one embodiment, the lower source / drain region 120 is formed in the substrate 102 between shallow trench isolation regions 104. The upper and lower source / drain regions 110, 120 are formed, for example, by an epitaxial growth process. The epitaxially grown upper and lower source / drain regions 110, 120 can be in-situ doped, meaning that dopants are incorporated into the epitaxy film during the epitaxy process. Other alternative doping techniques can be used, including, but not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implant doping, liquid phase doping, solid phase doping, etc., and the dopants may include various concentrations of n-type dopants selected from the group of, for example, phosphorus (P), arsenic (As), and antimony (Sb), and p-type dopants selected from the group of boron (B), gallium (Ga), indium (In), and thallium (Tl). For example, in a non-limiting example, the dopant concentration ranges from 1×10 18 / cm 3 ~1×10 21 / cm 3 According to one embodiment, the lower source / drain region 120 may be boron-doped SiGe for a p-type field effect transistor (P-FET) or phosphorus-doped silicon for an n-type field effect transistor (N-FET). It should be understood that the term "source / drain region" as used herein means that a given source / drain region can be either a source region or a drain region depending on the application.

[0046] Terms such as "epitaxial growth and / or deposition" and "epitaxially forming and / or growing" refer to the growth of a semiconductor material on a semiconductor substrate deposition surface, where the grown semiconductor material has the same crystalline properties as the semiconductor material on the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the depositing atoms reach the deposition surface of the semiconductor substrate with enough energy to move around the surface and orient themselves to the crystalline structure of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline properties as the deposition surface on which it is formed. For example, epitaxial semiconductor material deposited on a {100} crystalline surface will adopt a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process selectively forms on semiconductor surfaces and does not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0047] Examples of various epitaxial growth processes include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Temperatures for epitaxial deposition processes can range from 500°C to 900°C. Higher temperatures typically result in faster deposition, but faster deposition can lead to crystalline defects and film cracking.

[0048] A number of different sources may be used for epitaxial growth of the compressively strained layer. In some embodiments, the gas source for deposition of the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source, including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer may be deposited from a germanium gas source, including, but not limited to, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of such gas sources can be used to form epitaxial silicon-germanium alloy layers. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. After epi formation, a drive-in anneal can be applied to drive the dopants closer to the bottom of the fin channel.

[0049] In one embodiment, as used herein, "semiconductor fin" or fin 130 refers to a semiconductor material having a pair of parallel, vertical sidewalls. As used herein, a surface is "vertical" if there is a vertical plane whose deviation is within three times the root-mean-square roughness of the surface. In one embodiment, each fin 130 has a height ranging from about 20 nm to about 200 nm and a width ranging from about 5 nm to about 30 nm. Other heights and / or widths smaller or larger than the ranges mentioned herein can also be used herein. Each fin 130 is spaced from its nearest neighboring fin 130 by a pitch ranging from about 20 nm to about 100 nm; the pitch is measured from a point or reference surface on one semiconductor fin to the exact same point or reference surface on a neighboring semiconductor fin. The fins 130 are also generally oriented parallel to one another. Although this application describes and illustrates a single fin 130, any number of fins and surrounding gate regions may be used, and the fins may be of any shape.

[0050] The fin 130 may be formed from any suitable semiconductor structure, including various silicon-containing materials, including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multi-layer structures thereof. While silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be utilized as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like. In one exemplary embodiment, the fin 130 is silicon.

[0051] In one embodiment, a lower spacer layer 140 is formed on the STI regions 104 and the lower source / drain regions 120. In one embodiment, the lower spacer layer 140 is formed around the fin 130. Suitable materials for the lower spacer layer 140 include, for example, silicon boron nitride (SiBN), silicon boron nitride (SiBCN), silicon oxycarbonitride (SiOCN), SiN, and SiOx. The lower spacer layer 140 can be deposited using directional deposition techniques, such as high-density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition deposits the spacer material preferably on exposed horizontal surfaces rather than lateral sidewalls. Alternatively, the lower spacer layer 140 can be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and a dielectric recess.

[0052] In one embodiment, an upper spacer layer 160 is formed on the gate region between the fin 130 and the dielectric layer 170. In one embodiment, the upper spacer layer 160 is formed around the fin 130. Suitable materials for the upper spacer layer 160 include, for example, silicon boron nitride (SiBN), silicon boron nitride (SiBCN), silicon oxycarbonitride (SiOCN), SiN, and SiOx. The lower spacer layer 140 can be deposited using directional deposition techniques, such as high-density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition deposits the spacer material preferably on exposed horizontal surfaces rather than lateral sidewalls. Alternatively, the upper spacer layer 160 can be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and a dielectric recess.

[0053] A gate region is formed on the lower spacer layer 140 and around the fin 130. In an exemplary embodiment, the gate region is deposited on the lower spacer layer 140 and around the fin 130 using, for example, ALD, CVD, RFCVD, plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), or molecular layer deposition (MLD). The gate region may include a gate dielectric layer 150 and a gate conductor layer 132. The gate dielectric layer 150 may be formed from a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (YO3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. High-k materials may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate conductor layer 132 may include a metal gate or a work function metal (WFM). The WFM for the gate conductor layer may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), combinations of Ti and Al alloys, a stack including a barrier layer (e.g., TiN, TaN, etc.) followed by one or more of the above-mentioned WFM materials, etc. It should be understood that a variety of other materials may be used for the gate conductor layer 132 as desired.

[0054] In one embodiment, the dielectric layer 170 may be composed of, for example, silicon dioxide (SiOx), undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD), a low-k dielectric layer, or any combination thereof. As indicated above, the term "low-k" as used herein refers to a material having a dielectric constant k lower than that of silicon dioxide. In one embodiment, the dielectric layer 170 can be formed using a deposition technique including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, spin-on coating, or sputtering.

[0055] In one embodiment, the upper source / drain region 110, the lower source / drain region 120, and the gate region are connected to interconnect wiring and / or a power supply network (not shown) through contacts 114, 124, and 134, respectively. In one embodiment, as shown in FIG. 1 , contacts 114, 124, and 134 are formed to directly connect to interconnect wiring and / or a power supply network (not shown) on the front side of VTFET 100. In one embodiment, contacts 114, 124, and 134 may comprise any suitable conductive material, such as copper, aluminum, tungsten, cobalt, or alloys thereof. Examples of deposition techniques that can be used include, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). Optionally, electroplating techniques can be used to form contacts 114, 124, and 134.

[0056] In a second embodiment, FIG. 2 shows VTFET 200 having contacts 214 and 234 that are directly connected to interconnect wiring and / or a power distribution network (not shown) on the front side of VTFET 200, and contact 224 that is directly connected to interconnect wiring and / or a power distribution network (not shown) on the back side of VTFET 200. In the second embodiment, VTFET 200 shares substantially similar features to those described above with reference to VTFET 100. For example, upper source / drain region 210 is substantially similar to upper source / drain region 110. It should be noted that, although a substrate similar to substrate 102 shown in FIG. 1 is not shown in FIG. 2, it is known to those skilled in the art that VTFET 200 can be formed on a substrate similar to substrate 102 shown in FIG. 1.

[0057] In the second embodiment, the orientation of the contacts in VTFET 200 is the primary difference compared to VTFET 100. In the second embodiment, contacts 214 and 234 are directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 200, and contact 224 is directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 200.

[0058] In a third embodiment, FIG. 3 shows VTFET 300 having contact 314 directly connected to interconnect wiring and / or a power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 directly connected to interconnect wiring and / or a power distribution network (not shown) on the back side of VTFET 300. In the third embodiment, VTFET 300 shares substantially similar features to those described above with reference to VTFET 100 and VTFET 200. For example, upper source / drain region 310 is substantially similar to upper source / drain region 110 and upper source / drain region 210. While a substrate similar to substrate 102 shown in FIG. 1 is not shown in FIG. 3, it should be noted that one skilled in the art would know that VTFET 300 can be formed on a substrate similar to substrate 102 shown in FIG. 1.

[0059] In the third embodiment, the orientation of the contacts in VTFET 300 is the primary difference compared to VTFET 100 and VTFET 200. In the third embodiment, contact 314 is directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 are directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 300.

[0060] 4 illustrates a circuit schematic of an SRAM 400 according to one embodiment of the present invention. In one embodiment, the SRAM 400 consists of six transistors: a first transistor 410, a second transistor 412, a third transistor 420, a fourth transistor 422, a fifth transistor 430, and a sixth transistor 432. As known in the art, this is also referred to as a 6T SRAM cell. As described herein, each of the six transistors is a VTFET structure. However, embodiments of the present invention recognize that some or all of these six transistors may be other types of transistors.

[0061] In one embodiment, each bit of the SRAM 400 cell is stored in a third transistor 420, a fourth transistor 422, a fifth transistor 430, and a sixth transistor 432. In one embodiment, the third transistor 420 and the fourth transistor 422 form a first inverter. In one embodiment, the fifth transistor 430 and the sixth transistor 432 form a second inverter. In one embodiment, the first inverter is cross-coupled with the second inverter. In other words, the output 440 of the first inverter is connected to the gate 446 of the second inverter, and the output 442 of the second inverter is connected to the gate 444 of the first inverter. In one embodiment, the output 440 of the first inverter is also connected to the source / drain region of the first transistor 410. In one embodiment, the output 442 of the second inverter is connected to the source / drain region of the second transistor 412. In one embodiment, the source / drain regions of both the third transistor 420 and the fifth transistor 430 are connected to power or VDD supplies 426 and 436, respectively. In one embodiment, the source / drain regions of both the fourth transistor 422 and the sixth transistor 432 are connected to ground or GND supplies 428 and 438, respectively. In one embodiment, the gate regions of the first transistor 410 and the second transistor 412 are connected to a word line 450. In one embodiment, the word line 450 controls read and write operations in the SRAM 400 cell. In one embodiment, the source / drain region of the first transistor 410 is connected to a bit line 460, and the source / drain region of the second transistor 412 is connected to a bit line bar 462. In one embodiment, the bit line 460 and the bit line bar 462 are used to transfer data for both read and write operations. It should be noted that an SRAM may include only bit line 460 or bit line bar 462, although both signals are generally provided to improve noise margin when reading and writing to an SRAM cell.As shown in FIG. 4, the first transistor 410, the second transistor 412, the fourth transistor 422, and the sixth transistor 432 are “n-type” transistors, and the third transistor 420 and the fifth transistor 430 are “p-type,” although other doping configurations may be implemented.

[0062] FIG. 5 illustrates a top view of two adjacent SRAMs 500 according to one embodiment of the present invention. As shown in FIG. 5, a first SRAM 502 cell is adjacent to a second SRAM 504 cell. For simplicity, only two cells are shown. However, one skilled in the art will recognize that any number of SRAM cells may be found adjacent to one another. While the internal transistors of each SRAM cell are not shown in FIG. 5, it should be noted that, as discussed above and below, each SRAM cell includes multiple transistors. In one embodiment, the first SRAM 502 cell is connected to a word line (not shown) by a word line contact 530. In one embodiment, the second SRAM 504 cell is connected to a word line (not shown) by a word line contact 532. In one embodiment, the SRAM 500 includes a bit line 510, a bit line bar 512, grounds 520, 522, or GND, and a power supply 525, or VDD. In one embodiment, bit lines 510, bit line bars 512, ground 520, ground 522, and power supply 525 are found on the backside of the SRAM cells. In other words, the SRAM cells are on top of a wafer (not shown), and bit lines 510, bit line bars 512, ground 520, ground 522, and power supply 525 are between the SRAM cells and the wafer. In one embodiment, word lines (not shown) are on the front side of the SRAM cells or above the SRAM cells. It should be noted that word lines and bit lines / bit line bars may be interchanged in alternative configurations, as discussed below. It should be noted that VDD and GND may be interchanged in alternative configurations, as discussed below.

[0063] 6 illustrates a top view of an SRAM 600 cell according to a first embodiment of the present invention. In one embodiment, the SRAM 600 cell includes a first transistor 630, a second transistor 640, a third transistor 650, a fourth transistor 670, a fifth transistor 660, and a sixth transistor 680. It should be noted that, as described with reference to the functions in FIG. 4, the first transistor 630 is similar to the first transistor 410, the second transistor 640 is similar to the second transistor 412, the third transistor 650 is similar to the third transistor 420, the fourth transistor 670 is similar to the fourth transistor 422, the fifth transistor 660 is similar to the fifth transistor 430, and the sixth transistor 680 is similar to the sixth transistor 432.

[0064] As shown in FIG. 6 , the SRAM 600 cell includes a backside power distribution network including a power supply (i.e., VDD) 625, ground (i.e., GND) 620, 622, bit line 610, and bit line bar 612. As discussed above, the backside power distribution network is found on the backside, or between the device layers (i.e., transistors) and the wafer on which the device layers are formed. As shown in FIG. 6 , the SRAM 600 cell includes word lines 628, 629 on either side of the SRAM 600 cell, which are connected to gate regions 632, 642 of a first transistor 630 and a second transistor 640, respectively. In one embodiment, the word lines 628, 629 are formed on the front side, or above the device layers, on the side of the wafer opposite the device layers. In one embodiment, the word lines 628, 629 are within the conventional back end of the line interconnect wiring. 6, the word lines 628, 629 are on a first metal layer directly above the transistors of the SRAM 600 cell. In an alternative embodiment, the word lines 628, 629 are on any metal layer above the transistors of the SRAM 600 cell, as long as contacts from the word lines 628, 629 extend to the gate regions 632, 642 of the first transistor 630 and the second transistor 640, respectively.

[0065] In an alternative embodiment, as described above, power supply 625 may actually provide ground, and grounds 620, 622 may provide power. In other words, power supply and ground are swapped or reversed. Those skilled in the art will recognize that in this alternative embodiment, the layout of third transistor 650, fourth transistor 670, fifth transistor 660, and sixth transistor 680 may be different. In an alternative embodiment, as described above, word lines 628, 629 may provide the functionality of bit line 610 and bit line bar 612, and bit line 610, bit line bar 612 may provide the functionality of word lines. In other words, in this alternative embodiment, the wiring of word lines is swapped or reversed with the wiring of bit lines and bit line bar. Those skilled in the art will recognize that in this alternative embodiment, the layout of the first transistor 630, the second transistor 640, the third transistor 650, the fourth transistor 670, the fifth transistor 660, and the sixth transistor 680 may be different.

[0066] 6 , a first transistor 630 includes a lower source / drain region (not shown), a fin 634, a gate region 632, and an upper source / drain region 636. In one embodiment, the lower source / drain region (not shown) is connected to a bit line 610 by a backside contact (not shown). In one embodiment, the gate region 632 is connected to a word line 628 through a front side contact (not shown). In one embodiment, the upper source / drain region 636 is connected to a cross couple 690 by a front side contact 638. In one embodiment, the lower source / drain region (not shown) may be for the first transistor 630. In an alternative embodiment, the lower source / drain region (not shown) may be a shared lower source / drain region that is also a shared lower source / drain region for any number of first transistors in adjacent SRAM cells (not shown). 6 , an end of the fin 634 and an end of the gate region 632 both extend and are aligned with the RX edge of the first transistor 630 closest to the third transistor 650. In an alternative embodiment, the end of the fin 634 and the end of the gate region 632 may not be aligned with each other and / or with the RX edge of the first transistor 630. For example, the edges of the fin 634 and the gate region 632 may be aligned with the left edge of the first transistor 630 farthest from the third transistor 650. In one embodiment, the fin 634 has a first length in the same direction as the longer length of the SRAM 600 cell and a second length that is shorter than the first length.

[0067] 6 , the second transistor 640 includes a lower source / drain region (not shown), a fin 644, a gate region 642, and an upper source / drain region 646. In one embodiment, the lower source / drain region (not shown) is connected to the bitline bar 612 by a backside contact (not shown). In one embodiment, the gate region 642 is connected to the wordline 629 through a frontside contact (not shown). In one embodiment, the upper source / drain region 646 is connected to the cross-couple 694 by a frontside contact 648. In one embodiment, the lower source / drain region (not shown) may be for the second transistor 640. In an alternative embodiment, the lower source / drain region (not shown) may be a shared lower source / drain region that is also a shared lower source / drain region for any number of second transistors in adjacent SRAM cells (not shown). 6 , an end of the fin 644 and an end of the gate region 642 both extend and are aligned with the RX edge of the second transistor 640 that is closest to the fifth transistor 660. In an alternative embodiment, the end of the fin 644 and the end of the gate region 642 may not be aligned with each other and / or with the RX edge of the second transistor 640. For example, the edges of the fin 644 and the gate region 642 may be aligned with the right edge of the second transistor 640 that is farthest from the fifth transistor 660. In one embodiment, the fin 644 has a first length in the same direction as the longer length of the SRAM 600 cell and a second length that is shorter than the first length.

[0068] 6 , the third transistor 650 includes a lower source / drain region (not shown), a fin 654, a shared gate region 652 / 672, and an upper source / drain region 656. In one embodiment, the lower source / drain region (not shown) is connected to ground 620 by a backside contact (not shown). In one embodiment, the shared gate region 652 / 672 is connected to a cross-coupled 694 by a front contact 696 and the fourth transistor 670, as discussed below. In one embodiment, the shared gate region 652 / 672 is the gate region for both the third transistor 650 and the fourth transistor 670. In one embodiment, the upper source / drain region 656 is connected to a cross-coupled 690 by a front contact 658. In one embodiment, the lower source / drain region (not shown) may be for the third transistor 650. In alternative embodiments, the lower source / drain region (not shown) may be a shared lower source / drain region that is also the shared lower source / drain region of any number of third transistors in adjacent SRAM cells (not shown). In one embodiment, as shown in FIG. 6, the end of the fin 654 and the end of the gate region 652 / 672 both extend and are aligned with the RX edge of the third transistor 650 closest to the first transistor 630. In alternative embodiments, the end of the fin 654 and the end of the gate region 652 / 672 may not be aligned with each other and / or with the RX edge of the third transistor 650. For example, the edge of the fin 654 may be aligned with the right edge of the second transistor 640 farthest from the first transistor 630. In one embodiment, the fin 654 has a first length in the same direction as the longer length of the SRAM 600 cell and a second length that is shorter than the first length.

[0069] 6 , the fifth transistor 660 includes a lower source / drain region (not shown), a fin 664, a shared gate region 662 / 682, and an upper source / drain region 666. In one embodiment, the lower source / drain region (not shown) is connected to ground 622 by a backside contact (not shown). In one embodiment, the shared gate region 662 / 682 is connected to a cross-coupled 690 by a front contact 692 and the sixth transistor 680, as discussed below. In one embodiment, the shared gate region 652 / 672 is the gate region for both the third transistor 650 and the fourth transistor 670. In one embodiment, the upper source / drain region 666 is connected to a cross-coupled 694 by a front contact 668. In one embodiment, the lower source / drain region (not shown) may be for the fifth transistor 660. In an alternative embodiment, the lower source / drain region (not shown) may be a shared lower source / drain region that is also the shared lower source / drain region of any number of fifth transistors in adjacent SRAM cells (not shown). In one embodiment, as shown in FIG. 6 , an end of the fin 664 and an end of the gate region 662 / 682 both extend and are aligned with the RX edge of the fifth transistor 660 closest to the second transistor 640. In an alternative embodiment, the end of the fin 664 and the end of the gate region 662 / 682 may not be aligned with each other and / or with the RX edge of the fifth transistor 660. For example, an edge of the fin 664 may be aligned with the left edge of the fifth transistor 660 farthest from the second transistor 640. In one embodiment, the fin 664 has a first length in the same direction as the longer length of the SRAM 600 cell and a second length that is shorter than the first length.

[0070] 6 , the fourth transistor 670 includes a lower source / drain region (not shown), a fin 674, a shared gate region 652 / 672, and an upper source / drain region 676. In one embodiment, the lower source / drain region (not shown) is connected to a power supply 625 by a backside contact (not shown). In one embodiment, the shared gate region 652 / 672 is connected to a cross-coupled 694 by a front contact 696 and the third transistor 650, as discussed above. In one embodiment, the shared gate region 652 / 672 is a gate region for both the third transistor 650 and the fourth transistor 670, as discussed above. In one embodiment, the upper source / drain region 676 is connected to a cross-coupled 690 by a front contact 678. In one embodiment, the lower source / drain region (not shown) may be for the fourth transistor 670. In alternative embodiments, the lower source / drain region (not shown) may be a shared lower source / drain region that is also the shared lower source / drain region of any number of fourth transistors in adjacent SRAM cells (not shown). In one embodiment, as shown in FIG. 6, an end of the fin 674 and an end of the gate region 652 / 672 both extend and are aligned with the RX edge of the fourth transistor 670 closest to the sixth transistor 680. In alternative embodiments, the end of the fin 674 and the end of the gate region 652 / 672 may not be aligned with each other and / or with the RX edge of the fourth transistor 670 closest to the third transistor 650. For example, the edge of the fin 674 and the edge of the gate region 652 / 672 may be aligned with the left edge of the fourth transistor 670 closest to the third transistor 650. In one embodiment, the fin 674 has a first length in the same direction as the longer length of the SRAM 600 cell and a second length that is shorter than the first length.

[0071] 6 , the sixth transistor 680 includes a lower source / drain region (not shown), a fin 684, a shared gate region 662 / 682, and an upper source / drain region 686. In one embodiment, the lower source / drain region (not shown) is connected to a power supply 625 by a backside contact (not shown). In one embodiment, the shared gate region 662 / 682 is connected to a cross-coupled 690 by a front contact 692 and the fifth transistor 660, as discussed above. In one embodiment, the shared gate region 662 / 682 is a gate region for both the fifth transistor 660 and the sixth transistor 680, as discussed above. In one embodiment, the upper source / drain region 686 is connected to a cross-coupled 694 by a front contact 688. In one embodiment, the lower source / drain region (not shown) may be for the sixth transistor 680. In alternative embodiments, the lower source / drain region (not shown) may be a shared lower source / drain region that is also the shared lower source / drain region of any number of sixth transistors in adjacent SRAM cells (not shown). In one embodiment, as shown in FIG. 6 , an end of the fin 684 and an end of the gate region 662 / 682 both extend and are aligned with the RX edge of the sixth transistor 680 closest to the fourth transistor 670. In alternative embodiments, the end of the fin 684 and an end of the gate region 662 / 682 may not be aligned with each other and / or with the RX edge of the sixth transistor 680 closest to the fifth transistor 660. For example, the edge of the fin 684 and the edge of the gate region 662 / 682 may be aligned with the right edge of the sixth transistor 680 closest to the fifth transistor 660. In one embodiment, the fin 684 has a first length in the same direction as the longer length of the SRAM 600 cell and a second length that is shorter than the first length.

[0072] In one embodiment, as discussed above, the SRAM 600 cell includes a cross couple 690 and a cross couple 694. In one embodiment, the cross couple 690 and the cross couple 694 are on any metal layer above the transistors of the SRAM 600 cell. In one embodiment, the cross couple 690 and the cross couple 694 may be metal wire tracks. In one embodiment, the cross couple 690 is connected to the first transistor 630 by a front contact 638, to the third transistor 650 by a front contact 658, to the fourth transistor 670 by a front contact 678, and to the shared gate region 662 / 682 by a front contact 692. In one embodiment, the cross couple 694 is connected to the second transistor 640 by a front contact 648, to the fifth transistor 660 by a front contact 668, to the sixth transistor 680 by a front contact 688, and to the shared gate region 652 / 672 by a front contact 696.

[0073] FIG. 7 illustrates a cross-sectional view of section X of an SRAM 700 cell according to one embodiment of the present invention. In one embodiment, as illustrated in FIG. 7, the SRAM 700 cell includes a backside power delivery network including a power supply (i.e., VDD) 725, grounds (i.e., GND) 720, 722, bit lines 710, and bit line bars 712. As discussed above, the backside power delivery network is found on the backside or between the device layers (i.e., transistors) and the wafer on which the device layers are formed. In one embodiment, the power supply 725 may be connected to the backside power delivery network by a backside power delivery network contact 725A. In one embodiment, the grounds 720, 722 may be connected to the backside power delivery network by backside power delivery network contacts 720A, 722A, respectively. In one embodiment, the bit lines 710 may be connected to the backside power delivery network by a backside power delivery network contact 710A. In one embodiment, the bit line bars 712 may be connected to the backside power delivery network by a backside power delivery network contact 712A.

[0074] In one embodiment, a bitline 710 is connected to lower source / drain region 711. In one embodiment, a bitline bar 712 is connected to lower source / drain region 713. In one embodiment, a ground 720 is connected to lower source / drain region 721. In one embodiment, a ground 722 is connected to lower source / drain region 723. In one embodiment, a power supply 725 is connected to shared lower source / drain region 726. In an alternative embodiment, shared lower source / drain region 726 may be two individual and separate lower source / drain regions for each VTFET.

[0075] As shown in FIG. 7 , the SRAM 700 cell includes word lines 728, 729 on either side of the SRAM 700 cell, which connect to gate regions 732, 742 of the first transistor 630 and the second transistor 640, respectively. In one embodiment, the word lines 728, 729 are formed on the front side, or above the device layer, on the side of the wafer opposite the device layers formed thereon. In one embodiment, the word lines 728, 729 are in the conventional back end of the line interconnect wiring. As shown in FIG. 7 , the word lines 728, 729 are on the first metal layer directly above the transistors of the SRAM 600 cell. In an alternative embodiment, the word lines 728, 729 may be on any metal layer above the transistors of the SRAM 600 cell, as long as contacts from the word lines 728, 729 extend to the gate regions 732, 742 of the first transistor 630 and the second transistor 640, respectively. In one embodiment, word lines 728, 729 are connected to gate regions 732, 742, respectively, by front contacts.

[0076] In one embodiment, the gate region 732 surrounds at least a portion of the fin 734, which is connected to an upper source / drain region 736. In one embodiment, the upper source / drain region 736 is connected to a front contact 738, which is connected to a cross couple 690 (not shown), as discussed above. In one embodiment, the gate region 742 surrounds at least a portion of the fin 744, which is connected to an upper source / drain region 746. In one embodiment, the upper source / drain region 746 is connected to a front contact 748, which is connected to a cross couple 694 (not shown), as discussed above.

[0077] In one embodiment, the shared gate region 752 / 772 surrounds at least a portion of the fin 754 and the fin 774. In one embodiment, the fin 754 is connected to the upper source / drain region 756. In one embodiment, the upper source / drain region 756 is connected to the front contact 758, as discussed above, and the front contact 758 is connected to a cross couple 690 (not shown). In one embodiment, the fin 774 is connected to the upper source / drain region 776. In one embodiment, the upper source / drain region 776 is connected to the front contact 778, as discussed above, and the front contact 778 is connected to a cross couple 690 (not shown). In one embodiment, the shared gate region 752 / 772 is connected to the front contact 796, as discussed above, and the front contact 796 is connected to a cross couple 694 (not shown).

[0078] In one embodiment, the shared gate region 762 / 782 surrounds at least a portion of the fin 764 and the fin 784. In one embodiment, the fin 764 is connected to an upper source / drain region 766. In one embodiment, the upper source / drain region 766 is connected to a front contact 768, as discussed above, and the front contact 768 is connected to a cross couple 694 (not shown). In one embodiment, the fin 784 is connected to an upper source / drain region 786. In one embodiment, the upper source / drain region 786 is connected to a front contact 788, as discussed above, and the front contact 788 is connected to a cross couple 694 (not shown). In one embodiment, the shared gate region 762 / 782 is connected to a front contact 792, as discussed above, and the front contact 792 is connected to a cross couple 690 (not shown).

[0079] FIG. 8 illustrates a cross-sectional view of section Y of an SRAM 800 cell according to one embodiment of the present invention. In one embodiment, as illustrated in FIG. 8, the SRAM 800 cell includes a backside power delivery network including a power supply (i.e., VDD) 825, grounds (i.e., GND) 820, 822, bit lines 810, and bit line bars 812. As discussed above, the backside power delivery network is found on the backside or between the device layers (i.e., transistors) and the wafer on which the device layers are formed. In one embodiment, the power supply 825 may be connected to the backside power delivery network by a backside power delivery network contact 824. In one embodiment, the grounds 820, 822 may be connected to the backside power delivery network by backside power delivery network contacts 819, 821, respectively. In one embodiment, the bit lines 810 may be connected to the backside power delivery network by a backside power delivery network contact 809. In one embodiment, the bit line bars 812 may be connected to the backside power delivery network by a backside power delivery network contact 812A. In one embodiment, the power supply 825 may be connected to the backside power delivery network by a backside power delivery network contact 825A. In one embodiment, the grounds 820, 822 may be connected to the backside power delivery network by backside power delivery network contacts 820A, 822A, respectively. In one embodiment, the bit line 810 may be connected to the backside power delivery network by a backside power delivery network contact 810A. In one embodiment, the bit line bar 812 may be connected to the backside power delivery network by a backside power delivery network contact 812A.

[0080] In one embodiment, a bitline 810 is connected to lower source / drain region 811. In one embodiment, a bitline bar 812 is connected to lower source / drain region 813. In one embodiment, a ground 820 is connected to lower source / drain region 821. In one embodiment, a ground 822 is connected to lower source / drain region 823. In one embodiment, a power supply 825 is connected to shared lower source / drain region 826. In an alternative embodiment, shared lower source / drain region 826 may be two individual and separate lower source / drain regions for each VTFET.

[0081] 8, the SRAM 800 cell includes a cross couple 890. In one embodiment, the cross couple 890 is connected to a front contact 838, a front contact 858, a front contact 878, and a front contact 892. In one embodiment, the front contact 838 is connected to an upper source / drain region (not shown), as discussed above. In one embodiment, the front contact 858 is connected to an upper source / drain region (not shown), as discussed above. In one embodiment, the front contact 878 is connected to an upper source / drain region (not shown), as discussed above. In one embodiment, the front contact 892 is connected to a shared gate region (not shown), as discussed above.

[0082] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0083] In a preferred embodiment of the invention described herein, a semiconductor memory cell is provided that includes a plurality of vertical transport field effect transistors (VTFETs) on a wafer, each VTFET of the plurality of VTFETs being in a first layer, and six VTFETs of the plurality of VTFETs forming a memory cell; and at least one memory cell being in a column adjacent to at least one other memory cell.

[0084] In a preferred embodiment of the invention described herein, a semiconductor SRAM is provided that includes six vertical transport field effect transistors (VTFETs) on a wafer, six VTFETs in a first layer and six VTFETs in a first column.

[0085] In a preferred embodiment of the invention described herein, a semiconductor memory array is provided including a plurality of vertical transport field effect transistors (VTFETs) on a wafer, wherein six of the plurality of VTFETs are arranged in one or more memory cells in a first layer on the wafer, each of the one or more memory cells being arranged in a column. Each of the one or more memory cells may share a first contiguous lower source / drain region for a first VTFET and a second VTFET in the respective memory cell, the first contiguous lower source / drain region being connected to a power supply network on the backside of the wafer. Each of the one or more memory cells may share a second contiguous lower source / drain region for a third VTFET and a fourth VTFET in the respective memory cell, the second contiguous lower source / drain region being connected to a power supply network on the backside of the wafer. Each memory cell of the one or more memory cells may share a third contiguous lower source / drain region for a fifth VTFET and a fourth contiguous lower source / drain region for a sixth VTFET in the respective memory cell, the third contiguous lower source / drain region being connected to a power delivery network on the backside of the wafer, and the fourth contiguous lower source / drain region being connected to a power delivery network on the backside of the wafer.

[0086] In a preferred embodiment of the invention described herein, a semiconductor memory array is provided on a wafer, the semiconductor memory array including one or more vertical transistors arranged in one or more memory cells of a first layer, each memory cell of the one or more memory cells being in a column.

Claims

1. A semiconductor memory cell comprising six vertical transport field effect transistors (VTFETs) on a wafer, the six VTFETs being in a first layer and the six VTFETs being in a first column.

2. 2. The semiconductor memory cell of claim 1, wherein the power supplies of two of the six VTFETs are connected to a power supply network on the backside of the wafer.

3. 2. The semiconductor memory cell of claim 1, wherein the grounds of two of said six VTFETs are connected to a power supply network on the backside of said wafer.

4. 2. The semiconductor memory cell of claim 1, wherein a bit line and a bit line bar for two of the six VTFETs are connected to a power supply network on the backside of the wafer, and a word line for two of the six VTFETs is connected to a power supply network on the frontside of the wafer.

5. 2. The semiconductor memory cell of claim 1, wherein a bit line and a bit line bar for two of the six VTFETs are connected to a power delivery network on the front side of the wafer, and a word line for two of the six VTFETs is connected to a power delivery network on the back side of the wafer.

6. 10. The semiconductor memory cell of claim 1, wherein a first metal wire electrically connects a source / drain region of the first VTFET, a source / drain region of the second VTFET, a source / drain region of the third VTFET, a gate region of the fourth VTFET, and a gate region of the fifth VTFET.

7. 7. The semiconductor memory cell of claim 6, wherein a second metal wire electrically connects a gate region of the second VTFET, a gate region of the third VTFET, a source / drain region of the fourth VTFET, a source / drain region of the fifth VTFET, and a source / drain region of a sixth VTFET.

8. The semiconductor memory cell of claim 6 , wherein the first metal wire is within the semiconductor memory cell.

9. The semiconductor memory cell of claim 7 , wherein the second metal wire is within the semiconductor memory cell.

10. The semiconductor memory cell of claim 1 , wherein a fin edge and a gate edge of one or more of said six VTFETs are aligned with an RX edge.

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