Multipurpose low frequency eddy current array (ECA)

Abstract

A configuration for a sensor or coil assembly for performing eddy current (EC) testing is described. The sensor assembly can be fabricated using a printed circuit board (PCB) structure, such as including a flex circuit with a dielectric layer and a metallized layer. Adjacent coil elements can include overlapping portions, where the currents in the overlapping portions cancel each other out, resulting in a conceptually larger coil that can be used to support various receive or transmit configurations.

Description

[Technical Field]

[0001] Priority claims This patent application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 477,655, filed December 29, 2022, and entitled "MULTI-PURPOSE LOW-FREQUENCY EDDY CURRENT ARRAY (ECA)," the entirety of which is incorporated herein by reference.

[0002] This document relates generally, but not exclusively, to apparatus and techniques for non-destructive testing, such as facilitating eddy current testing, and more particularly to apparatus and techniques for providing eddy current array (ECA) probe assemblies with printed circuit board (PCB) structures, such as flexible circuits. [Background technology]

[0003] Nondestructive testing (NDT) can refer to the use of one or more different techniques to inspect an area on or within an object, for example, to determine whether flaws or defects are present in the inspected object or to otherwise characterize the inspected object. Some types of nondestructive testing can involve the use of eddy current testing approaches, in which electromagnetic energy is applied to an object by one or more probes, and the resulting induced current is detected on or within the object, with the value of the detected current (or associated impedance) providing an indication of the structure of the object under test, such as the presence of cracks, voids, porosity, or other inhomogeneities. Generally, eddy current (EC) sensors include one or more sensor elements, such as an induction coil that can be excited using an alternating current (AC) source. Such coils (or other electromagnetic sensing elements, such as Hall sensors) can be used to receive signals indicative of induced eddy currents on or within the structure. Summary of the Invention

[0004] Examples described herein relate to a coil array for eddy current (EC) inspection, including a first coil and a second coil disposed adjacent to the first coil, a first portion of the first coil overlapping a second portion of the second coil, the first portion of the first coil configured to allow a first current to flow in a first direction, and the second portion of the second coil configured to allow a second current to flow in a second direction, the first and second directions being substantially opposite.

[0005] Examples described herein relate to a method for eddy current (EC) inspection that includes providing a first coil and a second coil disposed adjacent to the first coil, wherein a first portion of the first coil overlaps a second portion of the second coil, and actuating the first coil and the second coil, wherein a first current associated with the first portion of the first coil flows in a first direction and a second current associated with the second portion of the second coil flows in a second direction, the first direction and the second direction being substantially opposite.

[0006] Examples described herein relate to a coil assembly for eddy current (EC) inspection, comprising a first set of coil elements disposed on one or more layers of a first set of printed circuit boards (PCBs) and a second set of coil elements disposed on one or more layers of a second set of PCBs, wherein at least one coil element of the first set of coil elements overlaps with at least one coil element of the second set of coil elements at an overlapping portion.

[0007] The subject matter of this specification may be better understood by referring to the following description in conjunction with the accompanying drawings. The drawings are not meant to limit the scope of the claims contained herein. For clarity, not every element may be labeled in every figure. The drawings are not necessarily to scale, emphasis instead being placed on illustrating embodiments, principles, and concepts. Thus, the features and advantages of the present disclosure will become more apparent from the following detailed description of embodiments thereof in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1A] 1 shows a simplified block diagram of an exemplary portion of a coil. [Figure 1B] FIG. 1 shows a simplified block diagram of an exemplary portion of an overlapping coil configuration. [Figure 1C] 1 shows a simplified tracing of an exemplary portion of an overlapping coil configuration. [Figure 2A] 1 illustrates an exemplary portion of an overlapping coil configuration on multiple layers of a PCB. [Figure 2B] 1 illustrates an exemplary portion of an overlapping coil configuration on multiple layers of a PCB. [Figure 2C] 1 illustrates an exemplary portion of an overlapping coil configuration on multiple layers of a PCB. [Figure 2D] 1 illustrates an exemplary portion of an overlapping coil configuration on multiple layers of a PCB. [Figure 2E] 1 illustrates an exemplary portion of an overlapping coil configuration on multiple layers of a PCB. [Figure 2F] 1 illustrates an exemplary portion of an overlapping coil configuration on multiple layers of a PCB. [Figure 2G] 1 illustrates an exemplary portion of an overlapping coil configuration on multiple layers of a PCB. [Figure 2H] 1 illustrates an exemplary portion of an overlapping coil configuration on multiple layers of a PCB. [Figure 3] 1 illustrates an exemplary portion of a coil assembly array having an overlapping coil configuration. [Figure 4] 1 illustrates an exemplary coil configuration of a coil assembly array for detecting longitudinal defects. [Figure 5] 3 illustrates an exemplary coil configuration of a coil assembly array 300 for detecting lateral defects. DETAILED DESCRIPTION OF THE INVENTION

[0009] A configuration for a sensor or coil assembly for performing eddy current (EC) testing is described. The sensor assembly can be fabricated using a printed circuit board (PCB) structure, such as including a flex circuit including a dielectric layer and a metallization layer. The metallization layer can define coil elements or provide electrical connections to the coil elements, and such elements can be operated by a multiplexer assembly for transmit and receive to support scans associated with different defect orientations. Adjacent coil elements can include overlapping portions, where currents in the overlapping portions cancel each other, resulting in a conceptually larger coil that can be used to support various receive or transmit configurations.

[0010] FIG. 1A shows a simplified block diagram of an exemplary portion of a coil 100. The coil 100 may have a width (w) parameter and a height (h) parameter. The coil 100 may include a metallization layer, such as a trace, and is configured for use in EC testing. For example, the coil 100 may be excited to generate electromagnetic energy for transmission to a test object, and the coil 100 may receive a resulting EC signal induced in the test object. For example, the EC signal may be used to detect different types of defects in the test object.

[0011] In some conventional systems, multiple coils (or coil elements) are arranged in an array. In these arrays, there is typically space between adjacent coils. This space between adjacent coils can reduce the sensitivity of the EC test.

[0012] 1B shows a simplified block diagram of an exemplary portion of an overlapping coil configuration. The overlapping coil configuration may include a first coil 100 and a second coil 102 having an overlapping portion 104. The first coil 100 and the second coil 102 may correspond to width (w) and height (h) parameters. In some examples, the first coil 100 and the second coil 102 may have the same width and height parameters.

[0013] The first coil 100 and the second coil 102 may be adjacent coils in the array, but with no space between the two coils. Instead, the two coils may overlap with an overlap portion 104 having a width (o). The overlap portion 104 may include one or more sets of traces belonging to the first coil 100 and one or more sets of traces belonging to the second coil 102. The orientation of each trace within the overlap portion 104 may result in opposing currents that cancel each other out, resulting in a response from the substantially larger coil without the overlap portion that is the combination of the first coil 100 and the second coil 102. The width of the larger coil may be expressed as (w1) + (w2) - (o), where (w1) is the width of the first coil 100, (w2) is the width of the second coil 102, and (o) is the width of the overlap portion. If the two coils have the same width, the width of the larger coil may be expressed as 2(w) - (o).

[0014] FIG. 1C shows a simplified tracing diagram of an exemplary portion of an overlapping coil configuration. The first coil 100 includes multiple traces. For example, the first coil 100 may include one or more sets of traces disposed on one or more layers of a printed circuit board (PCB). The second coil 102 includes multiple traces. For example, the second coil 102 may include one or more sets of traces disposed on one or more layers of a PCB. The overlapping portion 104 may include a portion of the traces for the first coil 100 and a portion of the traces for the second coil 102, such that, in the overlapping portion 104, the current induced in a portion of the traces for the first coil 100 is in the opposite direction to the current induced in a portion of the traces for the second coil 102. Thus, the overlapping portion 104 does not contribute to the induced EC signal (or transmission) from the coils 100, 102, and the two coils 100, 102 may effectively act as one larger coil. In practical applications, during receive, there may be little actual current flowing in the coils 100, 102 since the input may be high impedance, but the coils are configured as described herein to act as a larger coil during receive where the overlapping portion 104 does not contribute to the induced EC signal.

[0015] In some examples, one or more sets of traces for the first coil 100 may be provided on one or more (2, 4, 8, etc.) layers of a first set of PCBs, and one or more sets of traces for the second coil may be provided on one or more layers of a second set of PCBs.

[0016] 2A-2H show an example portion of an overlapping coil configuration on multiple layers of a PCB, where the PCB may include at least eight layers. Traces for the first coil 100 may be provided on layers 1, 4, 5, and 8 of the PCB, and traces for the second coil 102 may be provided on layers 2, 3, 6, and 7 of the PCB, as described in more detail below.

[0017] As shown in FIG. 2A, a first set of traces 200 for a first coil (left coil) is provided (eg, fabricated) on a first layer of a PCB.

[0018] 2B, a first set of traces 250 for the second coil (right coil) is provided on the second layer of the PCB. In the overlapping portion, a portion of the first set of traces 200 for the left coil overlaps a portion of the first set of traces 250 for the right coil. For example, the overlapping portion of the first set of traces 200 for the left coil is associated with current flow in a first direction, and the overlapping portion of the first set of traces 250 for the right coil is associated with current flow in a second direction opposite the first direction.

[0019] 2C, a second set of traces 252 for the right coil is provided on the third layer of the PCB, with a portion of the second set of traces 252 for the right coil provided in the overlapping portion.

[0020] 2D, the second set of traces 202 for the left coil are provided on the fourth layer of the PCB, with portions of the second set of traces 202 for the left coil provided in the overlapping portion.

[0021] 2E, the third set of traces 204 for the left coil is provided on the fifth layer of the PCB, with a portion of the third set of traces 204 for the left coil provided in the overlapping portion.

[0022] 2F, a third set of traces 254 for the right and left coils is provided on the sixth layer of the PCB, with a portion of the third set of traces 254 for the right coil provided in the overlapping portion.

[0023] 2G, a fourth set of traces 256 for the right coil is provided on the seventh layer of the PCB, with portions of the fourth set of traces 256 for the right coil provided in the overlapping portion.

[0024] 2H, a fourth set of traces 206 for the left coil is provided on the eighth layer of the PCB, with portions of the fourth set of traces 206 for the left coil provided in the overlapping portion.

[0025] The current flow in the set of traces 200-206 in the overlapping portion for the left coil is in a first direction, and the current flow in the set of traces 250-256 for the right coil in the overlapping portion is in a second, opposite direction such that the currents in the overlapping portion cancel each other out. Thus, when activated, the sets of traces 200-206, 250-256 can function as a larger coil for EC testing for both transmit and receive.

[0026] The overlapping coil configuration can be applied to a coil assembly array. FIG. 3 shows an example portion of a coil assembly array 300 having an overlapping coil configuration. The coil assembly array 300 may include a first row of coils 302.1-302.n (e.g., n=31 in this example). The coils 302.1-302.n may be arranged in an overlapping coil configuration as described herein. For example, coil 302.1 may overlap adjacent coil 302.2, which may overlap adjacent coil 302.3, which may overlap adjacent coil 302.4, etc. The coils 302.1-302.n may be arranged on multiple layers of a PCB. For example, the odd-numbered coils (302.1, 302.3, 302.5, ...) may be provided on a first set of layers of the PCB, and the even-numbered coils (302.2, 302.4, 302.6, ...) may be provided on a second set of layers of the PCB. Referring to the example illustrated in Figures 2A-2H, the odd-numbered coils (302.1, 302.3, 302.5, ...) may be provided on layers 1, 4, 5, and 8 of the PCB, and the even-numbered coils (302.2, 302.4, 302.6, ...) may be provided on layers 2, 3, 6, and 7 of the PCB.

[0027] The coil assembly array 300 may include a second row of coils 304.1-304.n (e.g., n=31 in this example). The first row of coils and the second row of coils may be separated by a distance (s). The coils 304.1-304.n may be arranged in an overlapping coil configuration, as described herein. For example, coil 304.1 may overlap adjacent coil 304.2, which may overlap adjacent coil 304.3, which may overlap adjacent coil 304.4, etc. The coils 304.1-304.n may be arranged on multiple layers of a PCB. For example, the odd-numbered coils (304.1, 304.3, 304.5, ...) may be provided on a first set of layers of the PCB, and the even-numbered coils (304.2, 304.4, 304.6, ...) may be provided on a second set of layers of the PCB. Referring to the example illustrated in Figures 2A-2H, the odd-numbered coils (304.1, 304.3, 304.5, ...) may be provided on layers 1, 4, 5, and 8 of the PCB, and the even-numbered coils (304.2, 304.4, 304.6, ...) may be provided on layers 2, 3, 6, and 7 of the PCB.

[0028] The coil assembly array 300 having an overlapping coil configuration can be used to perform EC inspections with different transmit and receive configurations. The different configurations can be used to detect defects of different orientations. For example, a different configuration using an overlapping coil configuration can be used to detect longitudinal and transverse defects.

[0029] FIG. 4 illustrates an exemplary coil configuration of a coil assembly array 300 for detecting longitudinal defects. In this example, a second row of coils 304.1 may be excited for transmission using a first transmission area 402 during each time slot. The first transmission area 402 may include coil 304.1 for transmitting signals used for EC inspection. The first row of coils 302.1, 302.2 may be activated to receive EC signals using a first receiving area 404. The first receiving area 404 may include coils 302.1, 302.2 that share overlapping portions with opposing currents, such that the first receiving area 404 functions as a larger coil including coils 302.1, 302.2, improving sensitivity for EC inspection.

[0030] Additional sets of coils may also be used within each time slot. In this example, a second row of coils 304.18 may be excited for transmission within each time slot using a second transmission area 406. The second transmission area 406 may include coil 304.18. The first row of coils 302.18, 302.19 may be activated to receive EC signals using a second reception area 408. The second reception area 408 may include coils 302.18, 302.19 that share overlapping portions with opposing currents, such that the second reception area 408 may function as a larger coil that includes coils 302.18, 302.19.

[0031] FIG. 5 illustrates an exemplary coil configuration of the coil assembly array 300 for detecting lateral defects. In this example, a second row of coils 304.1 may be excited for transmission using a first transmission area 502 during each time slot. The first transmission area 502 may include coil 304.1. The second row of coils 304.3 and 304.4 may be activated to receive EC signals using a first reception area 504. The first reception area 504 may include coils 304.3 and 304.4 that share overlapping portions with opposing currents, such that the first reception area 504 functions as a larger coil including coils 304.3 and 304.4, improving sensitivity for EC inspection.

[0032] Additional sets of coils may also be used within each time slot. In this example, a second row of coils 304.18 may be excited for transmission within each time slot using a second transmit area 506. The second transmit area 506 may include coil 304.18. The second row of coils 304.20, 304.21 may be activated to receive EC signals using a second receive area 508. The second receive area 508 may include coils 304.20, 304.21 that share overlapping portions with opposing currents, such that the second receive area 508 functions as a larger coil including coils 304.20, 304.21, improving sensitivity for EC testing.

[0033] Processing (e.g., performing one or more of the methods described herein) may be implemented in hardware, software, or a combination of the two. Processing may be implemented in a computer program running on a programmable computer / machine, each including a processor, a storage medium, or other article of manufacture readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and one or more output devices. Program code may be applied to data entered using the input device to perform processing and generate output information. Memory may include a machine-readable medium on which one or more sets of data structures or instructions (e.g., software) are stored that embody or are utilized by any one or more of the techniques or functions described herein.

[0034] In some embodiments, the system may be embodied by one or more programmable processors executing one or more computer programs to perform the functions of the system. In some other embodiments, all or a portion of the system may be implemented as special purpose logic circuitry (e.g., a field programmable gate array (FPGA) and / or an application specific integrated circuit (ASIC)). In some other embodiments, all or a portion of the system may be implemented using electronic hardware circuitry including, for example, electronic devices such as at least one of a processor, a memory, a programmable logic device, or logic gates.

[0035] In one embodiment, the methods described herein are not limited to the specific examples described. Rather, in further embodiments, any of the method steps may be rearranged, combined, or eliminated, or performed in parallel or sequentially as necessary to achieve the results described above.

[0036] In some embodiments, the system may be implemented, at least in part, via a computer program product (e.g., a non-transitory machine-readable storage medium, such as a non-transitory computer-readable medium) to be executed by or to control the operation of a data processing device (e.g., a programmable processor, computer, or multiple computers). In certain embodiments, each such program may be implemented in a high-level procedural or object-oriented programming language to communicate with a computer system. However, in certain other embodiments, the program may be implemented in assembly or machine language. In some embodiments, the language may be a compiled or interpreted language and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. In some other embodiments, the computer program may be deployed to be executed on one computer or multiple computers at one site, or distributed across multiple sites and interconnected by a communications network.

[0037] The disclosed methods and apparatus may take, at least in part, the form of program code (i.e., instructions) embodied in a tangible, non-transitory medium, such as a floppy diskette, a CD-ROM, a hard drive, a random-access or read-only memory, or any other machine-readable storage medium. When the program code is loaded and executed on a machine, such as the computer of FIG. 4, the machine becomes an apparatus for practicing examples of the inventive subject matter. When implemented on one or more general-purpose processors, the program code combines with such processors to provide a unique apparatus that operates analogously to specific logic circuits. Thus, a general-purpose digital machine can be transformed into a special-purpose digital machine. In some other embodiments, the non-transitory machine-readable medium may include, but is not limited to, a hard drive, a compact disk, a flash memory, a non-volatile memory, a volatile memory, a magnetic diskette, etc., but does not include the transitory signal itself.

[0038] The terms "machine-readable medium" or "machine-readable storage medium" may include any medium capable of storing, encoding, or retaining instructions for execution by a machine, causing a machine to perform any one or more of the techniques of this disclosure, or capable of storing, encoding, or retaining data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, and optical and magnetic media. Thus, a machine-readable medium is not a transitory, propagating signal. Specific examples of cohesive machine-readable media may include non-volatile memory such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices, magnetic or other phase-change or state-change memory circuits, magnetic disks such as internal hard disks and removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0039] Although the above examples have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. The scope of the present invention is limited only by the claims, and the present invention encompasses numerous alternatives, modifications, and equivalents. Many specific details have been set forth in the above specification to provide a thorough understanding of the present invention. These details are provided for illustrative purposes, and the present invention may be practiced according to the claims without some or all of these specific details. For clarity, technical material known in the art relevant to the present invention has not been described in detail so as not to unnecessarily obscure the present invention. Therefore, the above implementations should be considered illustrative and not limiting, and the present invention is not limited to the details given herein, but may be modified within the scope of the appended claims and their equivalents.

[0040] Various embodiments of the present disclosure are described with reference to the accompanying drawings. It can be understood that these exemplary embodiments are provided solely to enable those skilled in the art to better understand the present disclosure and then further practice the present invention, and are not intended to limit the scope of the present disclosure in any manner. It should be noted that these drawings and descriptions are presented only as examples of embodiments, and based on this description, alternative embodiments that may have the structures and methods as disclosed herein can be envisioned, and such alternative embodiments can be used without departing from the principles of the present disclosure as claimed in the present disclosure.

[0041] It may be noted that the flowcharts and block diagrams in the figures may illustrate apparatuses, methods, and architectures, functions, and operations executable by computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, program segment, or portion of code, which may include one or more executable instructions for implementing the specified logical function(s). It should be further noted that in some alternative implementations, the functions indicated in the blocks may occur in an order different from the order illustrated in the figures. For example, two blocks shown in succession may be performed substantially in parallel or in the reverse order, depending on the functionality involved. It should be further noted that each block and combination of blocks in the block diagrams or flowcharts may be implemented by a dedicated hardware-based system for implementing the specified function(s) or operation(s), or by a combination of dedicated hardware and computer instructions.

[0042] As used herein, the terms "comprise," "include," and their derivatives and similar expressions should be understood to be open (i.e., "comprising / including, but not limited to"). The term "based on" means "based at least in part on," the term "in one embodiment" means "at least one embodiment," and the term "in another embodiment" refers to "at least one further embodiment." Relevant definitions of other terms are provided.

[0043] As used herein, the terms "a" or "an" are used, as is common in patent documents, to include one or more, regardless of any other instance or usage of "at least one" or "one or more." As used herein, the term "or" is used to refer to a non-exclusive or, unless otherwise indicated, such that "A or B" includes "A but not B," "B but not A," and "A and B." As used herein, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, i.e., systems, devices, articles, compositions, formulations, or processes that include elements in addition to those recited after such terms in a claim are still deemed to be within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0044] The example methods described herein may be at least partially implemented in a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the examples. Implementations of such methods may include code, such as microcode, assembly language code, higher-level language code, etc. Such code may include computer-readable instructions for implementing various methods. The code may form part of a computer program product. Furthermore, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0045] The above description is intended to be illustrative, not limiting. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other implementations may be used by those of ordinary skill in the art who review the above description. The Abstract is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be construed as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed implementation. Thus, the following claims are incorporated into the Detailed Description as an example or implementation, and it is contemplated that each claim stands alone as a separate implementation, and that such implementations can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claims

1. 1. A coil array for eddy current (EC) inspection, comprising: a first coil; a second coil disposed adjacent to the first coil; Equipped with a first portion of the first coil overlapping a second portion of the second coil; a coil array, wherein the first portion of the first coil is configured to allow a first current to flow in a first direction and the second portion of the second coil is configured to allow a second current to flow in a second direction, the first direction and the second direction being substantially opposite.

2. 10. The coil array of claim 1, wherein the first coil comprises a first set of one or more traces disposed on one or more layers of a first set of printed circuit boards (PCBs), and the second coil comprises a second set of one or more traces disposed on one or more layers of a second set of PCBs.

3. further comprising a third coil disposed adjacent to the second coil; a third portion of the third coil overlapping with a fourth portion of the second coil; The coil array of claim 1 , wherein the third portion of the third coil is configured to allow a third current to flow in the first direction.

4. a first set of traces for the first coil is provided on a first layer of a printed circuit board (PCB); 10. The coil array of claim 1, wherein a first set of traces for the second coil is provided on a second layer of the PCB.

5. a second set of traces for the second coil is provided on a third layer of the PCB; 5. The coil array of claim 4, wherein a second set of traces for the first coil is provided on a fourth layer of the PCB.

6. a third set of traces for the first coil is provided on a fifth layer of the PCB; 6. The coil array of claim 5, wherein a third set of traces for the second coil is provided on a sixth layer of the PCB.

7. a fourth set of traces for the second coil is provided on a seventh layer of the PCB; 7. The coil array of claim 6, wherein a fourth set of traces for the second coil is provided on an eighth layer of the PCB.

8. The coil array of claim 1 , wherein the first coil and the second coil are configured to be operated together to operate as a substantially larger coil for receiving EC signals.

9. 10. The coil array of claim 1, wherein the first coil and the second coil are configured to operate together substantially as a larger coil to transmit at least one signal used for EC testing.

10. 1. A method for eddy current (EC) inspection, comprising: providing a first coil; providing a second coil disposed adjacent to the first coil, a first portion of the first coil overlapping a second portion of the second coil; and actuating the first coil and the second coil, wherein a first current associated with the first portion of the first coil flows in a first direction and a second current associated with the second portion of the second coil flows in a second direction, the first direction and the second direction being substantially opposite.

11. 11. The method of claim 10, wherein the first coil comprises a first set of one or more traces disposed on one or more layers of a first set of printed circuit boards (PCBs), and the second coil comprises a second set of one or more traces disposed on one or more layers of a second set of PCBs.

12. providing a third coil disposed adjacent to the second coil, a third portion of the third coil overlapping a fourth portion of the second coil; 11. The method of claim 10, further comprising: actuating the third coil, wherein a third current associated with a third portion of the third coil flows in the first direction.

13. a first set of traces for the first coil is provided on a first layer of a printed circuit board (PCB); 11. The method of claim 10, wherein a first set of traces for the second coil is provided on a second layer of the PCB.

14. a second set of traces for the second coil is provided on a third layer of the PCB; 14. The method of claim 13, wherein a second set of traces for the first coil is provided on a fourth layer of the PCB.

15. a third set of traces for the first coil is provided on a fifth layer of the PCB; 15. The method of claim 14, wherein a third set of traces for the second coil is provided on a sixth layer of the PCB.

16. a fourth set of traces for the second coil is provided on a seventh layer of the PCB; 16. The method of claim 15, wherein a fourth set of traces for the second coil is provided on an eighth layer of the PCB.

17. The method of claim 10 , wherein the first coil and the second coil are operated together to operate as a substantially larger coil for receiving an EC signal.

18. The method of claim 1 , wherein the first coil and the second coil are operated together to operate substantially as a larger coil to transmit at least one signal used for EC testing.

19. 1. A coil assembly for eddy current (EC) inspection, comprising: a first set of coil elements disposed on one or more layers of a first set of printed circuit boards (PCBs); a second set of coil elements disposed on one or more layers of a second set of the PCB; A coil assembly wherein at least one coil element of the first set of coil elements overlaps with at least one coil element of the second set of coil elements at an overlapping portion.

20. 20. The coil assembly of claim 19, wherein in the overlapping portion, a portion of the at least one coil element of the first set of coil elements and a portion of the at least one coil element of the second set of coil elements are configured to generate opposing currents.

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