Dipole formation process

Abstract

Methods for manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure provide methods for reducing thickness, reducing thermal budgets, and reducing V t Advantageously, methods for fabricating electronic devices that meet requirements and have improved device performance and reliability are provided. Advantageously, embodiments of the present disclosure provide methods for fabricating electronic devices that achieve the desired dipole effect without an annealing process. To achieve the desired dipole effect "thinner" than 3 Å, embodiments of the present disclosure advantageously include methods for controlling the surface adsorption equilibrium and, in turn, the percentage of substrate surface atomic sites occupied by dipole species, which is not believed to be possible by ALD processes.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular to transistors. More particularly, embodiments of the present disclosure relate to methods of manufacturing FinFET and GAA devices. [Background technology]

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest component (or line) that can be made using a manufacturing process) has decreased.

[0003] A transistor is a circuit component or element that is often formed in a semiconductor device. Depending on the circuit design, many transistors can be formed in a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Integrated circuits incorporate planar field-effect transistors (FETs), in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004] As device dimensions shrink, device geometries and materials become more challenging to maintain switching speeds without incurring failure. Several new technologies have emerged that allow chip designers to continue shrinking gate lengths. Controlling the dimensions of device structures is a key challenge for current and future technology generations.

[0005] The shrinking of materials currently used for N-MOS and P-MOS has led to a decrease in threshold voltage (V t) are challenging due to changes in fundamental properties such as temperature, humidity, and temperature. Furthermore, the transition from planar to FinFET and gate-all-around (GAA) transistor technologies requires conformal work function layers for multiple threshold voltages. V t The tuning range is limited by film thickness variations due to further shrinkage of device size. There are also challenges associated with traditional dipole engineering techniques. To achieve the desired dipole effect, the desired element is driven from the deposited film by spike annealing and then removed after drive-in. Spike annealing can potentially cause an equivalent oxide thickness (EOT) penalty and a high thermal budget because free oxygen atoms in the gate dielectric layer and the overlying dipole stack diffuse downward and oxidize the underlying silicon layer.

[0006] Additionally, precise control of the amount of dipolar species in a metal gate stack, such as a high-k metal gate stack, can be used to achieve the desired V t Conventional atomic layer deposition (ALD) processes can grow films as thin as 3 Å, but these are still too thick and contain unwanted excess V. t This can lead to tuning, EOT penalty, and / or device leakage.Below this thickness, discontinuous film growth (e.g., island growth) typically occurs and is not considered feasible by ALD processes.

[0007] Therefore, thickness reduction, thermal budget reduction, and V t What is needed is a method for manufacturing electronic devices that meets the requirements and incurs minimal, if any, EOT penalty. Summary of the Invention

[0008] One or more embodiments of the present disclosure relate to a method for manufacturing an electronic device. In one or more embodiments, the method includes treating a surface of a metal gate stack. The metal gate stack includes an interfacial layer on an upper surface of a channel located between a source and a drain on a substrate. In some embodiments, treating the surface of the metal gate stack includes flowing a metal-containing precursor onto the surface of the metal gate stack to form a treated interfacial layer having metal atoms formed thereon. In some embodiments, after treating the surface of the metal gate stack, the method then continues by depositing a high-k dielectric layer on the treated interfacial layer.

[0009] Additional embodiments of the present disclosure relate to methods for fabricating electronic devices. In one or more embodiments, the method includes treating a surface of a metal gate stack. The metal gate stack includes an interfacial layer on an upper surface of a channel located between a source and a drain on a substrate, the interfacial layer comprising silicon oxide (SiOx). In some embodiments, treating the surface of the metal gate stack includes flowing a metal-containing precursor carried by an inert gas onto the surface of the metal gate stack to form a treated interfacial layer having metal atoms formed thereon. The metal-containing precursor includes one or more of aluminum (Al), lanthanum (La), cesium (Cs), or gallium (Ga). In some embodiments, after treating the surface of the metal gate stack, the method then continues by depositing a high-k dielectric layer on the treated interfacial layer, the high-k dielectric layer comprising hafnium oxide (HfOx).

[0010] A further embodiment of the present disclosure relates to a processing tool including: a central transfer station including a robot configured to move substrates; a plurality of process stations, each process station connected to the central transfer station to provide a processing region separated from a processing region of an adjacent process station, the plurality of process stations including an interfacial layer deposition chamber and a high-k dielectric layer deposition chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to operate the robot to move the substrate between the process stations and control a process cycle for forming an electronic device, the process cycle including treating a surface of a metal gate stack, the metal gate stack including an interfacial layer on a top surface of a channel located between a source and a drain on the substrate, treating the surface of the metal gate stack including flowing a metal-containing precursor on the surface of the metal gate stack to form a treated interfacial layer, and then depositing a high-k dielectric layer on the treated interfacial layer.

[0011] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered as limiting the scope of the present disclosure, since the present disclosure may admit of other equally effective embodiments. The embodiments described herein are illustrated by way of example, and not by way of limitation, in the accompanying drawings, in which like reference numerals indicate like elements. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a process flow diagram of a method according to one or more embodiments. [Figure 2A] 1 is a cross-sectional view of a substrate according to one or more embodiments. [Figure 2B] 1 is a cross-sectional view of a substrate according to one or more embodiments. [Figure 3] FIG. 2C is an enlarged cross-sectional view of region III of the substrate of FIG. 2B according to one or more embodiments. [Figure 4] FIG. 2C is an enlarged cross-sectional view of region IV of the substrate of FIG. 2B according to one or more embodiments. [Figure 5] FIG. 1 illustrates a cluster tool according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0014] As used herein, the term "about" means approximately or approximately, and in the context of a stated numerical value or range, refers to a variation of no more than ±15% of the numerical value. For example, values ​​that vary by ±14%, ±10%, ±5%, ±2%, or ±1% meet the definition of about.

[0015] As used herein and in the appended claims, the term "substrate" or "wafer" refers to a surface or portion of a surface upon which a process acts. Also, those skilled in the art will understand that a reference to a substrate can refer to only a portion of a substrate unless the context clearly indicates otherwise. Furthermore, a reference to depositing on a substrate can refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0016] As used herein, "substrate" refers to any substrate or surface of a material formed on a substrate on which film processing occurs during a manufacturing process. For example, substrate surfaces that can be processed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in this disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include the underlying layer as the context dictates. Thus, for example, if a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer is the substrate surface.

[0017] The term "on" indicates direct contact between elements. The term "directly above" indicates direct contact between elements with no intervening elements.

[0018] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with a substrate surface.

[0019] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. A substrate or a portion of a substrate is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react with the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to two or more reactive compounds such that any given point on the substrate is not substantially simultaneously exposed to two or more reactive compounds. As used herein and in the appended claims, the term "substantially" means that only a small portion of the substrate may be simultaneously exposed to multiple reactive gases due to diffusion, and simultaneous exposure is not intended, as understood by those skilled in the art.

[0020] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compound or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, with only the purge gas flowing during the time delay between pulses of reactive compound. The reactive compounds are pulsed alternately until the desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle can begin with either compound A or compound B and continue in each order until a film having a predetermined thickness is achieved.

[0021] In one embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply system so that any given point on the substrate is exposed to both the first reactive gas and the second reactive gas.

[0022] A transistor is a circuit component or element that is often formed in a semiconductor device. Depending on the circuit design, transistors may be formed in the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is disposed over the channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0023] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. A field effect transistor is a voltage-controlled device whose current-carrying capability is changed by applying an electric field. Field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers exit the channel; and the gate (G), which is the terminal that regulates the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is designated IS, and the current entering the channel at the drain (D) is designated ID. The drain-source voltage is designated VDS. The current entering the channel at the drain (i.e., ID) can be controlled by applying a voltage to the gate (G).

[0024] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, the voltage across which determines the device's conductivity. This ability to change conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the regulation of charge concentration through metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to a separate heavily doped region separated by a body region. These regions can be p-type or n-type, but both are of the same type, opposite the body region. The source and drain (unlike the body) are heavily doped, as indicated by a "+" sign after the doping type.

[0025] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is an n-type substrate region. The source is so called because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers exit the channel.

[0026] An nMOS FET consists of an n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current is sent by electrons from the source to the drain through the induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three modes of operation: cutoff, triode, and saturation. Because DC current flows through the logic gate when the output is low, circuits with NMOS logic gates consume static power when the circuit is idle.

[0027] A pMOS FET consists of a p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (a negative voltage between the gate and source), a p-type channel of the opposite polarity is formed between the source and drain. Current is carried by holes from the source to the drain through the induced p-type channel. A high voltage on the gate makes the PMOS non-conductive, while a low voltage on the gate makes it conductive. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low cost and has good noise immunity.

[0028] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, the NMOS conducts, but the PMOS does not. Furthermore, when a low voltage is applied to the gate, the NMOS does not conduct, and the PMOS does. Because the carriers in NMOS are electrons, which move twice as fast as the holes in PMOS, NMOS is considered faster than PMOS. However, PMOS devices have higher noise immunity than NMOS devices. Furthermore, because NMOS can provide half the impedance provided by PMOS (with the same geometry and operating conditions), the IC of an NMOS can be smaller than the IC of a PMOS (giving the same functionality).

[0029] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate where the gate is located on two, three, or four sides of the channel or wrapped around the channel, forming a double-gate structure. FinFET devices are given the generic name FinFET because the source / drain regions form "fins" in the substrate. FinFET devices have fast switching times and high current densities.

[0030] As used herein, the term "gate-all-around (GAA)" refers to an electronic device, e.g., a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor can comprise a nanowire, nanoslab, or nanosheet, a bar-shaped channel, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has multiple vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0031] As used herein, the term "nanowire" refers to a wire measuring 10 nanometers (10 -9Nanowires refer to nanostructures with diameters on the order of 1000 nanometers. Nanowires can also be defined as having a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures with a thickness or diameter constrained to tens of nanometers or less and an unconstrained length. Nanowires are used in transistor and some laser applications and, in one or more embodiments, are formed from semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and nonvolatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to two-dimensional nanostructures with thicknesses on the scale of about 0.1 nm to about 1000 nm, or 0.5 nm to 500 nm, or 0.5 nm to 100 nm, or 1 nm to 500 nm, or 1 nm to 100 nm, or 1 nm to 50 nm.

[0032] As used herein, the term "in situ" refers to processes that are all performed in the same processing chamber or in different processing chambers connected as part of a processing system, such that each of the processes is performed without an intervening vacuum break. As used herein, the term "ex situ" refers to processes that are performed in at least two different processing chambers, such that one or more of the processes are performed with an intervening vacuum break. In some embodiments, the processes are performed without breaking vacuum or exposure to ambient air.

[0033] As used herein, the term "dipole first" refers to a process in which a metal-containing precursor is flowed over a surface to deposit metal atoms on the surface (forming a treated surface) to achieve the desired dipole effect, and then a high-k dielectric layer is deposited on the treated surface. As used herein, the term "dipole last" refers to a process in which an interfacial layer is formed on a substrate, a high-k dielectric layer is formed, a metal-containing precursor is flowed over the surface to deposit metal atoms on the surface of the high-k dielectric layer, and the substrate is annealed to drive the metal atoms into the interfacial layer and the high-k dielectric layer to achieve the desired dipole effect. In the dipole last process, instead of forming an ultrathin surface adlayer, an atomic layer deposition (ALD) process is performed to deposit a dipole layer with a thickness of 3 Å to 20 Å containing dipole atoms, typically in the form of an oxide or nitride. A capping material is typically required on top of the dipole oxide / nitride film to avoid silicon oxide regrowth during the annealing process. One or more embodiments described herein provide a method of manufacturing an electronic device that advantageously includes a dipole tip formation process.

[0034] The embodiments of the present disclosure provide reduced thickness, reduced thermal budget, and V t Advantageously, methods for fabricating electronic devices that meet the requirements and have improved device performance and reliability are provided. t The present disclosure provides a method for fabricating an electronic device having desired band-edge performance, such as a desired flat-band voltage (V fb ) for a metal gate stack having

[0035] In conventional dipole engineering techniques, such as conventional post-dipole formation processes, to achieve the desired dipole effect, the desired elements are driven out of the deposited film by a spike anneal and removed after drive-in. The spike anneal can potentially cause an equivalent oxide thickness (EOT) penalty and a high thermal budget because free oxygen atoms in the gate dielectric layer and the overlying dipole stack diffuse downward and oxidize the underlying silicon layer. Advantageously, embodiments of the present disclosure provide a method for fabricating electronic devices that achieve the desired dipole effect without an annealing process.

[0036] Advantageously, embodiments of the present disclosure provide methods for fabricating electronic devices that achieve the desired dipole effect at thicknesses of less than 3 Å, which was not believed to be possible by ALD processes.

[0037] Generally, thickness is measured in the z-direction of a continuous film / layer. As used herein, the thickness and the percentage of substrate surface atomic sites occupied by dipolar species can each be used to describe the amount of metal atoms in an interfacial layer.

[0038] To achieve the desired dipole effect at thicknesses "thinner" than 3 Å, embodiments of the present disclosure advantageously include methods for controlling the surface adsorption equilibrium and, in turn, the proportion of substrate surface atomic sites occupied by dipole species (e.g., metal atoms in the interfacial layer).

[0039] Without being bound by theory, it is believed that the adsorption and desorption of precursors, such as metal-containing precursors, reach thermal equilibrium when only a certain percentage of the surface atomic positions are occupied in one pulse / purge cycle. In other words, precursors, such as metal-containing precursors, do not occupy 100% of the surface atomic positions. For most metal-containing precursors, increasing the substrate temperature shifts the equilibrium toward more desorption, with a reduced amount of surface atomic positions occupied by precursor molecules. Therefore, decreasing the substrate temperature shifts the equilibrium toward less desorption, with an increased amount of surface atomic positions occupied by precursor molecules.

[0040] Embodiments of the present disclosure are illustrated by diagrams that show devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0041] 1 is a flow diagram of a method 100 for fabricating an electronic device according to one or more embodiments of the present disclosure. The method 100 begins in operation 102 by forming an interfacial layer on a top surface of a channel located between a source and a drain on a substrate. In operation 104, the surface of the interfacial layer is treated to form a treated interfacial layer having metal atoms thereon. In operation 106, a high-k dielectric layer is deposited on the treated interfacial layer. In operation 108, a metal gate layer may be formed on the high-k dielectric layer.

[0042] 2A and 2B are cross-sectional views of an electronic device (e.g., a transistor such as a FinFET or GAA) 200 according to one or more embodiments. The electronic device 200 shown in FIGS. 2A and 2B can be fabricated by the method 100 shown in FIG.

[0043] In one or more embodiments, electronic device 200 includes a semiconductor substrate 202 having a top surface 203. Semiconductor substrate 202 may be any suitable substrate material. In one or more embodiments, semiconductor substrate 202 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, semiconductor substrate 202 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). Although some examples of materials from which substrate 202 may be formed are described herein, any material capable of serving as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be built is within the spirit and scope of the present disclosure.

[0044] In one or more embodiments, the semiconductor substrate 202 is a p-type substrate or an n-type substrate. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of the electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a higher hole concentration than electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers.

[0045] In one or more embodiments, a source region 204a is at the top surface 203 of the semiconductor substrate 202. In one or more embodiments, the source region 204a has a source and a source contact (not shown). A drain region 204b is at the top surface 203 of the semiconductor substrate 202 opposite the source region 204a. In one or more embodiments, the drain region 204b has a drain and a drain contact (not shown).

[0046] In one or more embodiments, the source region 204a and / or the drain region 204b may be any suitable material known to one of ordinary skill in the art. In one or more embodiments, the source region 204a and / or the drain region 204b may have two or more layers. For example, the source region 204a and / or the drain region 204b may individually include three layers. In one or more embodiments, the source region 204a and the drain region 204b may individually include one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and the drain region 204b may individually include a bottom layer of silicon with doped epi (e.g., SiGe, SiP, etc.), a second layer of a silicide that may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer that may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, etc. In some embodiments, the source region 204a and the drain region 204b may be raised source / drain regions formed by EPI growth.

[0047] In one or more embodiments, the source and / or drain contacts may be individually selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the formation of the source and / or drain contacts is performed by any suitable process known to those skilled in the art, including, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0048] In one or more embodiments, a channel 206 is located between the source 204a and the drain 204b. In some embodiments, the channel 206 comprises an n-type material. In some embodiments, the channel 206 comprises a p-type material.

[0049] In one or more embodiments, the interfacial layer 210 overlies the channel 206 and is in contact with one or more of the channel 206, the source region 204a, and the drain region 204b. In one or more embodiments, the interfacial layer 210 has a thickness of 1 Å to 50 Å, or 5 Å to 45 Å, or 5 Å to 40 Å, or 5 Å to 35 Å. In one or more embodiments, the interfacial layer 210 has a thickness of 5 Å to 15 Å.

[0050] In one or more embodiments, in operation 102, an interfacial layer 210 is formed on the top surface 205 of the channel 206. In one or more embodiments, the interfacial layer 210 may be any suitable material known to those skilled in the art. For example, in one or more embodiments, the interfacial layer 210 comprises a dielectric material. In one or more embodiments, the dielectric material is selected from one or more of silicon (Si), silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon oxynitride (SiCONH), doped silicon, doped silicon oxide, doped silicon nitride, doped silicon oxynitride, spin-on dielectric, or diffusion seed growth. In one or more embodiments, the interfacial layer 210 comprises silicon dioxide (SiO). In other embodiments, the dielectric material is a low-k material. The interfacial layer 210 may be deposited using one or more deposition techniques known to those skilled in the art of microelectronic device fabrication. In one or more embodiments, the interfacial layer 210 is deposited using one of a number of deposition techniques, including, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the interfacial layer 210 may be formed by etching and forming an oxide on the top surface 205 of the channel 206. In one or more embodiments, the interfacial layer 210 has a thickness of 1 Å to 10 Å, or 6 Å to 8 Å.

[0051] In one or more embodiments, a wet chemical technique is performed to form the interfacial layer 210. The wet chemical technique may be any technique known to one of ordinary skill in the art. In some embodiments, the wet chemical technique includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using an SC-1 solution that includes one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using an SC-1 solution that does not include ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using dilute hydrofluoric acid (dilute HF) to etch away native oxide on the semiconductor substrate 202 after using the SC solution to form a hydrophobic surface (i.e., the interfacial layer 210).

[0052] Advantageously, embodiments of the present disclosure provide a method (e.g., method 100) for fabricating electronic devices that achieve the desired dipole effect at thicknesses less than 3 Å, which is not believed to be possible by ALD processes. Furthermore, like typical post-dipole formation processes, depositing a dipole layer by ALD further requires a capping layer on top of the dipole layer to avoid silicon oxide regrowth during the annealing process. To achieve the desired dipole effect at thicknesses "thinner" than 3 Å, embodiments of the present disclosure advantageously include a method for controlling the surface adsorption equilibrium and then controlling the percentage of substrate surface atomic sites occupied by dipole species (e.g., metal atoms in the interfacial layer).

[0053] Without being bound by theory, it is believed that the adsorption and desorption of precursors, such as metal-containing precursors, reach a thermal equilibrium where only a certain percentage of the surface atomic positions are occupied in one pulse / purge cycle. In other words, precursors, such as metal-containing precursors, do not occupy 100% of the surface atomic positions. For most chemicals, increasing the substrate temperature shifts the equilibrium toward more desorption, with a reduced amount of surface atomic positions occupied by precursor molecules. Therefore, decreasing the substrate temperature shifts the equilibrium toward less desorption, with an increased amount of surface atomic positions occupied by precursor molecules.

[0054] In one or more embodiments, operation 104 of method 100 includes treating the surface of interfacial layer 210 by flowing a metal-containing precursor over the surface of interfacial layer 210 to form a treated interfacial layer having metal atoms 207 thereon.

[0055] In some embodiments, the metal-containing precursor comprises one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), or cesium (Cs). In some embodiments, the metal-containing precursor comprises one or more of lanthanum (La) or cesium (Cs).

[0056] In some embodiments, the metal-containing precursor comprises one or more of aluminum (Al), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo). In some embodiments, the metal-containing precursor comprises one or more of aluminum (Al) or gallium (Ga). In some embodiments, the metal-containing precursor comprises aluminum chloride (AlCl).

[0057] The metal-containing precursor comprises the metal elements mentioned above and can be flowed in their metal halide or organometallic forms.

[0058] In some embodiments, the metal-containing precursor is carried to the surface of the metal gate stack by an inert gas. In some embodiments, the inert gas comprises one or more of nitrogen (N), argon (Ar), or helium (He). In some embodiments, the inert gas comprises argon (Ar).

[0059] In conventional dipole engineering techniques, a metal oxide film is deposited on the interlayer dielectric, followed by an annealing process. The spike anneal can potentially cause an equivalent oxide thickness (EOT) penalty and a high thermal budget because free oxygen atoms in the gate dielectric layer and the overlying dipole stack diffuse downward and oxidize the underlying silicon layer.

[0060] It has been advantageously found that the metal-containing precursors described herein adsorb (physisorbed or chemically adsorbed) to the surface of the interfacial layer 210 and / or the substrate surface 205, controlling the proportion of surface atomic sites occupied by metal atoms (e.g., dipolar species) through thermal equilibrium. The proportion of surface atomic sites occupied by the metal-containing precursor can be adjusted. To increase the amount of dipolar species on the surface (e.g., silicon oxide surface) of the interfacial layer 210 and the proportion of the silicon oxide surface occupied by the metal-containing precursor, the substrate temperature can be reduced, the partial pressure of the metal-containing precursor at the silicon oxide surface can be increased, and / or bonding between the silicon oxide surface and the metal-containing precursor, most typically between hydroxyl terminations (—OH) on the silicon oxide surface and halide elements in the halogen-containing metal-containing precursor, can be promoted.

[0061] In operation 104, the treatment of the surface of the metal gate stack can be performed in any suitable processing chamber. Advantageously, in operation 104, the surface of the metal gate stack can be treated in an atomic layer deposition (ALD) chamber, such as any ALD chamber known to those skilled in the art. It has been surprisingly discovered that while a dipole-precipitating process such as method 100 can achieve the desired dipole effect at thicknesses “thinner” than 3 Å by controlling the surface adsorption equilibrium and then controlling the percentage of substrate surface atomic sites occupied by dipole species in the ALD chamber, conventional ALD processes do not appear to be able to achieve the desired dipole effect at thicknesses less than 3 Å. In some embodiments, method 100 includes exposing the silicon oxide surface to a metal-containing precursor for a predetermined time to reach adsorption equilibrium.

[0062] In some embodiments, the treatment of the surface of the metal gate stack is carried out at a temperature of 150° C. to 500° C., a pressure of about 80 Torr, and for a time of 10 seconds to 120 seconds.

[0063] 2A and 2B , in operation 106, a high-k dielectric layer 212 is deposited on the treated interfacial layer having metal atoms 207 thereon. The high-k dielectric layer 212 may be any suitable high-k dielectric material known to those skilled in the art. In one or more embodiments, the high-k dielectric layer 214 includes one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx). In one or more embodiments, the high-k dielectric layer 212 is deposited using one of a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition technique known to those skilled in the art. In one or more embodiments, the high-k dielectric layer includes hafnium oxide (HfOx) and is formed by exposing the treated interfacial layer to hafnium tetrachloride (HfCl4) and water (HO). Water advantageously removes chlorine (Cl) atoms from metal-containing precursors, such as aluminum chloride (AlCl), and hafnium precursors, such as hafnium tetrachloride (HfCl). In one or more embodiments, the high-k dielectric layer 212 has a thickness between 10 Å and 25 Å, including all subranges and values ​​therebetween.

[0064] Figure 3 shows an enlarged cross-sectional view of region III of the substrate of Figure 2B. Figure 4 shows an enlarged cross-sectional view of region IV of the substrate of Figure 2B. Figures 3 and 4 illustrate the effect of substrate temperature on metal atoms from a metal-containing precursor, according to one or more embodiments of the present disclosure. In some embodiments, the treatment of the surface of the metal gate stack is performed at a temperature of 150°C or higher and 500°C or lower.

[0065] 3 illustrates region III of substrate 202 of FIG. 2B , showing channel 206, interfacial layer 210 formed in channel 206, and the treated interfacial layer having metal atoms 207 thereon. In some embodiments, FIG. 3 illustrates that increasing the substrate temperature, for example, to a temperature between 300° C. and 500° C., shifts the equilibrium toward more desorption, resulting in a reduced amount of surface atomic positions (e.g., in interfacial layer 210) being occupied by precursor molecules (e.g., metal atoms 207). In one or more embodiments, increasing the temperature of the substrate reduces the binding energy of metal atoms 207 that bind to the surface of the treated interfacial layer.

[0066] 4 shows region IV of substrate 202 of FIG. 2B , showing channel 206, interfacial layer 210 formed in channel 206, and the treated interfacial layer having metal atoms 207 thereon. In some embodiments, FIG. 4 shows that lowering the substrate temperature, for example, to a temperature between 150° C. and 300° C., shifts the equilibrium toward less desorption, with an increased amount of surface atomic sites (e.g., in interfacial layer 210) occupied by precursor molecules (e.g., metal atoms 207).

[0067] To increase the amount of dipolar species (e.g., metal atoms 207) on the surface (e.g., silicon oxide surface) of the interfacial layer 210 and the proportion of the silicon oxide surface occupied by the metal-containing precursor, the partial pressure of the metal-containing precursor at the silicon oxide surface can be increased and / or bonding between the silicon oxide surface and the metal-containing precursor, most typically between the hydroxyl termination (-OH) on the silicon oxide surface and the halide element in the halogen-containing metal-containing precursor, can be promoted. For example, the partial pressure of the metal-containing precursor at the silicon oxide surface can be controlled by the chamber pressure or by manipulating the flow of an inert gas flowing with the carrier gas. In some embodiments, the partial pressure of the metal-containing precursor at the silicon oxide surface can be increased to a pressure of 80 Torr or higher, increasing the proportion of the silicon oxide surface occupied by the metal-containing precursor. In other embodiments, the partial pressure of the metal-containing precursor at the silicon oxide surface can be decreased to a pressure of 80 Torr or lower, decreasing the proportion of the silicon oxide surface occupied by the metal-containing precursor.

[0068] Depending on the metal-containing precursor selected, the method 100 has been advantageously found to be capable of decreasing or increasing the effective work function of the metal gate stack in the electronic device 200. Thus, tuning of the effective work function can be achieved by using different dipoles and dipole amounts.

[0069] In certain embodiments, where the metal-containing precursor comprises one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), or cesium (Cs), the effective work function of the metal gate stack in the electronic device 200 may lower the work function from about 4.5 eV to about 4.2 eV.

[0070] In certain embodiments, where the metal-containing precursor comprises one or more of aluminum (Al), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo), the effective work function of the metal gate stack in the electronic device 200 may be increased from about 4.7 eV to about 4.9 eV.

[0071] Some embodiments of the present disclosure relate to methods including pre-dipole formation processes and post-dipole formation processes. In some embodiments, such processes include method 100, i.e., forming an interfacial layer on a top surface of a channel (operation 102), treating the surface of the interfacial layer to form a treated interfacial layer having metal atoms thereon (operation 104), depositing a high-k dielectric layer on the treated interfacial layer (operation 106), then flowing a metal-containing precursor onto the surface of the high-k dielectric layer to form a dipole layer in the high-k dielectric layer (not shown), and forming a metal gate layer on the dipole layer (e.g., operation 108).

[0072] 2A and 2B , in some embodiments, the method 100 may include, at operation 108, depositing a metal gate layer 214 on the top surface 213 of the high-k dielectric layer 212 to control post-deposition film oxidation. In one or more embodiments, the metal gate layer 214 is an in-situ metal gate layer. The metal gate layer 214 may be any suitable material known to those skilled in the art. In one or more embodiments, the metal gate layer 214 includes one or more of amorphous silicon, a metal, a metal carbide, a metal nitride, or a metal oxide. In one or more embodiments, the metal gate layer 214 includes one or more of titanium aluminum carbide (TiAlC) or titanium nitride (TiN). In some embodiments, the metal gate layer 214 has a thickness between 10 Å and 30 Å, including all subranges and values ​​therebetween. In some embodiments, the metal gate layer 214 includes titanium nitride (TiN) and has a thickness between 10 Å and 30 Å, e.g., 30 Å. In some other embodiments, the metal gate layer 214 has a total thickness of 30 Å, including a layer of titanium nitride (TiN) having a thickness of 10 Å and a layer of titanium aluminum carbide (TiAlC) having a thickness of 20 Å.

[0073] As described herein, in a pre-dipole formation process, for example, method 100 achieves the desired dipole effect without an annealing process. In one or more embodiments, a method including a pre-dipole formation process and a post-dipole formation process anneals the semiconductor substrate 202 at a temperature between 400°C and 900°C to drive metal atoms from a metal-containing precursor into the high-k dielectric layer 212. In one or more embodiments, annealing the semiconductor substrate 202 at a temperature between 400°C and 900°C drives metal atoms from the metal-containing precursor into the interfacial layer 210. In one or more embodiments, annealing the substrate includes rapid thermal processing (RTP). RTP can be any suitable process known to those skilled in the art. Without being bound by theory, it is believed that RTP densifies and improves the physical properties of the deposited dipole layer.

[0074] In one or more embodiments, a gate including one or more of a gate metal (not shown) or a gate contact (not shown) may be formed or deposited on the exposed surface of the high-k dielectric layer 212. The gate metal may be any material known to those skilled in the art. In one or more embodiments, the gate metal includes one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), aluminum (Al), or platinum (Pt). In one or more particular embodiments, the gate metal includes a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), iridium (Ir), aluminum (Al), or platinum (Pt). In other particular embodiments, the gate metal comprises a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), or ruthenium (Ru). In one or more embodiments, the gate contact may be any suitable material known to those skilled in the art. In one or more embodiments, the gate contact is selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), aluminum (Al), or platinum (Pt).

[0075] An additional embodiment of the present disclosure relates to a processing tool (i.e., cluster tool) 900 for forming the described logic / memory devices and methods, as shown in Figure 5. The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are disposed within the central transfer station 921, 931 and configured to move a robot blade and wafer to each of the multiple sides.

[0076] The cluster tool 900 includes multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station 921, 931. The various processing chambers provide separate processing regions isolated from adjacent process stations. The cluster tool 900 can include any suitable chambers, such as any suitable processing chambers known to those skilled in the art. The processing chambers can be any suitable chamber, including, but not limited to, a pre-clean chamber, a buffer chamber, a transfer space, a wafer orienter / degassing chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etch chamber, a thermal processing (RTP) chamber, a plasma oxidation chamber, a plasma nitridation chamber, and an atomic layer deposition (ALD) chamber. The specific arrangement of process chambers and components can vary depending on the cluster tool and should not be considered limiting of the scope of this disclosure.

[0077] In one or more embodiments, the cluster tool 900 includes an interfacial layer deposition chamber (e.g., a silicon oxide (SiOx) chamber configured to form silicon oxide (SiOx)). The silicon dioxide (SiO2) deposition chamber of some embodiments includes an atomic layer deposition chamber, a plasma-enhanced atomic layer deposition chamber, or a spatial atomic layer deposition chamber. In one or more embodiments, the cluster tool 900 includes a pre-clean chamber connected to a central transfer station.

[0078] In some embodiments, one or more of the operations of the methods described herein are performed in situ. In some embodiments, one or more of the operations of the methods described herein are performed ex situ.

[0079] Without being bound by theory, it is believed that, depending on the material, some n-type dipolar materials and some p-type dipolar materials, especially when in metallic form, are susceptible to spontaneous oxidation to the oxide form upon exposure to ambient air, which can result in an EOT penalty. Advantageously, an in situ process can control, minimize, or avoid this oxidation.

[0080] 4, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one skilled in the art will understand that this represents only one possible configuration.

[0081] The size and shape of the loading chamber 954 and unloading chamber 956 can vary depending on, for example, the substrate being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette with multiple wafers disposed within the cassette.

[0082] The robot 952 resides within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 to a load lock chamber 960 through the factory interface 950. The robot 952 can also transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be appreciated by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0083] The cluster tool 900 shown in FIG. 4 includes a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 via load lock chambers 960 and 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 disposed therein. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960 and 962, the process chambers 902, 904, 916, and 918, and the buffer chambers 922 and 924. In some embodiments, the robot 925 is a multi-arm robot capable of individually moving two or more wafers at a time. In one or more embodiments, the first transfer chamber 921 includes two or more robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are carried onto a wafer transport blade located at the distal end of the first robotic mechanism.

[0084] After processing the wafer in the first section 920, the wafer may be passed to the second section 930 via a pass-through chamber. For example, chambers 922, 924 may be one-way or two-way pass-through chambers. Pass-through chambers 922, 924 may be used, for example, to cryogenically cool the wafer before processing in the second section 930 or to allow for cooling or post-processing of the wafer before returning to the first section 920.

[0085] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0086] The processes may generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may be performed in hardware. Thus, the processes may be implemented in software and in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation to perform the processes.

[0087] Embodiments of the present disclosure relate to a non-transitory computer-readable medium. In one or more embodiments, the non-transitory computer-readable medium includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform any of the operations of the methods described herein. In one or more embodiments, the controller causes the processing chamber to perform the operations of method 100. In one or more embodiments, the controller causes the processing chamber to perform an operation of forming an interfacial layer on a top surface of the channel (operation 102), an operation of treating a surface of the interfacial layer to form a treated interfacial layer having metal atoms thereon (operation 104), and an operation of depositing a high-k dielectric layer on the treated interfacial layer (operation 106).

[0088] In one or more embodiments, the controller causes the processing chamber to perform operations of the methods described herein, including pre-dipole formation processes and post-dipole formation processes. In some embodiments, such processes include the controller causing the processing chamber to perform operations of forming an interfacial layer on an upper surface of the channel (operation 102), treating the surface of the interfacial layer to form a treated interfacial layer having metal atoms thereon (operation 104), depositing a high-k dielectric layer on the treated interfacial layer (operation 106), then flowing a metal-containing precursor onto the surface of the high-k dielectric layer to form a dipole layer in the high-k dielectric layer (not shown), and forming a metal gate layer on the dipole layer (e.g., operation 108).

[0089] In one or more embodiments, the processing tool 900 includes a central transfer station 921, 931 including at least one robot 925, 935 configured to transfer wafers, one or more of a rapid thermal processing (RTP) station, a separated plasma oxidation (DPO) station, or a separated plasma nitridation (DPN) station connected to the central transfer station, an atomic layer deposition (ALD) station connected to the central transfer station, an optional precleaning station connected to the central transfer station, and at least one controller connected to one or more of the central transfer station, the RTP station, the DPO station, the DPN station, the ALD station, or the optional precleaning station. In one or more embodiments, the at least one controller has at least one configuration selected from a configuration for transferring wafers between stations using a robot, a configuration for performing a rapid thermal process, a configuration for performing a separated plasma process, a configuration for controlling the flow of an oxidizing gas to the RTP station or the DPO station, a configuration for controlling the flow of a nitriding gas to the RTP station or the DPN station, a configuration for depositing a silicon oxide film by atomic layer deposition, and a configuration for precleaning wafers.

[0090] Spatially relative terms such as "below," "lower," "bottom," "upper," and "top" may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as shown. It will be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown. For example, if the device in the figures were inverted, elements described as being "below" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can include both an orientation of above and below. The device may be oriented otherwise (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0091] The use of the terms "a," "an," and "the" and similar referents in the context of describing the materials and methods described herein (particularly in the context of the claims below) is intended to include both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually listed herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of all examples or exemplary language (e.g., "etc.") provided herein is intended merely to better describe the materials and methods and does not pose a limitation on scope unless otherwise asserted. No language herein should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0092] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0093] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of manufacturing an electronic device, the method comprising: treating a surface of a metal gate stack, the metal gate stack including an interfacial layer on an upper surface of a channel located between a source and a drain on a substrate, wherein treating the surface of the metal gate stack includes flowing a metal-containing precursor onto the surface of the metal gate stack to form a treated interfacial layer having metal atoms formed thereon; then depositing a high-k dielectric layer on the treated interfacial layer; A method comprising:

2. 10. The method of claim 1, wherein the interfacial layer comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or a spin-on dielectric.

3. 10. The method of claim 1, wherein the high-k dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx).

4. The high-k dielectric layer comprises hafnium oxide (HfOx), and the treated interfacial layer is treated with hafnium tetrachloride (HfCl 4 ) and water (H 2 4. The method of claim 3, wherein the fluorine-containing polymer is formed by exposing the fluorine-containing polymer to a fluorine-containing compound.

5. 10. The method of claim 1, wherein the metal-containing precursor is carried to the surface of the metal gate stack by an inert gas.

6. 10. The method of claim 1, wherein the metal-containing precursor comprises one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), or cesium (Cs).

7. 7. The method of claim 6, wherein the metal-containing precursor comprises one or more of lanthanum (La) or cesium (Cs).

8. 10. The method of claim 1, wherein the metal-containing precursor comprises one or more of aluminum (Al), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo).

9. 9. The method of claim 8, wherein the metal-containing precursor comprises one or more of aluminum (Al) or gallium (Ga).

10. 10. The method of claim 1, wherein treating the surface of the metal gate stack is performed at a temperature of 150° C. to 500° C., a pressure of about 80 Torr, and for a time of 10 seconds to 120 seconds.

11. The method of claim 1 , wherein the channel comprises an n-type material.

12. The method of claim 1 , wherein the channel comprises a p-type material.

13. 10. The method of claim 1, further comprising flowing the metal-containing precursor over the surface of the high-k dielectric layer to form a dipole layer in the high-k dielectric layer.

14. The method of claim 13 further comprising forming a metal gate layer on the dipole layer.

15. 15. The method of claim 14, wherein the metal gate layer comprises one or more of amorphous silicon, a metal, a metal carbide, a metal nitride, or a metal oxide.

16. 16. The method of claim 15, wherein the metal gate layer comprises one or more of titanium aluminum carbide (TiAlC) or titanium nitride (TiN).

17. The method of claim 15, wherein the metal gate layer has a thickness of 10 Å to 30 Å.

18. The method of claim 1 , wherein the electronic device is a gate-all-around (GAA) device.

19. 1. A method of manufacturing an electronic device, the method comprising: treating a surface of a metal gate stack, the metal gate stack including an interfacial layer on a top surface of a channel located between a source and a drain on a substrate, the interfacial layer including silicon oxide (SiOx), treating the surface of the metal gate stack including flowing a metal-containing precursor carried by an inert gas onto the surface of the metal gate stack to form a treated interfacial layer having metal atoms formed thereon, the metal-containing precursor including one or more of aluminum (Al), lanthanum (La), cesium (Cs), or gallium (Ga); Next, depositing a high-k dielectric layer on the treated interfacial layer, the high-k dielectric layer comprising hafnium oxide (HfOx); A method comprising:

20. 1. A processing tool comprising: a central transfer station including a robot configured to move the substrate; a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from a processing region of an adjacent process station, the plurality of process stations including an interfacial layer deposition chamber and a high-k dielectric layer deposition chamber; a controller connected to the central transfer station and the plurality of process stations, the controller configured to operate the robot to move the substrate between the process stations and control a process cycle to form an electronic device; Including, The process cycle comprises: treating a surface of a metal gate stack, the metal gate stack including an interfacial layer on an upper surface of a channel located between a source and a drain on a substrate, wherein treating the surface of the metal gate stack includes flowing a metal-containing precursor onto the surface of the metal gate stack to form a treated interfacial layer; then depositing a high-k dielectric layer on the treated interfacial layer; Processing tools, including:

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