Display device and electronic device including the same

Abstract

To provide a display device in which a circuit configuration of a display panel is simplified, and an electronic device including the same.SOLUTION: The pixel includes a light emitting element connected to a first power line, a first transistor connected between a cathode of the light emitting element and a second power line, a second transistor connected between a first node and a data line, a third transistor connected between the first node and a reference voltage line, and a first light emission control transistor connected between the first transistor and the second power line and connected to a third node. The pixel includes a first capacitor connected between the first node and a second node to which the first transistor and the first light emission control transistor are connected, and a second capacitor connected between the second node and a third node.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device including the same, and more particularly to a display device with improved display quality and an electronic device including the same. [Background technology]

[0002] Among display devices, emissive display devices display images using light-emitting elements that generate light through the recombination of electrons and holes. Such emissive display devices have the advantages of having a fast response speed and low power consumption.

[0003] An emissive display device includes pixels connected to data lines and scan lines. A pixel generally includes a light emitting element and a pixel circuit for controlling the amount of current flowing through the light emitting element. The pixel circuit controls the amount of current flowing through the light emitting element in response to a data signal. Light of a predetermined brightness is generated in response to the amount of current flowing through the light emitting diode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 2023-0033789 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device having a simplified circuit configuration of a display panel, and an electronic device including the same. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a display device including a display panel having pixels, the pixels including: a light emitting element having an anode connected to a first power line and a cathode; a first transistor connected between the cathode and a second power line and operating in response to a potential of a first node; a second transistor connected between the first node and a data line and receiving a first scan signal; a third transistor connected between the first node and a reference voltage line and receiving a second scan signal; a first light emitting control transistor connected between the first transistor and the second power line and connected to a third node to receive a first light emitting control signal; a first capacitor connected between the first node and a second node to which the first transistor and the first light emitting control transistor are connected; and a second capacitor connected between the second node and the third node.

[0007] According to one aspect of the present invention, a display device includes a display panel including pixels, first and second scan lines, a first light-emitting control line, first and second power lines, a reference voltage line, and a data line, a first gate driving circuit connected to the first and second scan lines, and a second gate driving circuit connected to the first light-emitting control line.

[0008] The pixel includes a light emitting element including an anode connected to the first power line and a cathode; a first transistor connected between the cathode and the second power line and operating according to the potential of a first node; a second transistor connected between the first node and the data line and receiving a first scan signal through the first scan line; a third transistor connected between the first node and the reference voltage line and receiving a second scan signal through the second scan line; a first light emitting control transistor connected between the first transistor and the second power line and receiving a first light emitting control signal through the first light emitting control line; a first capacitor connected between the first node and a second node to which the first transistor and the first light emitting control transistor are connected; and a second capacitor connected between the second node and the first light emitting control line.

[0009] According to one aspect of the present invention, an electronic device includes a display panel including pixels, a panel driver for driving the display panel, a drive controller for controlling the driving of the panel driver, and a main processor for providing an image signal to the drive controller.

[0010] The pixel includes a light emitting element including an anode connected to a first power line and a cathode, a first transistor connected between the cathode and a second power line and operating in response to a potential of a first node, a second transistor connected between the first node and a data line and receiving a first scan signal, a third transistor connected between the first node and a reference voltage line and receiving a second scan signal, a first light emitting control transistor connected between the first transistor and the second power line and connected to a third node to receive a first light emitting control signal, a first capacitor connected between the first node and a second node to which the first transistor and the first light emitting control transistor are connected, and a second capacitor connected between the second node and the third node. [Effects of the Invention]

[0011] According to the present invention, by reducing the number of scan signals and light emission control signals applied to pixels, the number of scan driving circuits and light emission control circuits included in the gate driving circuit can be reduced, and as a result, the width of the non-display area of ​​the display panel can be reduced.

[0012] In addition, it is possible to provide a pixel circuit that can stably perform a compensation operation in a compensation period by using the coupling operation of the first and second capacitors even if the number of scan signals is reduced. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 2] 2 is a block diagram of the first and second gate driving circuits shown in FIG. 1; [Figure 3] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 4] 4 is a waveform diagram showing signals applied to the pixel shown in FIG. 3. FIG. [Figure 5A] 4 is a diagram illustrating an operation of a pixel during an initialization period according to an embodiment of the present invention; [Figure 5B] 4 is a diagram illustrating an operation of a pixel during an initialization period according to an embodiment of the present invention; [Figure 6A] 10 is a diagram illustrating an operation of a pixel during a compensation period according to an embodiment of the present invention; [Figure 6B] 10 is a diagram illustrating an operation of a pixel during a compensation period according to an embodiment of the present invention; [Figure 7A] 4 is a diagram illustrating an operation of a pixel during an interval according to an embodiment of the present invention; [Figure 7B] 4 is a diagram illustrating an operation of a pixel during an interval according to an embodiment of the present invention; [Figure 8A] 4 is a diagram illustrating an operation of a pixel during a data writing period according to an embodiment of the present invention; [Figure 8B] 4 is a diagram illustrating an operation of a pixel during a data writing period according to an embodiment of the present invention; [Figure 9A] 4 is a diagram illustrating an operation of a pixel during a light-emitting period according to an embodiment of the present invention; [Figure 9B] 4 is a diagram illustrating an operation of a pixel during a light-emitting period according to an embodiment of the present invention; [Figure 10] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 11] 11 is a waveform diagram showing signals applied to the pixel shown in FIG. 10. FIG. [Figure 12A] 4 is a diagram illustrating an operation of a pixel during an initialization period according to an embodiment of the present invention; [Figure 12B]4 is a diagram illustrating an operation of a pixel during an initialization period according to an embodiment of the present invention; [Figure 13A] 10 is a diagram illustrating an operation of a pixel during a compensation period according to an embodiment of the present invention; [Figure 13B] 10 is a diagram illustrating an operation of a pixel during a compensation period according to an embodiment of the present invention; [Figure 14] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 15] 15 is a waveform diagram showing signals applied to the pixel shown in FIG. 14. FIG. [Figure 16] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 17] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 18] FIG. 18 is a block diagram of the first and second gate driving circuits shown in FIG. 17. [Figure 19] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 20] 20 is a waveform diagram showing signals applied to the pixel shown in FIG. 19. FIG. [Figure 21A] 4 is a diagram illustrating an operation of a pixel during an initialization period according to an embodiment of the present invention; [Figure 21B] 4 is a diagram illustrating an operation of a pixel during an initialization period according to an embodiment of the present invention; [Figure 22A] 10 is a diagram illustrating an operation of a pixel during a compensation period according to an embodiment of the present invention; [Figure 22B] 10 is a diagram illustrating an operation of a pixel during a compensation period according to an embodiment of the present invention; [Figure 23A] 4 is a diagram illustrating an operation of a pixel during an interval according to an embodiment of the present invention; [Figure 23B] 4 is a diagram illustrating an operation of a pixel during an interval according to an embodiment of the present invention; [Figure 24A]4 is a diagram illustrating an operation of a pixel during a data writing period according to an embodiment of the present invention; [Figure 24B] 4 is a diagram illustrating an operation of a pixel during a data writing period according to an embodiment of the present invention; [Figure 25A] 4 is a diagram illustrating an operation of a pixel during a light-emitting period according to an embodiment of the present invention; [Figure 25B] 4 is a diagram illustrating an operation of a pixel during a light-emitting period according to an embodiment of the present invention; [Figure 26] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 27] 27 is a waveform diagram showing signals applied to the pixel shown in FIG. 26. FIG. [Figure 28A] 10 is a diagram illustrating an operation of a pixel during a compensation period according to an embodiment of the present invention; [Figure 28B] 10 is a diagram illustrating an operation of a pixel during a compensation period according to an embodiment of the present invention; [Figure 29] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 30] 30 is a waveform diagram showing signals applied to the pixel shown in FIG. 29. FIG. [Figure 31] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 32] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 33A] 33 is an enlarged cross-sectional view of a display panel according to an embodiment of the present invention, taken along an enlarged area AA in FIG. 32. FIG. [Figure 33B] 33 is an enlarged cross-sectional view of a display panel according to an embodiment of the present invention, enlarging a region BB in FIG. 32. FIG. [Figure 34] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 35A] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 35B] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 35C] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 36] 1 is a block diagram of an electronic device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] In this specification, when a certain component (or region, layer, portion, etc.) is described as being "on," "coupled," or "bonded" to another component, it means that it can be directly disposed / coupled / bonded to the other component, or that a third component can be disposed therebetween.

[0015] The same reference numerals refer to the same elements. Also, in the drawings, thickness, ratio, and size of elements are exaggerated for efficient explanation of technical contents. "And / or" includes all one or more combinations that the associated elements can define.

[0016] Terms such as "first," "second," etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component" without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0017] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0018] It should be understood that the use of terms such as "comprises" or "having" is intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, but does not preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted as being overly ideal or overly formal unless explicitly defined herein.

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0021] FIG. 1 is a block diagram of a display device DD according to an embodiment of the present invention, and FIG. 2 is a block diagram of first and second gate driving circuits 300 and 350 shown in FIG.

[0022] 1, the display device DD may include a display panel DP, a drive controller 100, and a panel driver. In one embodiment of the present invention, the panel driver may include a data drive circuit 200 (or a data driver), a first gate drive circuit 300, a second gate drive circuit 350, and a voltage generator 400.

[0023] The display panel DP may include a display area DA and a non-display area NDA surrounding at least a portion of the display area DA. The display panel DP may include a plurality of pixels PX arranged in the display area DA. The display panel DP may include write scan lines GWL1 to GWLn, compensation scan lines GCL1 to GCLn, and emission control lines EML1 to EMLn. The write scan lines GWL1 to GWLn may be referred to as first scan lines, and the compensation scan lines GCL1 to GCLn may be referred to as second scan lines. The emission control lines EML1 to EMLn may be referred to as first emission control lines.

[0024] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 generates the video data signal DATA by converting the data format of the image signal RGB so that it conforms to the interface specification with the data drive circuit 200. The drive controller 100 outputs a first gate control signal GCS1, a data control signal DCS, and a second gate control signal GCS2.

[0025] The data driving circuit 200 (or data driver) receives a data control signal DCS and a video data signal DATA from the driving controller 100. The data driving circuit 200 converts the video data signal DATA into a data signal and outputs the data signal to the data lines DL1 to DLm. The data signal is an analog voltage corresponding to the grayscale value of the video data signal DATA. The data lines DL1 to DLm may be arranged along a first direction DR1, and each of the data lines DL1 to DLm may extend along a second direction DR2.

[0026] The first and second gate driving circuits 300 and 350 may be disposed in the non-display area NDA of the display panel DP. In one embodiment, the first gate driving circuit 300 may be disposed adjacent to a first side (e.g., the left side) of the display area DA, and the second gate driving circuit 350 may be disposed adjacent to the first side and a second side (e.g., the right side) of the display area DA. In one embodiment, the second side may be the side opposite the first side. In the example shown in FIG. 1, the first and second gate driving circuits 300 and 350 are disposed on both sides of the display area DA, but the present invention is not limited thereto. For example, the first and second gate driving circuits 300 and 350 may be disposed adjacent to one of the first and second sides of the display panel DP. In one embodiment, the first and second gate driving circuits 300 and 350 may be integrated into a single circuit.

[0027] According to one embodiment of the present invention, each of the plurality of pixels PX includes a light-emitting element ED (see FIG. 3) and a pixel circuit PXCa (see FIG. 3) that controls the light emission of the light-emitting element ED (see FIG. 3).

[0028] The pixel circuit PXCa may include at least one transistor and at least one capacitor. The first and second gate driving circuits 300 and 350 may include transistors formed through the same process as the pixel circuit PXCa. The pixel circuit PXCa may be referred to as a pixel driving unit.

[0029] As an example of the present invention, the first gate driving circuit 300 may be connected to the write scan lines GWL1 to GWLn and the compensation scan lines GCL1 to GCLn. The first gate driving circuit 300 receives a first gate control signal GCS1 from the driving controller 100. The first gate driving circuit 300 may output a write scan signal and a compensation scan signal to the write scan lines GWL1 to GWLn and the compensation scan lines GCL1 to GCLn, respectively, in response to the first gate control signal GCS1. The write scan signal may be referred to as a first scan signal, and the compensation scan signal may be referred to as a second scan signal.

[0030] In one embodiment of the present invention, the second gate driving circuit 350 may be connected to the light emitting control lines EML1 to EMLn and may output a light emitting control signal to the light emitting control lines EML1 to EMLn in response to a second gate control signal GCS2 from the driving controller 100.

[0031] Each of the write scan lines GWL1 to GWLn, the compensation scan lines GCL1 to GCLn, and the emission control lines EML1 to EMLn may be extended in a first direction DR1, and the write scan lines GWL1 to GWLn, the compensation scan lines GCL1 to GCLn, and the emission control lines EML1 to EMLn may be spaced apart in a second direction DR2.

[0032] 2, the first gate driving circuit 300 may include a first scan driving circuit GWD and a second scan driving circuit GCD. The second gate driving circuit 350 may include an emission control circuit EMD. The arrangement order of the first and second scan driving circuits GWD and GCD in the first direction DR1 shown in FIG. 2 is merely an example and is not particularly limited.

[0033] 2, the first scan driving circuit GWD is connected to the i-th write scan line GWLi and the (i+1)-th write scan line GWLi+1, the second scan driving circuit GCD is connected to the i-th compensation scan line GCLi and the (i+1)-th compensation scan line GCLi+1, the light emitting control circuit EMD is connected to the i-th light emitting control line EMLi and the (i+1)-th light emitting control line EMLi+1, and the pixels PXi1, PX(i+1)1, PXim, and PX(i+1)m connected to the first data line DL1 and the m-th data line DLm are shown as an example.

[0034] Each of the pixels PXil, PX(i+1)l, PXim, and PX(i+1)m may be electrically connected to two scan lines, one light-emitting control line, and one data line. For example, the pixel in the i-th row may be connected to the i-th write and compensation scan lines GWLi and GCLi and the i-th light-emitting control line EMLi. The pixel in the first column may be connected to the first data line DL1. However, the embodiment is not limited thereto, and each of the pixels PXil, PX(i+1)l, PXim, and PX(i+1)m may be connected to more than two scan lines.

[0035] 1 and 2, a voltage generator 400 (or a power supply) generates voltages required for the operation of a display panel DP. In this embodiment, the voltage generator 400 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, and a reference voltage Vref. Alternatively, the voltage generator 400 may further generate an initialization voltage Vint (see FIG. 10).

[0036] Each of the pixels PXil, PX(i+1)l, PXim, and PX(i+1)m may be connected to a first power supply P line PL1, a second power supply P line PL2, and a reference voltage line VL1. The first power supply P line PL1 receives a first driving voltage ELVDD from the voltage generator 400, and the second power supply P line PL2 receives a second driving voltage ELVSS from the voltage generator 400. The reference voltage line VL1 receives a reference voltage Vref from the voltage generator 400. Alternatively, each of the pixels PXil, PX(i+1)l, PXim, and PX(i+1)m may be further connected to an initialization voltage line VL2 (see FIG. 10). In this case, the initialization voltage line VL2 may receive the initialization voltage Vint from the voltage generator 400.

[0037] 3 is a circuit diagram of a pixel PXij according to an embodiment of the present invention, and FIG. 4 is a waveform diagram of signals applied to the pixel PXij shown in FIG.

[0038] 3 shows a pixel PXij connected to the ith write scan line GWLi among the write scan lines GWL1 to GWLn (see FIG. 1) and the jth data line DLj among the data lines DL1 to DLm (see FIG. 1). The pixel PXij is connected to the ith compensation scan line GCLi among the compensation scan lines GCL1 to GCLn (see FIG. 1) and the ith emission control line EMLi among the emission control lines EML1 to EMLn (see FIG. 1).

[0039] The pixel PXij may include a pixel circuit PXCa (or a pixel driving circuit) and a light emitting element ED electrically connected to the pixel circuit PXCa. In this embodiment, the pixel circuit PXCa may include six transistors (first to fourth transistors T1 to T4, first and second light emitting control transistors ET1 and ET2) and two capacitors (hereinafter referred to as a first capacitor C1 and a second capacitor C2). In one embodiment of the present invention, any one of the six transistors of the pixel circuit PXCa may be omitted, or an additional transistor may be further included in the pixel circuit PXCa.

[0040] The i-th write scan line GWLi may transmit the i-th write scan signal GWi to the pixel PXij, and the i-th compensation scan line GCLi may transmit the i-th compensation scan signal GCi to the pixel PXij. The i-th emission control line EMLi may transmit the i-th emission control signal EMi to the pixel PXij, and the j-th data line DLj may transmit the j-th data signal DSj to the pixel PXij. The j-th data signal DSj may have a voltage level corresponding to the gray scale value of the image data signal DATA (see FIG. 1) output from the drive controller 100 (see FIG. 1).

[0041] Furthermore, pixel PXij may be connected to a first power supply P line PL1 receiving a first driving voltage ELVDD, a second power supply P line PL2 receiving a second driving voltage ELVSS, and a reference voltage line VL1 receiving a reference voltage Vref. The first driving voltage ELVDD may have a higher voltage level than the second driving voltage ELVSS, and the reference voltage Vref may have a lower voltage level than the second driving voltage ELVSS. In one example of the present invention, the first driving voltage ELVDD may be 8.4V, the second driving voltage ELVSS may be 0V, and the reference voltage Vref may be -1.0V. Alternatively, the reference voltage Vref may have a voltage level lower than the first driving voltage ELVDD and higher than the second driving voltage ELVSS.

[0042] In this embodiment, the first to fourth transistors T1 to T4 and the first and second light-emitting control transistors ET1 and ET2 may each be an N-type transistor, and may each include an oxide semiconductor as a semiconductor layer.

[0043] The light emitting element ED may include an anode and a cathode. If the light emitting element ED is an organic light emitting element, the light emitting element ED may further include an organic layer disposed between the anode and the cathode. The anode of the light emitting element ED may be connected to the first power line PL1. In this embodiment, the anode of the light emitting element ED may be directly connected to the first power line PL1. The cathode of the light emitting element ED may be connected to the pixel circuit PXCa. The light emitting element ED may emit light in response to the amount of current flowing through the first transistor T1 of the pixel circuit PXCa.

[0044] The first transistor T1 is connected between the cathode of the light emitting element ED and a second power supply P line PL2 receiving a second driving voltage ELVSS. The first transistor T1 may be referred to as a driving transistor. The first transistor T1 may include a first electrode, a second electrode, and a gate electrode. The first electrode of the first transistor T1 may be connected to a fourth node N4, the second electrode of the first transistor T1 may be connected to a second node N2, and the gate electrode of the first transistor T1 may be connected to the first node N1. The first electrode may be referred to as the drain of the first transistor T1, and the second electrode may be referred to as the source of the first transistor T1. The first transistor T1 may be operated in response to the potential of the first node N1. In this embodiment, the first transistor T1 may further include a back gate electrode. The back gate electrode may be connected to the second electrode of the first transistor T1.

[0045] The second transistor T2 is connected between the jth data line DLj and the first node N1 and receives the i-th first write scan signal GWi. The second transistor T2 may be referred to as a switching transistor. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first node N1, and a gate electrode connected to the i-th write scan line GWLi. The second transistor T2 may transmit the j-th data signal DSj received through the j-th data line DLj to the first node N1 in response to the i-th write scan signal GWi received through the i-th write scan line GWLi.

[0046] The third transistor T3 is connected between the reference voltage line VL1 and the first node N1 and receives the i-th compensation scan signal GCi. The third transistor T3 may be referred to as a compensation transistor. The third transistor T3 may include a first electrode connected to the reference voltage line VL1, a second electrode connected to the first node N1, and a gate electrode connected to the i-th compensation scan line GCLi. The third transistor T3 may be turned on in response to the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi to transmit the reference voltage Vref to the first node N1. The first node N1 may be defined as a node to which the gate electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the third transistor T3 are connected.

[0047] The first light-emitting control transistor ET1 is connected between the first transistor T1 and the second power line PL2 and can receive the i-th light-emitting control signal EMi. The first light-emitting control transistor ET1 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the second power line PL2, and a gate electrode connected to the i-th light-emitting control line EMLi. The first light-emitting control transistor ET1 is turned on in response to the i-th light-emitting control signal EMi received through the i-th light-emitting control line EMLi to electrically connect the second power line PL2 to the second electrode of the first transistor T1. The gate electrode of the first light-emitting control transistor ET1 can be connected to the i-th light-emitting control line EMLi through a third node N3.

[0048] The first capacitor C1 may be connected between the first node N1 and the second node N2. The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The first capacitor C1 may store a differential voltage between the first node N1 and the second node N2.

[0049] The second capacitor C2 may be connected between the second node N2 and the third node N3. The second capacitor C2 may include a first electrode connected to the second node N2 and a second electrode connected to the third node N3. The i-th light emitting control signal EMi may be applied to the third node N3. The second capacitor C2 may store a differential voltage between the third node N3 and the second node N2. In one example of the present invention, the capacitance of the second capacitor C2 may be the same as the capacitance of the first capacitor C1. However, the present invention is not limited thereto, and the relationship between the capacitances of the first and second capacitors C1 and C2 may be variously modified.

[0050] The second node N2 may be defined as a node to which the second electrode of the first transistor T1, the first electrode of the first light-emitting control transistor ET1, the second electrode of the first capacitor C1, and the first electrode of the second capacitor C2 are connected, and the third node N3 may be defined as a node to which the gate electrode of the first light-emitting control transistor ET1, the second electrode of the second capacitor C2, and the i-th light-emitting control line EMLi are connected.

[0051] The fourth transistor T4 is connected between the first power line PL1 and a fourth node N4 and receives the i-th compensation scan signal GCi. The fourth transistor T4 includes a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1 (i.e., the fourth node N4), and a gate electrode connected to the i-th compensation scan line GCLi. The fourth transistor T4 is turned on in response to the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi to transmit the first driving voltage ELVDD to the fourth node N4.

[0052] The second emission control transistor ET2 is connected between the first transistor T1 and the cathode of the light emitting element ED and can receive the i-th emission control signal EMi. The second emission control transistor ET2 includes a first electrode connected to the cathode of the light emitting element ED, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the i-th emission control line EMLi. The second emission control transistor ET2 is turned on in response to the i-th emission control signal EMi received through the i-th emission control line EMLi to electrically connect the cathode of the light emitting element ED to the first electrode of the first transistor T1.

[0053] The fourth node N4 may be defined as a node to which the first electrode of the first transistor T1, the second electrode of the fourth transistor T4, and the second electrode of the second light-emitting control transistor ET2 are connected.

[0054] In this embodiment, the third and fourth transistors T3 and T4 may receive the same scan signal (i.e., the i-th compensation scan signal GCi). Therefore, the number of scan signals required to drive the pixel PXij may be reduced to two, and as a result, the number of scan driving circuits required to drive the pixel PXij may be reduced to two. If the number of scan driving circuits is reduced, the width of the non-display area NDA (see FIG. 1) of the display panel DP (see FIG. 1) may be narrowed, thereby eliminating the problem of increased dead space on the display panel DP.

[0055] 4, each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, and the i-th emission control signal EMi may have an activation level (or high level) during a partial period (i.e., an activation period) and an inactivation level (or low level) during the remaining partial period (i.e., an inactivation period). If the six transistors T1 to T4, ET1, and ET2 described above are N-type transistors, each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, and the i-th emission control signal EMi may have a high activation level. Alternatively, if the six transistors T1 to T4, ET1, and ET2 are P-type transistors, each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, and the i-th emission control signal EMi may have a low activation level.

[0056] The inactive interval NAP of the i-th light emission control signal EMi may overlap with the active interval AP1 of the i-th write scan signal GWi and the active interval AP2 of the i-th compensation scan signal GCi. As an example of the present invention, the active interval AP1 of the i-th write scan signal GWi may have a duration shorter than or equal to the duration of the horizontal scan period 1H, and the active interval AP2 of the i-th compensation scan signal GCi may have a duration longer than the duration of the horizontal scan period 1H. For example, the duration of the active interval AP1 of the i-th write scan signal GWi may correspond to 1 / 3 of the duration of the horizontal scan period 1H, and the duration of the active interval AP2 of the i-th compensation scan signal GCi may correspond to 3 times the duration of the horizontal scan period 1H.

[0057] 5A and 5B are diagrams illustrating the operation of a pixel PXij during an initialization period Tint according to an embodiment of the present invention.

[0058] Referring to Figures 5A and 5B, during the initialization period Tint, the i-th compensation scan signal GCi and the i-th emission control signal EMi may have an activation level (e.g., a high level), and the i-th write scan signal GWi may have an inactivation level (e.g., a low level).

[0059] During the initialization period Tint, the third transistor T3 and the fourth transistor T4 are turned on in response to the i-th compensation scan signal GCi, so that the first node N1 is initialized to the reference voltage Vref and the fourth node N4 is initialized to the first driving voltage ELVDD.

[0060] During the initialization period Tint, the first and second light-emitting control transistors ET1 and ET2 are turned on in response to the i-th light-emitting control signal EMi. Therefore, during the initialization period Tint, the cathode of the light-emitting element ED is initialized to the first driving voltage ELVDD, and the second node N2 is initialized to the second driving voltage ELVSS.

[0061] During the initialization period Tint, the first node N1 and the second node N2 are initialized simultaneously, so that the first capacitor C1 can be initialized with the difference between the reference voltage Vref and the second driving voltage ELVSS. The second capacitor C2 can be initialized with the difference between the second driving voltage ELVSS and the high-level voltage (e.g., 14V) of the i-th light-emitting control signal EMi. The initialization period Tint can be defined as a period in which the gate electrode and the second electrode (i.e., source) of the first transistor T1 are initialized, and as a period in which the cathode of the light-emitting element ED is initialized.

[0062] During the initialization period Tint, the potential difference between the first and second nodes N1 and N2 (ie, the gate-source voltage Vgs of the first transistor T1) is smaller than the threshold voltage Vth of the first transistor T1, so the first transistor T1 may be turned off.

[0063] The initialization period Tint may end when the i-th light emission control signal EMi is deactivated.

[0064] 6A and 6B are diagrams illustrating the operation of a pixel PXij during a compensation period Tcom according to an embodiment of the present invention.

[0065] 6A and 6B, the compensation period Tcom occurs after the initialization period Tint (see FIG. 5B). That is, the compensation period Tcom occurs after the initialization period Tint.

[0066] During the compensation period Tcom, the i-th compensation scan signal GCi may have an activation level (e.g., a high level), and the i-th write scan signal GWi and the i-th light emitting control signal EMi may have an inactivation level (e.g., a low level). The compensation period Tcom may begin when the i-th light emitting control signal EMi is inactivated.

[0067] During the compensation period Tcom, the third transistor T3 and the fourth transistor T4 may maintain a turn-on state in response to the i-th compensation scan signal GCi, and therefore, during the compensation period Tcom, the reference voltage Vref may be applied to the first node N1 and the first driving voltage ELVDD may be applied to the fourth node N4.

[0068] During the compensation period Tcom, the first and second light-emitting control transistors ET1 and ET2 may be turned off in response to the i-th light-emitting control signal EMi. Therefore, at the start of the compensation period Tcom, the potential Vs of the second node N2 may be changed from the second driving voltage ELVSS to "Vref-Vth." The i-th light-emitting control signal EMi is pulled down to a low level (e.g., -4V) during the compensation period Tcom. As the i-th light-emitting control signal EMi is pulled down to a low level, the potential Vs of the second node N2 may become lower than "Vref-Vth" due to the second capacitor C2. If the potential Vs of the second node N2 decreases while the potential Vg of the first node N1 is maintained at the reference voltage Vref, the gate-source voltage Vgs may become higher than the threshold voltage Vth.

[0069] When the gate-source voltage Vgs becomes larger than the threshold voltage Vth, the first transistor T1 is switched to a turn-on state, and the threshold voltage Vth of the first transistor T1 can be compensated by the coupling of the first capacitor C1.

[0070] The compensation period Tcom may be ended when the i-th compensation scan signal GCi is deactivated.

[0071] 7A and 7B are diagrams illustrating the operation of pixel PXij during interval Tinv according to an embodiment of the present invention.

[0072] 7A and 7B, an interval section Tinv may be present after the compensation section Tcom (see FIG. 6B).

[0073] During the interval period Tinv, the i-th compensation scan signal GCi, the i-th write scan signal GWi, and the i-th light emission control signal EMi may have an inactive level (e.g., a low level). Therefore, during the interval period Tinv, the second to fourth transistors T2 to T4 and the first and second light emission control transistors ET1 and ET2, except for the first transistor T1, may all be turned off.

[0074] The interval Tinv may end when the i-th write scan signal GWi is activated.

[0075] 8A and 8B are diagrams illustrating the operation of a pixel during a data writing period according to an embodiment of the present invention.

[0076] 8A and 8B, when the interval period Tinv (see FIG. 7B) ends, the data write period Tdw occurs, that is, the data write period Tdw is executed after the compensation period Tcom and the interval period Tinv.

[0077] 7B illustrates an example in which the interval Tinv exists between the compensation interval Tcom and the data write interval Tdw, but the present invention is not limited thereto. For example, the interval Tinv may be omitted between the compensation interval Tcom and the data write interval Tdw, and the data write interval Tdw may occur immediately after the compensation interval Tcom.

[0078] During the data write period Tdw, the i-th write scan signal GWi may have an activation level (e.g., a high level), and the i-th compensation scan signal GCi and the i-th emission control signal EMi may have an inactivation level (e.g., a low level). The data write period Tdw may begin when the i-th write scan signal GWi is activated.

[0079] During the data write period Tdw, the second transistor T2 may be turned on in response to the ith write scan signal GWi, and thus the jth data signal DSj may be applied to the first node N1 during the data write period Tdw, and thus the potential Vg of the first node N1 may be switched from the reference voltage Vref to the data voltage Vdata corresponding to the jth data signal DSj.

[0080] When the potential Vg of the first node N1 is switched from the reference voltage Vref to the data voltage Vdata, the potential Vs of the second node N2 is changed due to the coupling of the first capacitor C1. Specifically, the potential Vs of the second node N2 satisfies the following mathematical formula (1):

[0081]

number

[0082] During the data write period Tdw, the i-th compensation scan signal GCi has an inactive level, so that the fourth transistor T4 can be turned off. That is, during the data write period Tdw, the first electrode (fourth node N4) of the first transistor T1 is in a floating state, so that the potential Vs of the second node N2 changes due to a current (i.e., leakage current) flowing through the first electrode of the first transistor T1. If the potential Vs of the second node N2 changes, the gate-source voltage Vgs of the first transistor T1 can also change. As a result, the longer the data write period Tdw, the longer the time during which the data voltage Vdata written to the first node N1 is affected by the leakage current. Therefore, by setting the data write period Tdw to be equal to or shorter than the horizontal scan period 1H, the influence of the leakage current on the gate-source voltage Vgs can be minimized, thereby enabling the data voltage Vdata to be accurately written to the first node N1. As an example of the present invention, the duration of the data write interval Tdwa may correspond to 1 / 2 or 1 / 3 times the duration of the horizontal scan interval 1H. The data write interval Tdw may end when the i-th write scan signal GWi is deactivated.

[0083] 9A and 9B are diagrams illustrating the operation of a pixel during a light-emitting period according to an embodiment of the present invention.

[0084] 9A and 9B, when the data write period Tdw (see FIG. 8B) ends, the light emitting period Tem occurs, that is, the light emitting period Tem is executed after the data write period Tdw.

[0085] During the light-emitting interval Tem, the i-th compensation scan signal GCi and the i-th write scan signal GWi may have an inactive level (e.g., a low level), and the i-th light-emitting control signal EMi may have an active level (e.g., a high level). The light-emitting interval Tem may begin when the i-th light-emitting control signal EMi is activated.

[0086] During the light-emitting period Tem, the first transistor T1 may maintain a turn-on state due to the gate-source voltage Vgs of the first transistor T1, which corresponds to the differential voltage stored in the first capacitor C1. During the light-emitting period Tem, the first and second light-emitting control transistors ET1 and ET2 may be turned on in response to the i-th light-emitting control signal EMi. When the i-th light-emitting control signal EMi is switched to an activated level during the light-emitting period Tem, the potential Vs of the second node N2 may rise due to coupling of the second capacitor C2. Even if the potential Vs of the second node N2 rises, the potential Vg of the first node N1 also rises due to coupling of the first capacitor C1, so the gate-source voltage Vgs of the first transistor T1 may be maintained unchanged during the light-emitting period Tem. Here, the gate-source voltage Vgs of the first transistor T1 may satisfy the following mathematical equation (2):

[0087]

number

[0088] According to the present invention, the threshold voltage Vth of the first transistor T1 does not affect the current flowing through the light-emitting element ED. The threshold voltage Vth of each of the first transistors T1 included in each of the pixels PX (see FIG. 1) may differ depending on the characteristics of the first transistor T1. However, even if the characteristics of the first transistor T1 included in each of the pixels PX (see FIG. 1) differ, the current flowing through the light-emitting element ED in the subsequent light-emitting period Tem may be constant. Therefore, the overall display quality of the display device DD (see FIG. 1) may be improved.

[0089] Figure 10 is a circuit diagram of pixel PXij according to an embodiment of the present invention, and Figure 11 is a waveform diagram showing signals applied to pixel PXij shown in Figure 10. However, among the components shown in Figure 10, the same components as those shown in Figure 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0090] 10, pixel PXij may include a pixel circuit PXCb (or a pixel driving circuit) and a light emitting element ED electrically connected to pixel circuit PXCb. In this embodiment, pixel circuit PXCb may include seven transistors (first to fourth transistors T1 to T4a and first to third light emitting control transistors ET1a, ET2, and ET3) and two capacitors (hereinafter referred to as a first capacitor C1 and a second capacitor C2). In one embodiment of the present invention, any one of the seven transistors of pixel circuit PXCb may be omitted, or an additional transistor may be further included in pixel circuit PXCb.

[0091] In this embodiment, each of the first to fourth transistors T1 to T4a and the first to third light-emitting control transistors ET1a, ET2, and ET3 may be an N-type transistor having an oxide semiconductor as a semiconductor layer.

[0092] The fourth transistor T4a is connected between the initialization voltage V line VL2 and the fourth node N4 and receives the i-th compensation scan signal GCi. The fourth transistor T4a includes a first electrode connected to the initialization voltage V line VL2, a second electrode connected to the first electrode of the first transistor T1 (i.e., the fourth node N4), and a gate electrode connected to the i-th compensation scan line GCLi. The fourth transistor T4a is turned on in response to the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi to transmit the initialization voltage Vint applied to the initialization voltage V line VL2 to the fourth node N4.

[0093] The first emission control transistor ET1a is connected between the first transistor T1 and the third emission control transistor ET3 and can receive the i-th emission control signal EMi. The first emission control transistor ET1a includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the third emission control transistor ET3, and a gate electrode connected to the i-th emission control line EMLi. The first emission control transistor ET1a is turned on in response to the i-th emission control signal EMi received through the i-th emission control line EMLi to electrically connect the third emission control transistor ET3 to the second electrode of the first transistor T1. The gate electrode of the first emission control transistor ET1a can be connected to the i-th emission control line EMLi through a third node N3.

[0094] The third light-emitting control transistor ET3 is connected between the first light-emitting control transistor ET1a and the second power line PL2 and can receive the (i-1)th light-emitting control signal EMi-1 (or referred to as the third light-emitting control signal). The third light-emitting control transistor ET3 includes a first electrode connected to the second electrode of the first light-emitting control transistor ET1a, a second electrode connected to the second power line PL2, and a gate electrode connected to the (i-1)th light-emitting control line EMLi-1. The third light-emitting control transistor ET3 is turned on in response to the (i-1)th light-emitting control signal EMi-1 received through the (i-1)th light-emitting control line EMLi-1 to electrically connect the second power line PL2 to the second electrode of the first light-emitting control transistor ET1a.

[0095] 11, the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th light emitting control signal EMi, and the (i-1)-th light emitting control signal EMi-1 may each have an activation level (or high level) during a partial period (i.e., an activation period) and an inactivation level (or low level) during the remaining partial period (i.e., an inactivation period). If the seven transistors T1 through T4a, ET1a, ET2, and ET3 described above are P-type transistors, the activation levels of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th light emitting control signal EMi, and the (i-1)-th light emitting control signal EMi-1 may each be high. Alternatively, if the seven transistors T1 through T4a, ET1a, ET2, and ET3 are P-type transistors, the activation levels of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th light emitting control signal EMi, and the (i-1)-th light emitting control signal EMi-1 may each be low.

[0096] The (i-1)th light-emitting control signal EMi-1 may be deactivated before the i-th light-emitting control signal EMi. Therefore, the start of the inactivation period NAP2 of the (i-1)th light-emitting control signal EMi-1 precedes the start of the inactivation period NAP1 of the i-th light-emitting control signal EMi. The inactivation period NAP1 of the i-th light-emitting control signal EMi-1 and the inactivation period NAP2 of the (i-1)th light-emitting control signal EMi-1 may overlap with the activation period AP1 of the i-th write scan signal GWi and the activation period AP2 of the i-th compensation scan signal GCi. As an example, the activation period AP1 of the i-th write scan signal GWi may have a duration shorter than or equal to the duration of the horizontal scan period 1H, and the activation period AP2 of the i-th compensation scan signal GCi may have a duration longer than the duration of the horizontal scan period 1H.

[0097] 12A and 12B are diagrams illustrating the operation of a pixel PXij during an initialization period Tinta according to an embodiment of the present invention.

[0098] Referring to Figures 12A and 12B, during the initialization period Tinta, the i-th compensation scan signal GCi, the i-1-th light emitting control signal EMi-1, and the i-th light emitting control signal EMi may have an activation level (e.g., a high level), and the i-th write scan signal GWi may have an inactivation level (e.g., a low level).

[0099] During the initialization period Tinta, the third transistor T3 and the fourth transistor T4a are turned on in response to the i-th compensation scan signal GCi, so that the first node N1 is initialized to the reference voltage Vref and the fourth node N4 is initialized to the initialization voltage Vint.

[0100] During the initialization period Tinta, the first and second light-emitting control transistors ET1a and ET2 are turned on in response to the i-th light-emitting control signal EMi. Therefore, during the initialization period Tinta, the cathode of the light-emitting element ED is initialized to the initialization voltage Vint. During the initialization period Tinta, the third light-emitting control transistor ET3 is turned on in response to the (i-1)th light-emitting control signal EMi-1. Therefore, the second node N2 can be initialized to the second driving voltage ELVSS through the turned-on first and third light-emitting control transistors ET1a and ET3.

[0101] During the initialization period Tinta, the first node N1 and the second node N2 are simultaneously initialized, so that the first capacitor C1 may be initialized with the difference between the reference voltage Vref and the second driving voltage ELVSS. The second capacitor C2 may be initialized with the difference between the second driving voltage ELVSS and the high-level voltage (e.g., 14V) of the i-th light-emitting control signal EMi. The initialization period Tinta may be defined as a period in which the gate electrode and the second electrode (i.e., source) of the first transistor T1 are initialized, and as a period in which the cathode of the light-emitting element ED is initialized.

[0102] During the initialization period Tinta, the potential difference between the first and second nodes N1 and N2 (ie, the gate-source voltage Vgs of the first transistor T1) is smaller than the threshold voltage Vth of the first transistor T1, so the first transistor T1 may be turned off.

[0103] The initialization period Tinta may end when the (i-1)th light emission control signal EMi-1 is deactivated.

[0104] 13A and 13B are diagrams illustrating the operation of a pixel during a compensation period according to an embodiment of the present invention.

[0105] 13A and 13B, after the initialization period Tinta (see FIG. 12B) ends, the compensation period Tcoma occurs, that is, the compensation period Tcoma is executed after the initialization period Tinta.

[0106] During the compensation period Tcoma, the i-th compensation scan signal GCi may have an activation level (e.g., a high level), and the i-th write scan signal GWi, the (i-1)-th light emitting control signal EMi-1, and the i-th light emitting control signal EMi may have an inactivation level (e.g., a low level). The compensation period Tcoma may begin when the i-th light emitting control signal EMi is inactivated.

[0107] During the compensation period Tcoma, the third transistor T3 and the fourth transistor T4a may maintain a turn-on state in response to the i-th compensation scan signal GCi, and therefore, during the compensation period Tcoma, the reference voltage Vref may be applied to the first node N1 and the initialization voltage Vint may be applied to the fourth node N4.

[0108] During the compensation period Tcoma, the first and second light-emitting control transistors ET1a and ET2 may be turned off in response to the i-th light-emitting control signal EMi. Also, during the compensation period Tcoma, the third light-emitting control transistor ET3 may be turned off in response to the (i-1)th light-emitting control signal EMi-1. Therefore, at the start of the compensation period Tcoma, the potential Vs of the second node N2 may be changed from the second driving voltage ELVSS to "Vref-Vth." The i-th light-emitting control signal EMi is lowered to a low level (e.g., -4V) during the compensation period Tcoma. Because the i-th light-emitting control signal EMi has a low level, the potential Vs of the second node N2 may also be lower than "Vref-Vth" due to the second capacitor C2. If the potential Vs of the second node N2 decreases while the potential Vg of the first node N1 is maintained at the reference voltage Vref, the gate-source voltage Vgs may become greater than the threshold voltage Vth.

[0109] When the gate-source voltage Vgs becomes larger than the threshold voltage Vth, the first transistor T1 is switched to a turn-on state, and the threshold voltage Vth of the first transistor T1 can be compensated by the coupling of the first capacitor C1.

[0110] The compensation period Tcoma may be ended when the i-th compensation scan signal GCi is deactivated.

[0111] Figure 14 is a circuit diagram of pixel PXij according to an embodiment of the present invention, and Figure 15 is a waveform diagram showing signals applied to pixel PXij shown in Figure 14. However, among the components shown in Figure 14, the same components as those shown in Figure 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0112] 14, pixel PXij may include a pixel circuit PXCc (or pixel driving circuit) and a light emitting element ED electrically connected to pixel circuit PXCc. In this embodiment, pixel circuit PXCc may include six transistors (first to fourth transistors T1 to T4b, first and second light emitting control transistors ET1 and ET2a) and two capacitors (hereinafter referred to as a first capacitor C1 and a second capacitor C2). In one embodiment of the present invention, any one of the six transistors of pixel circuit PXCc may be omitted, or an additional transistor may be further included in pixel circuit PXCc.

[0113] In this embodiment, each of the first to fourth transistors T1 to T4b and the first and second light-emitting control transistors ET1 and ET2a may be an N-type transistor having an oxide semiconductor as a semiconductor layer.

[0114] The fourth transistor T4b is connected between the initialization voltage V line VL2 and the fourth node N4a and receives the i-th compensation scan signal GCi. The fourth transistor T4b includes a first electrode connected to the initialization voltage V line VL2, a second electrode connected to the cathode of the light-emitting element ED (i.e., the fourth node N4a), and a gate electrode connected to the i-th compensation scan line GCLi. The fourth transistor T4b is turned on in response to the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi to transmit the initialization voltage Vint applied to the initialization voltage V line VL2 to the fourth node N4a. Because the cathode of the light-emitting element ED is directly connected to the fourth transistor T4b without passing through the second light-emitting control transistor ET2, the entire activation interval AP2 of the i-th compensation scan signal GCi can be used as an interval for initializing the cathode. Therefore, the cathode of the light-emitting element ED can be stably initialized.

[0115] The first light-emitting control transistor ET1 is connected between the first transistor T1 and the second power line PL2 and can receive the i-th first light-emitting control signal EM1i (or referred to as the first light-emitting control signal). The first light-emitting control transistor ET1 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the second power line PL2, and a gate electrode connected to the i-th first light-emitting control line EML1i. The first light-emitting control transistor ET1 is turned on by the i-th first light-emitting control signal EM1i received through the i-th first light-emitting control line EML1i to electrically connect the second power line PL2 to the second electrode of the first transistor T1. The gate electrode of the first light-emitting control transistor ET1 can be connected to the i-th first light-emitting control line EML1i through a third node N3.

[0116] The second light-emitting control transistor ET2a is connected between the first transistor T1 and the cathode of the light-emitting element ED (i.e., the fourth node N4a) and can receive the i-th second light-emitting control signal EM2i (or referred to as the second light-emitting control signal). The second light-emitting control transistor ET2a includes a first electrode connected to the fourth node N4a, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the i-th second light-emitting control line EML2i. The second light-emitting control transistor ET2a is turned on by the i-th second light-emitting control signal EM2i received through the i-th second light-emitting control line EML2i to electrically connect the cathode of the light-emitting element ED to the first electrode of the first transistor T1.

[0117] 15, each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th first light-emitting control signal EM1i, and the i-th second light-emitting control signal EM2i may have an activation level (or high level) during a partial period (i.e., an activation period) and an inactivation level (or low level) during the remaining partial period (i.e., an inactivation period). If the six transistors T1 to T4b, ET1, and ET2a described above are N-type transistors, each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th first light-emitting control signal EM1i, and the i-th second light-emitting control signal EM2i may have an activation level of a high level. Alternatively, if the six transistors T1 to T4b, ET1, and ET2a are P-type transistors, each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th first light-emitting control signal EM1i, and the i-th second light-emitting control signal EM2i may have an activation level of a low level.

[0118] The i-th first light-emitting control signal EM1i may be deactivated before the i-th second light-emitting control signal EM2i. Therefore, the start of the inactivation interval NAP1 of the i-th first light-emitting control signal EM1i precedes the start of the inactivation interval NAP3 of the i-th second light-emitting control signal EM2i. The inactivation interval NAP1 of the i-th first light-emitting control signal EM1i may overlap with the activation interval AP1 of the i-th write scan signal GWi and the activation interval AP2 of the i-th compensation scan signal GCi. The inactivation interval NAP3 of the i-th second light-emitting control signal EM2i may overlap with the activation interval AP1 of the i-th write scan signal GWi but not overlap with the activation interval AP2 of the i-th compensation scan signal GCi.

[0119] During the activation interval AP2 of the ith compensation scan signal GCi, the second light-emitting control transistor ET2a may be turned on in response to the ith second light-emitting control signal EM2i. As a result, during the initialization interval Tint and the compensation interval Tcom, the initialization voltage Vint applied to the fourth node N4a through the turned-on fourth transistor T4b may be applied to the first electrode of the first transistor T1 through the turned-on second light-emitting control transistor ET2a. That is, during the initialization interval Tint and the compensation interval Tcom, the cathode of the light-emitting element ED and the first electrode of the first transistor T1 may stably maintain an initialized state. During the initialization interval Tint, the ith compensation scan signal GCi, the ith first light-emitting control signal EM1i, and the ith second light-emitting control signal EM2i may have an activation level (e.g., a high level), and the ith write scan signal GWi may have an inactivation level (e.g., a low level). During the compensation period Tcom, the i-th compensation scan signal GCi may have an activation level (e.g., a high level), and the i-th write scan signal GWi and the i-th first light-emitting control signal EM1i may have an inactivation level (e.g., a low level). The compensation period Tcom may begin when the i-th first light-emitting control signal EM1i is inactivated.

[0120] Although not shown in the drawings, the pixel circuit PXCc may further include a third light-emitting control transistor ET3 (see FIG. 10) connected between the first light-emitting control transistor ET1 and the second power line PL2.

[0121] 16 is a circuit diagram of a pixel PXij according to an embodiment of the present invention, where the same components as those shown in FIG. 10 are denoted by the same reference numerals and will not be described in detail.

[0122] 16, pixel PXij may include a pixel circuit PXCd (or pixel driving circuit) and a light emitting element ED electrically connected to pixel circuit PXCd. In this embodiment, pixel circuit PXCd may include six transistors (first to fourth transistors T1 to T4a, first and second light emitting control transistors ET1 and ET2) and two capacitors (hereinafter referred to as a first capacitor C1 and a second capacitor C2). In one embodiment of the present invention, any one of the six transistors of pixel circuit PXCd may be omitted, or an additional transistor may be further included in pixel circuit PXCd.

[0123] In this embodiment, each of the first to fourth transistors T1 to T4a and the first and second light-emitting control transistors ET1 and ET2 may be an N-type transistor having an oxide semiconductor as a semiconductor layer.

[0124] The fourth transistor T4a is connected between the initialization voltage V line VL2 and the fourth node N4 and receives the i-th compensation scan signal GCi. The fourth transistor T4a includes a first electrode connected to the initialization voltage V line VL2, a second electrode connected to the first electrode of the first transistor T1 (i.e., the fourth node N4), and a gate electrode connected to the i-th compensation scan line GCLi. The fourth transistor T4a is turned on in response to the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi to transmit the initialization voltage Vint applied to the initialization voltage V line VL2 to the fourth node N4. In one example, the initialization voltage Vint may have different voltage levels depending on the color of the pixel PXij. That is, initialization voltages having different voltage levels may be applied to red, green, and blue pixels, respectively.

[0125] 1 to 16, by reducing the number of scan signals and emission control signals applied to the pixel PX to two and one, respectively, it is possible to reduce the number of scan driving circuits GWD, GCD and emission control circuits EMD included in the first and second gate driving circuits 300, 350. As a result, the circuit configuration provided in the non-display area NDA of the display panel DP can be simplified, and the width of the non-display area NDA can be reduced.

[0126] Figure 17 is a block diagram of a display device DDa according to an embodiment of the present invention, and Figure 18 is a block diagram of first and second gate driving circuits shown in Figure 17. However, among the components shown in Figures 17 and 18, the same components as those shown in Figures 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0127] 17 and 18, the display panel DPa may include write scan lines GWL1 to GWLn, compensation scan lines GCL1 to GCLn, reference scan lines GRL1 to GRLn, and emission control lines EML1 to EMLn. The write scan lines GWL1 to GWLn may be referred to as first scan lines, the compensation scan lines GCL1 to GCLn may be referred to as second scan lines, the reference scan lines GRL1 to GRLn may be referred to as third scan lines, and the emission control lines EML1 to EMLn may be referred to as first emission control lines.

[0128] As an example of the present invention, the first gate driving circuit 300 may be connected to the write scan lines GWL1 to GWLn and the compensation scan lines GCL1 to GCLn. The first gate driving circuit 300 receives a first gate control signal GCS1 from the driving controller 100. The first gate driving circuit 300 may output a write scan signal and a compensation scan signal to the write scan lines GWL1 to GWLn and the compensation scan lines GCL1 to GCLn, respectively, in response to the first gate control signal GCS1. The write scan signal may be referred to as a first scan signal, and the compensation scan signal may be referred to as a second scan signal.

[0129] In one embodiment of the present invention, the second gate driving circuit 350a may be connected to the reference scan lines GRL1 to GRLn and the light emitting control lines EML1 to EMLn. The second gate driving circuit 350a may output a reference scan signal and a light emitting control signal to the reference scan lines GRL1 to GRLn and the light emitting control lines EML1 to EMLn, respectively, in response to a second gate control signal GCS2 from the driving controller 100. The reference scan signal may be referred to as a third scan signal.

[0130] 18, the first gate drive circuit 300 may include a first scan drive circuit GWD and a second scan drive circuit GCD. The second gate drive circuit 350a may include a third scan drive circuit GRD and an emission control circuit EMD. The arrangement order of the third scan drive circuit GRD and the emission control circuit EMD in the first direction DR1 shown in FIG. 18 is merely an example and is not particularly limited.

[0131] 18, the first scan driving circuit GWD is connected to the i-th write scan line GWLi and the (i+1)-th write scan line GWLi+1, the second scan driving circuit GCD is connected to the i-th compensation scan line GCLi and the (i+1)-th compensation scan line GCLi+1, the third scan driving circuit GRD is connected to the i-th reference scan line GRLi and the (i+1)-th reference scan line GRLi+1, and the light emitting control circuit EMD is connected to the i-th light emitting control line EMLi and the (i+1)-th light emitting control line EMLi+1.

[0132] 18 shows an example in which the third scan driving circuit GRD is included in the second gate driving circuit 350a, but the present invention is not limited to this. The positions of the first to third scan driving circuits GWD, GCD, and GRD can be interchanged.

[0133] 18 also illustrates pixels PXil, PX(i+1)l, PXim, and PX(i+1)m connected to the first data line DL1 and the mth data line DLm. Each of the pixels PXil, PX(i+1)l, PXim, and PX(i+1)m may be electrically connected to three scan lines, one light-emitting control line, and one data line. For example, the pixel in the i-th row may be connected to the i-th write and compensation scan lines GWLi and GCLi, the i-th reference scan line GRLi, and the i-th light-emitting control line EMLi. The pixel in the first column may be connected to the first data line DL1. However, the embodiment is not limited thereto, and each of the pixels PXil, PX(i+1)l, PXim, and PX(i+1)m may be connected to more than three scan lines.

[0134] 19 is a circuit diagram of a pixel according to an embodiment of the present invention, and FIG 20 is a waveform diagram showing signals applied to the pixel shown in FIG 19.

[0135] 19 representatively illustrates a pixel PXij connected to the ith write scan line GWLi among the write scan lines GWL1 through GWLn (see FIG. 17) and connected to the jth data line DLj among the data lines DL1 through DLm (see FIG. 17). The pixel PXij is connected to the ith compensation scan line GCLi among the compensation scan lines GCL1 through GCLn (see FIG. 17) and connected to the ith reference scan line GRLi among the reference scan lines GRL1 through GRLn (see FIG. 17). The pixel PXij is connected to the ith emission control line EMLi among the emission control lines EML1 through EMLn (see FIG. 17).

[0136] The pixel PXij may include a pixel circuit PXC1 (or a pixel driving circuit) and a light emitting element ED electrically connected to the pixel circuit PXC1. In this embodiment, the pixel circuit PXC1 may include five transistors (first to fourth transistors T1, T2, T3a, and T4c, referred to as a first light emitting control transistor ET1) and two capacitors (hereinafter referred to as a first capacitor C1 and a second capacitor C2). In one embodiment of the present invention, any one of the five transistors of the pixel circuit PXC1 may be omitted, or an additional transistor may be further included in the pixel circuit PXC1.

[0137] The i-th write scan line GWLi can transmit the i-th write scan signal GWi to the pixel PXij, the i-th compensation scan line GCLi can transmit the i-th compensation scan signal GCi to the pixel PXij, the i-th reference scan line GRLi can transmit the i-th reference scan signal GRi to the pixel PXij, the i-th light emitting control line EMLi can transmit the i-th light emitting control signal EMi to the pixel PXij, and the j-th data line DLj can transmit the j-th data signal DSj to the pixel PXij.

[0138] In this embodiment, each of the first to fourth transistors T1, T2, T3a, and T4c and the first light-emitting control transistor ET1 may be an N-type transistor having an oxide semiconductor as a semiconductor layer.

[0139] The light emitting element ED may include an anode and a cathode. The anode of the light emitting element ED may be connected to the first power line PL1, and the cathode of the light emitting element ED may be connected to the pixel circuit PXC1. The light emitting element ED may emit light in response to the amount of current flowing through the first transistor T1 of the pixel circuit PXC1.

[0140] The third transistor T3a is connected between the reference voltage line VL1 and the first node N1 and receives the i-th reference scan signal GRi. The third transistor T3a may be referred to as a compensation transistor. The third transistor T3a may include a first electrode connected to the reference voltage line VL1, a second electrode connected to the first node N1, and a gate electrode connected to the i-th reference scan line GRLi. The third transistor T3a may be turned on in response to the i-th reference scan signal GRi received through the i-th reference scan line GRLi to transmit the reference voltage Vref to the first node N1. The first node N1 may be defined as a node to which the gate electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the third transistor T3a are connected.

[0141] The fourth transistor T4c is connected between the first power line PL1 and a fourth node N4b and receives the i-th compensation scan signal GCi. The fourth transistor T4c includes a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1 (i.e., the fourth node N4b), and a gate electrode connected to the i-th compensation scan line GCLi. The fourth transistor T4c is turned on in response to the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi to transmit the first driving voltage ELVDD to the fourth node N4b.

[0142] The fourth node N4b may be defined as a node to which the first electrode of the first transistor T1, the second electrode of the fourth transistor T4c, and the cathode of the light emitting element ED are connected.

[0143] In this embodiment, the third and fourth transistors T3a and T4c may receive different scan signals (ie, the i-th reference scan signal GRi and the i-th compensation scan signal GCi).

[0144] 20, the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, and the i-th emission control signal EMi may each have an activation level (or high level) during a partial period (i.e., an activation period) and an inactivation level (or low level) during the remaining partial period (i.e., an inactivation period). If the five transistors T1, T2, T3a, T4c, and ET1 described above are N-type transistors, the activation levels of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, and the i-th emission control signal EMi may each be high. Alternatively, if the five transistors T1, T2, T3a, T4c, and ET1 are P-type transistors, the activation levels of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, and the i-th emission control signal EMi may each be low.

[0145] The inactive interval NAPa of the ith light emission control signal EMi may overlap with the active interval APa of the ith write scan signal GWi, the active interval APb of the ith compensation scan signal GCi, and the active interval APc of the ith reference scan signal GRi. As an example of the present invention, the active interval APc of the ith reference scan signal GRi may not overlap with the active interval APa of the ith write scan signal GWi. The active interval APb of the ith compensation scan signal GCi may overlap with the active interval APc of the ith reference scan signal GRi and the active interval APa of the ith write scan signal GWi. In addition, the active interval APa of the ith write scan signal GWi may have a duration less than or equal to the duration of the horizontal scanning period 1H, and the active interval APb of the ith compensation scan signal GCi may have a duration greater than the duration of the horizontal scanning period 1H. The activation interval APc of the i-th reference scan signal GRi may have a duration longer than the activation interval APa of the i-th write scan signal GWi and shorter than the activation interval APb of the i-th compensation scan signal GCi.

[0146] 21A and 21B are diagrams illustrating the operation of a pixel PXij during an initialization period Tint1 according to an embodiment of the present invention.

[0147] Referring to Figures 21A and 21B, during the initialization period Tint1, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, and the i-th light emission control signal EMi may have an activation level (e.g., a high level), and the i-th write scan signal GWi may have an inactivation level (e.g., a low level).

[0148] During the initialization period Tint1, the third transistor T3a is turned on in response to the i-th reference scan signal GRi, and the fourth transistor T4c is turned on in response to the i-th compensation scan signal GCi. Therefore, during the initialization period Tint1, the first node N1 is initialized to the reference voltage Vref, and the fourth node N4b is initialized to the first driving voltage ELVDD.

[0149] During the initialization period Tint1, the first light-emitting control transistor ET1 is turned on in response to the i-th light-emitting control signal EMi, and therefore, the second node N2 can be initialized to the second driving voltage ELVSS during the initialization period Tint1.

[0150] During the initialization period Tint1, the first node N1 and the second node N2 are simultaneously initialized, so that the first capacitor C1 may be initialized with the difference between the reference voltage Vref and the second driving voltage ELVSS. The second capacitor C2 may be initialized with the difference between the second driving voltage ELVSS and the high-level voltage (e.g., 14V) of the i-th light-emitting control signal EMi. The initialization period Tint1 may be defined as a period in which the gate electrode and the second electrode (i.e., source) of the first transistor T1 are initialized, and as a period in which the cathode of the light-emitting element ED is initialized.

[0151] During the initialization period Tint1, the potential difference between the first and second nodes N1 and N2 (ie, the gate-source voltage Vgs of the first transistor T1) is smaller than the threshold voltage Vth of the first transistor T1, so the first transistor T1 may be turned off.

[0152] The initialization period Tint1 may end when the i-th light emission control signal EMi is deactivated.

[0153] 22A and 22B are diagrams illustrating the operation of a pixel during a compensation period according to an embodiment of the present invention.

[0154] 22A and 22B, after the initialization period Tint1 (see FIG. 21B) ends, the compensation period Tcom1 occurs, that is, the compensation period Tcom1 is executed after the initialization period Tint1.

[0155] During the compensation period Tcom1, the i-th compensation scan signal GCi and the i-th reference scan signal GRi may have an activated level (e.g., a high level), and the i-th write scan signal GWi and the i-th light emitting control signal EMi may have an inactivated level (e.g., a low level). The compensation period Tcom1 may begin when the i-th light emitting control signal EMi is inactivated.

[0156] During the compensation period Tcom1, the third transistor T3a may maintain a turn-on state in response to the i-th reference scan signal GRi, and the fourth transistor T4c may maintain a turn-on state in response to the i-th compensation scan signal GCi. Therefore, during the compensation period Tcom1, the reference voltage Vref may be applied to the first node N1, and the first driving voltage ELVDD may be applied to the fourth node N4b.

[0157] During the compensation period Tcom1, the first light-emitting control transistor ET1 may be turned off in response to the i-th light-emitting control signal EMi. Therefore, at the start of the compensation period Tcom1, the potential Vs of the second node N2 may be changed from the second driving voltage ELVSS to "Vref-Vth." The i-th light-emitting control signal EMi is pulled down to a low level (e.g., -4V) during the compensation period Tcom1. When the i-th light-emitting control signal EMi is pulled down to a low level, the potential Vs of the second node N2 may become lower than "Vref-Vth" due to the second capacitor C2. If the potential Vs of the second node N2 decreases while the potential Vg of the first node N1 is maintained at the reference voltage Vref, the gate-source voltage Vgs may become higher than the threshold voltage Vth.

[0158] When the gate-source voltage Vgs becomes larger than the threshold voltage Vth, the first transistor T1 is switched to a turn-on state, and the threshold voltage Vth of the first transistor T1 can be compensated by the coupling of the first capacitor C1.

[0159] The compensation period Tcom1 may be ended when the i-th reference scan signal GRi is deactivated.

[0160] 23A and 23B are diagrams illustrating pixel operations during an interval according to an embodiment of the present invention.

[0161] 23A and 23B, an interval section Tinv1 may be present after the compensation section Tcom1 (see FIG. 22B).

[0162] During the interval Tinv1, the i-th reference scan signal GRi, the i-th write scan signal GWi, and the i-th light-emitting control signal EMi may have an inactive level (e.g., a low level), and the i-th compensation scan signal GCi may have an active level (e.g., a high level). Therefore, during the interval Tinv1, the second and third transistors T2 and T3a and the first light-emitting control transistor ET1, except for the first and fourth transistors T1 and T4c, may be turned off.

[0163] During the interval Tinv1, the fourth transistor T4c may maintain a turn-on state in response to the i-th compensation scan signal GCi, and therefore the first driving voltage ELVDD may be applied to the fourth node N4b during the interval Tinv1.

[0164] The interval Tinv1 may start when the i-th reference scan signal GRi is deactivated and end when the i-th write scan signal GWi is activated.

[0165] 24A and 24B are diagrams illustrating the operation of a pixel during a data writing period according to an embodiment of the present invention.

[0166] 24A and 24B, when the interval period Tinv1 (see FIG. 23B) ends, the data write period Tdw1 occurs, that is, the data write period Tdw1 is executed after the compensation period Tcom1 and the interval period Tinv1.

[0167] 23B illustrates an example in which the interval Tinv1 exists between the compensation interval Tcom1 and the data write interval Tdw1, but the present invention is not limited to this. For example, the interval Tinv1 may be omitted between the compensation interval Tcom1 and the data write interval Tdw1, and the data write interval Tdw1 may occur immediately after the compensation interval Tcom1.

[0168] During the data write period Tdw1, the i-th write scan signal GWi and the i-th compensation scan signal GCi may have an activation level (e.g., a high level), and the i-th reference scan signal GRi and the i-th emission control signal EMi may have an inactivation level (e.g., a low level). The data write period Tdw1 may begin when the i-th write scan signal GWi is activated.

[0169] During the data write period Tdw1, the second transistor T2 may be turned on in response to the ith write scan signal GWi, and thus the jth data signal DSj may be applied to the first node N1 during the data write period Tdw1, and thus the potential Vg of the first node N1 may be switched from the reference voltage Vref to the data voltage Vdata corresponding to the jth data signal DSj.

[0170] When the potential Vg of the first node N1 is switched from the reference voltage Vref to the data voltage Vdata, the potential Vs of the second node N2 is changed due to the coupling of the first capacitor C1. Specifically, the potential Vs of the second node N2 satisfies the following mathematical formula (1):

[0171]

number

[0172] Although the threshold voltage Vth of the first transistor T1 may differ for each pixel PX (see FIG. 17), the pixel PXij shown in FIG. 19 can supply a current proportional to the data voltage Vdata to the light-emitting element ED regardless of the deviation in the threshold voltage Vth of the first transistor T1.

[0173] During the data write period Tdw1, the fourth transistor T4c can maintain a turn-on state in response to the i-th compensation scan signal GCi. Therefore, even during the data write period Tdw1, the first driving voltage ELVDD is applied to the fourth node N4b, so that the cathode of the light emitting element ED and the first electrode of the first transistor T1 can stably maintain an initialized state.

[0174] The data write period Tdw1 may end when the i-th write scan signal GWi is deactivated.

[0175] 25A and 25B are diagrams illustrating the operation of a pixel during a light-emitting period according to an embodiment of the present invention.

[0176] 25A and 25B, when the data write period Tdw1 (see FIG. 24B) ends, the light emitting period Tem1 occurs. That is, the light emitting period Tem1 is executed after the data write period Tdw1.

[0177] During the light-emitting interval Tem1, the i-th compensation scan signal GCi, the i-th write scan signal GWi, and the i-th reference scan signal GRi may have an inactive level (e.g., a low level), and the i-th light-emitting control signal EMi may have an active level (e.g., a high level). The light-emitting interval Tem1 may start when the i-th light-emitting control signal EMi is activated.

[0178] During the light-emitting period Tem1, the first light-emitting control transistor ET1 may be turned on in response to the i-th light-emitting control signal EMi. Also, during the light-emitting period Tem1, the first transistor T1 may maintain a turned-on state due to the gate-source voltage Vgs of the first transistor T1 corresponding to the differential voltage stored in the first capacitor C1. The gate-source voltage Vgs of the first transistor T1 may satisfy the following mathematical equation (2):

[0179]

number

[0180] According to the present invention, the threshold voltage Vth of the first transistor T1 does not affect the current flowing through the light-emitting element ED. The threshold voltage of each of the first transistors T1 included in each of the pixels PX (see FIG. 17) may vary depending on the characteristics of the first transistor T1. However, regardless of the characteristics of the first transistor T1 included in each of the pixels PX (see FIG. 17), the current flowing through the light-emitting element ED in the subsequent light-emitting period Tem1 may be constant. Therefore, the overall display quality of the display device DDa (see FIG. 17) may be improved.

[0181] Figure 26 is a circuit diagram of a pixel according to an embodiment of the present invention. Figure 27 is a waveform diagram showing signals applied to the pixel shown in Figure 26. However, among the components shown in Figure 26, the same components as those shown in Figure 19 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0182] 26, pixel PXij may include a pixel circuit PXC2 (or a pixel driving circuit) and a light emitting element ED electrically connected to pixel circuit PXC2. In this embodiment, pixel circuit PXC2 may include six transistors (first to fourth transistors T1, T2, T3a, T4c, and first and second light emitting control transistors ET1b, ET2b) and two capacitors (hereinafter referred to as a first capacitor C1 and a second capacitor C2). In another embodiment of the present invention, any one of the six transistors of pixel circuit PXC2 may be omitted, or an additional transistor may be further included in pixel circuit PXC2.

[0183] In this embodiment, each of the first to fourth transistors T1, T2, T3a, and T4c and the first and second light-emitting control transistors ET1b and ET2b may be an N-type transistor having an oxide semiconductor as a semiconductor layer.

[0184] The first light-emitting control transistor ET1b is connected between the first transistor T1 and the second light-emitting control transistor ET2b and can receive the i-th light-emitting control signal EMi (or referred to as the first light-emitting control signal). The first light-emitting control transistor ET1b can include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the second light-emitting control transistor ET2b, and a gate electrode connected to the i-th light-emitting control line EMLi. The first light-emitting control transistor ET1b can be turned on in response to the i-th light-emitting control signal EMi received through the i-th light-emitting control line EMLi to electrically connect the second light-emitting control transistor ET2b to the second electrode of the first transistor T1. The gate electrode of the first light-emitting control transistor ET1b can be connected to the i-th light-emitting control line EMLi through a third node N3.

[0185] The second light-emitting control transistor ET2b is connected between the first light-emitting control transistor ET1b and the second power line PL2 and can receive the (i-1)th light-emitting control signal EMi-1 (or referred to as the second light-emitting control signal). The second light-emitting control transistor ET2b includes a first electrode connected to the second electrode of the first light-emitting control transistor ET1b, a second electrode connected to the second power line PL2, and a gate electrode connected to the (i-1)th light-emitting control line EMLi-1. The second light-emitting control transistor ET2b is turned on in response to the (i-1)th light-emitting control signal EMi-1 received through the (i-1)th light-emitting control line EMLi-1 to electrically connect the second power line PL2 to the second electrode of the first light-emitting control transistor ET1b.

[0186] 27, each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, the i-th light emitting control signal EMi, and the (i-1)-th light emitting control signal EMi-1 may have an activation level (or high level) during a partial period (i.e., an activation period) and an inactivation level (or low level) during the remaining partial period (i.e., an inactivation period). If the six transistors T1, T2, T3a, T4c, ET1b, and ET2b described above are N-type transistors, the activation levels of each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, the i-th light emitting control signal EMi, and the (i-1)-th light emitting control signal EMi-1 may be high. Alternatively, if the six transistors T1, T2, T3a, T4c, ET1b, and ET2b are P-type transistors, the activation levels of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, the i-th light emitting control signal EMi, and the i-1-th light emitting control signal EMi-1 may be low.

[0187] The (i-1)th light-emitting control signal EMi-1 may be deactivated before the i-th light-emitting control signal EMi. Therefore, the start point of the inactivation period NAPb of the (i-1)th light-emitting control signal EMi-1 precedes the start point of the inactivation period NAPa of the i-th light-emitting control signal EMi. The inactivation period NAPa of the i-th light-emitting control signal EMi and the inactivation period NAPb of the (i-1)th light-emitting control signal EMi-1 may overlap with the activation period APa of the i-th write scan signal GWi, the activation period APb of the i-th compensation scan signal GCi, and the activation period APc of the i-th reference scan signal GRi.

[0188] 28A and 28B are diagrams illustrating the operation of a pixel during a compensation period according to an embodiment of the present invention.

[0189] Referring to Figures 28A and 28B, during the initialization period Tint2, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, the i-1-th light emitting control signal EMi-1, and the i-th light emitting control signal EMi may have an activation level (e.g., a high level), and the i-th write scan signal GWi may have an inactivation level (e.g., a low level).

[0190] During the initialization period Tint2, the third transistor T3a is turned on in response to the i-th reference scan signal GRi, and the fourth transistor T4c is turned on in response to the i-th compensation scan signal GCi. Therefore, during the initialization period Tint2, the first node N1 is initialized to the reference voltage Vref, and the fourth node N4b is initialized to the first driving voltage ELVDD.

[0191] During the initialization period Tint2, the first and second light-emitting control transistors ET1b and ET2b are turned on in response to the i-th light-emitting control signal EMi and the (i-1)-th light-emitting control signal EMi-1, respectively, so that the second node N2 can be initialized to the second driving voltage ELVSS during the initialization period Tint2.

[0192] During the initialization period Tint2, the first node N1 and the second node N2 are simultaneously initialized, so that the first capacitor C1 may be initialized with the difference between the reference voltage Vref and the second driving voltage ELVSS. The second capacitor C2 may be initialized with the difference between the second driving voltage ELVSS and the high-level voltage (e.g., 14V) of the i-th light-emitting control signal EMi. The initialization period Tint2 may be defined as a period in which the gate electrode and the second electrode (i.e., source) of the first transistor T1 are initialized, and as a period in which the cathode of the light-emitting element ED is initialized.

[0193] During the initialization period Tint2, the potential difference between the first and second nodes N1 and N2 (ie, the gate-source voltage Vgs of the first transistor T1) is smaller than the threshold voltage Vth of the first transistor T1, so the first transistor T1 may be turned off.

[0194] The initialization period Tint2 may end when the (i-1)th light emission control signal EMi-1 is deactivated.

[0195] When the initialization period Tint2 ends, the compensation period Tcom2 begins, i.e., the compensation period Tcom2 is executed after the initialization period Tint2.

[0196] During the compensation period Tcom2, the i-th compensation scan signal GCi and the i-th reference scan signal GRi may have an activated level (e.g., a high level), and the i-th write scan signal GWi, the (i-1)-th light emitting control signal EMi-1, and the i-th light emitting control signal EMi may have an inactivated level (e.g., a low level). The compensation period Tcom2 may begin when the i-th light emitting control signal EMi is inactivated.

[0197] During the compensation period Tcom2, the third transistor T3a may maintain a turn-on state in response to the i-th reference scan signal GRi, and the fourth transistor T4c may maintain a turn-on state in response to the i-th compensation scan signal GCi. Therefore, during the compensation period Tcom2, the reference voltage Vref may be applied to the first node N1, and the first driving voltage ELVDD may be applied to the fourth node N4b.

[0198] During the compensation period Tcom2, the first light-emitting control transistor ET1b may be turned off in response to the i-th light-emitting control signal EMi, and the second light-emitting control transistor ET2b may be turned off in response to the (i-1)th light-emitting control signal EMi-1. Therefore, at the start of the compensation period Tcom2, the potential Vs of the second node N2 may be changed from the second driving voltage ELVSS to "Vref-Vth." The i-th light-emitting control signal EMi is pulled down to a low level (e.g., -4V) during the compensation period Tcom2. When the i-th light-emitting control signal EMi is pulled down to a low level, the potential Vs of the second node N2 may become lower than "Vref-Vth" due to the second capacitor C2. If the potential Vs of the second node N2 decreases while the potential Vg of the first node N1 is maintained at the reference voltage Vref, the gate-source voltage Vgs may become higher than the threshold voltage Vth.

[0199] When the gate-source voltage Vgs becomes larger than the threshold voltage Vth, the first transistor T1 is switched to a turn-on state, and the threshold voltage Vth of the first transistor T1 can be compensated by the coupling of the first capacitor C1.

[0200] The compensation period Tcom2 may be ended when the i-th reference scan signal GRi is deactivated.

[0201] Figure 29 is a circuit diagram of a pixel according to an embodiment of the present invention, and Figure 30 is a waveform diagram showing signals applied to the pixel shown in Figure 29. However, among the components shown in Figure 29, the same components as those shown in Figure 19 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0202] 29, pixel PXij may include a pixel circuit PXC3 (or a pixel driving circuit) and a light emitting element ED electrically connected to pixel circuit PXC3. In this embodiment, pixel circuit PXC3 may include six transistors (referred to as first to fourth transistors T1, T2, T3a, T4c, and first and second light emitting control transistors ET1c, ET2c) and two capacitors (referred to as a first capacitor C1 and a second capacitor C2).

[0203] The first light-emitting control transistor ET1c is connected between the second light-emitting control transistor ET2c and the second power line PL2 and can receive the i-th light-emitting control signal EMi (or referred to as the first light-emitting control signal). The first light-emitting control transistor ET1c includes a first electrode connected to the second electrode of the second light-emitting control transistor ET2c, a second electrode connected to the second power line PL2, and a gate electrode connected to the i-th light-emitting control line EMLi. The first light-emitting control transistor ET1c is turned on by the i-th light-emitting control signal EMi received through the i-th light-emitting control line EMLi to electrically connect the second light-emitting control transistor ET2c to the second power line PL2. The gate electrode of the first light-emitting control transistor ET1c can be connected to the i-th light-emitting control line EMLi through a third node N3.

[0204] The second light-emitting control transistor ET2c is connected between the first transistor T1 and the first light-emitting control transistor ET1c and can receive the (i-1)th light-emitting control signal EMi-1 (or referred to as a second light-emitting control signal). The second light-emitting control transistor ET2c includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first light-emitting control transistor ET1c, and a gate electrode connected to the (i-1)th light-emitting control line EMLi-1. The second light-emitting control transistor ET2c is turned on by the (i-1)th light-emitting control signal EMi-1 received through the (i-1)th light-emitting control line EMLi-1 to electrically connect the first transistor T1 to the first electrode of the first light-emitting control transistor ET1c.

[0205] Referring to FIG. 30, each of the i-th write scan signal GWi, the i-th compensation scan signal GCi, the i-th reference scan signal GRi, the i-th light emitting control signal EMi, and the i-1-th light emitting control signal EMi-1 may have an activation level (or high level) during a partial period (i.e., an activation period) and an inactivation level (or low level) during the remaining partial period (i.e., an inactivation period).

[0206] The (i-1)th light-emitting control signal EMi-1 may be deactivated before the i-th light-emitting control signal EMi. Therefore, the start point of the inactivation period NAPc of the (i-1)th light-emitting control signal EMi-1 precedes the start point of the inactivation period NAPa of the i-th light-emitting control signal EMi. The inactivation period NAPa of the i-th light-emitting control signal EMi and the inactivation period NAPc of the (i-1)th light-emitting control signal EMi-1 may overlap with the activation period APa of the i-th write scan signal GWi, the activation period APb of the i-th compensation scan signal GCi, and the activation period APc of the i-th reference scan signal GRi.

[0207] 31 is a circuit diagram of a pixel according to an embodiment of the present invention, where the same components as those shown in FIG. 19 are denoted by the same reference numerals and will not be described in detail.

[0208] 31, pixel PXij may include a pixel circuit PXC4 (or pixel driving circuit) and a light emitting element ED electrically connected to pixel circuit PXC4. In this embodiment, pixel circuit PXC4 may include five transistors (first to fourth transistors T1, T2, T3a, and T4d, referred to as a first light emitting control transistor ET1) and two capacitors (hereinafter referred to as a first capacitor C1 and a second capacitor C2). In one embodiment of the present invention, any one of the five transistors of pixel circuit PXC4 may be omitted, or an additional transistor may be further included in pixel circuit PXC4.

[0209] The fourth transistor T4d is connected between the initialization voltage V line VL2 and the fourth node N4b and receives the i-th compensation scan signal GCi. The fourth transistor T4d includes a first electrode connected to the initialization voltage V line VL2, a second electrode connected to the first electrode of the first transistor T1 (i.e., the fourth node N4b), and a gate electrode connected to the i-th compensation scan line GCLi. The fourth transistor T4d is turned on in response to the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi to transmit the initialization voltage Vint applied to the initialization voltage V line VL2 to the fourth node N4b. In one example, the initialization voltage Vint may have different voltage levels depending on the color of the pixel PXij. That is, initialization voltages having different voltage levels may be applied to red, green, and blue pixels, respectively.

[0210] 17 to 31, by reducing the number of scan signals and emission control signals applied to the pixel PX to three and one, respectively, the number of scan driving circuits GWD, GCD, GRD and emission control circuits EMD included in the first and second gate driving circuits 300, 350a can be reduced, thereby simplifying the circuit configuration provided in the non-display area NDA of the display panel DPa and reducing the width of the non-display area NDA.

[0211] FIG. 32 is a cross-sectional view of a display panel DP according to an embodiment of the present invention.

[0212] Referring to FIG. 32, the display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, an upper insulating layer UIL, connecting wiring CN, a display element layer DP-ED, and an encapsulation layer ESL.

[0213] 32 illustrates one transistor TR and two capacitors C1 and C2 in the pixel circuit PXCa. The transistor TR corresponds to a transistor connected to the light emitting element ED through a connecting line CN, i.e., a transistor connected to a node corresponding to the cathode CE of the light emitting element ED (e.g., the fourth node N4 in FIG. 3). Specifically, the transistor TR may correspond to the second light emitting control transistor ET2 in FIG. 3 or the first transistor T1 in FIG. 19. Meanwhile, although not shown, other transistors constituting the pixel circuit PXCa may have the same structure as the transistor TR (hereinafter, referred to as a connecting transistor) illustrated in FIG. 32. However, this is merely an example, and the other transistors constituting the pixel circuit PXCa may have a different structure from the connecting transistor TR, and are not limited to any one embodiment.

[0214] The lower conductive layer BML may be disposed to overlap the connection transistor TR and may be covered by a first insulating layer 10. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the lower conductive layer BML and the base layer BL.

[0215] In this embodiment, the lower conductive layer BML may be connected to the source of the connection transistor TR through a source electrode pattern W1. In this case, the lower conductive layer BML may be synchronized with the source of the connection transistor TR. However, this is merely an example, and the lower conductive layer BML may be connected to the gate of the connection transistor TR and synchronized with the gate. Alternatively, the lower conductive layer BML may be connected to another electrode and independently receive a constant voltage or a pulse signal. Alternatively, the lower conductive layer BML may be provided in an isolated form from other conductive patterns. The lower conductive layer BML according to an embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0216] A connection transistor TR may be disposed on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CHR, which are divided according to the degree of conductivity.

[0217] The display panel according to this embodiment may further include a source electrode pattern W1 and a drain electrode pattern W2 connected to the source region SR and the drain region DR, respectively. Specifically, the source electrode pattern W1 and the drain electrode pattern W2 may each be integrally formed with one of the lines constituting the pixel driver, and are not limited to any one embodiment.

[0218] The second insulating layer 20 may overlap a plurality of pixels in common and cover the semiconductor pattern SP. The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the connection transistor TR.

[0219] A third insulating layer 30 may be disposed on the gate electrode GE, and a fourth insulating layer may be disposed on the third insulating layer 30. The plurality of conductive patterns may include a first capacitor electrode CPE1, a second capacitor electrode CPE2, and a third capacitor electrode CPE3.

[0220] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart by a first insulating layer 10 and a second insulating layer 20 interposed therebetween.

[0221] In an embodiment of the present invention, the first capacitor electrode CPE1 and the lower conductive layer BML may have an integral shape, and the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0222] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2 via the third insulating layer 30 and may overlap on a plane. The third capacitor electrode CPE3 may form a second capacitor C2 together with the second capacitor electrode CPE2.

[0223] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. A source electrode pattern W1 and a drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to a source region SR of the connection transistor TR through a first contact hole CNT1, and the source region SR of the source electrode pattern W1 and the semiconductor pattern SP may function as the source of the connection transistor TR. The drain electrode pattern W2 may be connected to a drain region DR of the connection transistor TR through a second contact hole CNT2, and the drain region DR of the drain electrode pattern W2 and the semiconductor pattern SP may function as the drain of the connection transistor TR. A fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0224] A connecting wire CN may be disposed on the fifth insulating layer 50. The connecting wire CN may electrically connect the pixel circuit PXCa and the light emitting element ED. That is, the connecting wire CN may electrically connect the connection transistor TR and the light emitting element. The connecting wire CN may be a connection node connecting the pixel circuit PXCa and the light emitting element ED. That is, the connecting wire CN may correspond to the fourth node N4 shown in FIG. 3 or the fourth node N4b shown in FIG. 19. However, this is merely an example, and as long as the connecting wire CN can be connected to the light emitting element ED, it may be defined as a connection node with various elements constituting the pixel circuit PXCa depending on the design of the pixel circuit PXCa, and is not limited to any one embodiment.

[0225] An upper insulating layer UIL may be disposed on the interconnection wiring CN. The upper insulating layer UIL may be disposed on the fifth insulating layer 50 to cover the interconnection wiring CN. The upper insulating layer UIL may be an organic layer. For example, the upper insulating layer UIL may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), and PS (Polystyrene), polymer derivatives having a phenol-based group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof.

[0226] The upper insulating layer UIL may have an opening exposing at least a portion of the connecting wire CN. The connecting wire CN may be electrically connected to the light emitting element ED through the portion exposed from the upper insulating layer UIL. That is, the connecting wire CN may electrically connect the connection transistor TR and the light emitting element ED. This will be described in detail later. Meanwhile, in the display panel DP according to an embodiment of the present invention, the upper insulating layer UIL may be omitted or may be provided in a plurality, and is not limited to any one embodiment.

[0227] A display element layer DP-ED may be disposed on the upper insulating layer UIL. The display element layer DP-ED may include a pixel defining layer PDL, a light emitting element ED, and a separator SPR. The light emitting element ED may include an anode AE, an intermediate layer IML, and a cathode CE.

[0228] In this embodiment, the anode AE ​​may be disposed on the upper insulating layer UIL. The anode AE ​​may be a semi-transparent, transparent, or reflective electrode. According to one embodiment of the present invention, the anode AE ​​may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the anode AE ​​may include an ITO / Ag / ITO stacked structure. The anode AE ​​may be connected to the first power supply line PL1 (see FIG. 3) and may receive the first driving voltage ELVDD (see FIG. 3).

[0229] The pixel defining layer PDL may define an emission opening OP-PDL exposing at least a portion of the anode AE. A plurality of emission openings OP-PDL may be provided and disposed corresponding to each light emitting element. All components of the light emitting element ED may be disposed overlapping each other in the emission opening OP-PDL, and the emission opening OP-PDL may be an area where light emitted by the light emitting element ED is substantially displayed.

[0230] The intermediate layer IML may be disposed between the anode AE ​​and the cathode CE. The intermediate layer IML may include an emitting layer EML and a functional layer FNL. The light-emitting device ED may include an intermediate layer IML of various structures and is not limited to any one embodiment. For example, the functional layer FNL may be provided as a plurality of layers, or as two or more layers separated by an emitting layer EML. Alternatively, in one embodiment, the functional layer FNL may be omitted. Although FIG. 32 illustrates an embodiment in which the emitting layer EML and the functional layer FNL have different shapes, this is not limiting, and the emitting layer EML and the functional layer FNL may be arranged in the same shape on a plane.

[0231] The functional layer FNL may be disposed between the anode AE ​​and the cathode CE. Specifically, the functional layer FNL may be disposed between the anode AE ​​and the emitting layer EML, or between the cathode CE and the emitting layer EML. Alternatively, the functional layer FNL may be disposed both between the anode AE ​​and the emitting layer EML and between the cathode CE and the emitting layer EML. In this embodiment, the emitting layer EML is illustrated as being inserted within the functional layer FNL. However, this is merely an example, and the functional layer FNL may include a layer disposed between the emitting layer EML and the anode AE ​​and / or a layer disposed between the emitting layer EML and the cathode CE. A plurality of each of these may be provided, and the present invention is not limited to any one embodiment. The functional layer FNL may include a hole control layer and an electron control layer, and at least a portion of the hole control layer may be disposed between the anode AE ​​and the emitting layer EML, and at least a portion of the electron control layer may be disposed between the emitting layer EML and the cathode CE.

[0232] The cathode CE may be disposed on the intermediate layer IML. As described above, the cathode CE may be connected to the connecting line CN to be electrically connected to the pixel circuit PXCa. That is, the cathode CE may be electrically connected to the connecting transistor TR through the connecting line CN.

[0233] As described above, the connecting wire CN may include a driving connection part CDP and an emission connection part CEP. The driving connection part CDP is a part of the connecting wire CN that is connected to the pixel circuit PXCa and may be substantially connected to the connecting transistor TR. In this embodiment, the driving connection part CDP may penetrate the fifth insulating layer 50 and be electrically connected to the drain region DR of the semiconductor pattern SP through the drain electrode pattern W2. The emission connection part CEP may be a part of the connecting wire CN that is connected to the light emitting element ED. The emission connection part CEP is defined in a region exposed from the upper insulating layer UIL and may be a portion to which the cathode CE is connected. In this case, a tip part TP may be defined in the emission connection part CEP.

[0234] The light-emitting connection part CEP of the connecting wire CN will be described in more detail with reference to FIGS. 32 and 33A. As shown in FIGS. 32 and 33A, the connecting wire CN may have a three-layer structure. Specifically, the connecting wire CN may include a first layer L1, a second layer L2, and a third layer L3 that are sequentially stacked along the third direction DR3. The second layer L2 may include a different material from the first layer L1. Also, the second layer L2 may include a different material from the third layer L3. The second layer L2 may have a relatively thicker thickness than the first layer L1. Also, the second layer L2 may have a relatively thicker thickness than the third layer L3. The second layer L2 may include a highly conductive material. In one embodiment, the second layer L2 may include aluminum (Al).

[0235] Meanwhile, the first layer L1 may include a material having a lower etching rate than the second layer L2. That is, the second layer L2 may be composed of a material having a higher etching selectivity relative to the first layer L1. In one embodiment, the first layer L1 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In this case, the side surface L1_W of the first layer L1 may be defined outward from the side surface L2_W of the second layer L2. That is, the light emitting connection portion CEP of the connecting wiring CN may have a shape in which the side surface L1_W of the first layer L1 protrudes outward from the side surface L2_W of the second layer L2. That is, the light emitting connection portion CEP of the connecting wiring CN may have a shape in which the side surface L2_W of the second layer L2 is recessed inward from the side surface L1_W of the first layer L1.

[0236] In addition, the third layer L3 may include a material having a lower etching rate than the second layer L2. That is, the third layer L3 and the second layer L2 may be made of materials having a high etching selectivity relative to each other. In one embodiment, the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In this case, the side surface L3_W of the third layer L3 may be defined outward from the side surface L2_W of the second layer L2. That is, the light emitting connection portion CEP of the connecting wire CN may have a shape in which the side surface L3_W of the third layer L3 protrudes outward from the side surface L2_W of the second layer L2. That is, the light emitting connection portion CEP of the connecting wire CN may have an undercut shape or an overhang structure, and the tip portion TP of the light emitting connection portion CEP may be defined by a portion of the third layer L3 that protrudes from the second layer L2.

[0237] The upper insulating layer UIL and the pixel defining layer PDL may expose at least a portion of the tip portion TP and at least a portion of the side surface L2_W of the second layer L2. Specifically, a first opening OP1 exposing one side of the connecting line CN may be defined in the upper insulating layer UIL, and a second opening OP2 overlapping the first opening OP1 may be defined in the pixel defining layer PDL. The planar area of ​​the second opening OP2 may be larger than the planar area of ​​the first opening OP1. However, the present invention is not limited thereto. As long as at least a portion of the tip portion TP and at least a portion of the side surface L2_W of the second layer L2 can be exposed, the planar area of ​​the second opening OP2 may be smaller than or equal to the planar area of ​​the first opening OP1.

[0238] An intermediate layer IML may be disposed on the pixel defining layer PDL. The intermediate layer IML may also be disposed on a portion of the upper insulating layer UIL exposed by the second opening OP2 of the pixel defining layer PDL. The intermediate layer IML may also be disposed on a portion of the connecting wire CN exposed by the first opening OP1 of the upper insulating layer UIL. As shown in FIG. 33A, the intermediate layer IML may include one end IN1 disposed along the upper surface of the fifth insulating layer 50 and the other end IN2 disposed along the upper surfaces of the connecting wire CN and the chip portion TP. That is, in cross section, the intermediate layer IML may have a shape that is partially disconnected from the chip portion TP in the region where the light emitting connection part CEP is defined. However, in plan view, the intermediate layer IML may have an integral shape that is entirely connected within the region defined by the closed line by the separator SPR (see FIG. 35A).

[0239] A cathode CE may be disposed on the intermediate layer IML. The cathode CE may also be disposed on a portion of the upper insulating layer UIL exposed by the second opening OP2 of the pixel defining layer PDL. The cathode CE may also be disposed on a portion of the connecting line CN exposed by the first opening OP1 of the upper insulating layer UIL. As shown in FIG. 33A, the cathode CE may include one end EN1 of the cathode CE disposed along the upper surface of the fifth insulating layer 50 and the other end EN2 disposed along the upper surfaces of the connecting line CN and the tip portion TP. That is, when viewed in cross section, the cathode CE may have a shape that is partially disconnected from the tip portion TP in the region where the light emitting connection portion CEP is defined. However, when viewed in plan, the cathode CE may have a single shape that is entirely connected within the region defined by a closed curve by the separator SPR (see FIG. 35A).

[0240] Meanwhile, one end EN1 of the cathode CE may be disposed along the side surface of the second layer L2 and may be in contact with the side surface L2_W of the second layer L2. Specifically, due to the difference in deposition angles between the cathode CE and the intermediate layer IML, the cathode CE may be formed to be in contact with the side surface L2_W of the second layer L2 exposed from the intermediate layer IML by the tip portion TP. That is, the cathode CE may be connected to the connecting line CN without a separate patterning process for the intermediate layer IML, and therefore the light emitting element ED may be electrically connected to the pixel circuit PXCa through the connecting line CN.

[0241] Furthermore, in this embodiment, the other end IN2 of the intermediate layer IML and the other end EN2 of the cathode CE are illustrated as covering the side L3_W of the third layer L3, but this is shown as an example, and at least a portion of the side L3_W of the third layer L3 may be exposed from the other end IN2 of the intermediate layer IML and / or the other end EN2 of the cathode CE.

[0242] The display panel DP according to this embodiment may include a separator SPR. The separator SPR may be disposed on the pixel defining layer PDL. In one embodiment, the cathode CE and the intermediate layer IML may be formed by common deposition on a plurality of pixels through an open mask. At this time, the cathode CE and the intermediate layer IML may be divided by the separator SPR. As described above, the separator SPR may have a closed line shape for each light emitting portion, and therefore the cathode CE and the intermediate layer IML may have a divided shape for each light emitting portion. That is, the cathode CE and the intermediate layer IML may be electrically independent for each adjacent pixel.

[0243] The separator SPR will be described in more detail with reference to Figures 32 and 33B. As shown in Figure 33B, the separator SPR may have a tapered shape. That is, the angle θ (hereinafter referred to as the taper angle) formed by the side surface SPR_W of the separator SPR with respect to the upper surface of the pixel defining layer PDL may be an obtuse angle. However, this is merely an example, and the taper angle θ may be set in various ways as long as the separator SPR can electrically disconnect the cathode CE for each pixel. Furthermore, the separator SPR may have a structure similar to that of the tip portion TP, and is not limited to any one embodiment.

[0244] In one embodiment, the separator SPR may include an insulating material, particularly an organic insulating material. The separator SPR may include an inorganic insulating material, or may be formed of a multilayer of organic and inorganic insulating materials. Depending on the embodiment, the separator SPR may include a conductive material. That is, as long as the separator SPR can electrically disconnect the cathode CE for each pixel, there is no particular limitation on the type of material.

[0245] A dummy layer UP may be disposed on the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the intermediate layer IML and may include the same material as the intermediate layer UP1. The second dummy layer UP2 may be formed in the same process as the cathode CE and may include the same material as the intermediate layer UP1. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the intermediate layer IML and the cathode CE. In another embodiment, the display panel DP may not include the dummy layer UP.

[0246] As shown in Figure 33B, in one embodiment, the cathode CE may include a first end EN1a, and the second dummy layer UP2 may include a second end EN2a. The first end EN1a may be spaced apart from the separator SPR and positioned on the pixel defining layer PDL, and the second end EN2a may be spaced apart from the first end EN1a and positioned on the side surface SPR_W of the separator SPR. Although Figure 33B illustrates the first end EN1a as being spaced apart from the side surface SPR_W of the separator SPR by a predetermined distance, the present invention is not limited thereto. If the first end EN1a is electrically disconnected from the second end EN2a, the first end EN1a may also contact the side surface SPR_W of the separator SPR. Furthermore, even if the first end EN1a and the second end EN2a are connected without being distinguished from each other, the thickness of the portion formed along the side surface SPR_W of the separator SPR is thin, so if the electrical resistance is high and the cathode CE is electrically disconnected between adjacent pixels, the cathode CE is considered to be divided by the separator SPR.

[0247] According to the present invention, the cathode CE and the intermediate layer IML can be separated for each pixel by forming the cathode CE and the intermediate layer IML thinly or not formed on the side surface SPR_W of the separator SPR without a separate patterning process for the cathode CE and the intermediate layer IML. Also, as long as the cathode CE and the intermediate layer IML can be electrically disconnected between adjacent pixels, the shape of the separator SPR can be variously modified and is not limited to any one embodiment.

[0248] Figure 34 is a cross-sectional view of a display panel according to an embodiment of the present invention. For ease of explanation, Figure 34 shows a cross-sectional view of an area corresponding to Figure 32. Hereinafter, the same components as those described in Figure 32 will be assigned the same reference numerals, and duplicated explanations will be omitted.

[0249] The display panel DP-1 shown in Fig. 34 may further include a capping pattern CPP compared to the display panel DP shown in Fig. 32. The capping pattern CPP may be disposed on the upper insulating layer UIL. The capping pattern CPP may also be disposed on a portion of the connecting wire CN exposed by the first opening OP1 in the upper insulating layer UIL. The capping pattern CPP may be disposed to overlap the connecting wire CN, specifically, the light emitting connection part CEP and / or the tip part TP.

[0250] 34, the capping pattern CPP may have a shape that is partially disconnected from the tip portion TP in the region where the light emitting connection portion CEP is defined. However, when viewed in plan, the capping pattern CPP may have a shape that is entirely connected within the region defined by the closed line by the separator SPR (see FIG. 35A). Meanwhile, one end of the partially disconnected capping pattern CPP may contact a side of the second connecting wire layer L2, and the other end of the capping pattern CPP may be disposed on top of the third connecting wire layer L3 to cover the tip portion TP.

[0251] The capping pattern CPP may include a conductive material. Therefore, the cathode CE may be electrically connected to the connecting wire CN through the capping pattern CPP. That is, the capping pattern CPP may contact the side of the connecting wire second layer L2, and then the cathode CE may contact the capping pattern CPP, thereby electrically connecting them all. The capping pattern CPP is disposed relatively outward from the connecting wire second layer L2, and the cathode CE may be electrically connected to the second layer L2 simply by being connected to the capping pattern CPP instead of the side of the second layer L2, thereby more easily connecting the connecting wire CN and the cathode CE.

[0252] In addition, the capping pattern CPP may include a material having a relatively low reactivity compared to the second connecting wiring layer L2. For example, the capping pattern CPP may include copper (Cu), silver (Ag), transparent conductive oxide, etc. The relatively low reactivity capping pattern CPP protects the sides of the second connecting wiring layer L2, thereby preventing oxidation of the material included in the second layer L2. In addition, it may prevent the silver (Ag) component included in the anode AE ​​layer from being reduced during the etching process for patterning the anode AE ​​and remaining as particles that cause defects.

[0253] In one embodiment, the capping pattern CPP may be formed through the same process as the anode AE ​​and may include the same material as the anode AE, but this is merely an example, and the capping pattern CPP may be formed through a different process than the anode AE ​​or may include other materials, and is not limited to any one embodiment.

[0254] Figures 35A to 35C are enlarged plan views of a portion of a display panel according to an embodiment. Figures 35A to 35C may correspond to enlarged plan views of the display panels DP and DP-1 according to the embodiments described above in Figures 32 to 34. Figure 35A illustrates an area in which a total of four light emitting units are arranged in two rows and two columns, and Figure 35B illustrates an enlarged view of a portion of Figure 35A. Figure 35C illustrates some components of Figure 35A in an exaggerated manner or omitted. The present invention will now be described with reference to Figures 35A to 35C.

[0255] Figure 35A shows two rows and two columns of light emitting units UT11, UT12, UT21, and UT22. The first row Rk light emitting unit includes light emitting units constituting the first row, first column light emitting unit UT11 and the first row, second column light emitting unit UT12, and the second row Rk+1 light emitting unit includes light emitting units constituting the second row, first column light emitting unit UT21 and the second row, second column light emitting unit UT22. Figure 35B shows the first row Rk light emitting unit. Figures 35A to 35C show separators SPR, a plurality of light emitting units EP1, EP2, and EP3 arranged in areas partitioned by the separators SPR, connecting wires CN1, CN2, and CN3, anodes AE, and cathodes CE in the display panel configuration.

[0256] As described above, each of the light-emitting portions EP1, EP2, and EP3 may correspond to the light-emitting opening OP-PDL (see FIG. 32). That is, each of the light-emitting portions EP1, EP2, and EP3 is an area where light is emitted by a light-emitting element, and may correspond to a unit that forms an image displayed on the display panel DP (see FIG. 32). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by the light-emitting opening OP-PDL (see FIG. 32), particularly an area defined by the bottom surface of the light-emitting opening OP-PDL.

[0257] The light-emitting units EP1, EP2, and EP3 may include a first light-emitting unit EP1, a second light-emitting unit EP2, and a third light-emitting unit EP3. The first light-emitting unit EP1, the second light-emitting unit EP2, and the third light-emitting unit EP3 may emit a first color light, a second color light, and a third color light, respectively, and the first, second, and third color lights may be lights of different colors. For example, the first light-emitting unit EP1 may emit red light, the second light-emitting unit EP2 may emit green light, and the third light-emitting unit EP3 may emit blue light, but the color combinations are not limited thereto. Furthermore, at least two of the light-emitting units EP1, EP2, and EP3 may emit light of the same color. For example, the first, second, and third light-emitting units EP1, EP2, and EP3 may all emit blue light or all emit white light.

[0258] Meanwhile, among the light emitting units EP1, EP2, and EP3, the third light emitting unit EP3 emitting a third color light may include two sub-light emitting units EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is merely an example, and the third light emitting unit EP3 may be provided in a single pattern having an integral shape like the other light emitting units EP1 and EP2, or at least one of the other light emitting units EP1 and EP2 may include a spaced-apart sub-light emitting unit, and is not limited to any one embodiment.

[0259] The first row Rk light-emitting unit includes light-emitting units EP1, EP2, and EP3 constituting the first row / first column light-emitting unit UT11 and the first row / second column light-emitting unit UT12, and the second row Rk+1 light-emitting unit includes light-emitting units EP1, EP2, and EP3 constituting the second row / first column light-emitting unit UT21 and the second row / second column light-emitting unit UT22. A portion of the first row Rk light-emitting unit and a portion of the second row Rk+1 light-emitting unit may have a symmetrical shape. For example, the first light-emitting unit EP1 and the second light-emitting unit EP2 of the second row / first column light-emitting unit UT21 and the first light-emitting unit EP1 and the second light-emitting unit EP2 of the first row / first column light-emitting unit UT11 may have a line-symmetrical shape and arrangement with respect to an axis aligned with the first direction DR1, and the third light-emitting unit EP3 of the second row / first column light-emitting unit UT21 and the third light-emitting unit EP3 of the first row / first column light-emitting unit UT11 may have a line-symmetrical shape and arrangement with respect to the axis aligned with the first direction DR1. However, this is merely an example and is not limiting.

[0260] The light emitting unit UT11 in the first row and first column will now be described. For ease of explanation, FIG. 35B illustrates a plurality of cathodes CE_1, CE_2, and CE_3, a plurality of pixel driving units PXCR, PXCG, and PXCB, and a plurality of connecting wires CN1, CN2, and CN3. The cathodes CE_1, CE_2, and CE_3 may be electrically disconnected by separators SPR. In this embodiment, one light emitting unit UT may include three light emitting parts EP1, EP2, and EP3. Therefore, the light emitting unit UT may include three cathodes CE_1, CE_2, and CE_3 (hereinafter referred to as first to third cathodes), three pixel driving units PXCR, PXCG, and PXCB, and three connecting wires CN1, CN2, and CN3. However, this is merely an example, and the number and arrangement of the light emitting units UT may be variously designed and are not limited to any one embodiment.

[0261] The first to third pixel driving units PXCR, PXCG, and PXCB are electrically connected to the light emitting elements constituting the first to third light emitting units EP1, EP2, and EP3, respectively. In this specification, "connected" refers to not only being connected by direct physical contact but also being electrically connected.

[0262] Furthermore, as shown in FIG. 35B, each area where the pixel driving units PXCR, PXCG, and PXCB are defined on a plane can correspond to a unit in which transistors and capacitor elements constituting a pixel circuit PXCa (see FIG. 3) for driving a light emitting element of a pixel are repeatedly arranged.

[0263] The first to third pixel driving units PXCR, PXCG, and PXCB may be sequentially arranged along the first direction DR1, and the arrangement positions of the first to third pixel driving units PXCR, PXCG, and PXCB may be designed independently regardless of the positions and shapes of the first to third light emitting units EP1, EP2, and EP3.

[0264] For example, the first to third pixel driving units PXCR, PXCG, and PXCB may be arranged in regions defined by the separators SPR, i.e., at positions different from where the first to third cathodes CE_1, CE_2, and CE_3 are arranged, or may be designed to have shapes and areas different from those of the first to third cathodes CE_1, CE_2, and CE_3. Alternatively, the first to third pixel driving units PXCR, PXCG, and PXCB may be arranged to overlap positions where the first to third light emitting units EP1, EP2, and EP3 are present, respectively, and may be designed to have shapes having areas similar to those of the regions defined by the separators SPR, e.g., the first to third cathodes CE_1, CE_2, and CE_3.

[0265] In this embodiment, the first to third pixel driving units PXCR, PXCG, and PXCB are each illustrated as a rectangle, the first to third light emitting units EP1, EP2, and EP3 are each arranged in a different shape with a smaller area than the rectangle, and the first to third cathodes CE_1, CE_2, and CE_3 are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3, and are illustrated as irregular shapes.

[0266] 35B, the first pixel driver PXCR may be disposed at a position where it partially overlaps with the first light emitter EP1, the second light emitter EP2, and other adjacent light emitters. The second pixel driver PXCG may be disposed at a position where it overlaps with the first light emitter EP1, the second light emitter EP2, and the third light emitter EP3. The third pixel driver PXCB may be disposed at a position where it overlaps with the third light emitter EP3. However, this is merely an example, and the positions and arrangements of the first to third pixel drivers PXCR, PXCG, and PXCB may be designed in various shapes and arrangements independent of the light emitters EP1, EP2, and EP3, and are not limited to any one embodiment.

[0267] A plurality of connection wires CN may be provided and arranged spaced apart from each other. One connection wire CN may electrically connect one of the pixel drivers PXCR, PXCG, and PXCB to a corresponding light emitting element. Specifically, the connection wire CN may correspond to a node (see the fourth node N4 in FIG. 3) where the light emitting element ED (see FIG. 32) is connected to the pixel circuit PXCa (see FIG. 3).

[0268] The connecting wire CN may include a first connecting portion (or a light emitting connecting portion CEP) and a second connecting portion (or a driving connecting portion CDP). The light emitting connecting portion CEP may be provided on one side of the connecting wire CN, and the driving connecting portion CDP may be provided on the other side of the connecting wire CN.

[0269] The driving connection part CDP may be a part of the connecting line CN that is connected to the pixel circuit PXCa. In this embodiment, the driving connection part CDP may be connected to one electrode of a transistor that constitutes the pixel circuit PXCa. Specifically, the driving connection part CDP may be connected to the first electrode of the second light-emitting control transistor ET2 shown in FIG. 3. Therefore, the position of the driving connection part CDP may correspond to the position of a transistor (see the connecting transistor TR in FIG. 32) that is physically connected to the connecting line CN in the pixel circuit PXCa. The light-emitting connection part CEP may be a part of the connecting line CN that is connected to the light-emitting element. In this embodiment, the light-emitting connection part CEP may be connected to the cathode CE (see FIG. 32) of the light-emitting element.

[0270] The light emitting unit UT may include first to third connecting wires CN1, CN2, and CN3. The first connecting wire CN1 may connect the light emitting element forming the first light emitting portion EP1 to the first pixel driving circuit PXCR, the second connecting wire CN2 may connect the light emitting element forming the second light emitting portion EP2 to the second pixel driving circuit PXCG, and the third connecting wire CN3 may connect the light emitting element forming the third light emitting portion EP3 to the third pixel driving circuit PXCB.

[0271] Specifically, the first to third connecting wires CN1, CN2, and CN3 connect the first to third cathodes CE_1, CE_2, and CE_3 to the first to third pixel driving units PXCR, PXCG, and PXCB, respectively. The first connecting wire CN1 may include a first driving connection part CDP1 connected to the first pixel driving unit PXCR and a first light-emitting connection part CEP1 connected to the first cathode CE_1. The second connecting wire CN2 may include a second driving connection part CDP2 connected to the second pixel driving unit PXCG and a second light-emitting connection part CEP2 connected to the second cathode CE_2. The third connecting wire CN3 may include a third driving connection part CDP3 connected to the third pixel driving unit PXCB and a third light-emitting connection part CEP3 connected to the third cathode CE_3.

[0272] The first to third driving connection parts CDP1, CDP2, and CDP3 may be aligned along the first direction DR1. As described above, the first to third driving connection parts CDP1, CDP2, and CDP3 may correspond to the positions of the connecting transistors constituting the first to third pixel driving parts PXCR, PXCG, and PXCB, respectively. The connecting transistor TR is a transistor having, in one electrode, a connection node connecting the pixel circuit PXCa and the light emitting element ED in one pixel, and may correspond to, for example, the second emission control transistor ET2 in FIG. 3. According to the present invention, the shape, position, and arrangement of the pixel driving parts of all pixels can be easily configured and designed, regardless of the shape, size, or emission color of the light emitting part.

[0273] In this embodiment, the first to third light emitting connectors CEP1, CEP2, and CEP3 may be disposed at positions that do not overlap with the light emitting portions EP1, EP2, and EP3 in a plan view. As will be described later, each of the light emitting connectors CEP1, CEP2, and CEP3 of the connecting wiring CN is a portion to which the light emitting element ED (see FIG. 32) is connected and a portion that defines the chip portion TP (see FIG. 32), and therefore may be disposed at a position that does not overlap with the light emitting opening OP-PDL (see FIG. 32). That is, the light emitting connectors CEP1, CEP2, and CEP3 may be disposed at positions spaced apart from the light emitting portions EP1, EP2, and EP3 in each of the cathodes CE_1, CE_2, and CE_3, and the cathodes CE_1, CE_2, and CE_3 may include partial regions that protrude from the light emitting portions EP1, EP2, and EP3 in a plan view to connect to the connecting wirings CN1, CN2, and CN3 at the positions where the light emitting connectors CEP1, CEP2, and CEP3 are disposed.

[0274] For example, the first cathode CE_1 may include a protrusion shaped to protrude from the first light emitting portion EP1 at a position not overlapping with the first light emitting portion EP1 to connect to the first connecting wiring CN1 at the position where the first light emitting connection portion CEP1 is disposed, and the first light emitting connection portion CEP1 may be provided on the protrusion.

[0275] In addition, the first pixel driver PXCR, particularly the first driver connection part CDP1 at which the first connecting line CN1 connects to the connection transistor TR (see FIG. 32), may be defined at a position not overlapping the first light emitting part EP1 in a plan view. According to this embodiment, the first connecting line CN1 is disposed in the first light emitting part EP1, so that the first cathode CE_1 and the first pixel driver PXCR, which are spaced apart from each other, can be easily connected.

[0276] Meanwhile, the third pixel driving unit PXCB, particularly the third driving connection part CDP3 at which the third connecting line CN3 connects to the connecting transistor TR, is defined at a position not overlapping the third light emitting connection part CEP3 in a plan view, and may be disposed at a position overlapping the third light emitting part EP3. According to this embodiment, since the third cathode CE_3 and the third pixel driving unit PXCB are connected through the third connecting line CN3, restrictions depending on the position and shape of the third light emitting part EP3 are reduced in designing the third pixel driving unit PXCB, and the degree of freedom in designing can be improved.

[0277] 35A again, the second row Rk+1 light-emitting part may be configured with the first row light-emitting units UT11 and UT12 having a shape and arrangement that are symmetrical with respect to an axis aligned with the first direction DR1 or the second direction DR2. Here, depending on the shape and arrangement of the first row light-emitting units UT11 and UT12, the second row light-emitting units UT21 and UT22 may be configured with light-emitting parts that are substantially shifted in the first direction DR1 from the first row Rk light-emitting units UT11 and UT12. That is, the second row Rk+1 first column light-emitting unit UT21 may be configured with a light-emitting part having the same shape as the first row Rk second column light-emitting unit UT12, and the second row second column light-emitting unit UT22 may be configured with a light-emitting part having the same shape as the first row Rk first column light-emitting unit UT11.

[0278] Therefore, the shape and arrangement of the connecting wires CN-c arranged in the second row, first column light emitting unit UT21 may be the same as the connecting wires CN1, CN2, and CN3 arranged in the first row, second column light emitting unit UT12. Similarly, the shape and arrangement of the connecting wires CN-d arranged in the second row, second column light emitting unit UT22 may be the same as the connecting wires CN1, CN2, and CN3 arranged in the first row, first column light emitting unit UT11.

[0279] 35C, the anode AE ​​of a light emitting device according to an embodiment of the present invention may be provided in common to the plurality of light emitting portions EP1, EP2, and EP3. That is, the anode AE ​​may be formed as a single layer integral with the entire display area DA, and therefore the anode AE ​​layer may be disposed overlapping the separator SPR. Alternatively, the anodes AE of the light emitting devices may be formed as independent conductive patterns spaced apart from each other and electrically connected to each other through other conductive layers, and therefore the anode AE ​​patterns may be disposed overlapping the separator SPR.

[0280] As described above, the first driving voltage ELVDD (see FIG. 3) is applied to the anode AE, and a common voltage can be provided to all the light emitting portions. The anode AE ​​can be connected to the first power supply line PL1 (see FIG. 3) that provides the first driving voltage ELVDD (see FIG. 3) in the non-display area NDA, or can be connected to the first power supply line PL1 (see FIG. 3) in the display area DA, and is not limited to either of these embodiments. In the latter case, the first power supply line PL1 (see FIG. 3) can be disposed in the non-display area NDA (see FIG. 1), and the anode AE ​​can have a shape that extends to the non-display area NDA (see FIG. 1).

[0281] 32 and 34, the anode AE ​​is illustrated as overlapping the light emitting opening OP-PDL and not overlapping the separator SPR, but as shown in Fig. 35C, the anode AE ​​of the light emitting device may have a one-piece shape and a mesh or lattice shape with openings defined in some regions. That is, as long as the same first driving voltage ELVDD (see Fig. 3) can be applied to each anode AE ​​of the plurality of light emitting devices, the shape of the anode AE ​​may be various and is not limited to any one embodiment.

[0282] Meanwhile, according to this embodiment, the anode AE ​​may be defined with a plurality of openings OP-AE, and the openings OP-AE may penetrate the anode AE ​​layer. The openings OP-AE in the anode AE ​​layer may be disposed at positions not overlapping the light emitting portion EP, and may be defined at positions overlapping the separator SPR. The openings facilitate the discharge of gas generated from organic layers disposed below the anode AE, such as an upper insulating layer UIL (see FIG. 32 ), described below. Therefore, gas generated from organic layers disposed below the light emitting device ED during the manufacturing process of the display panel DP can be sufficiently discharged, and the rate at which the light emitting device ED deteriorates can be reduced by reducing the amount of gas discharged from the organic layers after manufacturing.

[0283] According to this embodiment, by including a connecting wire between the light emitting element ED and the pixel driver, the light emitting element ED can be easily connected to the pixel driver by changing only the shape of the cathode CE without changing the arrangement or shape of the light emitting portion, which improves the design freedom for the arrangement of the pixel driver and easily increases the area of ​​the light emitting portion or the resolution of the display panel DP.

[0284] FIG. 36 is a block diagram of an electronic device according to one embodiment of the present invention.

[0285] 36, the electronic device 601 outputs various information within the operating system through a display module 640. When the processor 610 executes an application stored in the memory 620, the display module 640 provides application information to the user through a display panel 641.

[0286] The processor 610 acquires an external input through the input module 630 or the sensor module 661 and executes an application corresponding to the external input. For example, if a user selects a camera icon displayed on the display panel 641, the processor 610 acquires the user input through the input sensor 661-2 and activates the camera module 671. The processor 610 transmits image data corresponding to the captured image acquired through the camera module 671 to the display module 640. The display module 640 can display an image corresponding to the captured image on the display panel 641.

[0287] As another example, when personal information authentication is performed by the display module 640, the fingerprint sensor 661-1 acquires input fingerprint information as input data. The processor 610 compares the input data acquired through the fingerprint sensor 661-1 with authentication data stored in the memory 620 and executes an application according to the comparison result. The display module 640 can display information executed according to the logic of the application on the display panel 641.

[0288] As another example, when a music streaming icon displayed on display module 640 is selected, processor 610 acquires user input through input sensor 661-2 and activates a music streaming application stored in memory 620. When a music execution command is input in the music streaming application, processor 610 activates audio output module 663 to provide audio information corresponding to the music execution command to the user.

[0289] Above is a brief description of the operation of the electronic device 601. Below, we will explain in detail the configuration of the electronic device 601. Some of the components of the electronic device 601 described below may be integrated and provided as a single component, or one component may be provided as two or more separate components.

[0290] 36 , an electronic device 601 can communicate with an external electronic device 602 through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device 601 can include a processor 610, a memory 620, an input module 630, a display module 640, a power module 650, an embedded module 660, and an external module 670. According to one embodiment, the electronic device 601 can omit at least one of the above components or can include one or more other components. According to one embodiment, some of the above components (e.g., the sensor module 661, the antenna module 662, or the acoustic output module 663) can be integrated into another component (e.g., the display module 640).

[0291] The processor 610 may execute software to control at least one other component (e.g., a hardware or software component) of the electronic device 601 coupled to the processor 610, and may perform various data processing or calculations. According to one embodiment, as at least part of the data processing or calculations, the processor 610 may store instructions or data received from other components (e.g., the input module 630, the sensor module 661, or the communication module 673) in the volatile memory 621, process the instructions or data stored in the volatile memory 621, and store the resulting data in the non-volatile memory 622.

[0292] The processor 610 may include a main processor 611 and an auxiliary processor 612. The main processor 611 may include one or more of a central processing unit (CPU) 611-1 or an application processor (AP). The main processor 611 may further include one or more of a graphics processing unit (GPU) 611-2, a communication processor (CP), and an image signal processor (ISP). The main processor 611 may further include a neural network processing unit (NPU) 611-3. The neural network processing unit is a processor specialized in processing an artificial intelligence model, and the artificial intelligence model can be generated through machine learning. The artificial intelligence model may include multiple artificial neural network layers. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the above examples. The artificial intelligence model may include a software structure in addition to or mainly in addition to a hardware structure. At least two of the above processing units and processors may be implemented in an integrated structure (e.g., a single chip) or each may be implemented in an independent structure (e.g., multiple chips).

[0293] The auxiliary processor 612 may include a drive controller 612-1. The drive controller 612-1 may include an interface conversion circuit and a timing control circuit. The drive controller 612-1 receives image signals from the main processor 611, converts the data format of the image signals to match the interface specifications with the display module 640, and outputs image data. The drive controller 612-1 may output various control signals required to drive the display module 640. The configuration of the drive controller 612-1 is substantially similar to that of the drive controller 100 shown in FIG. 1, so a detailed description thereof will be omitted.

[0294] The auxiliary processor 612 may further include a data conversion circuit 612-2, a gamma correction circuit 612-3, a rendering circuit 612-4, etc. The data conversion circuit 612-2 receives image data from the drive controller 612-1 and compensates the image data so that an image is displayed at a desired brightness according to the characteristics of the electronic device 601 or a user setting, or converts the image data to reduce power consumption or compensate for image lag. The gamma correction circuit 612-3 converts image data or a gamma reference voltage, etc. so that an image displayed on the electronic device 601 has desired gamma characteristics. The rendering circuit 612-4 receives image data from the drive controller 612-1 and renders the image data taking into account the pixel layout of a display panel 641 applied to the electronic device 601, etc. At least one of the data conversion circuit 612-2, the gamma correction circuit 612-3, and the rendering circuit 612-4 may be integrated into another component (e.g., the main processor 611 or the controller 612-1). At least one of the data conversion circuit 612-2, the gamma correction circuit 612-3, and the rendering circuit 612-4 may be integrated into a data driver 643, which will be described later.

[0295] The memory 620 may store various data used by at least one component (e.g., the processor 610 or the sensor module 661) of the electronic device 601 and input or output data for associated instructions. The memory 620 may include at least one of a volatile memory 621 and a non-volatile memory 622.

[0296] The input module 630 can receive instructions or data for use by components of the electronic device 601 (e.g., the processor 610, the sensor module 661, or the acoustic output module 663) from outside the electronic device 601 (e.g., from a user or an external electronic device 602).

[0297] The input module 630 may include a first input module 631 through which commands or data are input from a user and a second input module 632 through which commands or data are input from the external electronic device 602. The first input module 631 may include a microphone, a mouse, a keyboard, keys (e.g., buttons), or a pen (e.g., a passive pen or an active pen). The second input module 632 may support a specified protocol for wired or wireless connection to the external electronic device 602. According to an embodiment, the second input module 632 may include a high definition multimedia interface (HDMI), a universal serial bus (USB), an SD card interface, or an audio interface. The second input module 632 may include a connector that can be physically connected to the external electronic device 602, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headset connector).

[0298] The display module 640 provides visual information to a user. The display module 640 may include a display panel 641, a scan driver 642, and a data driver 643. The display module 640 may further include a window, a chassis, and a bracket for protecting the display panel 641. The display module 640 may further include a light emitting driver and a voltage generator. The voltage generator may output various voltages (e.g., first and second driving voltages ELVDD and ELVSS (see FIG. 3)) required to drive the display panel 641. The configurations of the display panel 641, the scan driver 642, the data driver 643, and the voltage generator are substantially similar to the display panel DP, first and second gate driving circuits 300 and 350, data driving circuit 200, and voltage generator 400 shown in FIG. 1, and therefore detailed description thereof will be omitted.

[0299] The power supply module 650 supplies power to the components of the electronic device 601. The power supply module 650 may include a battery that charges the power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power supply module 650 may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and below. The power supply module 650 may include a wireless power transmitting / receiving member electrically connected to the battery. The wireless power transmitting / receiving member may include a plurality of antenna radiators in the form of coils.

[0300] The electronic device 601 may further include an embedded module 660 and an external module 670. The embedded module 660 may include a sensor module 661, an antenna module 662, and an acoustic output module 663. The external module 670 may include a camera module 671, a light module 672, and a communication module 673.

[0301] The sensor module 661 can sense input from the user's body or input from a pen in the first input module 631 and generate an electrical signal or data value corresponding to the input. The sensor module 661 can include at least one of a fingerprint sensor 661-1, an input sensor 661-2, and a digitizer 661-3.

[0302] The fingerprint sensor 661-1 can generate a data value corresponding to a user's fingerprint and can include either an optical or capacitive fingerprint sensor.

[0303] The input sensor 661-2 can generate data values ​​corresponding to coordinate information of input by the user's body or pen. The input sensor 661-2 generates data values ​​based on the amount of capacitance change due to the input. The input sensor 661-2 can sense input by a passive pen or send and receive data to and from an active pen.

[0304] The input sensor 661-2 may measure a biological signal such as blood pressure, water content, or body fat. For example, when a user touches a body part to the sensor layer or sensing panel and does not move for a certain period of time, the input sensor 661-2 can sense the biological signal based on a change in an electric field caused by the body part and output information desired by the user to the display module 640.

[0305] The digitizer 661-3 can generate data values ​​corresponding to the coordinate information of the input by the pen. The digitizer 661-3 generates data values ​​based on the amount of electromagnetic change caused by the input. The digitizer 661-3 can sense input by a passive pen or can send and receive data to and from an active pen.

[0306] At least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 may be implemented as a sensor layer formed on the display panel 641 through a continuous process. The fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 may be disposed on the upper side of the display panel 641, and one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3, for example, the digitizer 661-3, may be disposed on the lower side of the display panel 641.

[0307] At least two of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 may be formed to be integrated into one sensing panel through the same process. When integrated into one sensing panel, the sensing panel may be disposed between the display panel 641 and a window disposed above the display panel 641. According to an embodiment, the sensing panel may be disposed above the window, and the position of the sensing panel is not particularly limited.

[0308] At least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 may be embedded in the display panel 641. That is, at least one of the fingerprint sensor 661-1, the input sensor 661-2, and the digitizer 661-3 may be formed simultaneously through a process for forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 641.

[0309] Additionally, the sensor module 661 may generate an electrical signal or a data value corresponding to an internal or external state of the electronic device 601. The sensor module 661 may further include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0310] The antenna module 662 may include one or more antennas for transmitting or receiving signals or power to or from an external device. According to an embodiment, the communication module 673 may transmit or receive signals to or from an external electronic device through an antenna compatible with a communication method. The antenna pattern of the antenna module 662 may be integrated into one component of the display module 640 (e.g., the display panel 641) or the input sensor 661-2.

[0311] The audio output module 663 may include a speaker for general use, such as multimedia playback or recording playback, and a receiver for receiving telephone calls, as a device for outputting audio signals to the outside of the electronic device 601. According to an embodiment, the receiver may be formed integrally with or separate from the speaker. The audio output pattern of the audio output module 663 may also be integrated into the display module 640.

[0312] The camera module 671 can capture still images and video. According to an embodiment, the camera module 671 can include one or more lenses, image sensors, or image signal processors. The camera module 671 can further include an infrared camera that can measure the presence or absence of a user, the user's position, the user's line of sight, etc.

[0313] The light module 672 can provide light. The light module 672 can include a light emitting diode or a xenon lamp. The light module 672 can operate in conjunction with the camera module 671 or can operate independently.

[0314] The communication module 673 can support the establishment of a wired or wireless communication channel between the electronic device 601 and the external electronic device 602 and the execution of communication through the established communication channel. The communication module 673 can include any one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module, and a wired communication module such as a local area network (LAN) communication module or a power line communication module. The communication module 673 can communicate with the external electronic device 602 through a short-range communication network such as Bluetooth, WiFi Direct, or infrared data association (IrDA), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN). The various types of communication modules 673 described above can be implemented on a single chip, or each can be implemented on a separate chip.

[0315] The input module 630 , sensor module 661 , camera module 671 , etc. may be utilized in conjunction with the processor 610 to control the operation of the display module 640 .

[0316] The processor 610 outputs commands or data to the display module 640, the audio output module 663, the camera module 671, or the light module 672 based on input data received from the input module 630. For example, the processor 610 may generate image data corresponding to input data applied through a mouse, an active pen, or the like, and output the image data to the display module 640, or may generate command data corresponding to the input data and output the command data to the camera module 671 or the light module 672. If the processor 610 does not receive input data from the input module 630 for a certain period of time, the processor 610 may switch the operation mode of the electronic device 601 to a low power mode or a sleep mode to reduce power consumption of the electronic device 601.

[0317] The processor 610 outputs commands or data to the display module 640, the audio output module 663, the camera module 671, or the light module 672 based on the sensing data received from the sensor module 661. For example, the processor 610 may compare authentication data applied by the fingerprint sensor 661-1 with authentication data stored in the memory 620 and then execute an application according to the comparison result. The processor 610 may execute commands or output corresponding image data to the display module 640 based on sensing data sensed by the input sensor 661-2 or the digitizer 661-3. If the sensor module 661 includes a temperature sensor, the processor 610 may receive temperature data on the measured temperature from the sensor module 661 and further perform brightness correction on the image data based on the temperature data.

[0318] The processor 610 can receive measurement data regarding the presence or absence of a user, the user's position, the user's line of sight, etc. from the camera module 671. The processor 610 can further perform brightness correction, etc. on the image data based on the measurement data. For example, the processor 610, which determines the presence or absence of a user through input from the camera module 671, can output image data whose brightness has been corrected to the display module 640 via the data conversion circuit 612-2 or the gamma correction circuit 612-3.

[0319] Some of the components may be connected to each other via a peripheral communication method, such as a bus, a general purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or an ultrapath interconnect (UPI) link, to exchange signals (e.g., commands or data). The processor 610 may communicate with the display module 640 via a mutually agreed-upon interface, and may use, for example, any one of the above-mentioned communication methods, but is not limited to the above-mentioned communication methods.

[0320] The electronic device 601 according to various embodiments disclosed herein can be a variety of devices. The electronic device 601 can include, for example, at least one of a portable communication device (e.g., a smartphone), a computing device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronic device. The electronic device 601 according to embodiments of the present document is not limited to the aforementioned devices.

[0321] Although the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. [Explanation of symbols]

[0322] DD display device PXCa pixel circuit ED light emitting element T1 First transistor T2 Second transistor T3 Third transistor T4 Fourth transistor ET1 First light-emitting control transistor ET2 Second light-emitting control transistor ET3 Third light-emitting control transistor C1 First capacitor C2 Second capacitor Tint initialization section Tcom compensation section Tinv Interval section Tdw Data write section Tem light emission section

Claims

1. a display panel including pixels; The pixel is a light emitting device including an anode and a cathode connected to the first power line; a first transistor connected between the cathode and a second power line and operating in response to a potential of a first node; a second transistor connected between the first node and a data line and receiving a first scan signal; a third transistor connected between the first node and a reference voltage line and receiving a second scan signal; a first light-emitting control transistor connected between the first transistor and the second power line and connected to a third node to receive a first light-emitting control signal; a first capacitor connected between the first node and a second node to which the first transistor and the first light-emitting control transistor are connected; a second capacitor coupled between the second node and the third node.

2. During an initialization period, the second scan signal and the first light-emitting control signal have an activation level, The display device of claim 1 , wherein the first scan signal has an inactive level during the initialization period.

3. The compensation period is executed after the initialization period; During the compensation period, the second scan signal has an activation level; During the compensation period, the first scan signal and the first light-emitting control signal have an inactive level; The data write section is executed after the compensation section; During the data write period, the first scan signal has an activation level; The display device of claim 2 , wherein the second scan signal and the first light emission control signal are at an inactive level during the data write period.

4. The pixel is The display device of claim 3 , further comprising a second light-emitting control transistor connected between the first transistor and the cathode and receiving the first light-emitting control signal.

5. The pixel is 5. The display device of claim 4, further comprising a fourth transistor connected between a fourth node, to which the first transistor and the second light-emitting control transistor are connected, and the first power line, and configured to receive the second scan signal.

6. The pixel is 5. The display device of claim 4, further comprising a fourth transistor connected between a fourth node, to which the first transistor and the second light-emitting control transistor are connected, and an initialization voltage line receiving an initialization voltage, and receiving the second scan signal.

7. The pixel is The display device of claim 3 , further comprising a second light-emitting control transistor coupled between the first transistor and the cathode and receiving a second light-emitting control signal.

8. The pixel is 8. The display device of claim 7, further comprising a fourth transistor connected between the cathode and an initialization voltage line for receiving an initialization voltage, the fourth transistor receiving the second scan signal.

9. The pixel is The display device of claim 3 , further comprising a third light-emitting control transistor connected between the first light-emitting control transistor and the second power line and receiving a third light-emitting control signal.

10. The pixel is The display device of claim 3 , further comprising a fourth transistor connected between the cathode and the first power line and receiving a third scan signal.

11. The display device of claim 10 , wherein the activation period of the third scan signal overlaps with the activation period of the second scan signal and the activation period of the first scan signal, and overlaps with the inactivation period of the first light emission control signal.

12. The pixel is The display device of claim 10 , further comprising a second light-emitting control transistor connected between the first light-emitting control transistor and the second power line and receiving a second light-emitting control signal.

13. a start point of an inactive period of the second light-emitting control signal precedes a start point of an inactive period of the first light-emitting control signal; The display device of claim 12 , wherein an end point of the inactive period of the second light-emitting control signal precedes an end point of the inactive period of the first light-emitting control signal.

14. The pixel is The display device of claim 10 , further comprising a second light-emitting control transistor connected between the first light-emitting control transistor and the second node and receiving a second light-emitting control signal.

15. The pixel is The display device of claim 3 , further comprising a fourth transistor connected between the cathode and an initialization voltage line that receives an initialization voltage, the fourth transistor receiving a third scan signal.

16. 16. The display device of claim 15, wherein an activation period of the third scan signal overlaps with an activation period of the second scan signal and an activation period of the first scan signal, and overlaps with an inactivation period of the first light emission control signal.

17. a display panel including pixels, first and second scan lines, a first light-emitting control line, first and second power supply lines, a reference voltage line, and a data line; a first gate driving circuit connected to the first and second scan lines; a second gate driving circuit connected to the first light emitting control line; The pixel is a light emitting device including an anode and a cathode connected to the first power line; a first transistor connected between the cathode and the second power line and operating in response to a potential of a first node; a second transistor connected between the first node and the data line and receiving a first scan signal through the first scan line; a third transistor connected between the first node and the reference voltage line and receiving a second scan signal through the second scan line; a first light-emitting control transistor connected between the first transistor and the second power line and receiving a first light-emitting control signal through the first light-emitting control line; a first capacitor connected between the first node and a second node to which the first transistor and the first light-emitting control transistor are connected; a second capacitor connected between the second node and the first light emission control line.

18. The first gate drive circuit a first scan driving circuit connected to the first scan line; a second scan driving circuit connected to the second scan line; The second gate drive circuit The display device of claim 17 , further comprising a light emission control circuit connected to the first light emission control line.

19. The pixel is a fourth transistor connected between the cathode and the first power line and configured to receive a third scan signal through a third scan line; The first gate drive circuit a first scan driving circuit connected to the first scan line; a second scan driving circuit connected to the third scan line; The second gate drive circuit a light emitting control circuit connected to the first light emitting control line; The display device of claim 17 , further comprising: a third scan driving circuit connected to the second scan lines.

20. a display panel including pixels; a panel driver that drives the display panel; a drive controller for controlling the driving of the panel driver; a main processor for providing image signals to said drive controller; The pixel is a light emitting device including an anode and a cathode connected to the first power line; a first transistor connected between the cathode and a second power line and operating in response to a potential of a first node; a second transistor connected between the first node and a data line and receiving a first scan signal; a third transistor connected between the first node and a reference voltage line and receiving a second scan signal; a first light-emitting control transistor connected between the first transistor and the second power line and connected to a third node to receive a first light-emitting control signal; a first capacitor connected between the first node and a second node to which the first transistor and the first light-emitting control transistor are connected; a second capacitor coupled between the second node and the third node.

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