Semiconductor device

Abstract

To provide a semiconductor device having a large storage capacity per unit area.SOLUTION: A semiconductor device includes a memory transistor, in which the memory transistor includes a conductor having an opening, a first insulator in contact with an inner side surface of the opening, a second insulator in contact with an inner side surface of the first insulator, a third insulator in contact with an inner side surface of the second insulator, a first oxide in contact with an inner side surface of the third insulator, and a second oxide in contact with an inner side surface of the first oxide, and the second oxide has a narrower energy gap than the first oxide.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a memory device and a semiconductor device. The present invention relates to a memory device and a method for manufacturing a semiconductor device. The present invention also relates to a memory transistor and a method for manufacturing the memory transistor, for example, The present invention relates to a processor and an electronic device. Also, the present invention relates to a method for manufacturing a processor and an electronic device. The present invention also relates to a memory device, a processor, and a method for driving an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, semiconductor circuits, and The electronic equipment may include semiconductor devices. [Background technology]

[0004] In recent years, with the increase in the amount of data handled, there has been a demand for semiconductor devices with larger storage capacities. To increase the storage capacity per unit area, memory cells are stacked. It is effective to form the memory cells in a stacked manner (see Patent Documents 1 and 2). By doing so, the memory capacity per unit area can be increased in accordance with the number of stacked memory cells. can be done. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Publication No. 2011 / 0065270A1 [Patent Document 2] U.S. Patent Publication No. 9634097B2 Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1, a semiconductor pattern provided in a columnar shape is formed on an insulating substrate having a charge storage layer. In addition, in Patent Document 2, a semiconductor pattern provided in a columnar shape is The semiconductor is in direct contact with an insulator that acts as a tunnel dielectric. When a semiconductor and an insulating material are bonded to each other, trap centers may be formed at these interfaces. The trap centers formed at the interface with the body capture electrons and increase the threshold voltage of the transistor. In order to change the voltage in the positive direction, the current driving force in the on state of the transistor, that is, This may adversely affect the on-state current, field effect mobility, and reliability.

[0007] In view of the above problems, one aspect of the present invention is to provide a method for suppressing the formation of trap centers and achieving good electrical conductivity. An object of the present invention is to provide a semiconductor device having thermal characteristics.

[0008] Another object of the present invention is to provide a semiconductor device having a large storage capacity per unit area. Alternatively, a semiconductor device with a new structure in which memory cells (also called memory transistors) are stacked Another object of the present invention is to provide a semiconductor device with high productivity. This is one of the challenges.

[0009] Another object of the present invention is to provide a module including the semiconductor device. An object of the present invention is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. One of the objectives is to provide a novel electronic device. do.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a memory transistor, The conductor has an opening, a first insulator provided in contact with the inner side surface of the opening, and a second A second insulator is provided in contact with the inside of the first insulator, and a second insulator is provided in contact with the inside of the second insulator. a third insulator provided on the inner surface of the third insulator; a first oxide provided in contact with the inner surface of the third insulator; and a second oxide provided in contact with the inner surface of the oxide, and the energy gap of the second oxide is The gap is a semiconductor device having an energy gap narrower than that of the first oxide.

[0012] Another embodiment of the present invention is a semiconductor device including a memory transistor, The transistor includes a conductor having an opening and a first insulator provided in contact with the inner side surface of the opening. a second insulator provided in contact with the inside of the first insulator; a third insulator provided between the first oxide layer and the second oxide layer; and a first oxide provided in contact with the inner surface of the third insulator. A second oxide is provided in contact with the inside of the first oxide, and a second oxide is provided in contact with the inside of the second oxide. and a third oxide having an energy gap of 1000 .mu.m or less than that of the first oxide. The energy gap of the second oxide is narrower than that of the third oxide. This is a semiconductor device with a narrower energy gap.

[0013] In the above, the first oxide and the second oxide are made of In and an element M (M is Al, G It is preferable that the composition contains at least one of Sn, Y, or Sn) and Zn.

[0014] In the above, the atomic ratio of element M to In in the first oxide is It is preferable that the atomic ratio of element M to element B is larger than that of element C.

[0015] In the above, the semiconductor device further has a base, and the semiconductor device has a memory cell on the base. The plurality of memory transistors are arranged perpendicular to one surface of the substrate. It is preferable that the layers are laminated in the same direction.

[0016] In the above, the first insulator is any one of silicon, aluminum, and hafnium. It is preferably an oxide containing iodide.

[0017] In the above, the third insulator is any one of silicon, aluminum, and hafnium. It is preferably an oxide containing iodide.

[0018] In the above, the memory transistor may further have a fourth insulator, The insulator is preferably provided on the inside of the third oxide so as to be in contact with it. [Effects of the Invention]

[0019] According to one aspect of the present invention, the formation of trap centers is suppressed and good electrical properties are obtained. It is possible to provide a semiconductor device.

[0020] Furthermore, a semiconductor device having a large storage capacity per unit area can be provided. We provide a semiconductor device with a new structure in which memory cells (also called memory transistors) are stacked. Alternatively, a semiconductor device with high productivity can be provided.

[0021] Alternatively, a module having the semiconductor device can be provided. It is possible to provide a device or an electronic device having the module. A conductor device may be provided, or a novel module may be provided. Alternatively, a novel electronic device can be provided.

[0022] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above will be self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0023] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a perspective view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 3]FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A and 1B are a functional block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention, and a circuit diagram illustrating a configuration example of a memory string. [Figure 15] FIG. 1 illustrates an example of a three-dimensional structure of a memory cell array according to one embodiment of the present invention. [Figure 16] FIG. 1 illustrates an example of a three-dimensional structure of a memory cell array according to one embodiment of the present invention. [Figure 17] FIG. 1 illustrates an example of a three-dimensional structure of a memory cell array according to one embodiment of the present invention. [Figure 18] FIG. 10 is a circuit diagram illustrating the operation of a memory device according to one embodiment of the present invention. [Figure 19] FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a block diagram showing an example of the configuration of an AI system according to one embodiment of the present invention. [Figure 21]FIG. 1 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention. [Figure 22] 1 is a schematic perspective view showing an example of the configuration of an IC incorporating an AI system according to one embodiment of the present invention. [Figure 23] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 24] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the invention in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the mode and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0025] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations, and are not limited to the shapes or values ​​shown in the drawings. In this case, the same reference numerals are used in common between different drawings to designate the same parts or parts having similar functions. In addition, when referring to the same function, the hatch pattern is used. In some cases, the same symbol is not attached.

[0026] In addition, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" "the" or "third" can be used as appropriate for explanation. The ordinal numbers listed in the specification do not match the ordinal numbers used to identify an aspect of the present invention. There are cases where this happens.

[0027] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0028] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0029] In this specification, the term "nitride oxide" refers to a compound containing more nitrogen than oxygen. An oxynitride is a compound that contains more oxygen than nitrogen. The content of element can be measured by, for example, Rutherford Backscattering (RBS) spectroscopy. It can be measured using techniques such as backscattering spectrometry. do.

[0030] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0031] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Almost parallel" means that the two lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0032] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0033] In this specification, the term "barrier film" refers to a film that prevents impurities such as hydrogen and oxygen from permeating. When the barrier film has conductivity, it is called a conductive barrier film. Sometimes I call.

[0034] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. It can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0035] In addition, for this specification and the like, In:Ga:Zn = 4:2:3 or in the vicinity thereof means that when In is 4 with respect to the total number of atoms, Ga is 1 or more and 3 or less (1≤Ga≤3), and Zn is 2 or more and 4.1 or less (2≤Zn≤4.1). Also, In:Ga:Zn = 5:1:6 or in the vicinity thereof means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga≤2), and Zn is 5 or more and 7 or less (5≤Zn≤7). Also In:Ga:Zn = 1:1:1 or in the vicinity thereof means that when In is 1 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga≤2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn≤2).

[0036] (Embodiment 1) In this embodiment, the configuration, manufacturing method, circuit configuration, and operation of a semiconductor device according to an aspect of the disclosed invention will be described with reference to FIGS. 1 to 18.

[0037] (Memory Transistor, Memory Cell Array 700) First, the configuration of the memory transistor and the memory cell array of the semiconductor device will be described with reference to FIGS. 1 to 3. FIG. 1(A) is a top view of the memory cell array 700, FIG. 1(B) is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 1(A). Also FIG. 1(C) is a cross-sectional view of the portion indicated by the dashed line A3 - A4 in FIG. 1(A), which is a cross-sectional view for explaining memory stringing. Also, FIGS. 1(D), 2(A), and 2(B ) are enlarged views of the portion surrounded by the dashed line in FIG. 1(B), which are memory cells FIG. 1(D) is a diagram illustrating a memory transistor that functions. 2(A) and 2(B) are perspective views of the memory transistor. 2(C) is an enlarged view of the area enclosed by the dashed line in FIG. 1(C). FIG. 1 is a perspective view illustrating a transistor that functions as a selection transistor. In the following, for convenience, we will use an orthogonal coordinate system consisting of x-axis, y-axis, and z-axis as shown in Figure 1. Here, the x-axis and y-axis are the same as those of the substrate 700 on which the memory cell array 700 is provided. The axis is parallel to the upper surface of the substrate 720, and the z-axis is perpendicular to the upper surface of the substrate 720.

[0038] The memory cell array 700 includes a base 720 on which conductors 701 (conductors 701_1 to 701_2) are disposed. Conductors 701_m (where m is a natural number of 2 or more) or conductors 702 and insulating films are alternately stacked. The laminate has an insulator 7 inside an opening formed to penetrate the laminate. 703 (insulators 703_1 to 703_4), and an oxide 703 is formed inside the insulator 703. 04 (oxide 704_1 to oxide 704_4), and oxides 704_1 to 704_4 The upper ends of the conductors 705 (conductors 705_1 to 705_4) are electrically connected to the upper ends of the conductors 705. The oxides 704_1 to 704_4 are formed on the lower ends of the oxides 704_1 to 704_4, respectively. The conductive member 706 (the conductive members 706_1 to 706_4) is electrically connected. The conductors 701_1 to 701_m are electrically connected to the conductors 707 (conductors 707_1 to 707_m), conductors 707_1 to 707_m, Conductors 708 (conductors 708_1 to 708_m) are electrically connected to each other. In FIG. 1B, the conductors 701 are arranged in four or more stages to represent a plurality of conductors 701. Although shown above, this embodiment is not limited to FIG. 1(B), and at least the conductor 7 It is sufficient to have two or more rows of 01.

[0039] Here, as shown in FIGS. 1A and 1B, the conductor 701 extends in the x-axis direction. As shown in FIGS. 1B and 1C, the insulator 703 and the oxide The conductor 701, the insulator 703, and the insulator 704 are arranged to extend in the z-axis direction. and oxide 704 are preferably provided so as to intersect each other perpendicularly. As shown in Fig. 7B, the conductor 707 is provided extending in the z-axis direction. The wiring BL connected to the conductor 705 may be provided by extending in the y-axis direction. A functional conductor may be provided extending in the y-axis direction. The conductor may be arranged to function as a conductive film, and extend in the y-axis direction.

[0040] The oxide 704 is formed in a columnar shape and extends in the z-axis direction. The conductive material 703 is provided so as to surround the side periphery of the columnar oxide 704. 07 is formed in a columnar shape and extends in the z-axis direction.

[0041] The columnar oxide 704 is electrically connected to the conductor 706 at its lower end in the z-axis direction, and At the end, the conductor 705 is electrically connected. 706 is electrically connected to the bottom ends of two adjacent pillar-shaped oxides 704, and the two pillar-shaped oxides The upper ends of the conductors 704 are electrically connected to the electrically isolated conductors 705, respectively.

[0042] Here, the vicinity of the region where the conductor 701 intersects with the insulator 703 and the oxide 704 is It functions as a memory transistor. The area where these memory transistors intersect functions as a selection transistor. The channel length direction of the memory transistor and the select transistor is parallel to the z-axis. The memory string is a This constitutes a group.

[0043] Note that the structure of the semiconductor device described in this embodiment mode is an example, and the present invention is not limited to this embodiment mode. The number and arrangement of circuit elements, wiring, etc. shown in the drawings are not limited to those shown in the drawings. The number and arrangement of circuit elements, wirings, etc., included in the semiconductor device according to this embodiment etc. can be set appropriately in accordance with the circuit configuration and driving method.

[0044] The base 720 on which the memory cell array 700 is provided preferably has an insulating surface. Substrates having an insulating surface include semiconductor substrates with an insulating film formed on the surface, insulating substrates, and A conductive substrate with an insulator formed on its surface may be used. Semiconductor substrates such as silicon and germanium, or silicon carbide and silicon germanium , gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. The insulating substrate may be, for example, a glass substrate, a quartz substrate, or a sapphire substrate. Plates, stabilized zirconia substrates (yttria-stabilized zirconia substrates, etc.), resin substrates, etc. In addition, the semiconductor substrate having an insulator region therein, for example, SO A silicon-on-insulator (I) substrate may also be used. The substrate may be a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like.

[0045] The conductor 701 functions as the gate of the memory transistor and is electrically connected to the word line. That is, the conductor 701, the conductor 707, and the conductor 708 are part of the word line. Here, the conductor 701 functions as a barrier layer. It is preferable that O1 is provided in a stepped shape extending from the upper layer conductor 701 toward the A2 side. In this way, by providing the conductor 701, a part of the upper surface of the lower conductor 701 However, since the conductor 701 does not overlap with the conductor 701 in the upper layer, the conductor 701 in the corresponding region of each layer and each conductor 707 can be connected.

[0046] The conductor 701 can be made of a conductive material such as silicon or metal. When silicon is used as the conductor 701, amorphous silicon or polysilicon may be used. In addition, to make silicon conductive, p-type impurities or n-type impurities can be added. Pure materials may also be added. In addition, conductive materials containing silicon may include titanium, cobalt, or Alternatively, a silicide containing nickel can be used as the conductor 701. When the material is used for the conductor 701, aluminum, chromium, copper, silver, gold, platinum, tantalum, Nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese Choose from cancer, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more of the above metal elements can be used.

[0047] The conductor 702 is provided above the conductor 701 with an insulating film interposed therebetween. Select transistors (bit line side select transistor: SDT and source line side select transistor: The conductor 702 functions as a gate of the conductor 701. The conductor 702 can be made of the same material as the conductor 701. Depending on the application of the conductor 701 and the conductor 702, different materials may be used. Therefore, the materials to be used for the conductor 701 and the conductor 702 are determined in consideration of the work function, etc. That's fine.

[0048] The insulating films provided on the upper and lower layers of the conductor 701 and the conductor 702 are Oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, Metal nitride oxides, etc. can be used. Silicon oxide, silicon oxynitride, nitride oxide Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide Silicon oxide doped with carbon and nitrogen, silicon oxide with pores, or resins are comparatively Because of its low dielectric constant, it is suitable for use in the insulating film.

[0049] On the other hand, the insulating film may be made of aluminum oxide, gallium oxide, hafnium oxide, or zirconium oxide. oxides containing ruthenium, aluminum and hafnium, oxide nitride with silicon and hafnium, oxide with silicon and hafnium, Nitride oxide containing hafnium or nitride containing silicon and hafnium However, since these have a high relative dielectric constant, the conductors 701 may be separated from each other or from each other. Parasitic capacitance may occur between the conductor 702 and the conductor 703. The material to be used for the insulating film can be determined.

[0050] As shown in FIG. 1D, the insulator 703 includes an insulator 703a, an insulator 703b, and The insulator 703a is provided on the conductor 701 side, and the insulator 703 The insulator 703c is provided on the oxide 704 side, and the insulator 703b is provided on the oxide 704 side. The insulator 703a functions as a gate insulating layer, and the insulator 703b is The insulator 703c functions as a tunnel insulating layer.

[0051] As shown in FIG. 2C, the select transistor has a charge storage layer and a tunnel insulating layer. Therefore, the bit line side transistor: SDT and the source line side transistor: Transistor: In SST, the insulator 703 is made of insulator 703b and insulator 703 Alternatively, only the insulator 703a may be provided without providing the insulator c. The oxide 704 has a two-layer structure of oxide 704a and oxide 704b. As shown in FIG. 2B, the oxide 704 includes an oxide 704a and an oxide 704b. 4b and oxide 704c, or a laminated structure of four or more layers. An insulator 711 may be provided inside the oxide 704b.

[0052] The insulator 703a is preferably made of silicon oxide or silicon oxynitride. Also, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide Alternatively, these oxides may be stacked to form the insulator 703a.

[0053] The insulator 703b is preferably made of a material that functions as a charge storage layer, and silicon nitride is It is preferable to use silicon dioxide or silicon nitride oxide. Oxides containing niobium, or aluminum and hafnium may also be used.

[0054] The insulator 703c is preferably made of silicon oxide or silicon oxynitride. Also, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide Alternatively, an oxide such as SiO 2 may be used. Alternatively, these may be stacked to form the insulator 703c. The insulator 703c is preferably thinner than the insulator 703a. When writing or erasing data to the transistor, an oxide passes through the insulator 703c. Charge transfer occurs between the oxide 704 and the insulator 702b. functions as a tunnel insulating layer.

[0055] In particular, the opening formed in the laminated body having the conductor 701, the conductor 702, and the insulating film When forming the insulator 703, the insulator 703 formed at the bottom of the opening is removed by dry etching. It is necessary to remove it by anisotropic etching using a tool such as a grease gun. The side surfaces of the insulator 703c are also exposed to plasma, radicals, gas, chemicals, etc. When the side surface of the insulator 703c is damaged by these, a trap cell is formed in the insulator 703c. This can cause trap centers, which can affect the electrical characteristics of the transistor. To suppress the generation of ions, the side surface of the insulator 703c is made resistant to damage caused by etching. In this case, the insulator 703c is made of aluminum oxide. silicon oxide and aluminum oxide, or silicon oxynitride and aluminum oxide It is preferable to use a stack of silicon dioxide.

[0056] The insulators 703a, 703b, and 703c are formed by using an ALD method or a CVD method. In addition, the insulator 703a, the insulator 703b, and the insulator 70 To prevent contamination of the interface of 3c, the same chamber or a multi-chamber system Using a multi-chamber film-forming device, films are formed continuously without being exposed to the atmosphere. It is preferable.

[0057] The oxide 704 is a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor). It is preferable to use oxide semiconductors, which are superior to semiconductors made of silicon and the like. This is preferable because the transistor has good on-state characteristics and high mobility.

[0058] For example, the oxide 704 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Tantalum, tungsten, magnesium, etc.) The oxide 704 may be an In-Ga oxide or an In-Z n-oxides may also be used.

[0059] The oxide 704 is made up of an oxide 704a provided on the insulator 703c side and an oxide 704b provided on the insulator 703c side. It is preferable that the oxide 704a has an oxide 704b provided on the side of the oxide 704a. It is preferable to use an oxide having a relatively wide energy gap for the oxide 704b. Here, oxides with a wide energy gap are called wide-gap and An oxide with a narrow gap is sometimes called a narrow gap.

[0060] When the oxide 704a is a wide gap and the oxide 704b is a narrow gap, The energy of the conduction band minimum of the oxide 704a is equal to the energy of the conduction band minimum of the oxide 704b. In other words, the electron affinity of the oxide 704a is preferably higher than that of the oxide 704a. It is preferable that the electron affinity of the compound 704b is smaller than that of the compound 704b.

[0061] The oxide 704a and the oxide 704b have different atomic ratios of the metal atoms. Specifically, the metal oxide used for the oxide 704a has the following structure: The atomic ratio of element M in the element is It is preferable that the atomic ratio of the metal oxide used for the oxide 704a is larger than that of the element M. In the oxide 704b, the atomic ratio of element M to In is In the oxide 704, the atomic ratio of element M to In is preferably larger than that of element M. In the metal oxide used in oxide 704b, the atomic ratio of In to element M is It is preferable that the atomic ratio of In to M in the metal oxide is larger than that of In to M in the metal oxide.

[0062] The oxide 704a may have a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3 :2, or metal oxides having a composition of In:Ga:Zn=1:1:1 or a composition close to that The oxide 704b may be, for example, In:Ga:Zn=4: 2:3 to 4.1, In:Ga:Zn=1:1:1, or In:Ga:Zn=5:1: Metal oxides having compositions of 6 or close to these can be used. The compound 704a and the oxide 704b can be combined so as to satisfy the above atomic ratio relationship. For example, the oxide 704a may have a composition of In:Ga:Zn=1:3:4 and The metal oxide 704b having a composition close to In:Ga:Zn=4:2:3 It is preferable to use a metal oxide having a composition of 4.1 or a composition close to that. The composition is determined by the atomic ratio in the oxide formed on the substrate or the atomic ratio in the sputtering target. Indicates the ratio of the number of electrons.

[0063] The oxide 704a is made of CAAC-OS, which will be described later, and the oxide 704b is made of It is preferable to use CAAC-OS as the oxide 704a. In this case, the c-axis is parallel to the xy plane shown in FIG. 1(A), i.e., perpendicular to the z-axis, and It is preferable to orient the light from the side of the opening toward the center.

[0064] Here, at the junction between the oxide 704a and the oxide 704b, the conduction band minimum is gradually In other words, the conduction band edge at the junction between the oxide 704a and the oxide 704b changes as follows: In other words, it can be said that the acid changes or bonds continuously. The defect level density of the mixed layer formed at the interface between the oxide 704a and the oxide 704b is reduced. It is recommended to do so.

[0065] Specifically, the oxide 704a and the oxide 704b have a common element other than oxygen (mainly By using the oxide as a component, it is possible to form a mixed layer with a low defect level density. When the oxide 704b is an In-Ga-Zn oxide, the oxide 704a is an In-Ga-Zn oxide. It is recommended to use n-oxide, Ga-Zn oxide, gallium oxide, etc. The defect level density at the interface between the oxide 704a and the oxide 704b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the memory transistor 710 can be highly A large on-current can be obtained.

[0066] For a more detailed description of metal oxides that can be used as the oxide 704, see , as will be described later.

[0067] FIG. 1D is an enlarged view of the memory transistor 710 enclosed by the dashed line in FIG. 1B. FIG. 2(A) is a perspective view of the memory transistor 710. ), and as shown in FIG. 2(A), the oxide 704b is surrounded by the oxide 704a. In this configuration, the oxide 704 is provided with a conductor 705 and a conductor 706. When a carrier flows in the direction from conductor 706 to conductor 705, or from conductor 706 to conductor 705, Carriers mainly flow in the component with a low gap. When the transistor is turned on, the transistor has a high current driving capability, i.e., a large on-state current. High field effect mobility can be obtained.

[0068] Furthermore, by providing the oxide 704a between the oxide 704b and the insulator 703c, The oxide 704b, which serves as a carrier path, does not come into direct contact with the insulator 703c. The formation of a pit center can be suppressed at the interface between the semiconductor (oxide semiconductor) and the insulator. The trap centers formed in the This may adversely affect the reliability and on / off characteristics of the transistor. Therefore, the transistor using this oxide has poor electrical characteristics due to the trap center. Since the device is not affected by the The transistor and the semiconductor device can achieve high current and high field-effect mobility. A semiconductor device including such a transistor can have high reliability.

[0069] Note that the oxide 704 shown in FIG. 1D and FIG. 2A is an oxide 704a. 2B, the present embodiment is not limited to this. 2B shows another example of the memory transistor 710. The insulator 710 is formed with an oxide layer inside the insulators 703a, 703b, and 703c. 704a is provided, and oxide 704b is provided inside oxide 704a, and oxide 704 An oxide 704c is provided inside the insulating layer 704b. The insulator 711 may be embedded in the insulating layer 711. The inside of the oxide 704c may be hollow.

[0070] The oxide 704b is sandwiched between the oxide 704a and the oxide 704c. In this case, the oxide 704c may be a wide gap oxide like the oxide 704a. By providing the oxide 704c which is a wide gap, the oxide 70 4 can be confined in the oxide 704b, and the transistor is in the on state. In this case, it is possible to obtain a high current driving force, i.e., a large on-state current, and a high field-effect mobility. can.

[0071] In addition, when the insulator 711 is provided inside the oxide 704c, the insulator 711 is 04 is a material that can supply oxygen or impurities such as hydrogen and nitrogen. By using an oxide containing as little hydrogen or nitrogen as possible as the insulator 711, Oxygen can be supplied to the oxide 704. By supplying oxygen to the oxide 704, the oxide Impurities such as hydrogen and water contained in the oxide 704 can be removed. By using an oxide with as few impurities as possible as the oxide 704, A transistor and a semiconductor device using the transistor can have high reliability. can.

[0072] In addition, by using an oxide containing hydrogen or nitrogen as the insulator 711, the oxide 704 In some cases, hydrogen or nitrogen can be supplied. By supplying hydrogen or nitrogen to the oxide 704, the oxide The resistance of the oxide 704 may be reduced so that it does not adversely affect the circuit operation. By lowering the voltage to a level that does not cause a problem, it is possible to operate the memory transistor at a lower drive voltage. In addition, a high current driving force, that is, a large ON state, can be obtained in the memory transistor. Therefore, a high on-state current and a high field-effect mobility can be obtained.

[0073] The opening formed in the stacked body in which the memory transistor 710 is provided is 2(A)(B), the upper surface is circular, but this is not limited to this. For example, the upper surface may be elliptical, or may be polygonal, such as triangular or rectangular. In addition, when the polygonal shape is used, the corners may be rounded. The top surface shapes of the insulator 703 and the oxide 704 change in accordance with the top surface shape of the opening. In addition, the cross-sectional area of ​​the opening on the lower side (conductor 705 side) is larger than that of the opening on the upper side (conductor 705 side). The cross-sectional area of ​​the opening on the side of the conductor 706 may be narrowed.

[0074] The oxide 704, the insulator 703, and the conductor 701 (conductors 701_1 to 701_2) A memory transistor is formed by any one of the following: 1 shows an example in which transistors are stacked in m stages (m is a natural number of 4 or more).

[0075] The conductor 705 is electrically connected to the oxide 704 and is connected to the source line SL or the bit line BL The conductor 705 may be formed of a conductive material containing a metal element. In addition, the metal element of the conductor 705 is preferably present at the interface between the conductor 705 and the oxide 704. It is preferable that a metal compound layer containing the element and the component of the oxide 704 is formed. The formation of the metal compound reduces the contact resistance between the conductor 705 and the oxide 704. Alternatively, the conductor 705 absorbs oxygen contained in the oxide 704, and the oxide The resistance of the oxide 704 in the vicinity of the interface between the conductor 705 and the oxide 704 is reduced. The contact resistance between 705 and the oxide 704 can be reduced.

[0076] The conductor 705 may be aluminum, ruthenium, titanium, tantalum, chromium, tungsten, or the like. Use a conductive material containing one or more metal elements selected from stainless steel and copper. is preferred.

[0077] The conductor 706 is a conductor that functions as a part of the bit line BL, as shown in FIG. 705 and an oxide 704 electrically connected to the source line SL. 704, which is electrically connected to the oxide 705, thereby forming a memory string. The area enclosed by the dotted line in Figure 1(A) represents the memory string. That is, FIG. 1A shows a memory cell array 700 having four memory strings. There are.

[0078] The conductor 706 can be made of a material similar to that of the conductor 705. 6 may be made of the same material as the conductor 705 or may be made of a different material.

[0079] In addition, at the interface between the conductor 706 and the oxide 704, a metal element contained in the conductor 706 and an oxide It is preferable that a metal compound layer containing the metal compound 704 is formed. The formation of the oxide 704 reduces the contact resistance between the conductor 706 and the oxide 704. Alternatively, the conductor 706 absorbs oxygen contained in the oxide 704, and the oxide 70 4, by reducing the resistance near the interface between the conductor 706 and the oxide 704, Therefore, the contact resistance with the oxide 704 can be reduced.

[0080] (Memory cell array 700A) FIG. 3 shows a memory cell array 700 in which a plurality of memory cell arrays 700 each having six stages of memory transistors are combined. 3 is a top view illustrating a memory cell array 700A. For example, the selection transformer provided on the conductor 701 is omitted. transistors (bit line side transistor: SDT, and source line side transistor: SST) The conductor 702, which is a component of these, is omitted. A conductor 705 serving as part of the line SL and a conductor 706 serving as part of the word line WL are The conductor 708 is shown by a solid line.

[0081] In the memory cell array 700A, each memory cell array 700 has six stages of memory transistors. The memory cell has four memory strings each having a transistor.

[0082] The bit line side ends of the memory strings are connected to different bit lines BL (BL_1 to BL_B L_4), the source line side end of the memory string is electrically connected to the source line S The source line SL is electrically connected to the source line L and is given a common potential. Alternatively, a constant potential may be applied. The position may be changed.

[0083] The conductors 701_1 to 701_6 are electrically connected to different word lines WL. The conductors 701_1 to 701_6 on the bit line side are connected to WLa_1 to WLa_6, respectively. The conductors 701_1 to 701_6 on the source line side are electrically connected to , are electrically connected to WLb_1 to WLb_6, respectively.

[0084] Bit lines BL (BL_1 to BL_4) and word lines (WLa_1 to WLa_6) , and WLb_1 to WLb_6) are appropriately selected, Any memory transistor in the selected memory transistor can be selected. The data can be written to, read from, erased, etc.

[0085] In addition, each memory string is provided with a selection transistor (not shown). Therefore, an arbitrary memory cell array 700 in the memory cell array 700A is selected, and the selected Any memory transistor in the memory cell array 700 can be written to, read from, or You can erase it, etc.

[0086] <<Metal oxides>> Metal oxides applicable to the oxide 704 according to the present invention will be described below.

[0087] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, titanium, iron, etc. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or One or more types may be included.

[0088] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, a combination of the aforementioned elements may be used.

[0089] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0090] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0091] In this specification, CAAC (c-axis aligned crystal) l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. An example is shown below.

[0092] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconductor properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making these functions work in a complementary manner, the switching function (On / Off) The function of making the CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, the respective functions By separating the two, the functions of both can be maximized.

[0093] In addition, CAC-OS or CAC-metal oxide is a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive and insulating regions in the material are formed by nanoparticles. The conductive region and the insulating region may be separated by different materials. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0094] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0095] In addition, CAC-OS or CAC-metal oxide has different energy For example, CAC-OS or CAC-metal The oxide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, the carriers flow When the narrow gap is formed, carriers mainly flow in the narrow gap component. The component with a gap acts complementary to the component with a wide gap, Carriers also flow into the wide gap component in conjunction with the wide gap component. The above CAC-OS or CAC-metal oxide is used to form the transistor channel. When used in the ON region, a high current driving force is required in the ON state of the transistor, i.e., a large ON Current and high field-effect mobility can be obtained.

[0096] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0097] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor) and non crystalline oxide semiconductors.

[0098] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0099] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is difficult to confirm the lattice distortion. This is because the CAAC-OS crystals are grown in the ab-plane direction. In the case of the SiO2, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0100] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0101] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS should be free from impurities and defects (oxygen vacancies (V O :oxygen v Therefore, CAAC- Metal oxides with OS have stable physical properties. Metal oxides are heat resistant and highly reliable.

[0102] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0103] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low density regions. The ke-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0104] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention may be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more of them.

[0105] [Transistors with metal oxides] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0106] Note that by using the above metal oxide for the channel formation region of a transistor, a high field efficiency can be achieved. It is possible to realize a transistor with high mobility. It can be realized.

[0107] Here, an example of a hypothesis regarding electrical conduction in metal oxides will be described.

[0108] Electrical conduction in solids is hindered by scattering sources called scattering centers. For example, in single crystals, In the case of silicon, lattice scattering and ionized impurity scattering are known to be the main scattering centers. In other words, when there are few lattice defects or impurities, the electrical conduction in the solid There are no blocking factors and carrier mobility is high.

[0109] The above is also assumed to be true for metal oxides. In metal oxides containing less oxygen than the oxygen that fills the composition, oxygen vacancies V O There are many It is thought that the atoms around this oxygen vacancy are in a distorted position rather than in their essential state. It is possible that the distortion caused by this oxygen vacancy is the scattering center.

[0110] For example, in a metal compound containing more oxygen than the stoichiometric composition, Excess oxygen is present. Excess oxygen, which exists in a free state in the metal compound, accepts electrons. By doing so, O - Ya O 2- It becomes. - Ya O 2- The excess oxygen may become a scattering center. There is.

[0111] From the above, it is clear that metal oxides have an essential state in which oxygen is contained in a stoichiometric composition. In this case, the carrier mobility is considered to be high.

[0112] Indium-, a type of metal oxide containing indium, gallium, and zinc, Gallium zinc oxide (IGZO) tends to have difficulty growing crystals in the atmosphere. Therefore, smaller crystals are more likely to be formed than larger crystals (here, crystals of several mm or several cm). In some cases, crystals (such as the nanocrystals mentioned above) are structurally more stable. The strain energy is relieved more easily when small crystals are connected to each other than when large crystals are formed. This is thought to be because

[0113] In addition, in the region where small crystals are connected to each other, the strain energy of the region is relaxed. Therefore, defects may be formed in the region. By relaxing the strain energy, the mobility of carriers can be increased.

[0114] It is also preferable to use a metal oxide with a low carrier density for the transistor. When the carrier density of the metal oxide film is reduced, the impurity concentration in the metal oxide film is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides , the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. stomach.

[0115] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low density of defect states. Therefore, the trap level density may also be low.

[0116] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. be.

[0117] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be kept low. In order to reduce the impurity concentration in the metal oxide, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0118] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0119] When metal oxides contain silicon or carbon, which are elements of Group 14, they become metal oxides. Defect levels are formed in the oxides. This leads to the formation of silicon and carbon concentrations in the metal oxides. The concentration of silicon and carbon near the interface with the metal oxide was measured by secondary ion mass spectrometry (SIM). S: Secondary Ion Mass Spectrometry) concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0120] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor that uses a metal oxide containing metals in the channel formation region is normally on. Therefore, the concentration of alkali metals or alkaline earth metals in metal oxides It is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm 3 Below, I prefer Or 2 x 10 16 atoms / cm 3 Do the following:

[0121] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carriers As a result, the density increases and it becomes easier to make the metal oxide containing nitrogen into a channel type. The transistors used in the metal-doped region tend to be normally-on. In the oxide, it is preferable that the nitrogen content in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in metal oxides is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following .

[0122] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, metal oxides containing hydrogen can be used The transistor tends to be normally on. Therefore, hydrogen in the metal oxide is not formed. Specifically, in the case of metal oxides, the The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than.

[0123] Use of metal oxide with sufficiently reduced impurities in the channel formation region of a transistor Therefore, the off-state current of the transistor can be reduced and stable electrical characteristics can be provided.

[0124] (Method for fabricating a memory cell array) Next, one embodiment of a method for manufacturing a memory cell array of the present invention will be described with reference to FIGS. In each of Figures 4 to 13, (A) is a top view seen from the z-axis direction. , (B) is a cross-sectional view of the area indicated by the dashed line A1-A2 in (A). 12(D) and 12(E) are cross-sectional views of the area indicated by the dashed line A3-A4 in FIG. 12(B) and 13(D) are the areas surrounded by dashed lines in FIG. 12(B) and FIG. 13(B), respectively. FIG. 10 is an enlarged cross-sectional view of the enclosed portion.

[0125] First, a conductor 706 is formed on a substrate 720 having an insulating surface, and a metal film is formed on the substrate 720 so as to cover the conductor 706. As shown in FIG. 4, an insulating film 721 is formed.

[0126] The conductor 706 is formed by first forming a conductive film to be the conductor 706 and then forming the conductive film by lithography. However, the conductor 706 and the insulating film 7 The method for forming the insulating film 721 is not limited to this. By removing unnecessary portions of the conductive material 706, grooves and openings are formed, and the conductive material 706 is filled in the grooves and openings. Such a method for forming a conductor may be a damascene method (single damascene method). The conductor 706 formed by the damascene method is sometimes called a damascene method. By forming an insulating film on the insulating film 721, the structure shown in FIG. 4 can be obtained. can.

[0127] The conductor 706 and the insulating film 721 are formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE) E: Molecular Beam Epitaxy, Pulsed Laser Deposition (PLD) Pulsed Laser Deposition (ALD) or Atomic Laser Deposition (ALD) This can be done using a layer deposition method or the like.

[0128] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0129] The plasma CVD method can produce high-quality films at relatively low temperatures. This film formation method does not use a plasma, so it is possible to reduce plasma damage to the object being treated. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc. included in a semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. In addition, the thermal CVD method can increase the yield of semiconductor devices. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0130] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with few defects can be produced. is obtained.

[0131] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0132] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum chamber, the time required for film formation is shorter due to the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0133] In the lithography method, first, the resist is exposed to light through a photomask. The exposed areas are then removed or left behind using a developer to form a resist mask. Next, a conductive, semiconductive or insulating layer is formed by etching through the resist mask. For example, KrF excimer laser light, ArF Using excimer laser light, EUV (Extreme Ultraviolet) light, etc. The resist is exposed to light to form a resist mask. A liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the light source and the exposure is performed. Instead of the light, an electron beam or an ion beam may be used. When using a mask, the mask is not required. Dry etching processes such as etching or wet etching processes can be used. Alternatively, a wet etching process may be performed after the dry etching process, or a wet etching process may be performed after the wet etching process. After the etching process, the resist mask is removed by performing a dry etching process. This can be done.

[0134] In addition, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film that will be the hard mask material is formed on the conductive film. Then, a resist mask is formed on the hard mask, and the hard mask material is etched to form the desired A hard mask of a desired shape can be formed.

[0135] This processing can be performed by dry etching or wet etching. The etching method is suitable for microfabrication.

[0136] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0137] When a hard mask is used for etching the conductive film, the etching process is performed using the hard mask. This may be done after removing the resist mask used to form the mask, or after leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching the conductive film, the hard mask may be removed by etching. If the hard mask material does not affect the subsequent process or can be used in the subsequent process, There is no need to remove the hard mask.

[0138] The conductive film to be the conductor 706 is formed by sputtering a conductive film containing a metal element. It is also possible to form it by using a CVD method.

[0139] The surface of the insulating film 721 is preferably subjected to planarization treatment as necessary. The planarization process can be performed by chemical mechanical polishing (CMP) or reflow.

[0140] Next, a conductive film 701A and an insulating film 722A are formed on the conductor 706 and the insulating film 721. In this embodiment, a conductive film 701A is formed over the insulating film 721, and Although an example in which the insulating film 722A is formed on the film 701A is shown, the order of formation is not limited to this. An insulating film 722A is formed on the insulating film 721, and a conductive film 701A is formed on the insulating film 722A. The conductive film 701A and the insulating film 722A may be formed by using a CVD method. Alternatively, a sputtering method may be used.

[0141] In this embodiment, the conductive film 701A and the insulating film 722A are each formed into four layers. However, the number of layers is not limited to this. For example, the conductive film 701A and the insulating film 722A may be formed in five or more layers. The number of layers may be 32, 64, 128, or 200 or more.

[0142] A conductive film 702A is formed on the top layer of the insulating film 722A. The conductive film 702A is formed by the same method as that for the conductive film 701A. The conductive film 702A can be formed using the same material as the conductive film 70. It may be formed by the same method as that of the conductive film 702. A may be made of the same material as the conductive film 701A, or may be made of a different material.

[0143] Next, the conductive film 702A, the conductive film 701A, and the insulating film 722A are processed to form a film as shown in FIG. 7. The conductive film 701B, the conductive film 702B, and the insulating film 722B are formed in a stepped shape as shown in FIG. In processing the conductive film 702A, the conductive film 701A, and the insulating film 722A, 702A, the conductive film 701A, and the insulating film 722A are etched, and the mask 723 is thinned. By alternately performing the etching, the conductive film 701B, the conductive film 702B, and the insulating film 72 2B can be formed. By this processing, the mask 723 is reduced in both width and thickness to become a mask 723A (see FIG. 6). .).

[0144] Next, the mask 723A is removed, and an insulating film 724 is formed. The insulating film 724 is formed by a CVD method. The insulating film 724 can be formed by a flattening method using a CMP method or a reflow method. It is preferable that the insulating film 724 is subjected to a smoothing treatment. Next, a mask 725 is formed on the insulating film 724. By forming a mask 725 on the planarized insulating film 724, the accuracy of lithography is improved. (See Figure 7.)

[0145] Next, using a mask 725, the insulating film 724, the conductive film 702B, the conductive film 701B, and the insulating film 724 are The film 722B and the insulating film 721 are processed. A conductor 701 which functions as a gate and is electrically connected to a word line, and a gate of a select transistor The insulating film 722B is formed by the above processing. This becomes the edge body 722 (see FIG. 8).

[0146] Next, the mask 725 is removed, and the insulating film 724, the conductive film 702B, the conductive film 701B, and the insulating film 724 are removed. The insulating film 722B and the insulating film 721 are formed so as to fill in the portions removed by the above processing. The insulator 726 can be formed by using a CVD method or an ALD method. In particular, the ALD method allows for the formation of thick films even in grooves and openings with a large aspect ratio. Alternatively, the ALD method and the CVD method may be combined to form a film with a uniform thickness. The insulator 726 may be formed by combining the insulating layers 726. The insulator 726 may be formed by a CMP method or a reflow method. When the planarization process is performed using the CMP method, In this case, the insulator 726 may be polished until the surface of the insulating film 724 is exposed. The insulating film 724 and the insulator 726 may be polished together. In this case, the thickness of the insulating film 724 is reduced. do.

[0147] Next, the insulating film 724 is processed by lithography to expose the conductor 701. The first openings are formed in such a way that the conductors 701 are each formed in a stepped shape. Although not shown, an opening for exposing the conductor 702 may also be formed at the same time. Good (see Figure 9).

[0148] Next, a conductor 707 is formed so as to fill the first opening. The conductor 707 is formed by CVD. The ALD method can be used to form the film. This is preferred because it can form a film of uniform thickness even in grooves and openings with a large thickness ratio. Alternatively, the conductor 707 may be formed by combining the ALD method and the CVD method. The conductor 707 may have a laminated structure made up of multiple layers. A conductive film that will become the conductor 707 is formed on the insulating film 724 and inside the first opening, and then the conductive film is removed by CMP or the like. The conductive film can be formed by removing unnecessary conductive film using a film forming method.

[0149] Next, the insulating film 724, the conductor 702, the conductor 701, the insulator 722, and the insulating film 72 1 is processed using a lithography method to form a second opening so as to expose the conductor 706. (See Figure 10.)

[0150] Next, an insulator 703 is formed on the insulating film 724, the conductor 707, and inside the second opening. An insulating film 703A is formed (see FIG. 11). Although not shown, the insulating film 703 A is an insulating film that becomes the insulator 703a, an insulating film that becomes the insulator 703b, and an insulating film that becomes the insulator 703c. The insulating film 703A can be formed by sequentially stacking insulating films such as a CVD method or an ALD method. In particular, the ALD method allows for the formation of grooves with a large aspect ratio. This is preferable because it allows a film of uniform thickness to be formed even in holes or openings. The insulating film 703A may be formed by combining the ALD method and the CVD method. The insulating film to be the insulating film 703b, the insulating film to be the insulator 703c, and the insulating film to be the insulator 703c are the same. The insulator 7 may be formed in the same film forming apparatus or in a different film forming apparatus. The insulating film that becomes the insulator 703c is made thinner than the insulator 703a. It is preferable to form it thinner than the insulating film that will become 703a.

[0151] Next, the insulating film 703A formed on the bottom of the second opening is removed to obtain the insulator 703. It is preferable to use anisotropic etching to remove the insulating film 703A. 724 and the insulating film 703A on the conductor 707 are also removed. The insulating film 703A is formed only on the side wall of the second opening (see FIG. 12). By removing it, the conductor 706 is exposed again.

[0152] Here, as shown in FIG. 12(D), the insulator 703 located above the second opening 12(B) and the insulating layer 703b and the insulating layer 703c may be removed. First, the inside of the second opening is easily opened in a later process. A removable material 727 (also called a sacrificial layer) is formed to fill the second opening. The insulating layer 7 is then removed by etching or the like to a desired depth. By sequentially removing the conductor 702, the horizontal direction (x-y The insulator 703 located in the direction (the direction of the insulating film 703) can be only the insulator 703a. The gate insulating film of the select transistors SST and SDT is made of an insulator 703a. After removing insulator 703c and insulator 703b, material 727 is removed.

[0153] Next, an oxide 704 is formed inside the second opening. The oxide 704 is formed on the insulating film 724, The oxide 704a is formed on the conductor 707, on the insulator 703, and inside the second opening. Then, an oxide film that becomes the oxide 704b is formed in this order, and unnecessary oxide is removed by using a CMP method or the like. It can be formed by removing the pores (see FIG. 13).

[0154] FIG. 13(D) is an enlarged view of the part surrounded by the dashed line in FIG. 13(B). In FIG. 13D, the oxide 704 is divided into two oxides, an oxide 704a and an oxide 704b. As shown in FIG. 3B, the oxide 7 04 may have a three-layer stack structure of oxide 704a, oxide 704b, and oxide 704c. Alternatively, it may have a laminated structure of four or more layers.

[0155] The oxide 704 can be formed by using a CVD method, an ALD method, or a sputtering method. In particular, the ALD method allows for the formation of grooves and openings with large aspect ratios. ALD is preferable because it can form a film with a uniform thickness. The oxide 704 may be formed by a combination of methods. The oxide that becomes 704b and the oxide that becomes 704c are formed in the same film forming apparatus. Alternatively, the layers may be formed in different deposition apparatuses.

[0156] In addition, when the oxide 704 has a two-layer structure of the oxide 704a and the oxide 704b, The oxide 704 is formed inside the oxide 704b by the oxide 704a, the oxide 704b, and the oxide 704b. In the case of the three-layer laminated structure of the oxide 704c, as shown in FIG. Alternatively, an insulator 711 may be formed.

[0157] The insulator 711 is used for a memory transistor or a semiconductor device having the memory transistor. Depending on the required properties, materials that supply oxygen to the oxide 704 or materials that supply hydrogen are used. You can be there.

[0158] The oxide 704 is formed so as to be in contact with the conductor 706. 6 contacts with the conductor 706, the metal of the conductor 706 is formed at the interface between the conductor 706 and the oxide 704. A metal compound layer may be formed that contains the element and the components of the oxide 704. The formation of the oxide 704 reduces the contact resistance between the conductor 706 and the oxide 704. In addition, the conductor 706 absorbs oxygen contained in the region 728 of the oxide 704. In this case, the resistance of the oxide 704 in the vicinity of the interface between the conductor 706 and the oxide 704 may be increased. This is preferable because the resistance is reduced and the contact resistance between the conductor 706 and the oxide 704 is reduced. By performing heat treatment while the oxide 704 and the conductor 706 are in contact with each other, the oxide 704 The resistance of the conductor 706 is further reduced, and the contact resistance between the conductor 706 and the oxide 704 is further reduced. The heat treatment is carried out in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C. It is preferable to carry out the heating at a temperature of 0.degree. C. or higher and 400.degree. C. or lower.

[0159] In the subsequent steps, the conductor 705 and the like may be formed depending on the circuit configuration. In this description of the manufacturing process, the memory cell array can be manufactured. The memory array includes, but is not limited to, four layers of memory transistors and four memory strings. It may contain five or more layers of memory transistors. For example, the memory transistor may be formed in 32 layers, 64 layers, or 128 layers. It is possible to fabricate a memory cell array with more than 200 layers of memory transistors. It is possible to fabricate a memory cell array having such a memory cell.

[0160] By fabricating a memory cell array in this manner, memory transistors can be formed in each layer. Without the need for patterning to fabricate a memory transistor, multiple layers of memory transistors can be fabricated at once. Furthermore, when a memory cell array is fabricated by the above method, the memory Increasing the number of transistor layers also reduces the time required for patterning and etching memory transistors. The number of processing steps does not increase. In this way, the memory cell array manufacturing process can be shortened. Therefore, a semiconductor device with high productivity can be provided.

[0161] (3D NAND configuration example) Figure 14(A) shows the configuration of a three-dimensional NAND type nonvolatile memory device (3D NAND). 14A shows an example of a memory device 100 including a control circuit 105, a memory cell array 1 10, having peripheral circuits.

[0162] The control circuit 105 controls the entire storage device 100, and writes data, The control circuit 105 processes external command signals and controls the peripheral circuits. The peripheral circuits include a row decoder 121, a row driver 122, a sense amplifier 123, and a A filter 123, a source line driver 124, and an input / output circuit 125 are provided.

[0163] The memory cell array 110 has a plurality of memory strings 112. 1 shows an example of the circuit configuration of the memory string 112. In the memory string 112, Between the line BL and the source line SL, a selection transistor SST and memory transistors MT1 to M T2k (k is an integer equal to or greater than 1) and the select transistor SDT are electrically connected in series.

[0164] When the memory transistors MT1 to MT2k are not distinguished from one another, they are collectively referred to as It may be called a memory transistor MT. The same applies to other elements.

[0165] As described above, the select transistors SST and SDT, the memory transistors MT1 to MT 2k are transistors whose channels are made of metal oxide. The transistor MT has a charge storage layer and constitutes a nonvolatile memory cell.

[0166] The gates of the select transistors SST and SDT are connected to select gate lines SGL and DGL, respectively. The gates of the memory transistors MT1 to MT2k are electrically connected to The bit lines BL extend in the column direction and are electrically connected to the word lines WL1 to WL2k. The select gate lines SGL, DGL and word lines WL extend in the row direction.

[0167] The input / output circuit 125 temporarily stores data to be written to the memory cell array 110. and temporarily holding the data read from the memory cell array 110. .

[0168] The source line driver 124 drives the source line SL.

[0169] The bit line BL is electrically connected to a sense amplifier 123. When reading data, the voltage read from the memory string 112 to the bit line BL is When writing data, the voltage corresponding to the write data is detected and amplified. A voltage is input to the bit line BL.

[0170] The row decoder 121 decodes address data input from the outside and outputs the accessed data. The row driver 122 selects a row to be read according to the result of decoding by the row decoder 121. The voltages required for writing, reading, and erasing data are applied to the selection signal lines DGL and SGL and the word line Enter into WL.

[0171] 15 to 17 show examples of a three-dimensional stacked structure of the memory cell array 110. FIG. 16 is a schematic circuit diagram illustrating an example of a three-dimensional structure of the memory cell array 110. 17 is a cross-sectional view showing an example of a three-dimensional structure of the memory cell array 110. 15 is a cross-sectional view showing an example of the three-dimensional structure of the connection part of the conductor 701. The re-cell array 110 is stacked in the area where the sense amplifier 123 is formed. This allows the layout area of ​​the storage device 100 to be reduced. As shown in FIG. 17, even among the conductors 701 in the same row, the conductor 701a on the bit line BL side is The conductor 701b on the source line SL side is connected to the word line WLb. 15 to 17, one memory string 112 has eight memory cells. An example in which transistors MT1 to MT8 are provided is shown.

[0172] (Explanation of the circuit operation of the memory device) Next, the operation of writing and reading data to the memory string 112 will be described with reference to FIG. The following description will be made using (A) to (C). A group of memory transistors MT that share WL2k is called a page.

[0173] In FIGS. 18A to 18C, as an example, the memory string 112 is Although an example having memory transistors MT1 to MT8 is shown, the number of memory transistors MT is Not limited.

[0174] <Erase operation> When writing data to the memory transistor MT, the data is erased before the write operation. It is preferable to erase the data. The operation of erasing data is sometimes called a reset operation. The erase operation is performed by, for example, sequentially selecting the memory transistors MT from which data is to be erased. First, the word line connected to the gate of the memory transistor MT from which data is to be erased is A low potential (a potential to extract electrons stored in the charge storage layer, e.g., -18 V) is applied to the line WL. A positive potential (a potential at which a transistor is turned on) is applied to the word lines WL other than the word line WL. Also, an erase potential VE( For example, 0V) is applied to the selection transistor SDT and the selection transistor SST to make them conductive. By doing so, the data in the desired memory transistor MT can be erased. ), a low potential is applied to the word line WL1 to make the memory transistor MT1 non-conductive. A positive potential is applied to the word lines WL2 to WL8, and the memory transistors MT2 to M T8 is made conductive, and an erase potential VE is applied to the source line SL and the bit line BL. The memory transistor MT Then, the word lines WL2 to WL8 are selected in order, and the data in the word lines WL1 to WL8 are erased. A low potential is applied to the selected word line WL, and a positive potential is applied to the other word lines WL. This allows the data in the memory transistors MT1 to MT8 to be erased. By this reset operation, the charge storage of each of the memory transistors MT1 to MT8 This allows the electrons stored in the memory transistor MT1 to be extracted. The data "1" is held in the memory from MT8 to MT8. It is not necessary to erase the memory transistors MT of the You can also select only T and erase the data. For example, if data "0" is written, Alternatively, the erase operation may be performed only on the memory transistor MT that is in use.

[0175] The erase operation is not limited to the above method. In this case, data can be erased in units of memory strings 112 (also called blocks). For example, all gates of the memory transistors MT in the block from which data is to be erased can be A low potential (for example, 0 V) ​​is applied to the word line WL to be connected, and the source line SL and the bit line Apply a high voltage (for example, +18V) to BL. This operation The electrons stored in the charge storage layers of the transistors MT1 to MT8 can be simultaneously extracted. Cut.

[0176] The data in the memory transistors MT that are not rewritten is erased when the block is erased. It is preferable to store it in a separate memory area before the delete operation.

[0177] <Write operation> Next, a data write operation will be described with reference to FIG.

[0178] The data write operation can be performed for each page as described above. A write potential (for example, 15 V) is applied to the word line of the page to be written, and a write potential (for example, 15 V) is applied to the word line of the page to be written. A positive potential (a potential at which the transistor is conductive, for example, 3 V) is applied to the word line of the page. As shown in FIG. 18B, a write potential is first applied to the word line WL1. A positive potential is applied to the lines WL2 to WL8, and the select transistor SST is set to a non-conductive state. Then, a positive potential is applied to the selection transistor SDT to make it conductive. Data corresponding to the potential of the bit line BL is written to the memory transistor MT1. When the potential of the bit line BL is low (for example, 0 V), the voltage applied to the word line WL1 is The potential difference between the applied write potential and the stored write potential increases, causing the charge in the memory transistor MT1 to increase. Electrons are injected into the storage layer. Also, the potential of the select transistor SDT and the bit line BL When both are at a positive potential, the select transistor SDT is non-conductive. Since the transistor MT is electrically floating, the charge storage layer of the memory transistor MT1 In other words, when a low potential is applied to the bit line BL, electrons are not injected into the memory cell. When data "0" is written to transistor MT1 and a positive potential is applied, a memory transaction The data of transistor MT1 remains at "1".

[0179] Here, by applying a different potential to each memory string 112 to the bit line BL, Data can be written page by page.

[0180] It is also possible to write multi-level data to the memory transistor MT. The charge storage layer of the memory transistor is determined by the potential of the charge line BL and the time for which the potential is applied. The amount of injected charge may be controlled.

[0181] <Read operation> Next, the data read operation will be described with reference to FIG.

[0182] Data read operations can also be performed page by page. A positive potential (a potential at which the transistor is conductive) is applied to the word lines of the pages and pages that are not read. Here, as shown in FIG. 18(C), a voltage of 3 V is applied to the word lines WL1 to WL2. A positive potential is applied to WL8. Then, the select transistor SDT and the select transistor S ST is set to a conductive state. Also, a read potential (for example, 1 V) is applied to the bit line BL. A low potential (for example, 0 V) ​​is applied to the source line SL. If the data is "1", a current flows through the memory string 112, and the potential of the bit line BL becomes If the data in the memory transistor MT1 is "0", No current flows through the bit line BL2, and the potential of the bit line BL does not change. The potential of BL is detected and amplified. It is possible.

[0183] Here, by reading out the data of each memory string 112 to the bit line BL, the page Data can be read in units of 1.

[0184] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0185] (Embodiment 2) This embodiment mode will describe an application example of a memory device using the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can be used in various electronic devices (for example, Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video playback devices, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (for example, D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 19 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a flash memory and used in various storage devices and removable memory.

[0186] 19A is a schematic diagram of a USB memory. The USB memory 1100 is a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0187] Figure 19(B) is a schematic diagram of the external appearance of an SD card, and Figure 19(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 is a schematic diagram of the structure. The SD card 1110 comprises a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, the SD card 1110 The capacity can be increased. In addition, a wireless chip having a wireless communication function can be installed on the substrate 1113. This allows the host device and the SD card 1110 to communicate wirelessly. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0188] FIG. 19(D) is a schematic diagram of the external appearance of the SSD, and FIG. 19(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a memory The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DRAM chip may be used. A memory chip 1154 is also provided on the back side of the substrate 1153. By providing the memory chip 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0189] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0190] (Embodiment 3) In this embodiment mode, a semiconductor device according to the above embodiment mode is applied to a semiconductor device A. I will explain the system.

[0191] FIG. 20 is a block diagram showing an example of the configuration of the AI ​​system 4041. 1 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.

[0192] The calculation unit 4010 includes an analog calculation circuit 4011, a DOSRAM 4012, and a NOSR. It has AM4013, FPGA4014, and 3D-NAND4015.

[0193] Here, DOSRAM (registered trademark) is a trademark of Dynamic Oxide Semiconductor It is an abbreviation for "Inductor RAM" and is a 1T (transistor) 1C (capacitance) type memory. Refers to RAM with a resettable register.

[0194] NOSRAM (registered trademark) stands for "Nonvolatile Oxide Semiconductor It is an abbreviation for "Semiconductor RAM" and is a memory of the gain cell type (2T type, 3T type). DOSRAM and NOSRAM are RAMs that use oxide as a semiconductor. A memory device utilizing the low off-state current of an OS transistor (hereinafter referred to as an OS transistor) In the following, we will refer to memory using OS transistors such as NOSRAM. The device may be referred to as OS memory.

[0195] The control unit 4020 includes a CPU (Central Processing Unit) 40 21, GPU (Graphics Processing Unit) 4022, and P LL (Phase Locked Loop) 4023 and SRAM (Static R andom Access Memory) 4024 and PROM (Programma ble Read Only Memory) 4025 and memory controller 4026 , a power supply circuit 4027, and a PMU (Power Management Unit) 40 28 and has.

[0196] The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, and a video a codec 4033, a general-purpose input / output module 4034, and a communication module 4035; It has.

[0197] The calculation unit 4010 can perform learning or inference using a neural network. Cut.

[0198] The analog arithmetic circuit 4011 is an A / D (analog / digital) conversion circuit, a D / A (digital It has a digital / analog conversion circuit and a multiply-and-accumulate circuit.

[0199] The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog arithmetic circuit 4011 using a transistor has an analog memory and performs learning or This makes it possible to perform the multiply-and-accumulate operations required for inference with low power consumption.

[0200] The DOSRAM4012 is a DRAM formed using OS transistors. The SRAM4012 temporarily stores digital data sent from the CPU4021. The DOSRAM4012 is a memory that uses memory cells that include OS transistors and Si The memory cell and the readout circuit section are stacked. Since the DOSRAM4012 can be placed on different layers, the total circuit area can be reduced It can be made smaller.

[0201] Calculations using neural networks can involve input data sets exceeding 1,000. When storing the above input data in SRAM, the circuit area of ​​SRAM is limited and the memory capacity is Because the amount is small, the input data must be stored in small chunks. 12 allows memory cells to be highly integrated even in a limited circuit area, and SR The memory capacity is larger than that of the AM. Therefore, the DOSRAM4012 stores the above input data It can be stored efficiently.

[0202] NOSRAM4013 is a non-volatile memory that uses OS transistors. The M4013 is a memory card that can be used with flash memory and ReRAM (Resistive Random Access Memory). Access Memory), MRAM (Magnetoresistive Ran Compared to other non-volatile memories such as DDR Memory (DDR3), writing data is It consumes less power when writing data. The elements do not deteriorate when writing, and there is no limit to the number of times data can be written.

[0203] In addition to 1-bit binary data, the NOSRAM4013 can also handle multi-level data of 2 or more bits. NOSRAM4013 can store multi-value data. The memory cell area per bit can be reduced.

[0204] In addition, NOSRAM4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 converts the NOSRAM 4013 into an analog memory. The NOSRAM4013 can also be used as a memory. Therefore, D / A conversion circuits and A / D conversion circuits are not required. The RAM 4013 can reduce the area of ​​the peripheral circuits. Analog data refers to data with a resolution of 3 bits (8 values) or more. In some cases, multi-valued data is included in the analog data.

[0205] The data and parameters used in the neural network calculations are stored in NOSRA. The above data and parameters can be stored in the M4013 via the CPU4021. The data may be stored in a memory provided outside the AI ​​system 4041, but may also be stored in a memory provided inside the AI ​​system 4041. The NOSRAM4013, which is equipped with the DDR3 RAM, stores the above data and parameters at higher speeds and with lower power consumption. The NOSRAM4013 also has a higher bit rate than the DOSRAM4012. Since the bit lines can be made longer, the storage capacity can be increased.

[0206] The FPGA 4014 is an FPGA that uses OS transistors. 1 uses FPGA4014 to implement the deep neural network described below in hardware. Neural Networks (DNN), Convolutional Neural Networks (CNN), Recurrent Neural Networks (RNN) Neural Networks (RNN), Autoencoders, Deep Boltzmann Machines (DBM), Deep It is possible to configure the connections of neural networks, such as layered belief networks (DBNs). By configuring the above neural network connections in hardware, it is possible to achieve higher performance. It can be executed quickly.

[0207] The FPGA 4014 is an FPGA with OS transistors. The memory area can be made smaller than that of an FPGA that is configured with RAM. Even if a context switching function is added, the area increase is small. Sting allows data and parameters to be transmitted at high speed.

[0208] 3D-NAND4015 is a non-volatile memory that uses oxide semiconductors. The D4015 is a highly integrated memory with a large memory capacity per unit area. is.

[0209] In addition to 1-bit binary data, 3D-NAND4015 can also handle multi-value data of 2 or more bits. 3D-NAND4015 can store multi-level data. Therefore, the memory cell area per bit can be further reduced.

[0210] In addition, as the 3D-NAND 4015, for example, the semiconductor device shown in the above embodiment is used. This allows the area occupied by the memory cell to be reduced. Therefore, the 3D-NAND4015 can be further integrated. The storage capacity per unit area of ​​the ND4015 can be increased.

[0211] The AI ​​system 4041 is composed of an analog arithmetic circuit 4011, a DOSRAM 4012, and an NOS The RAM4013 and FPGA4014 can be mounted on a single die (chip). Therefore, the AI ​​system 4041 is designed to be fast and low power consumption, and to use neural networks. In addition, the analog arithmetic circuit 4011 and the DOSRAM4 The 012, NOSRAM4013, and FPGA4014 are manufactured using the same manufacturing process. Therefore, the AI ​​system 4041 can be manufactured at low cost. .

[0212] The calculation unit 4010 includes a DOSRAM 4012, a NOSRAM 4013, and an FP It is not necessary to have all of GA4014. Depending on the problem that AI system 4041 wants to solve, DOSRAM4012, NOSRAM4013, and FPGA4014. A plurality of the above may be selected and provided.

[0213] AI System 4041 uses deep neural networks to solve various problems. (DNN), Convolutional Neural Network (CNN), Recurrent Neural Network RNN, autoencoder, deep Boltzmann machine (DBM), deep belief network The PROM4025 can implement techniques such as DBN. It is possible to store a program for executing at least one program. Store some or all of the program in NOSRAM4013 or 3D-NAND4015. 3D-NAND4015 is a highly integrated memory, and the number of records per unit area is The large memory capacity allows for the storage of large programs.

[0214] Existing programs that exist as libraries are based on GPU processing. Therefore, it is preferable that the AI ​​system 4041 has a GPU 4022. The system 4041 performs the multiply-and-accumulate operation, which is the rate-limiting operation used in learning and inference. The multiplication and accumulation operations can be executed by the calculation unit 4010, and other multiplication and accumulation operations can be executed by the GPU 4022. This allows for faster learning and inference.

[0215] The power supply circuit 4027 not only generates a low power supply potential for the logic circuit but also The power supply circuit 4027 may also use an OS memory. 27 can reduce power consumption by storing the reference potential in the OS memory.

[0216] PMU4028 has the function of temporarily turning off the power supply to AI System 4041. do.

[0217] The CPU 4021 and the GPU 4022 preferably have OS memory as a register. The CPU 4021 and the GPU 4022 have OS memory, so the power supply is Even when the power is turned off, the data (logical values) can still be stored in the OS memory. As a result, the AI ​​system 4041 can save power.

[0218] The PLL 4023 has the function of generating a clock. It operates based on the clock generated by PLL4023. PLL4023 has OS memory. It is preferable that the PLL4023 has an OS memory, which allows the clock oscillation period to be adjusted. The analog potential to be controlled can be held.

[0219] The AI ​​system 4041 may store data in external memory such as DRAM. Therefore, the AI ​​System 4041 uses memory that acts as an interface with external DRAM. It is preferable that the memory controller 4026 is included. It is preferable to place it near the CPU 4021 or the GPU 4022. This allows for high-speed data exchange.

[0220] Some or all of the circuits shown in the control unit 4020 are formed on the same die as the operation unit 4010. By doing so, the AI ​​system 4041 can achieve high speed and low power consumption. Neural network calculations can be performed.

[0221] The data used for neural network calculations is stored in an external storage device (HDD). Hard Disk Drive, SSD (Solid State Drive), etc.) Therefore, the AI ​​system 4041 does not have an interface with an external storage device. It is preferable that the external memory control circuit 4031 functions as an interface.

[0222] Learning and inference using neural networks often involves audio and video, so The I system 4041 has an audio codec 4032 and a video codec 4033 . The audio codec 4032 encodes and decodes audio data. The video codec 4033 encodes and decodes the video data.

[0223] The AI ​​system 4041 performs learning or inference using data obtained from external sensors. Therefore, the AI ​​system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 is, for example, a USB (Universal Ser ial Bus) and I2C (Inter-Integrated Circuit), etc. Includes:

[0224] AI system 4041 uses data obtained via the internet to learn or Therefore, the AI ​​system 4041 can perform inference. It is preferred to have 5.

[0225] The analog arithmetic circuit 4011 uses a multi-level flash memory as an analog memory. This is also possible. However, flash memory has a limit on the number of rewritable times. Also, multi-value flash memory is very difficult to form embedded (forming the arithmetic circuit and memory on the same die).

[0226] Also, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limit on the number of rewritable times and also has problems in terms of storage accuracy. Furthermore, since it is an element with two terminals, the circuit design for separating data writing and reading becomes complicated.

[0227] Also, the analog arithmetic circuit 4011 may use MRAM as an analog memory. However, MRAM has a low resistance change rate and has problems in terms of storage accuracy.

[0228] In view of the above, it is preferable for the analog arithmetic circuit 4011 to use the OS memory as an analog memory.

[0229] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0230] (Embodiment 4) <Application Examples of AI System> In this embodiment, the application examples of the AI system shown in the above embodiment will be described using FIG. 21.

[0231] FIG. 21(A) shows an AI system 4041A in which the AI systems 4041 described in FIG. 20 are arranged in parallel and signal transmission and reception between systems are enabled via a bus line.

[0232] The AI system 4041A shown in FIG. 21(A) includes a plurality of AI systems 4041_1. ​​​​​to AI systems 4041_n (n is a natural number). The AI ​​systems 4041_n are connected to each other via a bus line 4098.

[0233] 21(B) shows the AI ​​system 4041 described in FIG. 20 in the same manner as in FIG. 21(A). AI systems are arranged in parallel, enabling signals to be sent and received between systems via a network. The stem is 4041B.

[0234] The AI ​​system 4041B shown in FIG. 21(B) is a system including a plurality of AI systems 4041_1 The AI ​​systems 4041_1 to 4041_n are 041_n are connected to each other via a network 4099.

[0235] The network 4099 is a network of the AI ​​systems 4041_1 to 4041_n. Each of them may be provided with a communication module, and configured to perform wireless or wired communication. The communication module can communicate via an antenna. For example, World Wi The Internet, intranets, and extranets that form the foundation of the World Wide Web (WWW) PAN (Personal Area Network), LAN (Local A rea Network), CAN (Campus Area Network), MA N (Metropolitan Area Network), WAN (Wide Ar Network), GAN (Global Area Network), etc. Each AI system can be connected to a computer network and communicate with each other. When carrying out this, LTE (Long Term Evolution) is used as the communication protocol or communication technology. lution), GSM (Global System for Mobile Communications) communication: registered trademark), EDGE (Enhanced Data Rate s for GSM Evolution), CDMA2000 (Code Divis ion Multiple Access 2000), W-CDMA (registered trademark), etc. communication standard, or Wi-Fi (registered trademark), Bluetooth (registered trademark), Zig Specifications standardized by IEEE such as Bee (registered trademark) can be used.

[0236] By using the configurations shown in Figures 21(A) and 21(B), analog signals obtained from external sensors etc. can be It can be processed by separate AI systems. For example, biometric information such as brain waves, pulse, Information such as blood pressure and body temperature is transmitted via a brain wave sensor, pulse wave sensor, blood pressure sensor, and temperature sensor. It is possible to acquire data from various sensors and process the analog signals with separate AI systems. Each AI system processes signals or learns, creating a single AI system. Therefore, the amount of information processing required for signal processing or learning can be reduced. As a result, recognition accuracy can be improved. The system can instantly and comprehensively grasp complex changes in biological information. It is expected that this will be possible.

[0237] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0238] (Embodiment 5) This embodiment shows an example of an IC incorporating the AI ​​system shown in the above embodiment. .

[0239] The AI ​​system shown in the above embodiment is a digital processor such as a CPU, which is made up of Si transistors. logic circuits, analog arithmetic circuits using OS transistors, 3D-NAND, OS-FPG A and OS memory such as DOSRAM and NOSRAM can be integrated on a single die. Cut.

[0240] Figure 22 shows an example of an IC incorporating an AI system. The IC7000 has leads 7001 and a circuit section 7003. For example, the IC chip is mounted on a printed circuit board 7002. These are electrically connected to each other on the printed circuit board 7002, and electronic components are mounted on them. The circuit portion 7003 has the same structure as that shown in the above embodiment mode. The circuit section 7003 is similar to the circuit section shown in the previous embodiment. As shown in the figure, it has a laminated structure, and is made up of a Si transistor layer 7031, a wiring layer 7032, an OS transistor layer 7033, and a The OS transistor layer 7033 is divided into a Si transistor layer 703 1, making it easy to miniaturize the AI ​​system IC7000. .

[0241] In Figure 22, the AI ​​system IC7000 is packaged in a QFP (Quad Flat Packaging) However, the form of the package is not limited to this.

[0242] Digital processing circuits such as CPUs and analog arithmetic circuits using OS transistors, 3D- NAND, OS-FPGA and OS memories such as DOSRAM and NOSRAM are all Formed in a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033 In other words, the elements constituting the AI ​​system can be manufactured using the same manufacturing process. Therefore, the IC shown in this embodiment mode can be formed by increasing the number of constituent elements. Even if it is added, there is no need to increase the manufacturing process, and the AI ​​system can be incorporated at low cost. can.

[0243] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0244] (Sixth embodiment) <Electronic equipment> The semiconductor device according to one embodiment of the present invention can be used in various electronic devices. 24A and 24B illustrate specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention.

[0245] The robot 2000 shown in FIG. 23(A) includes a computing device 2001, a sensor 2002, a light 2003, a lift 2004, a drive unit 2005, and a moving mechanism 2011. These robots can be used in security systems and surveillance equipment. It can be used as a visual system.

[0246] The robot 2000 further includes a communication means 2006, a speaker 2007, a microphone 2008, a display unit 2009, a light emitting unit 2010, etc.

[0247] The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 2001. The arithmetic unit 2001 uses an IC incorporating an AI system according to one embodiment of the present invention. The sensor 2002 acts as a camera that captures the surroundings of the robot 2000. The light 2003 captures the surroundings of the robot 2000 using the sensor 2002. It can be used as a light when taking a still image with the sensor 2002. Preferably, the light 2003 functions as a flashlight. 2002 is connected to the robot body via a lift 2004. The height can be adjusted by the lift 2004. The lift 2004 is telescopic. The lift 2004 is preferably a foldable type consisting of multiple booms. The robot 2000 may also include a driving unit 2005 and a Since the moving mechanism 2011 is provided, the photographing range of the sensor 2002, i.e. This is preferable as it broadens the monitoring range.

[0248] The communication means 2006 communicates the information captured by the sensor 2002 to the administrator or the person in charge of the information. The information captured by the sensor 2002 can be transmitted to a server that performs calculations. If the device 2001 analyzes the data and determines that it is an emergency such as a crime, accident, or fire, the security committee You can contact the company, police, fire department, medical institution, land or building owner. Speaker 2 007 will be using robots to warn criminals, question injured or suddenly ill people, and guide them to safety. The microphone 2008 can transmit information to the surroundings of the robot 2000. The communication means 2006 and the speaker 2007 can be used to acquire the voice. When used in combination with the above, the robot 2000 can function as a telephone. People around the robot 2000 can converse with the administrator or any other person. 009 can display any information you like. In case of an emergency, disaster information and evacuation routes can be displayed. In addition, the communication means 2006, the speaker 2007, and the microphone When used in conjunction with Phone 2008, Robot 2000 functions as a videophone. The people around the robot 2000 can communicate with the administrator or any other person on the display unit 2000. You can have a conversation while looking at 9.

[0249] The light emitting unit 2010 can indicate the direction of travel and the stopped state of the robot 2000 with letters and light. It is also possible to indicate an emergency situation with letters or lights.

[0250] 23(B) is a block diagram showing the configuration of the robot 2000. Based on information such as images obtained by the sensor 2002, the system determines whether the light 2003 is turned on or off, The brightness can be adjusted. Also, the height of the lift 2004 or the drive unit 2005 can be adjusted. It controls the robot 2000 and the sensor 2002 and aligns them. The operating status of the communication means 200 can be displayed using the light emitting unit 2010. 6, the robot 2000's information obtained from the sensor 2002 and the microphone 2008 is It can send information about the surroundings to the administrator or a server owned by the administrator. The computer 2001, or at the discretion of the administrator, may use the speaker 2007 or the display unit 2009. The robot 2000 can transmit information to the surrounding area.

[0251] As the sensor used for the sensor 2002, a sensor capable of taking pictures even in dark surroundings may be used. In this case, the light 2003 may not be provided. An image sensor using Se can be used.

[0252] Such a robot 2000 can be used to guard commercial facilities and offices. The information obtained from the sensor 2002 and the microphone 2008 is transmitted to the computing device 2001 and the server. The stored information is analyzed by an AI system to detect lost or damaged items, It determines whether there are any abnormalities such as the intrusion of suspicious individuals or disasters such as fires. If it is determined that an abnormality has occurred, the robot 2000 Contact the person in question and send information to those around them, and record the situation in the surrounding area.

[0253] The robot 2000 may also be used to monitor the growth status of agricultural crops. The placed robot 2000 detects the shape and size of the leaves or fruit of the crops using a sensor 2002. It monitors the size and color of the plants to determine whether they are diseased or infested with pests. Robot 2 000 is equipped with a mobile mechanism 2011, allowing it to monitor the growth of crops over a wide area. In addition, the robot 2000 is provided with a lift 2004. It is possible to monitor leaves and fruits at any height, regardless of the type of crop or growth status. The results of the observation are sent to the producers using the communication means 2006, and the producers then purchase the necessary fertilizers and other necessary ingredients for their crops. The type, amount, and spraying time of pesticides can be determined. The monitoring results are analyzed by an AI system to determine the type, amount, and application of fertilizer and pesticides required for the crops. The system can determine the timing and notify producers. Deep learning is used to analyze the monitoring results. It may be used.

[0254] FIG. 24(A) shows a sorting system 3000 using a robot 3001. The robot 3001 includes a computing device 3002, a boom 3003, and an arm 3004. The robot 3001 may also be equipped with wired or wireless communication means 3011. Sorting system 3000 also includes a housing 3008 having a sensor 3009 . The housing 3008 includes a communication means 3010. The housing 3008 is a 00, or on the ceiling, wall, or beams (none of which are shown) of the sorting work area. The housing 3008 may be provided on the robot 3001. For example, the boom 3003 Alternatively, the housing 3008 may be provided on the arm 3004. If the sensor 3009 is connected to the communication means 3010, the information obtained by the sensor 3009 is transmitted to the communication means 3010, and The data may be sent to the arithmetic device 3002 and processed therein without going through the communication means 3011.

[0255] The boom 3003 is movable, and the arm 3004 can be positioned at a desired position. The arm 3004 may be extendable. The arm 3004 is extended, the desired object 3007 is grasped, and the arm 3004 is retracted. 003 may move the arm 3004.

[0256] Sorting system 3000 moves item 3007 in container 3005 to container 3006. The container 3005 and the container 3006 may have the same shape or different shapes. In addition, multiple items 3007 placed in one container 3005 can be stored in multiple containers 3006. You can also move them by dividing them into

[0257] The containers 3005 and 3006 include containers, cardboard boxes, and boxes for packing products. , cases, films, bags, food storage trays, lunch boxes, etc. At least one of the containers 3005 and 3006 is a cooking utensil such as a pot or a frying pan. That's fine too.

[0258] The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 3002. The arithmetic device 3002 uses an IC incorporating an AI system according to one embodiment of the present invention. It is possible.

[0259] The sensor 3009 detects the position of the container 3005, the position of the container 3006, the inside of the container 3005, and and the state of the article 3007 in the container 3005 is read, and the state of the article 3007 in the container 3005 is read by the communication means 3010. The information is transmitted to the communication means 3002. The information is transmitted wirelessly or by wire. The information may be transmitted by wire without using the arithmetic unit 3002. Here, the state of the items 3007 is determined by the shape, number, overlapping of the items 3007, etc. The computing device 3002 analyzes the information from the sensor 3009, Derive detailed information of the item 3007. Communicate with the computing device 3002 or the robot 3001. The three-dimensional shape and hardness (softness) of the object 3007 are compared with the data stored on the server. Also, the arm 30 calculates the three-dimensional shape and hardness (softness) of the object 3007. The shape of 04 can be changed.

[0260] To derive detailed information about item 3007, analysis using an AI system can be used. Yes, deep learning can be used to analyze the information.

[0261] In FIG. 24(B), a pair of plates 3021 move horizontally and can sandwich an article 3007. The pair of plates 3021 move horizontally toward the center, allowing the item to be picked up. Such an arm can grasp the object 3007 by its surface. It is suitable for grasping a columnar object 3007 such as a cube or rectangular parallelepiped. (C) is an aerial photograph in which multiple bars 3022 move horizontally and can clamp an article 3007. The bars 3022 move horizontally toward the center, and the article 30 Such an arm can grasp the article 3007 at a point. The object 3007 has a spherical shape, or the object 3007 has an irregular shape, i.e., an irregular shape. It is suitable for grasping a regular object 3007. In FIG. 24(C), the number of bars 3022 is Although four bars are used, this embodiment is not limited to this. The number of bars 3022 may be three, or five or more. In FIG. 24(D), a pair of plates 3023 approach each other around a common axis. By rotating in this manner, the arm can pinch the article 3007. can capture the object 3007 on its surface, and can capture thin-film-like objects such as paper and film. 24(E) shows a pair of hook-shaped plates 3024 that are suitable for gripping a common By rotating around the axis so that the tips of the two come closer together, the item 3007 can be clamped. Such an arm can capture the item 3007 as a point or a line. , paper, film, etc., having a thin film shape 3007, or having a smaller granular shape It is suitable for grasping an article 3007. Also, as shown in FIG. 24(F), the tip of the arm has A spatula 3025 may be attached to scoop up items 3007 having a smaller granular shape.

[0262] The arms shown in Figures 24(A) to 24(F) are examples, and one aspect of the present invention is to The description of the uses of each arm is also an example, and one aspect of the present invention is not limited to these. This is not limited to the description.

[0263] The robot 3001 moves the boom 3003 based on a signal from the computing device 3002. The arm 3004 is moved onto the desired item 3007 in the container 3005. In the case of the arm 3004, the arm 3004 is extended and the tip of the arm 3004 is placed at the height of the article 3007. The tip of the arm is moved to grab the desired item 3007. The boom 3003 is moved again, and the arm 3004 is moved toward the container 300. At this time, the angle of the article 3007 relative to the container 3006 is adjusted. The arm 3004 may be rotated to accommodate the item 3007. The object 3007 is placed in the container 3006, and the arm 3004 releases the object 3007. The above operations are repeated. The robot 3001 moves the item 3007 from the container 3005 to the container 3006. This can be done.

[0264] The location information of the container 3005 and the container 3006, and the status of the item 3007 are sent to the AI ​​system. Since the analysis is performed using a system, the analysis can be performed reliably regardless of the shape or hardness of the object 3007. 7 can be moved. Examples of the object 3007 include a cube, a rectangular box, or or items packed in boxes or cases of any shape, as well as eggs, hamburgers, croquettes, etc. processed foods, irregular vegetables such as potatoes and tomatoes, screws and nails, etc. Examples of the materials include machine parts such as a mouse, thin films such as paper, and films. The sorting system 3000 changes the shape of the arm in consideration of the shape and hardness of the article 3007. Therefore, the above-mentioned example article 3007 can be stored in the container 3005 regardless of its shape or hardness. can be transferred from the container 3006.

[0265] For example, a memory device using the semiconductor device of one embodiment of the present invention can be used for the control information of the above-described electronic devices. The semiconductor device according to one aspect of the present invention can store information, control programs, and the like for a long period of time. By using the device, highly reliable electronic equipment can be realized.

[0266] In addition, for example, the AI ​​system is incorporated into the arithmetic unit of the electronic device. Therefore, the electronic device described in this embodiment can be implemented as an AI system. This allows for appropriate operation according to the situation to be performed with low power consumption.

[0267] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible. [Explanation of symbols]

[0268] 100: memory device, 105: control circuit, 110: memory cell array, 112: memory store ring, 121: row decoder, 122: row driver, 123: sense amplifier, 124: data line driver, 125: input / output circuit, 700: memory cell array, 700A: memory cell 701: conductor, 701_m: conductor, 701_1: conductor, 701_6: conductor Electric body, 701a: Conductor, 701A: Conductive film, 701b: Conductor, 701B: Conductive film, 7 02: conductor, 702A: conductive film, 702b: insulator, 702B: conductive film, 703: insulation body, 703_1: insulator, 703_4: insulator, 703a: insulator, 703A: insulating film, 703b: insulator, 703c: insulator, 704: oxide, 704_1: oxide, 704_ 4: oxide, 704a: oxide, 704b: oxide, 704c: oxide, 705: conductor , 705_1: conductor, 705_4: conductor, 706: conductor, 706_1: conductor, 7 06_4: Conductor, 707: Conductor, 707_m: Conductor, 707_1: Conductor, 708 : conductor, 708_m: conductor, 708_1: conductor, 710: memory transistor, 7 11: insulator, 720: substrate, 721: insulating film, 722: insulator, 722A: insulating film, 7 22B: insulating film, 723: mask, 723A: mask, 724: insulating film, 725: mask ,726: Insulator, 727: Material, 728: Area, 1100: USB memory, 1101: Housing, 1102: Cap, 1103: USB connector, 1104: Board, 1105: Memory chip, 1106: Controller chip, 1110: SD card, 1111: Housing, 1112: Connector, 1113: Board, 1114: Memory chip, 1115: Controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: board, 1154: Memory chip, 1155: Memory chip, 1156: Controller chip, 2 000: CDMA, 2000: Robot, 2001: Computing device, 2002: Sensor, 20 03: Light, 2004: Lift, 2005: Drive unit, 2006: Communication means, 2007: Speaker, 2008: Microphone, 2009: Display, 2010: Light-emitting part, 2011 :Moving mechanism, 3000:System, 3001:Robot, 3002:Calculating device, 3003 : boom, 3004: arm, 3005: container, 3006: container, 3007: article, 30 08: Housing, 3009: Sensor, 3010: Communication means, 3011: Communication means, 3021: Plate, 3022: bar, 3023: plate, 3024: plate, 3025: spatula, 4010: calculation unit ,4011: Analog arithmetic circuit, 4012: DOSRAM, 4013: NOSRAM, 4 014: FPGA, 4015: 3D-NAND, 4020: control unit, 4021: CPU, 4022: GPU, 4023: PLL, 4024: SRAM, 4025: PROM, 40 26: Memory controller, 4027: Power supply circuit, 4028: PMU, 4030: Input / output 4031: external memory control circuit; 4032: audio codec; 4033: video codec 4034: General-purpose input / output module, 4035: Communication module, 4041: AI system system, 4041_n: AI system, 4041_1: AI system, 4041A: AI system Stem, 4041B: AI system, 4098: Bus line, 4099: Network, 70 00: AI system IC, 7001: Lead, 7002: Printed circuit board, 7003: Circuit part, 7004: mounting substrate, 7031: Si transistor layer, 7032: wiring layer, 7033 :OS transistor layer

Claims

[Claim 1] A semiconductor device having a memory transistor, The memory transistor is a conductor having an opening; a first insulator provided in contact with an inner side surface of the opening; a second insulator provided in contact with the inner surface of the first insulator; a third insulator provided in contact with the inner surface of the second insulator; a first oxide provided in contact with the inner surface of the third insulator; a second oxide provided on the inner surface of the first oxide in contact therewith; a third oxide provided on the inner surface of the second oxide in contact therewith; and the energy gap of the second oxide is narrower than the energy gap of the first oxide; the energy gap of the second oxide is narrower than the energy gap of the third oxide; the first oxide and the second oxide contain In, an element M (M is Al, Ga, Y, or Sn), and Zn; an atomic ratio of the element M to In in the first oxide is greater than an atomic ratio of the element M to In in the second oxide; A plurality of the memory transistors are provided on a substrate, the plurality of memory transistors are stacked in a direction perpendicular to one surface of the base, the first insulator is an oxide containing any one of silicon, aluminum, and hafnium; the third insulator is an oxide containing any one of silicon, aluminum, and hafnium; the memory transistor has a fourth insulator; The fourth insulator is provided in contact with the inner surface of the third oxide.

Images