Semiconductor device

Abstract

To provide a signal processing circuit capable of suppressing power consumption.SOLUTION: In a period during which the storage element is not supplied with the power supply voltage, data stored in the first storage circuit corresponding to a volatile memory is held in the first capacitor provided in the second storage circuit. With the use of a transistor whose channel is formed in an oxide semiconductor layer, a signal is held in the first capacitor for a long time. The storage element can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped. In addition, the signal held in the first capacitor is converted into the one corresponding to the state (the on state or the off state) of the second transistor to be read from the second memory circuit; thus, the original signal can be accurately read.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] A nonvolatile memory device whose stored logic state is not lost even when the power is turned off, and a memory device using the same The present invention also relates to a signal processing circuit and a method for driving the memory device and the signal processing circuit. The present invention also relates to an electronic device using the signal processing circuit. [Background technology]

[0002] Central Processing Unit (CPU), etc. The signal processing circuit has a wide variety of configurations depending on the application, but generally, In addition to the main memory for storing programs, there are registers, cache memory, etc. Various memory devices are provided. Registers are used to store the execution status of calculations and programs. Cache memory is used to temporarily store data for the following reasons: It is placed between the arithmetic circuit and main memory, and reduces access to the slow main memory to speed up the calculation. It is provided for the purpose of speeding up processing.

[0003] Storage devices such as registers and cache memory write data faster than main memory. Therefore, flip-flops are usually used as registers, and caches are used as SRAM (Static Random Access Memory) In other words, the supply of power supply potential to these registers, cache memories, etc. Volatile storage devices are used, which lose data if the power supply is interrupted.

[0004] In order to reduce power consumption, the power to the signal processing circuit is reduced during periods when no data is being input or output. A method has been proposed in which the supply voltage is temporarily stopped. A nonvolatile storage device is arranged around a volatile storage device such as a cache memory, and the nonvolatile storage device is The data is temporarily stored in the nonvolatile storage device. Even while the supply of power supply potential is stopped, registers, cache memories, etc. retain data (e.g. For example, see Patent Document 1.

[0005] In addition, when the supply of power supply voltage to the signal processing circuit is stopped for a long period of time, Before stopping the supply, transfer the data in the volatile storage device to an external device such as a hard disk or flash memory. By transferring the data to an external storage device, data loss can be prevented. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 10-078836 Summary of the Invention [Problem to be solved by the invention]

[0007] While the supply of power supply voltage to the signal processing circuit is stopped, In the method of storing data of a volatile storage device in a nonvolatile storage device, Since magnetic elements and ferroelectrics are mainly used as the memory devices for the electric field, the construction of the signal processing circuit is difficult. The manufacturing process is complicated.

[0008] In addition, while the supply of power voltage to the signal processing circuit is stopped, volatile data is stored in the external storage device. In the method of storing data in a storage device, data is returned from an external storage device to a volatile storage device. Therefore, backing up data using an external storage device consumes a lot of power. It is not suitable for short-term power outages aimed at reducing power consumption.

[0009] In view of the above-mentioned problems, the present invention is directed to a method for manufacturing a semiconductor device that does not require a complicated manufacturing process and can reduce power consumption. One of the objects of the present invention is to provide a signal processing circuit that can achieve high speed and a method for driving the signal processing circuit. A signal processing circuit capable of reducing power consumption by stopping the power supply for a certain period of time, One of the objects is to provide a driving method. [Means for solving the problem]

[0010] (One aspect of the configuration of the memory element) One embodiment of the configuration of the memory element of the present invention is as follows.

[0011] (Memory element configuration 1) A first memory circuit, a second memory circuit, a first switch, a second switch, and a third and a switch, and the first memory circuit stores data only while a power supply voltage is being supplied. The second memory circuit includes a first capacitor, a first transistor, and a second transistor. and a memory element having the following configuration.

[0012] The first transistor is a transistor in which a channel is formed in an oxide semiconductor layer. Here, as the first transistor in which the channel is formed in the oxide semiconductor layer, An enhancement type (normally off type) n-channel transistor with extremely low off-state current. When the supply of power supply voltage to the memory element is stopped, the first transistor The gate of the first transistor is configured to be continuously supplied with a ground potential (0V). The gate of the first transistor is grounded via a load such as a resistor. One of the source and drain of the first capacitor element is connected to one of the pair of electrodes of the second capacitor element. The first transistor is electrically connected to the gate of the second transistor. One is electrically connected to the first power supply line, and the other is electrically connected to the first terminal of the first switch. The second terminal of the first switch is electrically connected to the first terminal of the second switch. The second terminal of the second switch is electrically connected to the second power supply line.

[0013] A first control signal is input to the gate of the first transistor. The second switch is configured to connect the first terminal and the second terminal by a second control signal different from the first control signal. The conduction or non-conduction state between the first and second terminals of one switch is selected. When the terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. The third switch outputs a third control signal different from the first control signal and the second control signal. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by the signal.

[0014] The other of the source and drain of the first transistor is connected to a data held in the first memory circuit. a signal corresponding to the input of the first switch and a signal output from the second terminal of the first switch; The inverted signal is transmitted through the third switch, which has a conductive state between the first and second terminals. The signal is input to the first memory circuit.

[0015] Another aspect of the configuration of the memory element of the present invention is as follows.

[0016] (Memory element configuration 2) A first memory circuit, a second memory circuit, a first switch, a second switch, and a third A switch and a logic element that inverts the phase of the input signal and outputs it (hereafter referred to as a phase inversion element) The first memory circuit stores data only while the power supply voltage is being supplied. The second memory circuit includes a first capacitor, a first transistor, and a second transistor. and a memory element having the following configuration.

[0017] The first transistor is a transistor in which a channel is formed in an oxide semiconductor layer. Here, as the first transistor in which the channel is formed in the oxide semiconductor layer, An enhancement type (normally off type) n-channel transistor with extremely low off-state current. When the supply of power supply voltage to the memory element is stopped, the first transistor The gate of the first transistor is configured to be continuously supplied with a ground potential (0V). The gate of the first transistor is grounded via a load such as a resistor. One of the source and drain of the first capacitor element is connected to one of the pair of electrodes of the second capacitor element. The first transistor is electrically connected to the gate of the second transistor. One is electrically connected to the first power supply line, and the other is electrically connected to the first terminal of the first switch. The second terminal of the first switch is electrically connected to the first terminal of the second switch. The second terminal of the second switch is electrically connected to the second power supply line. The second terminal of the first switch, the first terminal of the second switch, and the input terminal of the phase inversion element are are electrically connected.

[0018] A first control signal is input to the gate of the first transistor. The second switch is configured to connect the first terminal and the second terminal by a second control signal different from the first control signal. The conduction or non-conduction state between the first and second terminals of one switch is selected. When the terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. The third switch outputs a third control signal different from the first control signal and the second control signal. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by the signal.

[0019] The other of the source and drain of the first transistor is connected to a data held in the first memory circuit. A signal corresponding to the input is input, and the signal output from the phase inversion element, or its inverted signal, is , the first memory circuit via the third switch in which the first terminal and the second terminal are in a conductive state. is entered into

[0020] In the above (Configuration 2 of the storage element), the phase inversion element receives the voltage input to the first power line. A voltage corresponding to the potential difference between the potential of the first power supply line and the potential input to the second power supply line is supplied as a power supply voltage. It may be done.

[0021] In the above (Configuration 2 of the storage element), the storage element further includes a second capacitance element, and One of the pair of electrodes of the second capacitance element is electrically connected to the input terminal of the capacitance element. The other of the pair of electrodes of the second capacitor may be configured to receive a constant potential. For example, a low power supply potential or a high power supply potential may be input. The other of the pair of electrodes of the second capacitor is electrically connected to the first power supply line. It may also be used.

[0022] In the above (Configuration 1 of the storage element) or (Configuration 2 of the storage element), the first switch is The second switch is configured using a transistor of one conductivity type, and the second switch is configured using a transistor of a conductivity type different from the first conductivity type. In this specification, the term "switch" refers to a transistor of the type When a transistor is used as the switch, the first terminal of the switch is connected to the source and drain of the transistor. The second terminal of the switch corresponds to the other of the source and drain of the transistor. The switch operates by controlling the first terminal and the second terminal (i.e., the on or off state of the transistor). ) shall be selected.

[0023] In the above (Configuration 1 of the memory element) or (Configuration 2 of the memory element), the third switch is The transistor can be an n-channel transistor. It may be a p-channel transistor or an n-channel transistor. A combination of a p-channel transistor and a n-channel transistor may be used. The switch may be an analog switch.

[0024] In the above (Configuration 1 of the storage element) or (Configuration 2 of the storage element), one of the first capacitance elements The other electrode of the pair may be configured to have a constant potential input thereto. A power supply potential or a high power supply potential can be input to the first pair of capacitors. The other of the electrodes may be electrically connected to the first power supply line.

[0025] In the above (Configuration 1 of the memory element) or (Configuration 2 of the memory element), the first memory circuit This corresponds to the potential difference between the potential input to the first power supply line and the potential input to the second power supply line. The voltage may be supplied as a power supply voltage. During the period when the potential difference between the potential input to the first power supply line and the potential input to the second power supply line is can be (virtually) eliminated.

[0026] In the above (Configuration 1 of the memory element) or (Configuration 2 of the memory element), the first transistor The transistor may have two gates, one above the other and one below the oxide semiconductor layer, sandwiching the oxide semiconductor layer. A first control signal is input to one gate, and a fourth control signal is input to the other gate. The fourth control signal may be a signal of a constant potential. The potential may be applied to the first power supply line or the second power supply line. The gates may be electrically connected to each other and a first control signal may be input to the gate. Therefore, it is possible to control the threshold voltage of the first transistor. It is also possible to further reduce the off-state current of the transistor.

[0027] In the above (Configuration 1 of memory element) or (Configuration 2 of memory element), Among the transistors, the transistors other than the first transistor are made of a material other than an oxide semiconductor. The transistor may have a channel formed in a semiconductor layer or substrate. For example, the transistor may have a channel formed in a silicon layer or silicon substrate. In addition, all the transistors used in the memory element have channels in an oxide semiconductor layer. Alternatively, a transistor used in a memory element may be formed. The first transistor and the second transistor each have a channel formed in an oxide semiconductor layer. The remaining transistors are made of a layer or a semiconductor other than an oxide semiconductor. It may also be a transistor in which the channel is formed in the substrate.

[0028] In the above (Configuration 1 of the memory element) or (Configuration 2 of the memory element), the first memory circuit is A first phase inversion element and a second phase inversion element are included, and the input terminal of the first phase inversion element is The input terminal of the second phase inversion element is electrically connected to the output terminal of the first phase inversion element. The first phase may be electrically connected to the output terminal of the phase inversion element. The inverting element and the second phase inverting element are connected to the input terminal only during the period when the power supply potential is supplied. The phase inversion element may be an inverter or a clock. A clocked inverter or the like can be used. However, the first memory circuit is not limited to this. Volatile memories such as known latch circuits and flip-flop circuits can be freely used. Cut.

[0029] (Method of driving memory element) In the memory element, power consumption during data retention after supply of power supply voltage is reduced. The driving method when supplying power supply voltage again is as follows: It can be done like this.

[0030] (normal operation) While the power supply voltage is being supplied to the memory element, the first memory circuit holds data. At this time, the third control signal causes a non-conductive state between the first terminal and the second terminal of the third switch. In addition, between the first terminal and the second terminal of the first switch and the second switch, The state (conducting state, non-conducting state) can be either state. That is, the second control signal is The potential may be either a high level potential or a low level potential. The state (ON state, OFF state) can be either state. It may be either a high level potential or a low level potential.

[0031] (Operation before power supply is stopped) Before the supply of the power supply voltage to the storage element is stopped, the first control signal is used to turn off the first transistor. In this way, a signal corresponding to the data held in the first memory circuit is A signal is input to the gate of the second transistor via the first transistor. The signal input to the gate of the transistor is held by the first capacitance element. The first transistor is turned off. In this way, the data stored in the first memory circuit is The corresponding signal is stored in the second memory circuit. At this time, the third control signal is used to store the third The first terminal and the second terminal of the switch are in a non-conductive state. The state (conducting state, non-conducting state) between the first terminal and the second terminal of the second switch is either It may be in the state of

[0032] (Power supply voltage supply stop operation) After the above operation, the supply of the power supply voltage to the memory element is stopped. Even after the power supply is stopped, the data held in the first memory circuit is retained by the first capacitor. A signal corresponding to the first transistor is held. An enhancement type (normally off type) n-channel transistor with extremely low When the supply of power supply voltage to the memory element is stopped, the gate of the first transistor is turned off. Since the ground potential (0V) is continuously input to the Even after the power supply is stopped, the first transistor can be kept in an off state, and the first capacitor element Therefore, the stored potential can be maintained for a long period of time. data even after the system is stopped.

[0033] (Power supply restart operation) After the supply of the power supply voltage to the storage element is resumed, the second switch is turned on by the second control signal. and a first terminal and a second terminal of the first switch are electrically connected to each other. In this case, the first transistor remains in an off state. , the first terminal and the second terminal of the third switch are in a non-conductive state. When a power supply voltage is supplied to the second terminal of the switch and the first terminal of the second switch, Therefore, the potential given to the power supply line of the first switch is input to the second terminal of the first switch. The potential of the first terminal of the second switch is set to the potential of the second power supply line (hereinafter referred to as the precharge operation). This can be called a "work."

[0034] After the precharge operation, the first terminal of the first switch and the second terminal of the first switch are connected to each other by the second control signal. The second terminals are brought into a conductive state, and the first and second terminals of the second switch are brought into a non-conductive state. At this time, the first transistor remains in an off state. There is no conduction between the first terminal and the second terminal of the capacitor. In response to the received signal, the potential of the second terminal of the first switch and the potential of the first terminal of the second switch are changed. The potential is determined as the potential given to the first power supply line when the power supply voltage is supplied, or , which is the potential given to the second power supply line when the power supply voltage is supplied.

[0035] Then, a third control signal is applied to conduct current between the first terminal and the second terminal of the third switch. By turning on the second terminal of the first switch and the first terminal of the second switch, A signal corresponding to the potential of the element or an inverted signal thereof can be input to the first memory circuit. In this way, the first memory circuit stores the data that was held before the supply of the power supply voltage to the memory element was stopped. The data can be retained again.

[0036] This completes the description of the method for driving the memory element.

[0037] (Signal processing circuit) One aspect of the storage device of the present invention is a storage device configured using one or more of the above storage elements. Furthermore, one embodiment of a signal processing circuit of the present invention is a signal processing circuit using the memory device. For example, the registers and cache memory included in the signal processing circuit may be used. The memory element is used in a memory or other storage device.

[0038] Furthermore, the signal processing circuit includes, in addition to the storage device, an operation circuit for exchanging data with the storage device. The memory device may have various logic circuits such as a logic circuit. At the same time, the supply of power supply voltage to the arithmetic circuit that exchanges data with the storage device is stopped. You can do it like this.

[0039] The storage device includes a switching element that controls the supply of a power supply voltage to the storage element. In addition, when the supply of the power supply voltage to the arithmetic circuit is stopped, the arithmetic circuit The power supply circuit may include a switching element for controlling the supply of the power supply voltage. [Effects of the Invention]

[0040] While the power supply voltage is not supplied to the memory element, the first memory circuit, which corresponds to a volatile memory, The stored data is held by a first capacitor provided in the second memory circuit. It is possible.

[0041] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer increases depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the first transistor, The signal held in the first capacitance element is maintained for a long period of time even when the power supply voltage is not supplied. In this way, the memory element can retain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to do this.

[0042] In the second memory circuit, the signal held by the first capacitor is transferred to the second transistor. Therefore, after the supply of power supply voltage to the memory element is resumed, The signal held by the first capacitance element is transferred to the second transistor in the ON state or The first memory circuit can be read out by converting the first memory circuit to a high-state or an off-state. Even if the potential corresponding to the signal held in the capacitance element fluctuates slightly, the original signal can be read accurately. It is possible to issue it.

[0043] Such a memory element is referred to as a memory element such as a register or cache memory in a signal processing circuit. By using this in equipment, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped is restored in a short time. Therefore, the entire signal processing circuit or one or more components constituting the signal processing circuit can be In a number of logic circuits, power can be stopped even for a short time, reducing power consumption. and a driving method for the signal processing circuit capable of suppressing power consumption. It can provide a law. [Brief explanation of the drawings]

[0044] [Figure 1] Circuit diagram of a memory element. [Figure 2] 4 is a timing chart showing the operation of a storage element. [Figure 3] FIG. 1 is a diagram showing the configuration of a storage device. [Figure 4] FIG. 1 is a block diagram of a signal processing circuit. [Figure 5] Block diagram of a CPU using a storage device. [Figure 6] 1A to 1C illustrate a manufacturing process of a memory element. [Figure 7] 1A to 1C illustrate a manufacturing process of a memory element. [Figure 8] 1A to 1C illustrate a manufacturing process of a memory element. [Figure 9] FIG. 1 is a cross-sectional view showing a configuration of a memory element. [Figure 10] 1 is a cross-sectional view illustrating a structure of a transistor in which a channel is formed in an oxide semiconductor layer. [Figure 11] FIG. 1 is a cross-sectional view showing a configuration of a storage device. [Figure 12] FIG. 1 is a cross-sectional view showing a configuration of a storage device. [Figure 13] Block diagram of a portable electronic device. [Figure 14] FIG. 1 is a block diagram of a memory circuit. [Figure 15] Block diagram of an e-book. [Figure 16] 1A and 1B are diagrams illustrating the structure of an oxide material. [Figure 17] 1A and 1B are diagrams illustrating the structure of an oxide material. [Figure 18] 1A and 1B are diagrams illustrating the structure of an oxide material. [Figure 19] FIG. 10 is a graph illustrating the gate voltage dependence of mobility obtained by calculation. [Figure 20] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 21] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 22] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 23] 1A and 1B are diagrams illustrating cross-sectional structures of transistors used in calculations. [Figure 24] 10 is a graph showing characteristics of a transistor including an oxide semiconductor film. [Figure 25] FIG. 10 shows Vg-Id characteristics of the transistor of Sample 1 after a BT test. [Figure 26] FIG. 10 shows Vg-Id characteristics of the transistor of Sample 2 after a BT test. [Figure 27] FIG. 1 shows XRD spectra of sample A and sample B. [Figure 28] FIG. 10 is a graph showing the relationship between the off-state current of a transistor and the substrate temperature during measurement. [Figure 29] FIG. 1 shows the Vg dependence of Id and field-effect mobility. [Figure 30] FIG. 10 is a graph showing the relationship between threshold voltage and field-effect mobility and substrate temperature. [Figure 31] FIG. 1 illustrates the structure of a transistor. [Figure 32] FIG. 1 illustrates the structure of a transistor. DETAILED DESCRIPTION OF THE INVENTION

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and methods thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0046] The functions of "source" and "drain" may differ depending on the type of transistor used. Or, when the direction of the current changes during circuit operation, the positions may be reversed. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably. It shall be possible.

[0047] "Electrically connected" means that the device is connected via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" means an electrical There are no particular restrictions as long as it is possible to send and receive signals. For example, "some kind of electrical action" "Things having" include electrodes and wiring, as well as switching elements such as transistors and resistors. This includes elements, inductors, capacitors, and other elements with various functions.

[0048] A circuit diagram shows separate components as electrically connected to each other. Even in this case, in reality, for example, when a part of the wiring also functions as an electrode, In some cases, the electrically conductive film may have the functions of multiple components. Connection means that even when one conductive film has the functions of multiple components, Include it in that category.

[0049] The terms "above" and "below" indicate the relative positions of the components "directly above" and "directly below." For example, the expression "gate electrode on a gate insulating layer" means However, this does not exclude the inclusion of other components between the insulating layer and the gate electrode.

[0050] The position, size, range, etc. of each component shown in the drawings are not necessarily the same as those of the actual components for ease of understanding. The position, size, range, etc. may not be shown. Therefore, the disclosed invention may not necessarily be The position, size, range, etc. are not limited to those disclosed in the drawings, etc.

[0051] Ordinal numbers such as "first," "second," and "third" are used to avoid confusion of the components. That is why.

[0052] (Embodiment 1) The signal processing circuit has a memory device, and the memory device can store 1 bit of data. It has one or more memory elements.

[0053] In addition, CPU, microprocessor, image processing circuit, DSP (Digital Signal Processor) nal Processor), FPGA (Field Programmable G LSI (Large Scale Integrated Circuit) The signal processing circuit of the present invention includes the above-mentioned circuits.

[0054] (Configuration of memory element) FIG. 1 shows an example of a circuit diagram of a memory element. The memory element 100 includes a memory circuit 101 and a memory A circuit 102, a switch 103, a switch 104, a switch 105, and a phase inversion element The memory circuit 101 includes a power supply voltage. The memory circuit 102 includes a capacitor 108 and a transistor 109. and a transistor 110.

[0055] The memory element 100 may include other elements such as diodes, resistors, and inductors as needed. The circuit may further include other circuit elements.

[0056] The transistor 109 is a transistor in which a channel is formed in an oxide semiconductor layer. In FIG. 1, the transistor 109 is a transistor in which a channel is formed in an oxide semiconductor layer. Here, the channel is formed in the oxide semiconductor layer. The transistor 109 to be used is an enhanced A normally-off n-channel transistor is used. When the supply of power supply voltage to 100 is stopped, the gate of transistor 109 is set to ground potential (0 For example, the gate of the transistor 109 is connected to a load such as a resistor. The circuit is configured to be grounded via

[0057] In FIG. 1, the switch 103 is a transistor 11 of one conductivity type (for example, n-channel type). 3, and the switch 104 is configured using a conductivity type different from the one conductivity type (for example, p-channel Here, the first transistor 114 of the switch 103 is used. The terminal corresponds to one of the source and drain of the transistor 113, and the second terminal of the switch 103. This terminal corresponds to the other of the source and drain of the transistor 113, and the switch 103 The control signal S2 input to the gate of the transistor 113 controls the first terminal and the second terminal. The conduction or non-conduction between the two (i.e., the on or off state of transistor 113) is selected. The first terminal of the switch 104 is connected to one of the source and drain of the transistor 114. Correspondingly, the second terminal of the switch 104 is connected to the other of the source and drain of the transistor 114. Correspondingly, the switch 104 is turned on by a control signal S2 input to the gate of the transistor 114. This allows for conduction or non-conduction between the first terminal and the second terminal (i.e., the on / off state of the transistor 114). The ON or OFF state is selected.

[0058] One of the source and drain of the transistor 109 is connected to one of the pair of electrodes of the capacitor 108. and the gate of the transistor 110. One of the source and drain of the transistor 110 is applied with a potential V1. The other terminal is electrically connected to the first terminal of the switch 103 (transistor 11 The second terminal (the source or drain of the switch 103) is electrically connected to the second terminal (the drain of the switch 103). The other of the source and drain of the transistor 113 is connected to the first terminal of the switch 104 (transistor The second terminal of the switch 104 is electrically connected to the source or drain of the transistor 114. The terminal (the other of the source and drain of the transistor 114) is connected to a power supply line to which a potential V2 is applied. The second terminal of the switch 103 (the source and drain of the transistor 113) is electrically connected to the the other input of the switch 104 (the source and drain of the transistor 114) one of the pair of electrodes of the capacitor 107, the input terminal of the phase inverter 106, and The other side is electrically connected. Here, the connection point is referred to as node M1. The other of the pair of electrodes may be configured to have a constant potential input thereto. For example, The capacitor may be configured to receive a low power supply potential (such as a ground potential) or a high power supply potential. The other of the pair of electrodes of the element 107 is electrically connected to a power supply line to which a potential V1 is applied. A constant potential may be input to the other of the pair of electrodes of the capacitor 108. For example, a low power supply potential (ground potential, etc.) or a high power supply potential may be input. The other of the pair of electrodes of the capacitor 108 can be connected to a potential V1. In FIG. 1, the pair of capacitors 107 may be electrically connected to a power supply line. A potential V1 is applied to the other of the electrodes and the other of the pair of electrodes of the capacitor 108. An example is shown in which the power supply line is electrically connected to the power supply.

[0059] The capacitor 107 is formed by actively utilizing the parasitic capacitance of a transistor. The capacitor 108 may be omitted. It is also possible to omit it by using

[0060] A control signal S1 is input to the gate of the transistor 109. The switch 104 is connected between the first terminal and the second terminal by a control signal S2 different from the control signal S1. The first and second terminals of one switch are connected to select a conductive or non-conductive state. When the state between the first terminal and the second terminal of the other switch is conductive, the state between the first terminal and the second terminal of the other switch is non-conductive. The switch 105 is driven by a control signal S3 that is different from the control signals S1 and S2. A conductive or non-conductive state between the first terminal and the second terminal is selected.

[0061] The other of the source and drain of the transistor 109 is connected to a memory circuit 101. In FIG. 1, the output terminal of the memory circuit 101 (OUT The signal output from the transistor 109 is input to the other of the source and drain of the transistor 109. The second terminal of the switch 103 (the source and drain of the transistor 113) The signal output from the other terminal (the other terminal) is inverted by the phase inverting element 106. The control signal S3 causes a switch to be in a conductive state between the first terminal and the second terminal. The signal is input to the memory circuit 101 via the switch 105.

[0062] In FIG. 1, the second terminal of the switch 103 (the source and drain of the transistor 113) The signal output from the other end of the amplifier is stored in the memory through a phase inverter 106 and a switch 105. Although an example in which the signal is input to the input terminal (shown as IN in FIG. 1) of the circuit 101 is shown, the present invention is not limited to this. The second terminal of the switch 103 (the other of the source and drain of the transistor 113) The signal output from the memory circuit 101 may be input to the memory circuit 101 without being phase-inverted. For example, if a signal whose phase is the inverse of the signal input from the input terminal is stored in the memory circuit 101, When a node to be held exists, the second terminal of the switch 103 (transistor 113 A signal output from the other of the source and drain of the transistor can be input to the node.

[0063] In FIG. 1, a voltage corresponding to the potential difference between potential V1 and potential V2 is applied to the memory element as a power supply voltage. The memory circuit 101 receives a potential difference between the potential V1 and the potential V2. The voltage may be supplied as a power supply voltage. During this period, the potential difference between the potential V1 and the potential V2 can be (substantially) eliminated. For example, Both the potential V1 and the potential V2 can be set to the ground potential.

[0064] The switch 105 can be configured using a transistor. The transistor may be an n-channel transistor or a p-channel transistor. Alternatively, a combination of n-channel transistors and p-channel transistors may be used. For example, the switch 105 may be an analog switch.

[0065] In FIG. 1, the transistor 109 has two gates, one above the other and one below the other, with an oxide semiconductor layer sandwiched therebetween. A control signal S1 is input to one gate of the transistor, and a control signal S2 is input to the other gate of the transistor. A control signal S4 can be input to the gate. The control signal S4 is a signal of a constant potential. The constant potential may be a potential V1 or a potential V2. Two gates, one above the other and one below the other, are electrically connected and a control signal S1 is input. The signal input to the other gate of the transistor 109 may For example, the threshold voltage of the transistor 109 can be controlled by It can also be reduced further.

[0066] In FIG. 1, among the transistors used in the memory element 100, the transistor 109 The transistors other than the above have a channel formed in a layer or substrate made of a semiconductor other than an oxide semiconductor. For example, a transistor may be formed by adding a channel to a silicon layer or a silicon substrate. The transistor used in the memory element 100 can be a transistor in which a channel is formed. All the transistors may be transistors whose channels are formed in oxide semiconductor layers. Alternatively, the memory element 100 may include a transistor other than the transistor 109 whose channel is made of an oxide semiconductor. The transistors may include transistors formed in a conductive layer, with the remaining transistors being oxide semiconductors. The transistor may have a channel formed in a layer or substrate made of a semiconductor other than the silicon. Cut.

[0067] The oxide semiconductor layer can be made of an In-Ga-Zn oxide semiconductor material. In addition, semiconductors other than oxide semiconductors can be amorphous, microcrystalline, polycrystalline, or single crystalline. The oxide semiconductor layer can be made of silicon or germanium. The transistor in which the channel is formed has an off-state current density of 100 zA / μm or less, preferably It is preferably 10 zA / μm or less, and more preferably 1 zA / μm or less. Therefore, this off-state current is higher than that of a transistor using crystalline silicon. As a result, when the transistor 109 is in an off state, the potential of the node M1, That is, the potential of the gate of the transistor 110 can be held for a long period of time.

[0068] In the above, instead of the oxide semiconductor material, a material having an off-state current equivalent to that of the oxide semiconductor material is used. Materials that can realize these characteristics, such as wide-gap materials such as silicon carbide (more Specifically, for example, a semiconductor material with an energy gap Eg of 3 eV or larger is used. It may be used.

[0069] The memory circuit 101 in FIG. 1 includes a first phase inverter and a second phase inverter. The input terminal of the first phase inversion element is electrically connected to the output terminal of the second phase inversion element, The input terminal of the second phase inversion element is electrically connected to the output terminal of the first phase inversion element. The first phase inversion element and the second phase inversion element can be respectively Only during the period when the signal is being supplied, a signal corresponding to the input signal is output.

[0070] In addition, as the phase inversion element, for example, an inverter or a clocked inverter may be used. This can be done.

[0071] This concludes the description of the configuration of the memory element 100. Next, the driving method thereof will be described. .

[0072] (Method of driving memory element) In the memory element 100, power consumption during data retention after supply of power supply voltage is reduced. The driving method when the supply of power supply voltage is stopped to reduce the power consumption and then supplied again is as follows. The driving method will be described with reference to the timing chart of FIG. In the timing chart of FIG. 2, 101 indicates the data stored in the memory circuit 101. S1 indicates the potential of the control signal S1, S2 indicates the potential of the control signal S2, and S3 indicates the potential of the control signal S3. The potentials of the control signal S3 are indicated by V1 and V2, respectively. When the potential difference V of the potential V2 is 0, it corresponds to the case where the power supply voltage is not supplied. The potential of node M1 is shown, and M2 is the potential of node M2.

[0073] In the driving method described below, the switch 103 is set to n-channel in the configuration shown in FIG. switch 104 is a p-channel transistor, and control signal When S2 is at a high level potential, the first terminal and the second terminal of the switch 103 are in a conductive state. The first terminal and the second terminal of the switch 104 are in a non-conductive state, and the control When the signal S2 is at a low level potential, the first terminal and the second terminal of the switch 103 are not connected. In this example, the first terminal and the second terminal of the switch 104 are electrically connected. When the control signal S3 is at a high level potential, the switch 105 is connected to the first terminal and When the second terminal is in a conductive state and the control signal S3 is at a low level potential, the first terminal and In this example, the second terminal of the transistor 109 is in a non-conduction state. As a transistor, when the control signal S1 is at a high level potential, the transistor 109 is turned on. When the control signal S1 is at a low potential, the transistor 109 is in an off state. Here is an example:

[0074] However, the driving method of the present invention is not limited to this. 103, switch 104, switch 105, and transistor 109 are in the same state. The potential of each control signal can be determined as follows.

[0075] The potential V1 is a low power supply potential (hereinafter referred to as VSS), and the potential V2 is a high power supply potential (hereinafter referred to as VSS). Below, an example is shown of switching between VSS and ground potential. The driving method of the present invention is not limited to this. The potential V1 may be switched between VDD and VSS.

[0076] (normal operation) 2, the operation during period 1 will be described. During period 1, a power supply voltage is supplied to the memory element 100. Here, the potential V2 is VDD. A power supply voltage is supplied to the memory element 100. During this time, the memory circuit 101 holds the data (denoted as dataX in FIG. 2). , the control signal S3 is set to a low level potential, and the first terminal and the second terminal of the switch 105 are connected to each other. The first terminal and the second terminal of the switch 103 and the switch 104 are in a non-conducting state. The state between the terminals (conduction state, non-conduction state) can be either state. The signal S2 may be at a high level potential or a low level potential (denoted as A in FIG. 2). The state of the transistor 109 (on state or off state) may be either state. That is, the control signal S1 may be at a high level potential or a low level potential (see FIG. 2, denoted as A). During period 1, node M1 may be at any potential (see Figure 2). 2, denoted as A). During period 1, node M2 ​​may be at any potential (see Fig. (In 2, it is indicated as A). The operation in period 1 is called normal operation.

[0077] (Operation before power supply is stopped) The operation in the period 2 in FIG. 2 will be described. Before this, the control signal S1 is set to a high level potential to turn on the transistor 109. In this way, a signal corresponding to the data (dataX) held in the memory circuit 101 is transmitted to the The signal is input to the gate of the transistor 110 via the transistor 109. The signal input to the gate of node M is held by the capacitance element 108. The potential of 2 is a signal potential (represented as VX in FIG. 2) corresponding to the data stored in the memory circuit 101. After that, the control signal S1 is set to a low level potential to turn off the transistor 109. In this way, a signal corresponding to the data held in the memory circuit 101 is output to the memory circuit 10 During period 2, the first terminal of the switch 105 and the second terminal of the switch 106 are held at 2 by the control signal S3. The first terminals of the switches 103 and 104 are in a non-conductive state. The state between the first terminal and the second terminal (conducting state, non-conducting state) may be either state. The control signal S2 may be either a high level potential or a low level potential (see A in FIG. 2). In the period 2, the node M1 may have any potential (indicated as A The operation in period 2 is called the operation before the power supply voltage is stopped.

[0078] (Power supply voltage supply stop operation) The operation of the period 3 in FIG. 2 will be described. After the operation before the power supply voltage supply is stopped, At the beginning of step 3, the supply of the power supply voltage to the memory element 100 is stopped. The potential V2 becomes VSS. When the supply of power supply voltage is stopped, the data (dataX) held in the memory circuit 101 However, even after the supply of the power supply voltage to the storage element 100 is stopped, the capacitance element A signal corresponding to the data (dataX) held in the memory circuit 101 by the slave 108 A potential (VX) is held at node M2. Here, the channel of transistor 109 is A transistor formed in an oxide semiconductor layer is used. The leakage current (off current) is extremely small, and it is an enhancement type (normally off type). When the supply of the power supply voltage to the memory element 100 is stopped, Since the gate of the transistor 109 is continuously supplied with the ground potential (0V), Even after the supply of the power supply voltage to the memory element 100 is stopped, the transistor 109 is kept in an off state. The potential held by the capacitor 108 (potential VX of the node M2) can be In this way, the memory element 100 can maintain its charge for a long period of time even after the supply of power supply voltage is stopped. The data (dataX) is held. In period 3, the supply of the power supply voltage to the memory element 100 is stopped. This corresponds to the period in which

[0079] (Power supply restart operation) The operation in the period 4 in FIG. 2 will be described. The supply of the power supply voltage to the memory element is restarted, and the potential After V2 is set to VDD, the control signal S2 is set to a low level potential, and the first and a second terminal of the switch 103 is electrically connected to the first terminal and the second terminal of the switch 103. At this time, the control signal S1 is at a low level potential, and the transistor 109 The control signal S3 is at a low level potential, and the switch 105 remains in an off state. Thus, the second terminal of the switch 103 is in a non-conductive state. The potential V2 when the power supply voltage is supplied, i.e., VDD, is applied to the terminal and the first terminal of the switch 104. Therefore, the second terminal of the switch 103 and the first terminal of the switch 104 are The potential of the node M1 is set to a constant potential (for example, VDD) (hereinafter referred to as the precharge potential). The potential of the node M1 is held by the capacitor 107. do.

[0080] After the precharge operation, in period 5, the control signal S2 is set to a high level potential. This brings the first terminal and the second terminal of the switch 103 into a conductive state, and the switch 1 The first terminal and the second terminal of the control signal S1 are set to a low level. The control signal S 3 is at a low level potential, and the first terminal and the second terminal of the switch 105 are in a non-conductive state. In response to the signal held in the capacitor 108 (potential VX of the node M2), the transistor The on or off state of the switch 110 is selected, and the second terminal of the switch 103 and the The potential of the first terminal of the switch 104, that is, the potential of the node M1, is determined. In the ON state, a potential V1 (for example, VSS) is input to the node M1. When the transistor 110 is in the off state, the potential of the node M1 is The transistor is thus maintained at a constant potential (for example, VDD) determined by the The potential at node M1 is either VDD or VSS depending on whether the capacitor 110 is on or off. For example, if the signal held in the memory circuit 101 is "1" and the voltage is high, When the potential of the node M1 corresponds to the potential (VDD), the potential of the node M2 ​​corresponds to the low level corresponding to the signal "0". On the other hand, the signal held in the memory circuit 101 is "0" and When the potential of the node M1 corresponds to a low level potential (VSS), the potential of the node M1 corresponds to a signal "1". That is, the signal stored in the memory circuit 101 is reversed. The inversion signal is held at node M1. In FIG. 2, this potential is represented as VXb. That is, in the period 2, the data (dataX) input from the memory circuit 101 is The signal is converted into the potential (VXb) of the node M1.

[0081] After that, in period 6, the control signal S3 is set to a high level potential, and the first At this time, the control signal S2 is set to a high level potential. Furthermore, the control signal S1 remains at a low level potential, and the transistor 109 Then, the second terminal of the switch 103 and the first terminal of the switch 104 are connected to each other. A signal corresponding to the potential of the terminal (potential (VXb) of node M1) is input to phase inverter 106. The inverted signal can be input to the memory circuit 101. The memory circuit 101 stores the data ( dataX) can be retained again.

[0082] Furthermore, the potential of node M1 is maintained at a constant potential (Fig. In period 2, after the voltage V VDD is applied, in period 5, the voltage V corresponding to the data (dataX) is applied. Xb. Because a precharge operation is being performed, the potential of node M1 becomes a predetermined potential VXb In this way, the time required for the memory circuit to be determined after the power supply voltage is restarted can be shortened. This shortens the time it takes for the path 101 to retain the original data again.

[0083] This completes the description of the method for driving the memory element.

[0084] In the memory element and the driving method thereof of the present invention, while the power supply voltage is not supplied to the memory element 100, The data stored in the memory circuit 101, which corresponds to a volatile memory, is written to the memory circuit 10. The voltage can be held by the capacitor 108 provided in the capacitor 2.

[0085] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer increases depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using this transistor as the transistor 109, Even when power supply voltage is not supplied to the capacitor 108, the signal held in the capacitor 108 is maintained for a long period of time. In this way, the memory element 100 maintains its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold

[0086] Furthermore, by providing the switches 103 and 104, the precharge operation Since the memory element is characterized by performing the above-described operation, after the power supply voltage is restarted, the memory circuit 101 This can shorten the time it takes to restore the original data.

[0087] In the memory circuit 102, the signal held by the capacitor 108 is transferred to the transistor 103. Therefore, the supply of the power supply voltage to the memory element 100 is resumed. After the signal is transferred, the signal held by the capacitor 108 is transferred to the transistor 110 in the ON state. The state can be converted to a positive state (positive or negative state) and read out from the storage circuit 102. Even if the potential corresponding to the signal held in the capacitance element 108 fluctuates slightly, the original signal can be accurately It is possible to read it out.

[0088] Such a memory element 100 may be used as a register or cache memory in a signal processing circuit. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire signal processing circuit, or any part of the signal processing circuit, In addition, power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. A signal processing circuit capable of suppressing power consumption, and the signal processing circuit capable of suppressing power consumption A driving method can be provided.

[0089] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0090] (Embodiment 2) In this embodiment mode, a configuration of a memory device using a plurality of memory elements shown in Embodiment Mode 1 will be described. I will explain.

[0091] FIG. 3A shows an example of the configuration of a memory device in this embodiment. The memory device shown in the figure includes a switching element 401 and a memory element group 402. Specifically, each storage element 402 has the same structure as that described in the first embodiment. The memory element 100 having the configuration can be used. A high-level power supply potential VDD is supplied to the transistor 402 via the switching element 401. Furthermore, each memory element 402 included in the memory element group 403 is supplied with a potential of the signal IN. , a low-level power supply potential VSS is applied.

[0092] In FIG. 3A, a transistor is used as the switching element 401. The switching of the transistor is controlled by the control signal SigA applied to its gate electrode. can be.

[0093] In FIG. 3A, the switching element 401 has only one transistor. However, the present invention is not limited to this configuration. The element 401 may have a plurality of transistors. When a plurality of transistors functioning as switching elements are provided, the plurality of transistors The capacitors may be electrically connected in parallel or in series. The electrical connections may be a combination of series and parallel connections.

[0094] In addition, in FIG. 3A, the switching element 401 controls each of the memory element groups 403. The supply of a high-level power supply potential VDD to the storage element 402 is controlled. The supply of the low-level power supply potential VSS may be controlled by the switching element 401. 3(B), a switching element 401 is connected to each memory element 402 included in a memory element group 403. 1 shows an example of a memory device to which a low-level power supply potential VSS is supplied via a switch The signal from the signal input element 401 is a low level signal to each of the memory elements 402 in the memory element group 403. The supply of the power supply potential VSS can be controlled.

[0095] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0096] (Embodiment 3) In this embodiment mode, the memory element shown in Embodiment 1 or the memory device shown in Embodiment 2 The configuration of a signal processing circuit using this will be described.

[0097] FIG. 4 illustrates an example of a signal processing circuit according to one embodiment of the present invention. The memory device has at least a plurality of arithmetic circuits and one or a plurality of memory devices. The signal processing circuit 150 includes an arithmetic circuit 151, an arithmetic circuit 152, a storage device 153, and a storage device 154, a memory device 155, a control device 156, and a power supply control circuit 157.

[0098] The arithmetic circuits 151 and 152 include logic circuits that perform simple logical operations, as well as adders. , multipliers, and various arithmetic circuits. It functions as a register that temporarily stores data during the arithmetic processing in the memory device. The register 154 is a register that temporarily stores data during the arithmetic processing in the arithmetic circuit 152. It functions as a

[0099] The storage device 155 can also be used as a main memory, and the control device 156 can execute The program to be executed is stored as data, or the program is executed by the arithmetic circuit 151 or the arithmetic circuit 152. Data can be stored.

[0100] The control device 156 controls the arithmetic circuit 151, the arithmetic circuit 152, the recording circuit 153, and the like included in the signal processing circuit 150. This is a circuit that controls the overall operation of storage device 153, storage device 154, and storage device 155. Although FIG. 4 shows a configuration in which the control device 156 is a part of the signal processing circuit 150, The control device 156 may be provided outside the signal processing circuit 150 .

[0101] The memory element shown in the first embodiment and the memory device shown in the second embodiment are used as the memory device 153, By using it for the storage device 154 and the storage device 155, the storage device 153, the storage device 154, the storage device Even if the supply of power supply voltage to the storage device 155 is stopped, the data can be retained. Therefore, the supply of power supply voltage to the entire signal processing circuit 150 can be stopped, thereby reducing power consumption. Alternatively, any one of the storage devices 153, 154, and 155 The power supply voltage to the signal processing circuit 150 can be stopped, and the power consumption of the signal processing circuit 150 can be reduced. In addition, after the supply of power voltage is resumed, the device must be able to return to the state it was in before the power supply was stopped in a short time. can be done.

[0102] In addition, when the supply of power voltage to the storage device is stopped, the storage device and data Even if the supply of power supply voltage to the arithmetic circuit or control circuit that exchanges For example, if no operation is performed in the arithmetic circuit 151 and the storage device 153, the arithmetic circuit 151 and the storage device 153 may The supply of power supply voltage to the circuit 151 and the memory device 153 may be stopped.

[0103] The power supply control circuit 157 controls the arithmetic circuit 151 and the arithmetic circuit 152 of the signal processing circuit 150. 152, storage device 153, storage device 154, storage device 155, and control device 156. The magnitude of the power supply voltage is controlled. When the supply of the power supply voltage is stopped, the power supply voltage is stopped. The switching element for stopping the power supply may be provided in the power supply control circuit 157, Arithmetic circuit 151, arithmetic circuit 152, storage device 153, storage device 154, storage device 155, In the latter case, the power supply control circuit 157 may be provided in each of the control devices 156. However, it is not necessarily required to provide it in the signal processing circuit of the present invention.

[0104] The storage device 155, which is the main memory, the arithmetic circuit 151, the arithmetic circuit 152, the control A storage device that functions as a cache memory may be provided between the devices 156. By providing a memory, access to the slow main memory can be reduced, improving the reliability of calculations and other processes. The storage device that functions as a cache memory also has the By using the above-described memory element, the power consumption of the signal processing circuit 150 can be reduced. In addition, after the supply of power voltage is resumed, the device can quickly return to the state it was in before the power supply was stopped. Cut.

[0105] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0106] (Fourth embodiment) In this embodiment, a CPU, which is one of the signal processing circuits according to one embodiment of the present invention, is used. We will explain about this.

[0107] 5 shows the configuration of the CPU of this embodiment. The CPU shown in FIG. 5 is mounted on a board 9900. , ALU9901, ALU Controller9902, Instruction Decoder9903, Interrupt Controller9904, Tim ing Controller9905, Register9906, Register Controller 9907, Bus I / F 9908, Rewritable ROM 99 09, ROM·I / F9920 and mainly have. ALU is Arithmet ic logic unit, Bus·I / F is a bus interface, R OM·I / F is a ROM interface. ROM9909 and ROM·I / F99 20 may be provided on a separate chip. Of course, the CPU shown in FIG. 5 is shown in a simplified configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications.

[0108] The instructions input to the CPU via the Bus I / F 9908 are After being input to the Decoder9903 and decoded, the ALU Controller r9902, Interrupt Controller9904, Register Controller9907, Timing Controller9905 can be.

[0109] ALU・Controller9902, Interrupt・Controller 9904, Register Controller9907, Timing Control roller9905 performs various controls based on the decoded commands. The LU Controller 9902 sends signals to control the operation of the ALU 9901. The Interrupt Controller 9904 also generates During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and The Register Controller 9907 determines and processes the status of the disk. Generates the address of Register 9906 and writes it to Register 9906 according to the CPU state. Read and write to 9906.

[0110] The Timing Controller 9905 also supports ALU9901, ALU Co ntroller9902, Instruction・Decoder9903, Int errupt・Controller9904, Register・Controller Generates a signal to control the timing of the r9907 operation. For example, Timing Con The troller9905 generates an internal clock signal CLK based on the reference clock signal CLK1. The internal clock generator generates clock signal CLK2, which is then sent to the various circuits listed above. Supply.

[0111] In the CPU of this embodiment, the register 9906 stores the structure shown in the above embodiment. A memory element having a configuration is provided. 7 follows the instruction from the ALU 9901 and stores the value in the storage element of the Register 9906. In this case, whether data is stored in the memory circuit 101 or in the memory circuit 102 is determined. If data retention by the feedback loop of the phase inversion element is selected, In this case, the power supply voltage is supplied to the storage element in the register 9906. If data retention is selected, the data is written to the storage element in Register 9906. As shown in Figure 3, the power supply voltage can be stopped. A switch is connected between the memory element group and a node to which the power supply potential VDD or VSS is applied. This can be achieved by providing a chipping element.

[0112] In this way, when the CPU operation is temporarily stopped and the supply of power voltage is stopped, Even if the power is turned off, data can be retained, which reduces power consumption. For example, a user of a personal computer inputs information into an input device such as a keyboard. The CPU can be stopped even while input is stopped, thereby reducing power consumption. It is possible.

[0113] In this embodiment, a CPU has been taken as an example for explanation, but the signal processing circuit of the present invention may be implemented in a CPU. It is not limited to this, but can also be applied to LSIs such as microprocessors, image processing circuits, DSPs, and FPGAs. It is possible.

[0114] This embodiment mode can be implemented in combination with the above embodiment modes.

[0115] (Embodiment 5) In the memory element 100 shown in FIG. 1, the channel of the transistor 110 is formed in silicon. In the case where the transistor 110 is formed, the channel is formed in the oxide semiconductor layer. A method for manufacturing the memory element 100 will be described below using the transistor 109 and the capacitor 108 as examples. Note that other elements included in the memory element 100 include a transistor 109, The transistor 110 and the capacitor 108 can be manufactured in a similar manner.

[0116] As shown in FIG. 6A, an insulating film 701 and a single-crystal semiconductor substrate are formed on a substrate 700. A separated semiconductor film 702 is formed.

[0117] There is no significant limitation on the material that can be used as the substrate 700, but at least It is necessary for the substrate 700 to have heat resistance to the extent that it can withstand the heat treatment. is a glass substrate, quartz substrate, semiconductor substrate, ceramic substrate manufactured by the fusion method or float method. A glass substrate can be used when the temperature of the subsequent heat treatment is high. In this case, it is advisable to use one having a strain point of 730° C. or higher.

[0118] In this embodiment mode, the semiconductor film 702 is made of single crystal silicon. A method for manufacturing the transistor 110 will be described below. An example of a method for producing the semiconductor film 702 will be briefly described. An ion beam consisting of ions accelerated by an electric field is injected into the bond substrate. A brittle layer is formed in a region at a certain depth from the surface, where the crystal structure is disrupted and the layer is locally weakened. The depth of the region where the embrittlement layer is formed depends on the acceleration energy of the ion beam and the The angle of incidence of the beam can be adjusted. The insulating film 701 is sandwiched between the substrate 700 and the insulating film 701. After the bond substrate and the substrate 700 are superimposed, a first insulating film is formed on a part of the bond substrate and the substrate 700. N / cm 2 More than 500N / cm 2 Less than 11N / cm, preferably 2More than 20N / cm 2 Below When pressure is applied, the bond substrate and the insulating film 701 are bonded from that portion. The bonding begins, and eventually the entire surface is bonded. As a result, the microvoids in the embrittlement layer combine with each other, increasing the volume of the microvoids. As a result, the single crystal semiconductor film, which is a part of the bond substrate, is separated from the bond substrate in the embrittlement layer. The temperature of the heat treatment is set so as not to exceed the strain point of the substrate 700 .

[0119] Although this embodiment mode describes an example in which a single-crystal semiconductor film 702 is used, However, the present invention is not limited to this configuration. For example, the insulating film 701 may be formed by vapor deposition. A polycrystalline, microcrystalline or amorphous semiconductor film formed by a known technique may be used. Known crystallization methods include laser crystallization using laser light. There are two types of crystallization methods: one using a catalytic element and the other using laser crystallization. It is also possible to use a substrate with excellent heat resistance such as quartz. When used, the thermal crystallization method using an electric furnace, the lamp heating crystallization method using infrared light, the catalyst A crystallization method using elements and a crystallization method combining high-temperature heating at about 950°C may also be used. stomach.

[0120] Next, as shown in FIG. 6B, a gate insulating film 703 is formed on the semiconductor film 702 .

[0121] The gate insulating film 703 is formed by performing high density plasma treatment, heat treatment, etc. The surface of the silicon dioxide can be oxidized or nitrided by high-density plasma treatment. For example, rare gases such as He, Ar, Kr, and Xe, and oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen In this case, plasma excitation is performed by introducing microwaves. By doing so, it is possible to generate high density plasma at a low electron temperature. Oxygen radicals (which may contain OH radicals) and nitrogen radicals (N The surface of the semiconductor film is oxidized or nitrided by the H radicals. An insulating film having a thickness of 1 to 20 nm, preferably 5 to 10 nm, can be formed so as to contact the semiconductor film. For example, nitrous oxide (NO) is diluted 1 to 3 times (flow ratio) with Ar, and the A microwave (2.45 GHz) power of 3 to 5 kW was applied at a pressure of a to form the semiconductor film 702 This treatment oxidizes or nitrides the surface of the An insulating film (up to 6 nm) is formed. Nitrous oxide (N2O) and silane (SiH4) are then introduced. Then, microwave (2.45 GHz) power of 3 to 5 kW was applied at a pressure of 10 to 30 Pa. A silicon oxynitride film is formed by vapor deposition to form a gate insulating film. By combining reactions in the growth method, a gate with low interface state density and excellent dielectric strength is achieved. An insulating film can be formed.

[0122] The oxidation or nitridation of the semiconductor film by the high-density plasma treatment described above proceeds as a solid-phase reaction. The interface state density between the gate insulating film 703 and the semiconductor film 702 can be made extremely low. The semiconductor film 702 is directly oxidized or nitrided by high-density plasma treatment. The thickness of the insulating film can be prevented from varying. The surface of the semiconductor film is oxidized by a solid-phase reaction using high-density plasma treatment. This prevents oxidation from progressing too quickly only at the interface, resulting in a gate with good uniformity and low interface state density. The insulating film formed by the high density plasma treatment can be used to form a gate insulating film. The transistor formed by including the gate insulating film in part or the whole can suppress the variation in characteristics. This can be done.

[0123] In addition, silicon oxide, silicon nitride oxide, Silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide, iridium oxide Tritium, Hafnium Silicate (HfSi x O y (x>0, y>0)), nitrogen is added Hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen added Hafnium aluminate (HfAl x O y (x>0, y>0)) etc., in a single layer, Alternatively, the gate insulating film 703 may be formed by stacking.

[0124] In this specification, the term "oxynitride" refers to a material having a composition in which the oxygen content is higher than the nitrogen content. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It means a substance that is

[0125] The thickness of the gate insulating film 703 is, for example, 1 nm or more and 100 nm or less, preferably 10 nm or less. In this embodiment, the thickness can be set to 50 nm or more by using the plasma CVD method. A single layer insulating film containing silicon oxide is used as the gate insulating film 703 .

[0126] Next, as shown in FIG. 6(B), a mask 705 is formed on the gate insulating film 703. Then, as shown in FIG. 6(C), etching is performed using a mask 705. Then, a semiconductor layer 772 and a gate insulating layer 773 are formed.

[0127] The semiconductor layer 772 may contain boron, aluminum, gallium, or the like to control the threshold voltage. impurity elements that impart p-type conductivity, or impurities that impart n-type conductivity, such as phosphorus and arsenic The addition of impurity elements for controlling the threshold voltage may be performed by etching. This may be performed on the semiconductor film 702 before etching, or on the semiconductor film 702 formed after etching. The semiconductor layer 772 may also be doped with an impurity element for controlling the threshold voltage. The doping may be performed on the bond substrate. Alternatively, the doping of the impurity element may be performed on the substrate to reduce the threshold voltage. To roughly adjust the threshold voltage, the bond substrate is used, and then to fine-tune the threshold voltage, The semiconductor film 702 before etching or the semiconductor film formed by etching This may also be done to the body layer 772.

[0128] Next, after removing the mask 705, a gate electrode 707 is formed as shown in FIG. 6(C). Complete.

[0129] The gate electrode 707 is formed by forming a conductive film and then etching the conductive film into a predetermined shape. The conductive film can be formed by the CVD method, the sputtering method, The conductive film may be formed by evaporation, spin coating, or the like. Tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), etc. can be used. Alternatively, an alloy containing the above metal may be used, or a compound containing the above metal may be used. It uses semiconductors such as polycrystalline silicon doped with impurity elements such as phosphorus to give it conductivity. It may be formed as follows.

[0130] In this embodiment, the gate electrode 707 is formed of a single layer of conductive film. The gate electrode 707 is formed of a plurality of stacked conductive films. It's okay to have it.

[0131] The combination of two conductive films is tantalum nitride or tantalum for the first layer and tantalum for the second layer. In addition to the above examples, tungsten nitride and tungsten, nitride can be used. Examples include molybdenum chloride and molybdenum, aluminum and tantalum, and aluminum and titanium. Tungsten and tantalum nitride have high heat resistance, so after forming the two-layer conductive film, In the process, a heat treatment for the purpose of thermal activation can be performed. As a combination of these, for example, silicon doped with an impurity element that gives n-type conductivity can be used. silicon and nickel silicide, silicon doped with impurity elements that give n-type conductivity, Tungsten silicide or the like can also be used.

[0132] In the case of a three-layer structure in which three or more conductive films are stacked, a molybdenum film, an aluminum film, and a molybdenum film are stacked. It is advisable to adopt a laminated structure of butene films.

[0133] The gate electrode 707 may be made of indium oxide, indium tin oxide, or indium oxide. Zinc oxide, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, or zinc oxide gas Alternatively, a light-transmitting conductive oxide film such as a fluorine-containing oxide film can be used.

[0134] It is to be noted that the gate electrode 707 may be selectively formed by a droplet discharge method without using a mask. The droplet ejection method is a method of ejecting or spraying droplets containing a predetermined composition from a fine hole to form a predetermined shape. This refers to a method for forming a pattern, and inkjet methods are included in this category.

[0135] The gate electrode 707 is formed by ICP (Inductively Conductive Plasma) deposition after forming a conductive film. Inductively Coupled Plasma (ICP) etching method was used, and the etching conditions were (The amount of power applied to the coil-type electrode layer, the amount of power applied to the substrate-side electrode layer, the amount of power applied to the substrate-side electrode layer By appropriately adjusting the electrode temperature, etching can be performed to obtain the desired tapered shape. The angle of the tapered shape can also be controlled by the shape of the mask. The etching gas may be chlorine, boron chloride, silicon chloride, or tetrachloride. chlorine-based gases such as carbon tetrafluoride, sulfur fluoride or nitrogen fluoride, or Oxygen can be used as needed.

[0136] Next, as shown in FIG. 6(D), one conductivity is imparted using the gate electrode 707 as a mask. By adding an impurity element to the semiconductor layer 772, a channel overlapping with the gate electrode 707 is formed. The region 710 and a pair of impurity regions 709 sandwiching the channel forming region 710 are semiconductor It is formed in layer 772.

[0137] In this embodiment, the semiconductor layer 772 is doped with an impurity element (for example, boron) that imparts p-type conductivity. Let's take the example of adding

[0138] Next, as shown in FIG. 7(A), a gate insulating layer 773 and a gate electrode 707 are formed. Specifically, the insulating films 712 and 713 are formed as follows: , silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide In particular, the insulating film 712 and the insulating film 713 can be made of an inorganic material such as aluminum. By using a low-k material for the This is preferable because it is possible to sufficiently reduce the capacitance. A porous insulating film using the above-mentioned material may be applied to the third insulating film. The dielectric constant is lower than that of high insulating films, further reducing the parasitic capacitance caused by electrodes and wiring. It is possible to do this.

[0139] In this embodiment mode, the insulating film 712 is made of silicon oxynitride, and the insulating film 713 is made of silicon nitride oxide. In this embodiment, an insulating film 707 is formed on the gate electrode 707. 12, the case where the insulating film 713 is formed is illustrated, but the present invention is not limited to the case where the insulating film 713 is formed on the gate electrode 707. Only one insulating film may be formed on the insulating film, or three or more insulating films may be laminated. It may be completed.

[0140] Next, as shown in FIG. 7(B), the insulating film 712 and the insulating film 713 are subjected to CMP (chemical mechanical polishing). By performing mechanical polishing or etching, the surface of the gate electrode 707 is exposed. In order to improve the characteristics of the transistor 109 to be formed later, the insulating film 712, It is preferable that the surface of the insulating film 713 be as flat as possible.

[0141] Through the above steps, the transistor 110 can be formed.

[0142] Next, a manufacturing method of the transistor 109 will be described. As shown, the oxide semiconductor layer 716 is formed over the insulating film 712 or the insulating film 713.

[0143] The oxide semiconductor layer 716 is an oxide semiconductor film formed over the insulating films 712 and 713. The oxide semiconductor film can be formed by processing the oxide semiconductor film into a desired shape. 2 nm or more and 200 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 3 nm or more The oxide semiconductor film is formed by using an oxide semiconductor as a target. The oxide semiconductor film is formed by sputtering under a rare gas (for example, argon) atmosphere. , sputtering in an oxygen atmosphere, or a mixture of rare gas (e.g., argon) and oxygen atmosphere. It can be formed by the method.

[0144] Before forming the oxide semiconductor film by sputtering, argon gas was introduced into the plasma. Reverse sputtering is performed to generate a smear, and the smear is formed on the surfaces of the insulating films 712 and 713. It is preferable to remove dust particles that may be present on the target. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is a method to modify the surface by using nitrogen or helium instead of argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. Alternatively, the treatment may be carried out in an argon atmosphere to which chlorine, carbon tetrafluoride, or the like has been added.

[0145] The material (oxide semiconductor) constituting the oxide semiconductor film is at least indium (I It is preferable that the alloy contains In or zinc (Zn). It is particularly preferable that the alloy contains In and Zn. In addition, the variation in electrical characteristics of a transistor formed using the oxide semiconductor film can be reduced. In addition to these, it is preferable to contain gallium (Ga) as a stabilizer for It is also preferable that tin (Sn) is contained as a stabilizer. It is preferable that hafnium (Hf) is contained as a stabilizer. It is preferable that the material contains aluminum (Al).

[0146] Other stabilizers include lanthanides such as lanthanum (La) and cerium. (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium Eu, Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), aluminium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), It may contain one or more of lutetium (Lu).

[0147] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. oxides such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides Oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides , In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, I n-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, which is an oxide of a quaternary metal, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides It can be used.

[0148] Here, for example, In-Ga-Zn oxide refers to an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn does not matter. The metal element may be included.

[0149] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer ) may be used, where M is selected from Ga, Fe, Mn and Co. In addition, the oxide semiconductor is In3SnO 5(ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0150] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In: In-Ga-Zn system with an atomic ratio of Ga:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The oxide or an oxide having a similar composition can be used. 1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3: 1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn oxide having an atomic ratio of 100% or an oxide having a composition close to that.

[0151] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In order to obtain the required semiconductor properties, a material with an appropriate composition can be used. Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to set the degree etc. appropriately.

[0152] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b +c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+ C=1) is close to the oxide composition when a, b, and c are (a-A) 2 +(b-B) 2 +(c-C) 2 ≦r 2 The above expression means that the value of r is satisfied, and r can be set to 0.05, for example. The same is true for oxides.

[0153] The oxide semiconductor film may be amorphous (non-crystalline) or crystalline. It's fine.

[0154] Amorphous oxide semiconductors can be easily flattened. This can reduce interface scattering when a transistor is fabricated, and can be fabricated relatively easily and relatively easily. High mobility can be obtained.

[0155] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and By improving the flatness of the surface, it is possible to obtain a mobility higher than that of an amorphous oxide semiconductor. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably Preferably, it is formed on the surface to a thickness of 0.1 nm or less.

[0156] Note that Ra is the centerline average roughness defined in JIS B0601 applied to the surface. It is a three-dimensional extension of the method, which calculates the average absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of times the

[0157]

number

[0158] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y 1) The area of ​​the rectangular region bounded by four points (x2, y2), Z0 indicates the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0159] In this embodiment, the material contains In (indium), Ga (gallium), and Zn (zinc). 30 nm thick In-Ga-Zn oxide obtained by sputtering using a target The semiconductor thin film is used as an oxide semiconductor film. The composition ratio of In:Ga:Zn=1:1:0.5, In:Ga:Zn=1:1:1, or I A target with n:Ga:Zn=1:1:2 can be used. and the filling rate of the target containing Zn is 90% or more and 100% or less, preferably 95% or more. By using a target with a high filling rate, the oxide semiconductor film formed The body membrane becomes a dense membrane.

[0160] In this embodiment, the substrate is held in a processing chamber maintained in a reduced pressure state, and the remaining water in the processing chamber is removed. While removing the components, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the target is used. During the film formation, the substrate temperature is preferably 100° C. or higher and 600° C. or lower. Alternatively, the temperature may be 200°C or higher and 400°C or lower. The concentration of impurities contained in the formed oxide semiconductor film can be reduced. Damage caused by the ring is reduced. To remove residual moisture in the processing chamber, an adsorption-type vacuum is used. It is preferable to use a pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use an air pump. A cold trap may be added. The processing chamber is evacuated using a cryopump. and, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H2O) (more preferably a carbon atom) Since the exhaust gas contains oxygen, the oxide semiconductor film formed in the treatment chamber is This can reduce the concentration of impurities.

[0161] An example of the film formation conditions is a distance between the substrate and the target of 100 mm and a pressure of 0.6 P. a) DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere In addition, if a pulsed direct current (DC) power supply is used, dust generated during film formation can be reduced, This is preferable because the film thickness distribution is uniform.

[0162] In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10 -10 Pa·m3 / seconds or more By setting the temperature lower, it is possible to prevent the alkali metal from being deposited on the oxide semiconductor film during the film formation by sputtering. It is possible to reduce the inclusion of impurities such as silicon metals and hydrides. By using an adsorption type vacuum pump, alkali metals, hydrogen atoms, and hydrogen molecules from the exhaust system can be removed. , the backflow of impurities such as water, hydroxyl radicals, or hydrides can be reduced.

[0163] In addition, by setting the purity of the target to 99.99% or higher, it is possible to prevent the target from being mixed into the oxide semiconductor film. It is possible to reduce the amount of alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, etc. In addition, by using the target, lithium, sodium, and the like can be easily formed in the oxide semiconductor film. The concentrations of alkali metals such as thorium and potassium can be reduced.

[0164] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment for film formation, the insulating film 712 and the insulating film 71 The substrate 700 on which the above-mentioned steps 3 are formed is preheated to remove moisture or hydrogen adsorbed on the substrate 700. It is preferable to desorb and exhaust impurities. The preheating temperature is 100°C or higher and 400°C or lower. The temperature is set to 150°C or lower, preferably 150°C or higher and 300°C or lower. A cryopump is preferably used for the first stage. However, this preheating process can be omitted. In addition, this pre-heating is performed before the formation of the gate insulating film 721, which will be performed later. The same process may be carried out on the substrate 700 on which the film 720 has been formed.

[0165] Note that the etching for forming the oxide semiconductor layer 716 can be dry etching or wet etching. Dry etching may be used, or both may be used. The gas may be a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BC 13), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.) are preferred. Fluorine-containing gases (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6) , nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr) , oxygen (O2), and these gases are added with rare gases such as helium (He) and argon (Ar). A gas containing a gas added thereto can be used.

[0166] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) hing method and ICP (Inductively Coupled Plasma) Inductively coupled plasma etching can be used. It can be etched into the desired shape. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0167] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Organic acids such as enoic acid and oxalic acid can be used. N (manufactured by Kanto Chemical Co., Ltd.) is used.

[0168] A resist mask for forming the oxide semiconductor layer 716 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, no photomask is required. , and manufacturing costs can be reduced.

[0169] Note that reverse sputtering is performed before forming a conductive film in the next step. It is preferable to remove resist residues and the like adhering to the surfaces of the insulating film 712 and the insulating film 713. I wish.

[0170] Note that the oxide semiconductor film formed by sputtering or the like contains moisture or hydrogen ( Water or hydrogen may easily form donor levels. Therefore, in one embodiment of the present invention, In order to reduce impurities such as moisture or hydrogen in the semiconductor film (dehydration or dehydrogenation), The compound semiconductor layer 716 is subjected to a treatment under a reduced pressure atmosphere or an inert gas atmosphere such as nitrogen or a rare gas. Under oxygen gas atmosphere or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. In an atmosphere of air, preferably 1 ppm or less, preferably 10 ppb or less, oxide semiconductor The body layer 716 is subjected to a heat treatment.

[0171] By performing heat treatment on the oxide semiconductor layer 716, moisture or water in the oxide semiconductor layer 716 is removed. Specifically, the temperature is 250°C or higher and 750°C or lower, preferably 40 Heat treatment can be performed at a temperature above 0°C and below the distortion point of the substrate. For example, heat treatment can be performed at 500°C for 3 minutes or more. If the RTA method is used for the heat treatment, dehydration or dehydration can be achieved in a short time. Because hydrogenation can be performed, processing can be performed at temperatures exceeding the strain point of the glass substrate.

[0172] In this embodiment mode, an electric furnace, which is one of the heat treatment devices, is used.

[0173] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas such as a rare gas such as argon or nitrogen that does not react with the material to be treated by heat treatment. A gas is used.

[0174] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is added to the It is preferable that hydrogen and the like are not contained. Alternatively, nitrogen or helium introduced into the heat treatment device The purity of rare gases such as ammonium, neon, and argon is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than 1 ppm.

[0175] Note that oxide semiconductors are insensitive to impurities, and the film contains a considerable amount of metal impurities. It is not a problem if it is used in a low-cost soda that contains a large amount of alkali metals such as sodium. It has been pointed out that lime glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide Semiconductors" "Current Status of Physical Properties and Device Development of ZnO," Solid State Physics, September 2009, Vol. 44, pp. 6 21-633.) However, this is not an appropriate indication. Alkali metals are oxide semiconductors. Alkaline earth metals are also impurities because they are not elements that make up oxide semiconductors. In particular, Na, one of the alkali metals, is an impurity when it is not an element that can be oxidized. When the insulating film in contact with the semiconductor layer is an oxide, Na diffuses into the insulating film. + This becomes: In addition, Na acts to form bonds between the metals and oxygen that make up the oxide semiconductor in the oxide semiconductor layer. As a result, for example, the threshold voltage is shifted in the negative direction. Deterioration of transistor characteristics such as normally-on and reduced mobility due to the shift to This impurity causes transistor characteristics to fluctuate. The degradation and variation of the characteristics of the capacitor occur when the hydrogen concentration in the oxide semiconductor layer is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor layer is 1×10 18 / cm 3 below , more preferably 1 × 10 17 / cm 3 If the concentration of the impurities is less than or equal to Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5 × 1 0 16 / cm 3 Less than 1 × 10 16 / cm 3 or less, more preferably 1 × 10 1 5 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / cm 3 below , preferably 1 x 10 15 / cm 3 Similarly, the measured value of the K concentration should be 5× 10 15 / cm3 Less than 1 × 10 15 / cm 3 The following would be appropriate.

[0176] Through the above steps, the concentration of hydrogen in the oxide semiconductor layer 716 can be reduced.

[0177] Note that the oxide semiconductor layer may be amorphous (non-crystalline) or crystalline. In the latter case, it may be a single crystal, a polycrystal, or a crystal with a portion having crystallinity. It may be a structure in which a portion having crystallinity is included in an amorphous state, or a structure in which a portion having crystallinity is included in an amorphous state, or a non-amorphous structure. For example, the oxide semiconductor layer may be c-axis oriented and ab-plane, surface or The atomic arrangement is triangular or hexagonal when viewed from the interface direction, and the metal atoms are arranged in the c-axis. The molecules are arranged in layers or the metal atoms and oxygen atoms are arranged in layers, and the a-axis or The crystal with a different b-axis orientation (rotated around the c-axis) is called CAAC (C Axis Al Oxides containing ZnO (also called ignited crystal) can be used.

[0178] An oxide semiconductor film using an oxide containing CAAC can also be formed by a sputtering method. To obtain CAAC by sputtering, the oxide semiconductor film must first be deposited. In the initial stage, hexagonal crystals are formed, and the crystals are used as seeds to grow crystals. To achieve this, it is important to increase the distance between the target and the substrate. The substrate heating temperature is set to 100°C to 500°C, preferably The temperature is preferably 200 to 400°C, and more preferably 250 to 300°C. In addition, the deposited oxide semiconductor film is heated at a temperature higher than the substrate heating temperature during film formation. Heat treatment can repair micro defects contained in the film and defects at the interface of the laminate. do.

[0179] In a broad sense, oxides containing CAAC are non-single crystals that are perpendicular to the ab plane. When viewed from the outside, the atomic arrangement is triangular, hexagonal, equilateral triangular, or equilateral hexagonal, and perpendicular to the c-axis direction. When viewed from any direction, it contains a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to oxides.

[0180] CAAC is not a single crystal, but it is not composed of only amorphous material. AAC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is Sometimes it is not possible to clearly distinguish.

[0181] When CAAC contains oxygen, a part of the oxygen may be replaced by nitrogen. The c-axis of each crystalline part that constitutes C is in a certain direction (for example, the substrate surface supporting the CAAC, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal of the ab plane of each crystal part is in a certain direction (e.g., the substrate surface supporting the CAAC, It may be oriented in a direction perpendicular to the surface of C, etc.

[0182] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, they may be transparent or opaque to visible light. Or something like that.

[0183] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from various directions, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, Then, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals such as these can also be mentioned.

[0184] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 16 to 18. 16 to 18, the upward direction is the c-axis direction, and the direction perpendicular to the c-axis is The intersecting plane is the ab plane. When simply referring to the upper half and the lower half, it means that the ab plane is the boundary. In Figure 16, the circled O represents a tetrahedral O, The double circled O indicates a three-coordinate O.

[0185] Figure 16(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as The structure shown has four-coordinated oxygen atoms. Here, one metal atom has four adjacent oxygen atoms. The structure showing only atoms is called a small group. The structure in Figure 16(A) has an octahedral structure, For simplicity, the structure is shown as a plane. There are three tetracoordinate O atoms in each group. The small group shown in Figure 16(A) has a zero charge.

[0186] Figure 16(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as The structure shows a tricoordinate O and two adjacent tetracoordinate O. The upper and lower halves of Figure 16(B) each contain one 4-coordinate atom. In addition, since In also has a 5-coordinate structure, it can take the structure shown in Figure 16(B). The small group shown in 6(B) has a charge of 0.

[0187] FIG. 16(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The structure of Figure 16(C) shows one tetracoordinate O in the upper half and three tetracoordinate O in the lower half. Or, in Figure 16(C), there are three tetracoordinate O atoms in the upper half and one in the lower half. There may be four-coordinated O atoms. The small group shown in Figure 16(C) has a zero charge.

[0188] FIG. 16(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The structure of Figure 16(D) shows three tetracoordinate O atoms in the upper half and three tetracoordinate O atoms in the lower half. The small group shown in Figure 16(D) has a charge of +1.

[0189] Figure 16(E) shows a small group containing two Zn atoms. The upper half of Figure 16(E) shows one Zn atom. The small group shown in Figure 16(E) has four tetrahedral O atoms, and the lower half has one tetrahedral O atom. The charge of the atom is -1.

[0190] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a is called a large group (also called a unit cell).

[0191] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In have three neighboring In atoms in the downward direction, The three O atoms have three adjacent In atoms in the upward direction. One O in the upper half of Ga has one neighboring Ga below it, and one O in the lower half has one neighboring Ga above it. One O atom in the upper half of the 4-coordinate Zn shown in Figure 16(C) faces downward. The three Os in the lower half have three neighboring Zns each in the upward direction. In this way, the number of tetrahedral O atoms above the metal atom and the number of neighboring metal atoms below the O atoms Similarly, the number of tetrahedral O atoms below the metal atom and the number of neighboring O atoms above the O atoms are The number of metal atoms is equal. Since O is tetracoordinated, the number of neighboring metal atoms below is equal to the number of neighboring metal atoms above. The sum of the number of neighboring metal atoms is 4. Therefore, the number of 4-coordinated O atoms above the metal atom is When the sum of the number of tetrahedral O atoms below another metal atom is 4, Two small groups can be bonded together. For example, a hexacoordinated metal atom (In or When Sn) is bonded through the tetracoordinate O in the lower half, there are three tetracoordinate O atoms, so the pentad It bonds to either a tetrahedral metal atom (Ga or In) or a tetrahedral metal atom (Zn) This will happen.

[0192] Metal atoms with these coordination numbers are bonded via tetracoordinated oxygen atoms in the c-axis direction. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. The medium group is composed of these.

[0193] Figure 17(A) shows a model of the middle group, which consists of a layered structure of In-Sn-Zn oxide. Figure 17(B) shows a large group consisting of three medium groups. 17(C) shows the atomic arrangement when the layer structure of FIG. 17(B) is observed from the c-axis direction.

[0194] In FIG. 17(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of tetracoordinate O atoms is shown. For example, the upper and lower halves of Sn each contain three tetrahedral O atoms. Similarly, in FIG. 17(A), the upper and lower halves of In are Each of the has one tetracoordinated O atom, which is shown as a circle 1. Similarly, in Figure 1 In 7(A), the bottom half has one tetracoordinate O atom, and the top half has three tetracoordinate O atoms. A Zn atom has one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. n.

[0195] In Figure 17(A), the middle group, which forms a layered structure of In-Sn-Zn oxide, From the top, Sn has three tetrahedral O atoms in the upper half and one in the lower half, and Each In is bonded to an In atom in the upper half and a In atom in the lower half, and the In atom is bonded to three tetracoordinate O atoms in the upper half. It bonds to a certain Zn, and three tetracoordinate O atoms are bonded to the lower half of the Zn via one tetracoordinate O atom. It bonds to In in the upper and lower halves, and the In has one tetracoordinated O in the upper half. It bonds to a small group consisting of two Zn atoms and is connected to the lower half of this small group via a tetracoordinate O atom. The structure is such that three tetracoordinated O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple medium groups combine to form large groups.

[0196] Here, for a three-coordinate O and a four-coordinate O, the charge per bond is -0. 667, -0.5. For example, In (6-coordinate or 5-coordinate), Zn ( The charges of Sn (four-coordinated), Sn (five-coordinated or six-coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, when a layer structure containing Sn is formed, To achieve this, a charge of -1 is required to cancel out the charge of +1. As shown in 16(E), there is a small group containing two Zn atoms. For example, If there is one small group containing two Zn atoms for every small group containing one Zn atom, the charges will be cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0197] Specifically, the large group shown in Figure 17(B) is repeated to form an In-Sn-Z The resulting In2SnZn3O8 crystals are -The layer structure of Sn-Zn oxide is In2SnZn2O7(ZnO) m (m is 0 or It can be expressed by the formula (a natural number).

[0198] In addition to these, there are also oxides of quaternary metals such as In-Sn-Ga-Zn oxides, In-Ga-Zn oxide (also written as IGZO), which is a ternary metal oxide, -Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn- Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In- Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-S m-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb -Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er- Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Z n-based oxides, binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, and A l-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, The same applies when an In-Ga oxide is used.

[0199] For example, in Figure 18(A), a middle group consisting of a layer structure of In-Ga-Zn oxide is shown. A model diagram of the above is shown.

[0200] In Figure 18(A), the middle group, which forms a layer structure of In-Ga-Zn oxide, , from the top, there are three tetrahedral O atoms in the upper half and three in the lower half, and one tetrahedral O atom It bonds to the Zn in the upper half, and via the three tetracoordinate O atoms in the lower half of the Zn, is bonded to Ga in the upper half and the lower half, and one 4-coordinate The structure is such that three tetracoordinate O atoms are bonded to In atoms in the upper and lower halves via O atoms. Multiple medium groups combine to form large groups.

[0201] Figure 18(B) shows a large group consisting of three medium groups. shows the atomic arrangement when the layer structure of FIG. 18(B) is observed from the c-axis direction.

[0202] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3, respectively, so they are in a small group that includes either In, Zn, or Ga. The charge is 0. Therefore, if these small groups are combined, The total charge is always zero.

[0203] The middle group, which is made up of a layer structure of In-Ga-Zn oxide, is shown in Figure 18(A). It is not limited to the middle group shown here, but can be made by combining middle groups with different arrangements of In, Ga, and Zn. It is also possible to take large groups.

[0204] Next, as shown in FIG. 8A, a layer having an oxide semiconductor layer A conductive film 719 in contact with the oxide semiconductor layer 716 and a conductive film 720 in contact with the oxide semiconductor layer 716 are formed. The conductive films 719 and 720 function as a source electrode and a drain electrode.

[0205] Specifically, the conductive films 719 and 720 are formed by sputtering so as to cover the gate electrode 707. After forming a conductive film by a deposition method or vacuum deposition method, the conductive film is etched into a predetermined shape. It can be formed by:

[0206] The conductive films to be the conductive films 719 and 720 may be formed using aluminum, chromium, copper, or tantalum. , titanium, molybdenum, tungsten, or a material containing the above elements. Examples of the thin film include an alloy film or an alloy film made of a combination of the above elements. Chromium, tantalum, titanium, molybdenum, tungsten under or on top of any metal film The metal film may be a laminate of a high melting point metal film such as aluminum or copper. To avoid problems with corrosion and heat resistance, it is recommended to use it in combination with high melting point metal materials. Metallic materials include molybdenum, titanium, chromium, tantalum, tungsten, and neodymium. , scandium, yttrium, etc. can be used.

[0207] The conductive films to be the conductive films 719 and 720 may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, an aluminum film A two-layer structure with a titanium film laminated on top, and an aluminum film laminated on top of the titanium film. A three-layer structure is possible, in which a titanium film is formed on top of the laminated Cu-M. γ-Al alloy, Mo-Ti alloy, Ti, Mo, have high adhesion to oxide film. The layer is a conductive film made of Cu-Mg-Al alloy, Mo-Ti alloy, Ti, or Mo. A conductive film made of Cu is laminated on the layer, and the laminated conductive film is made into a conductive film 719 and a conductive film By using the insulating film 720, the adhesion between the insulating film, which is an oxide film, and the conductive film 719 and the conductive film 720 can be improved. It can improve sexuality.

[0208] The conductive films to be the conductive films 719 and 720 are formed of a conductive metal oxide. The conductive metal oxide may be indium oxide, tin oxide, zinc oxide, Indium tin oxide, indium zinc oxide or the above metal oxide material with silicon or The insulating film may contain silicon oxide.

[0209] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand this heat treatment. It is preferable to do so.

[0210] Note that the conductive film is etched so as not to remove the oxide semiconductor layer 716 as much as possible. The materials and etching conditions are adjusted accordingly. Depending on the etching conditions, oxidation The exposed portion of the compound semiconductor layer 716 is partially etched to form a groove (recess). It may also be possible.

[0211] In this embodiment mode, a titanium film is used as the conductive film. A solution containing ammonia and hydrogen peroxide is used to selectively wet etch the conductive film. Specifically, a mixture of 31% by weight of hydrogen peroxide, 28% by weight of ammonia water, and water A mixture of ammonia and hydrogen peroxide in a volume ratio of 5:2:2 is used. The conductive film may be dry-etched using a gas containing boron dioxide (BCl3) or the like.

[0212] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives the transmitted light multiple levels of intensity is used. The resist mask formed using the multi-tone mask may be used for multiple etching processes. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A single multi-tone mask can be used to create a register that corresponds to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, which simplifies the process.

[0213] In addition, the oxide semiconductor layer 716 and the conductive film 7 functioning as a source electrode or a drain electrode Between the conductive film 720 and the oxide conductive film 19, the oxide conductive film 19 functions as a source region and a drain region. The oxide conductive film may be made of a material containing zinc oxide. It is preferable that the oxide is free of indium oxide. As conductive films, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc oxide Gallium and the like can be used.

[0214] For example, when forming an oxide conductive film, etching is performed to form the oxide conductive film. and etching for forming the conductive films 719 and 720 are performed simultaneously. You can do that too.

[0215] By providing an oxide conductive film that functions as a source region and a drain region, an oxide semiconductor Since the resistance between the conductive layer 716 and the conductive film 719 and the conductive film 720 can be reduced, In addition, the source and drain regions can be made of silicon dioxide. By providing an oxide conductive film that functions as a gate insulating film, the withstand voltage of the transistor can be increased.

[0216] Next, plasma treatment using gas such as N2O, N2, or Ar may be performed. This plasma treatment removes water and the like attached to the exposed surface of the oxide semiconductor layer. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0217] After the plasma treatment, the conductive film 719 and the conductive film 7 A gate insulating film 721 is formed to cover the oxide semiconductor layer 716 and the gate insulating film 721. A gate electrode 72 is formed on the gate insulating film 721 at a position overlapping with the oxide semiconductor layer 716. 2 is formed, and a conductive film 723 is formed in a position overlapping with the conductive film 719.

[0218] The gate insulating film 721 is formed using the same material and the same laminated structure as the gate insulating film 703. The gate insulating film 721 is extremely resistant to impurities such as moisture and hydrogen. It is preferable that the insulating film does not contain any insulating material, and it may be a single layer insulating film or a laminate of multiple insulating films. If the gate insulating film 721 contains hydrogen, the hydrogen may be converted into an oxide semiconductor. The hydrogen penetrates into the oxide semiconductor layer 716, or the hydrogen extracts oxygen from the oxide semiconductor layer 716, forming the oxide semiconductor. If this occurs, the resistance of the semiconductor layer 716 will become low (become n-type), and a parasitic channel may be formed. Therefore, the gate insulating film 721 is formed by a method for forming the film so that the film contains as little hydrogen as possible. It is important that no material with high barrier properties is used for the gate insulating film 721. For example, a silicon nitride film or a silicon nitride oxide film is used as an insulating film with high barrier properties. , an aluminum nitride film, an aluminum nitride oxide film, or the like can be used. When using a laminated insulating film, a silicon oxide film or a silicon oxynitride film with a low nitrogen content is used. The insulating film is formed closer to the oxide semiconductor layer 716 than the insulating film with high barrier property. Then, the conductive film 719 and the conductive film 720 are formed with an insulating film having a low nitrogen content sandwiched therebetween. An insulating film with high barrier properties is formed so as to overlap with the oxide semiconductor layer 716. By using an insulating film with high thermal conductivity, the oxide semiconductor layer 716, the gate insulating film 721, or the like can be formed. Impurities such as moisture or hydrogen are present at the interface between the oxide semiconductor layer 716 and the other insulating film and in the vicinity thereof. In addition, the ratio of nitrogen to the oxide semiconductor layer 716 can be increased. By forming insulating films such as silicon oxide films and silicon oxynitride films with low barrier properties, This can prevent the insulating film using such a material from being in direct contact with the oxide semiconductor layer 716.

[0219] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The gate insulating film has a structure in which a 100 nm thick silicon nitride film formed by the SiO2 method is stacked. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. In the form, it is 100°C.

[0220] Note that heat treatment may be performed after the gate insulating film 721 is formed. Preferably, the reaction is carried out under an atmosphere of nitrogen, ultra-dry air, or a rare gas (argon, helium, etc.). The temperature is 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. The content is 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less. In this embodiment, for example, heating is performed in a nitrogen atmosphere at 250° C. for 1 hour. Alternatively, before the conductive films 719 and 720 are formed, moisture or hydrogen is removed. Similar to the previous heat treatment performed on the oxide semiconductor layer to reduce R After the gate insulating film 721 containing oxygen is provided, heat treatment is performed. By performing the heat treatment, the oxide semiconductor layer 716 is oxidized. Even if oxygen vacancies occur in the oxide semiconductor layer 716, the oxide semiconductor is Oxygen is supplied to the conductor layer 716. Then, by supplying oxygen to the oxide semiconductor layer 716, As a result, oxygen vacancies serving as donors are reduced in the oxide semiconductor layer 716, and the stoichiometric composition is The oxide semiconductor layer 716 contains an oxide having a stoichiometric ratio exceeding the stoichiometric ratio. As a result, the oxide semiconductor layer 716 becomes closer to i-type. This reduces variations in the electrical characteristics of transistors due to oxygen vacancies, and improves the electrical characteristics. The timing of this heat treatment is determined by the thickness of the gate insulating film 721. There are no particular limitations as long as it is after formation, and other processes, such as heat treatment during resin film formation and transparent conductive By combining this with the heat treatment to reduce the resistance of the film, oxide semiconductor can be formed without increasing the number of processes. The conductor layer 716 can be made closer to i-type.

[0221] Further, by performing heat treatment on the oxide semiconductor layer 716 in an oxygen atmosphere, Oxygen may be added to reduce oxygen vacancies that serve as donors in the oxide semiconductor layer 716. The temperature of the heat treatment is, for example, 100°C or higher and lower than 350°C, preferably 150°C or higher and lower than 25°C. The heat treatment is carried out at a temperature below 0°C. The oxygen gas used in the heat treatment under the oxygen atmosphere does not contain water, hydrogen, etc. It is preferable that the purity of the oxygen gas introduced into the heat treatment device is not more than 6N( 99.9999%) or more, preferably 7N (99.99999%) or more (i.e., oxygen It is preferable to keep the impurity concentration at 1 ppm or less, preferably 0.1 ppm or less.

[0222] Alternatively, the oxide semiconductor layer 716 may be doped with an ion implantation method, an ion doping method, or the like. By adding oxygen, the oxygen vacancies that act as donors may be reduced. For example, 2.45G Oxygen plasma generated by microwaves at 100 Hz may be added to the oxide semiconductor layer 716 .

[0223] The gate electrode 722 and the conductive film 723 are formed by forming a conductive film on the gate insulating film 721. After that, the conductive film is etched to form the gate electrode 722 and The conductive film 723 and the gate electrode 707 are made of the same material as the conductive film 719 and the conductive film 720. It is possible to form it using a material.

[0224] The thickness of the gate electrode 722 and the conductive film 723 is 10 nm to 400 nm, preferably 10 In this embodiment, a sputtering process using a tungsten target is performed. After forming a conductive film for the gate electrode with a thickness of 150 nm by the photolithography method, the conductive film was removed by etching. The gate electrode 722 and the conductive film 723 are formed by etching the film into a desired shape. The resist mask may be formed by an ink-jet method. When formed by the jet method, no photomask is used, which reduces manufacturing costs.

[0225] Through the above steps, the transistor 109 is formed.

[0226] Note that the portion where the conductive film 719 and the conductive film 723 overlap with each other with the gate insulating film 721 interposed therebetween is , corresponds to the capacitance element 108.

[0227] Although the transistor 109 has been described as a single-gate transistor, If necessary, a plurality of electrically connected gate electrodes may be provided to form a channel forming region. A transistor having a multi-gate structure having a plurality of gate electrodes can also be formed.

[0228] Note that the insulating film in contact with the oxide semiconductor layer 716 (in this embodiment, the gate insulating film 721 applies.) may be made of an insulating material containing a group 13 element and oxygen. Many oxide semiconductor materials contain Group 13 elements, and insulating materials containing Group 13 elements has good compatibility with oxide semiconductors, and by using it for the insulating film in contact with the oxide semiconductor layer, The state of the interface with the oxide semiconductor layer can be kept good.

[0229] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide and aluminum oxide. gallium oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Aluminum gallium is a material that has a higher aluminum content (atomic %) than the gallium content (atomic %). Gallium aluminum oxide refers to the gallium content (atomic %) of indicates an aluminum content (atomic %) of 100 or more.

[0230] For example, when an insulating film is formed in contact with an oxide semiconductor layer containing gallium, By using a material containing gallium oxide, the interface characteristics between the oxide semiconductor layer and the insulating film can be maintained favorably. For example, an oxide semiconductor layer and an insulating film containing gallium oxide can be provided in contact with each other. This reduces the pile-up of hydrogen at the interface between the oxide semiconductor layer and the insulating film. When an element of the same group as the component element of the oxide semiconductor is used for the insulating film, For example, it is possible to obtain the same effect by using a material containing aluminum oxide. It is also effective to form a film of aluminum oxide, which has the characteristic of being difficult for water to pass through. Therefore, the use of this material is effective in preventing water from entering the oxide semiconductor layer. This is also preferable in this respect.

[0231] The insulating film in contact with the oxide semiconductor layer 716 is subjected to heat treatment in an oxygen atmosphere or oxygen deposition. It is preferable to make the insulating material have more oxygen than the stoichiometric composition ratio by using a groove or the like. Oxygen doping refers to adding oxygen to the bulk. The term is used to clarify that the element is added not only to the surface of the thin film but also to the inside of the thin film. Oxygen doping includes oxygen plasma doping, in which oxygen plasma is added to the bulk. The oxygen doping may be performed by ion implantation or ion doping.

[0232] For example, when gallium oxide is used as the insulating film in contact with the oxide semiconductor layer 716, oxygen By performing heat treatment under atmospheric conditions and oxygen doping, the composition of gallium oxide is changed to GaO X (X=3+α, 0<α<1).

[0233] When aluminum oxide is used as the insulating film in contact with the oxide semiconductor layer 716, By heat treatment in a nitrogen atmosphere or oxygen doping, the composition of aluminum oxide is changed to A l2O X (X=3+α, 0<α<1).

[0234] Further, an insulating film in contact with the oxide semiconductor layer 716 is formed of gallium aluminum oxide (aluminum oxide). When using aluminum gallium, heat treatment in an oxygen atmosphere or oxygen doping can be performed. By this, the composition of gallium aluminum oxide (aluminum gallium oxide) is Ga X Al 2-X O 3+α (0 <X<2、0<α<1)とすることができる。

[0235] By performing oxygen doping treatment, an insulating film having a region with more oxygen than the stoichiometric composition ratio is obtained. When the insulating film having such a region is in contact with the oxide semiconductor layer, As a result, excess oxygen in the insulating film is supplied to the oxide semiconductor layer, and oxygen is released into the oxide semiconductor layer or The oxide semiconductor layer is made i-type or It can be made as close as possible to the i-type.

[0236] Note that the insulating film having a region with more oxygen than the stoichiometric composition is the oxide semiconductor layer 716 Among the insulating films in contact with the It may be used in only one of the insulating films, but it is preferable to use it in both insulating films. The insulating film having a region with a higher oxygen content is formed on the upper and lower layers of the insulating film in contact with the oxide semiconductor layer 716. The above-mentioned effect can be achieved by using the insulating film as a lower insulating film and sandwiching the oxide semiconductor layer 716. can be further increased.

[0237] The insulating films used as the upper and lower layers of the oxide semiconductor layer 716 have the same structure. The insulating film may have an element, or may have a different element. For example, both the upper and lower layers have a composition of GaO X (X=3+α, 0<α<1) gallium oxide It is also acceptable that one of the upper layer and the lower layer has a composition of Ga2O X (X = 3 + α, 0 < α < 1) gallium oxide as lithium, and the other has a composition of Al2O X (X = 3 + α, 0 < α < 1) aluminum oxide and it is also acceptable.

[0238] In addition, the insulating film in contact with the oxide semiconductor layer 716 may be a stack of insulating films having a region where oxygen is more than the stoichiometric composition ratio. For example, on the upper layer of the oxide semiconductor layer 716, gallium oxide with a composition of Ga 2O is formed, and on this, gallium oxide aluminum with a composition of Ga X (X = 3 + α, 0 < α < 1) is formed, and on this, gallium aluminum oxide with a composition of Ga X Al 2-X O 3+α (0 < X < 2, 0 < α < 1) (aluminum gallium oxide) may be formed. Note that the lower layer of the oxide semiconductor layer 716 may be a stack of insulating films having a region where oxygen is more than the stoichiometric composition ratio, or both the upper layer and the lower layer of the oxide semiconductor layer 716 may be a stack of insulating films having a region where oxygen is more than the stoichiometric composition ratio. It is also acceptable. Next, as shown in FIG. 8(C), an insulating film 724 is formed so as to cover the gate insulating film 7, the conductive film 723, and the gate electrode 72[[ID=3,1]] 2. The insulating film 724 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, aluminum oxide, etc. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. It is also acceptable.

[0239] Next, as shown in FIG. 8(C), an insulating film 724 is formed so as to cover the gate insulating film 721, the conductive film 723, and the gate electrode 72[[ID=,39]] 2. The insulating film 724 can be formed using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, aluminum oxide, etc. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. using a method such as PVD or CVD. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, aluminum oxide, etc. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, aluminum oxide, etc. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, aluminum oxide, etc. Note that it is desirable to use a material having a low dielectric constant or a structure having a low dielectric constant (such as a porous structure) for the insulating film 724. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. structure, etc.) is used. By reducing the dielectric constant of the insulating film 724, the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. This is because the parasitic capacitance generated between wirings and electrodes can be reduced, and the operation speed can be increased. Note that although the insulating film 724 has a single-layer structure in this embodiment, one embodiment of the present invention However, the present invention is not limited to this, and a laminated structure of two or more layers may also be used.

[0240] Next, an opening 725 is formed in the gate insulating film 721 and the insulating film 724, and a portion of the conductive film 720 is Then, the conductive film 720 and the insulating film 724 are formed on the insulating film 724 in the opening 725. A contacting wiring 726 is formed.

[0241] The wiring 726 is formed by forming a conductive film using a PVD method or a CVD method, and then etching the conductive film. The conductive film is formed by a thin film process. An element selected from chromium, copper, tantalum, titanium, molybdenum, tungsten, or any of the above. Alloys containing the elements manganese, magnesium, zirconium, etc. can be used. Materials made of aluminum, beryllium, neodymium, scandium, or a combination of these Fees may also be used.

[0242] More specifically, for example, a titanium film is formed by PVD in the region including the opening of the insulating film 724. After forming a thin titanium film (about 5 nm) by PVD, an opening 725 A method of forming an aluminum film so as to embed the PV The titanium film formed by the D method reduces the oxide film (such as the natural oxide film) on the surface on which it is formed, It has a function of reducing contact resistance with an electrode or the like (here, the conductive film 720). It is possible to prevent hillocks in the aluminum film. After forming the rear film, a copper film may be formed by plating.

[0243] Next, an insulating film 727 is formed so as to cover the wiring 726. By the above-described series of steps, A memory element can be fabricated.

[0244] In the above manufacturing method, the conductive film 719 and the conductive film 720 functioning as a source electrode and a drain electrode are The conductive film 720 is formed after the oxide semiconductor layer 716. As shown in the figure, the transistor 109 obtained by the above manufacturing method has a conductive film 719 and a conductive film 720. A conductive film 720 is formed on the oxide semiconductor layer 716. However, in the transistor 10 9, a conductive film functioning as a source electrode and a drain electrode is formed under the oxide semiconductor layer 716. That is, the insulating film 712 is provided between the oxide semiconductor layer 716 and the insulating film 713. That's fine.

[0245] 9, a conductive film 719 and a conductive film 720 which function as a source electrode and a drain electrode are formed. , when the insulating film 712 is provided between the oxide semiconductor layer 716 and the insulating film 713, 9 is a cross-sectional view of the transistor 109. The transistor 109 shown in FIG. After the formation of the oxide semiconductor layer 716, the conductive films 719 and 720 are formed. The above-mentioned formation can be carried out to obtain the above-mentioned.

[0246] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0247] (Sixth embodiment) In this embodiment, a transistor using an oxide semiconductor layer having a structure different from that of Embodiment 5 will be described. The transistor will now be described.

[0248] A transistor 901 shown in FIG. 10A includes a gate insulating film 902 and a gate insulating film 903 as an active layer. and a source electrode 903 formed on the oxide semiconductor layer 903. The oxide semiconductor layer 903, the source electrode 904, and the drain electrode 905 are A gate insulating film 906 on the electrode 905 and an oxide semiconductor layer 9 903 and a gate electrode 907 provided at a position overlapping the gate electrode 903.

[0249] In the transistor 901 shown in FIG. 10A, a gate electrode 907 is formed on the oxide semiconductor layer 903. 904 and the drain electrode 905. The electrode 905 is a top-contact type formed on the oxide semiconductor layer 903. The transistor 901 has a source electrode 904, a drain electrode 905, and a gate electrode That is, the source electrode 904 and the drain electrode 905 do not overlap with the gate electrode 907. A gap larger than the thickness of the gate insulating film 906 is provided between the gate electrode 907 and the Therefore, the transistor 901 has a source electrode 904, a drain electrode 905, and a gate electrode The parasitic capacitance formed between the electrode 907 can be kept small, realizing high-speed operation. It is possible.

[0250] The oxide semiconductor layer 903 is formed by removing the oxide semiconductor layer 903 from the oxide semiconductor layer 903 after the gate electrode 907 is formed. A pair of high-concentration regions obtained by adding a dopant that gives n-type conductivity to 03 In addition, the oxide semiconductor layer 903 has a gate insulating film 906 sandwiched therebetween. A region overlapping with the gate electrode 907 is a channel formation region 909. In the semiconductor device, a channel forming region 909 is provided between a pair of high concentration regions 908. The dopant can be added to form the region 908 by ion implantation. Dopants include rare gases such as helium, argon, and xenon, as well as nitrogen, phosphorus, and arsenic. , antimony, and other group 15 atoms can be used.

[0251] For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 908 is , 5×10 19 / cm 3 More than 1×10 22 / cm 3 It is desirable that the following:

[0252] The high concentration region 908, to which a dopant that imparts n-type conductivity is added, is an oxide semiconductor. The high concentration region 908 is therefore made to be an oxide. By providing the semiconductor layer 903, the resistance between the source electrode 904 and the drain electrode 905 can be reduced. It can be done.

[0253] When an In-Ga-Zn-based oxide semiconductor is used for the oxide semiconductor layer 903, nitrogen is After adding, heat treatment is carried out at 300°C to 600°C for about an hour to obtain a high concentration The oxide semiconductor in the region 908 has a wurtzite crystal structure. The oxide semiconductor in 08 has a wurtzite crystal structure, which allows for a higher concentration region 908 and the resistance between the source electrode 904 and the drain electrode 905 can be reduced. Note that an oxide semiconductor having a wurtzite crystal structure is formed to form the source electrode 904. In order to effectively reduce the resistance between the drain electrodes 905, nitrogen is used as a dopant. In this case, the concentration of nitrogen atoms in the high concentration region 908 is set to 1×10 20 / cm 3 More than 7 atoms It is desirable to keep the nitrogen concentration below 5%. However, even if the nitrogen concentration is lower than the above range, In some cases, an oxide semiconductor having a wurtzite crystal structure can be obtained.

[0254] The oxide semiconductor layer 903 may be formed using an oxide containing CAAC. When the oxide semiconductor layer 903 is formed using an oxide containing CAAC, an amorphous Since the conductivity of the oxide semiconductor layer 903 can be increased compared to the case where the source electrode 90 4 and the drain electrode 905 can be reduced.

[0255] By reducing the resistance between the source electrode 904 and the drain electrode 905, the transistor Even if the size of the transistor 901 is further reduced, a high on-state current and high-speed operation can be ensured. In addition, by miniaturizing the transistor 901, the area occupied by a memory element using the transistor can be reduced. This reduces the product and increases the storage capacity per unit area.

[0256] The transistor 911 shown in FIG. 10B has a source electrode 9 formed over an insulating film 912. 914 and drain electrode 915, and a gate electrode formed on the source electrode 914 and drain electrode 915. The oxide semiconductor layer 913 functions as an active layer, and the oxide semiconductor layer 913 and the source electrode 9 14 and the gate insulating film 916 on the drain electrode 915, and A gate electrode 917 is provided so as to overlap with the oxide semiconductor layer 913 .

[0257] In the transistor 911 illustrated in FIG. 10B, the gate electrode 917 is formed on the oxide semiconductor layer 913. 914 and the drain electrode 915. The electrode 915 is a bottom-contact type formed under the oxide semiconductor layer 913. Similarly to the transistor 901, the transistor 911 has a source electrode 914 and a drain electrode 915. Since the source electrode 915 and the gate electrode 917 do not overlap, the source electrode 914 and the gate electrode 917 The parasitic capacitance formed between the drain electrode 915 and the gate electrode 917 can be reduced. This allows high-speed operation to be achieved.

[0258] The oxide semiconductor layer 913 is formed by removing the oxide semiconductor layer 913 after the gate electrode 917 is formed. A pair of high-concentration regions obtained by adding a dopant that gives n-type conductivity to 13 In addition, the oxide semiconductor layer 913 has a gate insulating film 918 therebetween. A region overlapping with the gate electrode 917 is a channel formation region 919. In the example, a channel forming region 919 is provided between a pair of high concentration regions 918 .

[0259] The high concentration region 918 is the same as the high concentration region 908 of the transistor 901 described above. Similarly, the high concentration region 918 can be formed by using the ion implantation method. The type of dopant used to form the high concentration region 908 can be referred to. Cut.

[0260] For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 918 is , 5×10 19 / cm 3 More than 1×10 22 / cm 3 It is desirable that the following:

[0261] The high concentration region 918, to which a dopant that imparts n-type conductivity is added, is an oxide semiconductor. The high concentration region 918 is therefore made to be an oxide. By providing the semiconductor layer 913, the resistance between the source electrode 914 and the drain electrode 915 can be reduced. It can be done.

[0262] When an In-Ga-Zn-based oxide semiconductor is used for the oxide semiconductor layer 913, nitrogen is After adding, by performing a heat treatment at about 300 to 600°C, the high concentration region 9 The oxide semiconductor in the high concentration region 918 has a wurtzite crystal structure. The oxide semiconductor has a wurtzite crystal structure, which further improves the conductivity of the high-concentration region 918. This can improve the conductivity and reduce the resistance between the source electrode 914 and the drain electrode 915. An oxide semiconductor having a wurtzite crystal structure is formed, and the source electrode 914 and the drain electrode 915 are formed. In order to effectively reduce the resistance between the silicon electrodes 915, nitrogen is used as a dopant. , the concentration of nitrogen atoms in the high-concentration region 918 is 1×10 20 / cm 3 More than 7atoms% However, even if the nitrogen atom concentration is lower than the above range, In some cases, an oxide semiconductor having a rhombohedral crystal structure can be obtained.

[0263] The oxide semiconductor layer 913 may be formed using an oxide containing CAAC. When the oxide semiconductor layer 913 is formed using an oxide containing CAAC, an amorphous Since the conductivity of the oxide semiconductor layer 913 can be increased compared to the case where the source electrode 91 4 and the drain electrode 915 can be reduced.

[0264] By reducing the resistance between the source electrode 914 and the drain electrode 915, the transistor Even if the size of the transistor 911 is further reduced, a high on-state current and high-speed operation can be ensured. In addition, by miniaturizing the transistor 911, the area occupied by a memory element using the transistor can be reduced. This reduces the product and increases the storage capacity per unit area.

[0265] A transistor 921 shown in FIG. 10C has a gate insulating film 922 formed thereon as an active layer. and a source electrode 9 formed on the oxide semiconductor layer 923. 24 and drain electrode 925, the oxide semiconductor layer 923, the source electrode 924 and drain electrode A gate insulating film 926 on the electrode 925 and an oxide semiconductor layer 9 The transistor 92 has a gate electrode 927 provided at a position overlapping with the transistor 92. 1 has a sidewall insulator 930 formed of an insulating film provided on the side of the gate electrode 927. do.

[0266] In the transistor 921 illustrated in FIG. 10C, the gate electrode 927 is formed on the oxide semiconductor layer 923. 924 and the drain electrode 925. The electrode 925 is a top-contact type formed on the oxide semiconductor layer 923. Similarly to the transistor 901, the transistor 921 has a source electrode 924 and a drain electrode 925. Since the source electrode 925 and the gate electrode 927 do not overlap, the source electrode 924 and the gate electrode 927 The parasitic capacitance formed between the drain electrode 925 and the gate electrode 927 can be reduced. This allows high-speed operation to be achieved.

[0267] The oxide semiconductor layer 923 is formed by removing the oxide semiconductor layer 923 from the oxide semiconductor layer 923 after the gate electrode 927 is formed. A pair of high-concentration regions obtained by adding a dopant that gives n-type conductivity to 23 The oxide semiconductor layer 923 has a pair of low-concentration regions 928 and a pair of low-concentration regions 929. The region overlapping the gate electrode 927 with the gate insulating film 926 sandwiched therebetween is a channel forming region 931 In the oxide semiconductor layer 923, a pair of low-concentration regions 928 is formed between a pair of high-concentration regions 928. A channel forming region 931 is provided between a pair of low concentration regions 929. The pair of low-concentration regions 929 are formed between the gate insulating film 92 and the oxide semiconductor layer 923. 6 is provided in an area overlapping with the sidewall insulator 930.

[0268] The high concentration region 928 and the low concentration region 929 are the high concentration regions of the transistor 901 described above. As in the case of the concentration region 908, it can be formed by using the ion implantation method. The type of dopant used to form the high concentration region 928 is the same as that used for the high concentration region 908. You can refer to the case.

[0269] For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 928 is , 5×10 19 / cm 3 More than 1×10 22 / cm 3 It is desirable that the following is true. For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the low concentration region 929 is 5 x10 18 / cm 3 5x10 or more 19 / cm 3 It is desirable that it be less than this.

[0270] The high concentration region 928, to which a dopant that imparts n-type conductivity is added, is an oxide semiconductor. The high concentration region 928 is therefore made to be an oxide. By providing the semiconductor layer 923, the resistance between the source electrode 924 and the drain electrode 925 can be reduced. In addition, the low concentration region 929 can be divided into a channel forming region 931 and a high concentration region 92 By providing it between 8, the negative shift of the threshold voltage due to the short channel effect can be reduced. can be done.

[0271] When an In-Ga-Zn-based oxide semiconductor is used for the oxide semiconductor layer 923, nitrogen is After adding, by performing a heat treatment at about 300 to 600°C, the high concentration region 9 The oxide semiconductor in 28 has a wurtzite crystal structure. Depending on the concentration of nitrogen, the region 929 may also have a wurtzite crystal structure due to the heat treatment. The oxide semiconductor in the high-concentration region 928 may have a wurtzite crystal structure. The conductivity of the high concentration region 928 is further increased, and the source electrode 924 and the drain electrode 925 The resistance between the layers can be reduced. Therefore, in order to effectively reduce the resistance between the source electrode 924 and the drain electrode 925, When nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 928 is set to 1×10 20 / cm 3 However, it is desirable that the nitrogen atoms be in the range of 100 to 700 atoms. Even if the concentration is lower than the above range, an oxide semiconductor having a wurtzite crystal structure may be obtained. There are also cases where this is the case.

[0272] The oxide semiconductor layer 923 may be formed using an oxide containing CAAC. When the oxide semiconductor layer 923 is formed using an oxide containing CAAC, an amorphous Since the conductivity of the oxide semiconductor layer 923 can be increased compared to the case where the source electrode 92 4 and the drain electrode 925 can be reduced.

[0273] By reducing the resistance between the source electrode 924 and the drain electrode 925, the transistor Even if the size of the transistor 921 is further reduced, a high on-state current and high-speed operation can be ensured. In addition, by miniaturizing the transistor 921, the area occupied by the memory cell using the transistor can be reduced. The area can be reduced and the storage capacity per unit area of ​​the cell array can be increased.

[0274] The transistor 941 shown in FIG. 10D has a source electrode 9 formed over an insulating film 942. 44 and drain electrode 945, and a gate electrode formed on the source electrode 944 and drain electrode 945. The oxide semiconductor layer 943 functions as an active layer, and the oxide semiconductor layer 943 and the source electrode 9 44 and a gate insulating film 946 on the drain electrode 945, and A gate electrode 947 is provided so as to overlap with the oxide semiconductor layer 943. The transistor 941 has a sidewall formed of an insulating film provided on the side of the gate electrode 947. It has an insulator 950 .

[0275] In the transistor 941 illustrated in FIG. 10D, the gate electrode 947 is formed on the oxide semiconductor layer 943. 944 and the drain electrode 945. The electrode 945 is a bottom-contact type formed under the oxide semiconductor layer 943. Similarly to the transistor 901, the transistor 941 has a source electrode 944 and a drain electrode 945. Since the source electrode 945 and the gate electrode 947 do not overlap, the source electrode 944 and the gate electrode 947 The parasitic capacitance formed between the drain electrode 945 and the gate electrode 947 can be reduced. This allows high-speed operation to be achieved.

[0276] The oxide semiconductor layer 943 is formed by removing the oxide semiconductor layer 943 from the oxide semiconductor layer 943 after the gate electrode 947 is formed. A pair of high-concentration regions obtained by adding a dopant that gives n-type conductivity to 43 The oxide semiconductor layer 943 has a pair of low-concentration regions 948 and a pair of low-concentration regions 949. The region overlapping the gate electrode 947 with the gate insulating film 946 sandwiched therebetween is a channel forming region 951 In the oxide semiconductor layer 943, a pair of low-concentration regions 948 is formed between a pair of high-concentration regions 948. A channel forming region 951 is provided between a pair of low concentration regions 949. The pair of low concentration regions 949 are formed in the oxide semiconductor layer 943 by the gate insulating film 94 6 is provided in an area overlapping the sidewall insulator 950.

[0277] The high concentration region 948 and the low concentration region 949 are the high concentration regions of the transistor 901 described above. As in the case of the concentration region 908, it can be formed by using the ion implantation method. The type of dopant used to form the high concentration region 948 is the same as that used for the high concentration region 908. You can refer to the case.

[0278] For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 948 is , 5×10 19 / cm 3 More than 1×10 22 / cm 3 It is desirable that the following is true. For example, when nitrogen is used as a dopant, the concentration of nitrogen atoms in the low concentration region 949 is 5 x10 18 / cm 3 5x10 or more 19 / cm 3 It is desirable that it be less than this.

[0279] The high concentration region 948, to which a dopant that imparts n-type conductivity is added, is an oxide semiconductor. The high concentration region 948 is therefore made to be an oxide. By providing the semiconductor layer 943, the resistance between the source electrode 944 and the drain electrode 945 can be reduced. In addition, the low concentration region 949 can be formed as a channel forming region 951 and a high concentration region 94 By providing it between 8, the negative shift of the threshold voltage due to the short channel effect can be reduced. can be done.

[0280] When an In-Ga-Zn-based oxide semiconductor is used for the oxide semiconductor layer 943, nitrogen is After adding, by performing a heat treatment at about 300 to 600°C, the high concentration region 9 The oxide semiconductor in 48 has a wurtzite crystal structure. Depending on the concentration of nitrogen, the region 949 may also have a wurtzite crystal structure due to the heat treatment. The oxide semiconductor in the high concentration region 948 may have a wurtzite crystal structure. The conductivity of the high concentration region 948 is further increased, and the source electrode 944 and the drain electrode 945 The resistance between the layers can be reduced. Therefore, in order to effectively reduce the resistance between the source electrode 944 and the drain electrode 945, When nitrogen is used as a dopant, the concentration of nitrogen atoms in the high concentration region 948 is set to 1×10 20 / cm 3 However, it is desirable that the nitrogen atoms be in the range of 100 to 700 atoms. Even if the concentration is lower than the above range, an oxide semiconductor having a wurtzite crystal structure may be obtained. There are also cases where this is the case.

[0281] The oxide semiconductor layer 943 may be formed using an oxide containing CAAC. When the oxide semiconductor layer 943 is formed using an oxide containing CAAC, an amorphous Since the conductivity of the oxide semiconductor layer 943 can be increased compared to the case where the source electrode 94 4 and the drain electrode 945 can be reduced.

[0282] By reducing the resistance between the source electrode 944 and the drain electrode 945, the transistor Even if the size of the transistor 941 is further reduced, a high on-state current and high-speed operation can be ensured. In addition, by miniaturizing the transistor 941, the area occupied by a memory element using the transistor can be reduced. This reduces the product and increases the storage capacity per unit area.

[0283] In a transistor including an oxide semiconductor, One method for fabricating high concentration regions that function as a self-aligned region is oxidation. The surface of the oxide semiconductor layer is exposed and subjected to argon plasma treatment. A method for reducing the resistivity of areas exposed to plasma is disclosed (S. Jeon et al. “180nm Gate Length Amorphous InGa ZnO Thin Film Transistor for High Densit y Image Sensor Applications”, IEDM Tech. Dig., pp.504-507, 2010.).

[0284] However, in the above manufacturing method, after forming the gate insulating film, the source region or the drain region is The gate insulating film must be partially removed to expose what will become the drain region. Therefore, when the gate insulating film is removed, the underlying oxide semiconductor layer is also partially over-etched. The film thickness of the portion that will become the source or drain region becomes smaller. As a result, the resistance of the source or drain region increases and over-etching This makes it more likely that transistor characteristics will be impaired due to aging.

[0285] To advance the miniaturization of transistors, it is necessary to adopt a dry etching method with high processing accuracy. However, the over-etching is necessary because the selectivity between the oxide semiconductor layer and the gate insulating film is low. This is particularly likely to occur when dry etching is used, in which sufficient etching efficiency cannot be ensured.

[0286] For example, if the oxide semiconductor layer is thick enough, over-etching is not a problem. However, when the channel length is set to 200 nm or less, the channel The thickness of the oxide semiconductor layer in the region that will become the panel formation region is 20 nm or less, preferably 10 nm or less. When dealing with such a thin oxide semiconductor layer, Over-etching of the semiconductor layer may result in the resistance of the source or drain region increasing as described above. This is undesirable because it causes a deterioration in the characteristics of the transistor.

[0287] However, as in one embodiment of the present invention, the dopant is added to the oxide semiconductor layer by By leaving the gate insulating film intact without exposing the conductor layer, the over-etching of the oxide semiconductor layer can be prevented. Etching can be prevented, and excessive damage to the oxide semiconductor layer can be reduced. In addition, the interface between the oxide semiconductor layer and the gate insulating film is kept clean. The characteristics and reliability of the device can be improved.

[0288] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0289] (Embodiment 7) In this embodiment, an oxide semiconductor having a structure different from that of the fifth and sixth embodiments is used. The following describes a transistor using an oxide semiconductor layer. The conductor is an oxide semiconductor containing In, Sn, and Zn (In-Sn-Zn oxide semiconductor). Alternatively, any of the oxide semiconductors described in other embodiments may be used.

[0290] Figure 31 shows the structure of a coplanar top-gate / top-contact transistor. 31(A) shows a top view of a transistor. FIG. 31B shows a cross section AB corresponding to the dashed line AB in FIG.

[0291] The transistor shown in FIG. 31B includes a substrate 1100 and a lower A base insulating film 1102, a protective insulating film 1104 provided around the base insulating film 1102, and a A high resistance region 1106a and a low resistance region 1106b are provided on the base insulating film 1102 and the protective insulating film 1104. The oxide semiconductor layer 1106 has a resistive region 1106b. The oxide semiconductor layer 1106 is formed by interposing the gate insulating film 1108 therebetween. A gate electrode 1110 is provided so as to overlap with the gate electrode 1110, and a gate electrode 1111 is provided so as to contact the side surface of the gate electrode 1110. a pair of sidewall insulating films 1112 provided in contact with at least the low resistance region 1106b; The electrode 1114, at least the oxide semiconductor layer 1106, the gate electrode 1110, and a pair of electrodes An interlayer insulating film 1116 is provided to cover the electrode 1114, and a Wiring 1118 is provided so as to be connected to at least one of the pair of electrodes 1114 through the opening. and,

[0292] Although not shown, a protective film is provided to cover the interlayer insulating film 1116 and the wiring 1118. By providing a protective film, the surface conduction of the interlayer insulating film 1116 can be prevented. This can reduce the minute leakage current that occurs due to the gate insulating film, thereby reducing the off-state current of the transistor. It is possible.

[0293] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0294] (Embodiment 8) In this embodiment, an oxide semiconductor having a structure different from that of the fifth to seventh embodiments is used. In this embodiment, a transistor using an oxide semiconductor layer is described. As the oxide semiconductor constituting the above, an oxide semiconductor containing In, Sn, and Zn (In-Sn Although a case where a Zn-based oxide semiconductor is used will be described, it will be explained in other embodiments. Other oxide semiconductors may also be used.

[0295] FIG. 32 is a top view and a cross-sectional view illustrating the structure of a transistor manufactured in this embodiment mode. FIG. 32(A) is a top view of a transistor. FIG. 32(B) is a top view of the transistor shown in FIG. FIG. 1 is a cross-sectional view corresponding to the dashed dotted line AB.

[0296] The transistor shown in FIG. 32B includes a substrate 1200 and a lower A base insulating film 1202, an oxide semiconductor layer 1206 provided on the base insulating film 1202, and an oxide semiconductor layer 1206 a pair of electrodes 1214 in contact with the oxide semiconductor layer 1206; A gate insulating film 1208 is provided on the pair of electrodes 1214, and A gate electrode 1210 is provided to overlap with the oxide semiconductor layer 1206, and a gate insulating film 1 208 and the gate electrode 1210, and an interlayer insulating film 1216 provided to cover the gate electrode 1210. Wiring 1218 is connected to the pair of electrodes 1214 through an opening provided in layer 1216, and and a protective film 1220 provided to cover the interlayer insulating film 1216 and the wiring 1218.

[0297] The substrate 1200 is a glass substrate, the base insulating film 1202 is a silicon oxide film, The oxide semiconductor layer 1206 is an In—Sn—Zn oxide film, and the pair of electrodes 1214 is a tungsten film as the gate insulating film 1208, a silicon oxide film as the gate electrode The layer 1210 is a laminated structure of a tantalum nitride film and a tungsten film, and the interlayer insulating film 1216 The wiring 1218 is a laminated structure of a silicon oxynitride film and a polyimide film. The laminated structure in which the silicon film, the aluminum film, and the titanium film are formed in this order is used as the protective film 1220. A polyimide film was used for each of the electrodes.

[0298] In the transistor having the structure shown in FIG. 32A, the gate electrode 1210 and the pair of The overlap width with the electrode 1214 is referred to as Lov. The protrusion of the pair of electrodes 1214 is called dW.

[0299] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0300] (Embodiment 9) In this embodiment, one mode of a structure of a memory device will be described.

[0301] 11 and 12 are cross-sectional views of the storage device. The memory device 3002 has a plurality of memory elements formed in multiple layers in the upper portion and a logic circuit 3004 in the lower portion. Among these memory elements, memory elements 3170a and 3170b are shown as representatives. The memory element 3170a and the memory element 3170b may be, for example, the memory element 3170a described in the above embodiment. Alternatively, the memory circuit 102 may have the same configuration as the memory circuit 102.

[0302] Note that the transistor 3171a included in the memory element 3170a is shown as a representative. The transistor 3171b included in 3170b is shown as a representative. The transistor 3171b has a channel formation region in an oxide semiconductor layer. The structure of the transistor in which the channel forming region is formed in the semiconductor layer may be the same as that of other embodiments. Since the configuration is the same as that described in the previous embodiment, the description will be omitted.

[0303] The electrode 35 formed in the same layer as the source electrode and the drain electrode of the transistor 3171a 3001a is electrically connected to electrode 3003a via electrode 3502a. The electrode 3501c formed in the same layer as the source and drain electrodes of the transistor 3171b , and is electrically connected to electrode 3003c via electrode 3502c.

[0304] The logic circuit 3004 uses a semiconductor material other than an oxide semiconductor as a channel formation region. The transistor 3001 is made of a semiconductor material (e.g., An element isolation insulating film 3106 is provided on a substrate 3000 containing silicon or the like, The region surrounded by 106 is used to form a channel forming region. The transistor 3001 can be formed on an insulating surface. A channel formation region is formed in a semiconductor film such as a silicon film or a silicon film of an SOI substrate. The transistor 3001 may have a known structure. Since it is possible to do so, the explanation will be omitted.

[0305] The layer in which the transistor 3171a is formed and the layer in which the transistor 3001 is formed Between them, a wiring 3100a and a wiring 3100b are formed. An insulating film 3140a is provided between the layer on which the resistor 3001 is formed and the wiring 3100 An insulating film 3141a is provided between the wiring 3100a and the transistor 3100b. An insulating film 3142a is provided between the layer on which the resistor 3171a is formed and the insulating film 3142b.

[0306] Similarly, the layer in which the transistor 3171b is formed and the layer in which the transistor 3171a is formed are Between the layer and the wiring 3100, a wiring 3100c and a wiring 3100d are formed. an insulating film 3140b is provided between the layer in which the transistor 3171a is formed and the layer in which the transistor 3171a is formed; An insulating film 3141b is provided between the wiring 3100c and the wiring 3100d. An insulating film 3142b is provided between the layer 0d and the layer in which the transistor 3171b is formed. are.

[0307] Insulating film 3140a, insulating film 3141a, insulating film 3142a, insulating film 3140b, insulating film The insulating film 3141b and the insulating film 3142b function as an interlayer insulating film, and the surface thereof is flattened. It can be concluded that

[0308] The wiring 3100a, the wiring 3100b, the wiring 3100c, and the wiring 3100d Electrical connection between the elements, and electrical connection between the logic circuit 3004 and the memory element can be performed. .

[0309] The electrode 3303 included in the logic circuit 3004 is electrically connected to the circuit provided above. It is possible.

[0310] For example, as shown in FIG. 11, the electrode 3505 connects the electrode 3303 to the wiring 3100a. The wiring 3100a can be electrically connected to the electrode 350 by the electrode 3503a. 1b. In this way, the wiring 3100a and the electrode 3303 can be electrically connected to each other. It can be electrically connected to the source or drain of the transistor 3171a. The electrode 3501b is electrically connected to the electrode 3003b via the electrode 3502b. The electrode 3003b is electrically connected to the wiring 3100c via the electrode 3503b. It is possible.

[0311] In FIG. 11, the electrode 3303 and the transistor 3171a are electrically connected to each other through the wiring 3100. However, this is not limited to the example in which the electrode 3303 and the transistor 31 The electrical connection with 71a may be made via wiring 3100b, or via wiring 3100a. 12, the electrode 330 may be connected to the wiring 3100b. The electrical connection between the transistor 3171a and the transistor 3171b is not via the wiring 3100a or the wiring 3100b. In FIG. 12, the electrode 3303 is connected to the electrode 3003 by the electrode 3503. The electrode 3003b is electrically connected to the source or is electrically connected to the drain of the transistor 3171a. The electrical connection can be made as follows.

[0312] 11 and 12, two storage elements (storage element 3170a and storage element 3170b) are shown. 70b) is shown as an example of a stacked configuration, but the number of stacked memory elements is not limited to this. do not have.

[0313] 11 and 12, the layer in which the transistor 3171a is formed and the layer in which the transistor 3171b is formed are Between the layer on which the electrode 3001 is formed and the layer on which the electrode 3002 is formed, there is a wiring layer on which the wiring 3100a is formed and a wiring 3100b. Although the configuration in which two wiring layers are provided, one of which is a wiring layer in which 00b is formed, is shown, the present invention is not limited to this. The layer in which the transistor 3171a is formed and the layer in which the transistor 3001 is formed are not formed. Between the layers, one wiring layer may be provided, or three or more wiring layers may be provided. That's fine.

[0314] 11 and 12, the layer in which the transistor 3171b is formed and the layer in which the transistor 3171b is formed are Between the layer on which the electrode 3171a is formed and the layer on which the electrode 3171b is formed, there is a wiring layer on which the wiring 3100c is formed and a wiring 3100b. Although the configuration in which two wiring layers are provided, including the wiring layer in which 100d is formed, is not limited to this. The layer in which the transistor 3171b is formed and the layer in which the transistor 3171a is formed are not formed. Between the layers, one wiring layer may be provided, or three or more wiring layers may be provided. It may be possible.

[0315] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0316] (Embodiment 10) In this embodiment, the field effect mobility of the transistor described in the above embodiment will be I will explain.

[0317] The field-effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured. The mobility of electrons is lower than the original mobility due to various reasons. There are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using this method, we can theoretically derive the field-effect mobility assuming that there are no defects inside the semiconductor. Therefore, in this embodiment, an ideal oxide semiconductor with no defects inside the semiconductor can be obtained. The field effect mobility is theoretically derived, and fine transistors are fabricated using such oxide semiconductors. The calculation results of the characteristics when a transistor is fabricated are shown below.

[0318] Let μ0 be the intrinsic mobility of the semiconductor, and μ be the measured field-effect mobility. Assuming the existence of a potential barrier (grain boundary, etc.), this can be expressed by the following equation.

[0319]

number

[0320] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In addition, if we assume that the potential barrier originates from defects, then in the Levinson model, is expressed by the following formula:

[0321]

number

[0322] where e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the semiconductor is the dielectric constant of the channel, n is the number of carriers contained in the channel per unit area, C ox is per unit area capacitance, V gis the gate voltage, and t is the channel thickness. If the layer is a conductor, the thickness of the channel may be the same as the thickness of the semiconductor layer. Drain current I d becomes:

[0323]

number

[0324] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, V d is the drain voltage (voltage between the source and drain). g in Dividing this by 1 and then taking the logarithm of both sides gives us the following:

[0325]

number

[0326] The right side of number 5 is V g As can be seen from this equation, the vertical axis is a function of ln(I d / V g ) , the horizontal axis is 1 / V g The defect density can be calculated from the slope of the line on the graph obtained by plotting the measured values ​​as N is calculated. That is, the I d -V g The defect density can be evaluated from the characteristics For oxide semiconductors, the ratio of indium (In), tin (Sn), and zinc (Zn) is: In the case of In:Sn:Zn=1:1:1, the defect density N is 1×10 12 / cm 2 To an extent .

[0327] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / V The mobility measured in the defective In-Sn-Zn oxide system is 40 cm 2 However, there is no defect inside the semiconductor or at the interface between the semiconductor and the insulating layer. The mobility μ0 of semiconductor compounds is 120 cm 2 It can be expected that / Vs.

[0328] However, even if there are no defects inside the semiconductor, scattering at the interface between the channel and the gate insulating film can cause The transport characteristics of the transistor are affected by the distance x from the gate insulating film interface. The mobility μ1 at the location is expressed by the following formula:

[0329]

number

[0330] Here, D is the electric field in the gate direction, and B and G are constants. B and G are determined by actual measurements. From the above measurement results, B = 4.75 × 10 7 cm / s, G=10 nm (depth of interface scattering). D increases (i.e., gate voltage increases). Since the second term in equation 6 increases, the mobility μ1 decreases.

[0331] Transistor transfer using an ideal oxide semiconductor channel with no internal defects The results of calculating the degree μ2 are shown in Figure 19. The calculation was performed using a Synopsys device simulator. Sentaurus Device is a software application for bandgap measurement of oxide semiconductors. The gap, electron affinity, relative permittivity, and thickness are 2.8 eV and 4.7 eV, respectively. These values ​​were measured for thin films formed by sputtering. This was obtained by doing so.

[0332] Furthermore, the work functions of the gate, source, and drain are set to 5.5 eV and 4.6 eV, respectively. The gate insulating film thickness was 100 nm and the dielectric constant was 4.6 eV. The channel length and width were both 10 μm, and the drain voltage V d is 0 .1V.

[0333] As shown in Figure 19, the gate voltage V g At just over 1V, the mobility is 100cm 2 / Vs or more However, if the gate voltage is further increased, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, it is necessary to flatten the semiconductor layer surface at the atomic level. and (Atomic Layer Flatness) are desirable.

[0334] When a miniaturized transistor is manufactured using an oxide semiconductor having such mobility, The results of calculating the characteristics are shown in Figures 20 to 22. Note that the cross section of the transistor used in the calculations The structure is shown in Figure 23. The transistor shown in Figure 23 has an n-type oxide semiconductor layer. + Conductivity type The semiconductor regions 1303a and 1303c are formed by the semiconductor regions 1303a and 1303c. The resistivity of the semiconductor region 1303c is 2×10 -3 Let it be Ωcm.

[0335] The transistor shown in FIG. 23A includes a base insulating film 1301 and a The aluminum oxide insulator 1302 is formed on the surface of the insulator 1302. The transistor is made up of a semiconductor region 1303a, a semiconductor region 1303c, and a semiconductor region sandwiched between them. The semiconductor layer 1303 has an intrinsic semiconductor region 1303b which becomes a channel forming region and a gate electrode 1305. The width of the gate electrode 1305 is set to 33 nm.

[0336] A gate insulating layer 1304 is provided between the gate electrode 1305 and the semiconductor region 1303b. In addition, sidewall insulators 1306a and 1306b are formed on both sides of the gate electrode 1305. On the top of the gate electrode 1305, a thin film is formed to prevent short-circuiting between the gate electrode 1305 and other wirings. The width of the sidewall insulator is set to 5 nm. 3a and a semiconductor region 1303c, and a source 1308a and a drain 1308b are provided. The channel width of this transistor is set to 40 nm.

[0337] The transistor shown in FIG. 23B has a base insulating film 1301 and a thin film transistor made of aluminum oxide. The semiconductor region 1303a and the semiconductor region 1303b are formed on the buried insulator 1302. c, an intrinsic semiconductor region 1303b sandwiched therebetween, and a gate electrode 130 5, the gate insulating layer 1304, the sidewall insulator 1306a, the sidewall insulator 1306b, and the insulator 1 23(A) at the point where the transistor 307 has a source 1308a and a drain 1308b. It is the same as Transistor.

[0338] The difference between the transistor shown in FIG. 23A and the transistor shown in FIG. 23B is that the sidewall The conductivity type of the semiconductor region under the insulator 1306a and the sidewall insulator 1306b. In the transistor shown in A), the half under the sidewall insulator 1306a and the sidewall insulator 1306b The conductor area is n + The semiconductor regions 1303a and 1303c have the same conductivity type. However, in the transistor shown in FIG. 23(B), it is an intrinsic semiconductor region 1303b. That is, in the semiconductor layer shown in FIG. 23(B), the semiconductor region 1303a (semiconductor region 1303 c) and the gate electrode 1305 do not overlap by Loff. The offset length is called the offset area, and its width Loff is called the offset length. The set length is the same as the width of the sidewall insulator 1306a (sidewall insulator 1306b).

[0339] The other parameters used in the calculation are as described above. We used the Sentaurus Device, a chair simulation software. , the drain current (I d , solid line) and mobility (μ, dotted line) gate voltage (V g The drain voltage (gate-source potential difference) dependence is shown. Flow I d is the drain voltage V d (potential difference between drain and source) is set to +1V, and the mobility μ is Rain voltage V d This is calculated assuming that the voltage is +0.1V.

[0340] FIG. 20(A) shows the case where the thickness of the gate insulating film is 15 nm, and FIG. 20(B) shows the case where the thickness of the gate insulating film is 10 In Figure 20(C), the thickness is set to 5 nm. The drain current I d On the other hand, the off-state current (OFF current) is significantly reduced. The peak value of the temperature μ and the drain current I d There is no noticeable change in the on-state current.

[0341] FIG. 21 shows the offset length Loff of the transistor having the structure shown in FIG. 23(B). nm, the drain current I d (solid line) and mobility μ (dotted line) depending on gate voltage Vg The drain current I d is the drain voltage V d is set to +1V, and the mobility μ is the drain voltage Pressure V d The calculation was performed with the gate insulating film thickness set to +0.1V. 21(B) is for 5 nm, FIG. 21(B) is for 10 nm, and FIG. 21(C) is for 5 The value is nm.

[0342] FIG. 22 shows the offset length Lof The drain current I d (solid line) and mobility μ (dotted line) V g The drain current I d is the drain voltage V d is set to +1V, and the mobility μ is Rain voltage V d The calculation was performed with the gate insulating film set at +0.1V. The thickness is set to 15 nm in FIG. 22(A), 10 nm in FIG. 22(B), and C) is set to 5 nm.

[0343] In both cases, the thinner the gate insulating film, the more significantly the off-state current decreases, while the peak of the mobility μ There is no noticeable change in the peak value or on-state current.

[0344] The peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 21 0cm 2 / Vs, 40cm in Figure 22 2 / Vs, the offset length Loff increases The off-current also shows a similar trend. On the other hand, the on-current also decreases with increasing offset length. It decreases with increasing Loff, but the decrease is much slower than the decrease in off-state current. do.

[0345] (Embodiment 11) In this embodiment, an oxide semiconductor film containing In, Sn, and Zn as main components (In- Transistors using a Sn-Zn oxide semiconductor film (an example) in the channel formation region explain.

[0346] An oxide semiconductor film containing In, Sn, and Zn as its main components was used for the channel formation region. The transistor is formed by heating the substrate when forming the oxide semiconductor film. Alternatively, heat treatment can be performed after the oxide semiconductor film is formed to obtain favorable characteristics. The term "major component" refers to an element that is contained in a composition ratio of 5 atomic % or more.

[0347] When forming an oxide semiconductor film containing In, Sn, and Zn as main components, the substrate is intentionally By forming the film under a partially heated condition, the field effect mobility of the transistor can be improved. In addition, the threshold voltage of the transistor is shifted to the positive side, resulting in a normally-off state. It is possible to do this.

[0348] For example, Figs. 24(A) to (C) show the results of the analysis of the SiO2 alloy containing In, Sn, and Zn as the main components. The oxide semiconductor film has a channel length L of 3 μm and a channel width W of 10 μm, and a gate electrode with a thickness of 100 nm. 1 is a diagram showing the electrical characteristics of a transistor using a gate insulating film. d was set to 10V .

[0349] Figure 24(A) shows the results of sputtering In, Sn, and Zn without intentionally heating the substrate. 10A and 10B are diagrams showing transistor characteristics when an oxide semiconductor film containing the oxide semiconductor as a main component is formed. When 2 On the other hand, the board is When an oxide semiconductor film containing In, Sn, and Zn as its main components is formed by heating the film, an electric field The substrate is heated to 200°C, and the I Transistor characteristics when an oxide semiconductor film containing n, Sn, and Zn as main components is formed The field effect mobility μ is 32.2 cm 2 / Vsec is obtained.

[0350] The field-effect mobility is improved by forming an oxide semiconductor film containing In, Sn, and Zn as main components. This can be further enhanced by heat treatment after the heating. An oxide semiconductor film containing Sn and Zn as its main components was formed by sputtering at 200°C. The transistor characteristics are shown after heat treatment at 650°C. At this time, the field effect mobility is 34.5cm 2 / Vsec is obtained.

[0351] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during sputtering. In addition, by performing a heat treatment after film formation, Hydrogen, a hydroxyl group, or moisture can be released and removed from the oxide semiconductor film. The field effect mobility can be improved as follows. In addition to removing impurities through hydration and dehydrogenation, the interatomic distance is shortened by densification. It is also estimated that crystallization can be achieved by removing impurities from oxide semiconductors and purifying them. Such a highly purified non-single-crystal oxide semiconductor can be ideally 00cm 2 It is estimated that it will be possible to achieve a field-effect mobility of more than 1 / Vsec. .

[0352] In addition, oxygen ions are implanted into an oxide semiconductor film containing In, Sn, and Zn as main components. The heat treatment causes hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor to be released, and the heat The oxide semiconductor may be crystallized by heat treatment simultaneously with or after the treatment. A non-single-crystal oxide semiconductor with good crystallinity can be obtained by crystallization or recrystallization. Cut.

[0353] The effects of intentionally heating the substrate to form the film and / or performing heat treatment after film formation are as follows: Not only does it improve field-effect mobility, but it also contributes to making transistors normally off. The substrate was not intentionally heated, and the main components were In, Sn, and Zn. A transistor in which an oxide semiconductor film containing the oxide semiconductor film has a channel formation region has a threshold voltage of minus However, oxide semiconductors formed by intentionally heating the substrate tend to shift. When a film is used, this negative shift in threshold voltage is eliminated. The voltage moves in the direction that the transistor becomes normally off, and this tendency is shown in Figure 24(A). This can also be confirmed by comparing Figure 24(B) with Figure 24(C).

[0354] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. By setting the composition ratio to In:Sn:Zn=2:1:3, Normally-off operation can be realized. In addition, the composition ratio of the target is In:Sn:Z When n=2:1:3, an oxide semiconductor film with high crystallinity can be realized.

[0355] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher. The temperature is preferably 400°C or higher, and the film is formed or heat-treated at a higher temperature. This makes it possible to make the transistor normally off.

[0356] In addition, intentionally heating the substrate during film formation and / or performing heat treatment after film formation can cause gate Stability against bias stress can be improved. For example, 2MV / cm, 15 When applied for 1 hour at 0°C, the drift should be less than ±1.5V, preferably 1. Less than 0V can be obtained.

[0357] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor film formation, and Sample 2 was subjected to heat treatment at 650°C. The processed transistor of sample 2 was subjected to a BT test.

[0358] First, the substrate temperature is set to 25°C, and V d is set to 10V, and the V of the transistor g -I d Measurement of characteristics Next, the substrate temperature was set to 150°C, and V d was set to 0.1V. Next, the gate insulating film V so that the electric field strength applied to is 2MV / cm g Apply 20V to the Then, V g Next, the substrate temperature was set to 25°C, and V d is set to 10V, Transistor V g -I d This measurement was called the Plus BT test.

[0359] Similarly, first set the substrate temperature to 25°C, and then V dis set to 10V, and the V of the transistor g -I d Special Next, the substrate temperature was set to 150°C, and V d was set to 0.1V. The V is set so that the electric field strength applied to the insulating film is -2MV / cm. g Apply -20V to This was kept for 1 hour. g Next, the substrate temperature was set to 25°C, and V d of 10V, and the transistor's V g -I d This is called the minus BT test.

[0360] The results of the positive BT test for sample 1 are shown in Figure 25(A), and the results of the negative BT test are shown in Figure 25(B). The results of the positive BT test for sample 2 are shown in Figure 26(A), and the results of the negative BT test for sample 2 are shown in Figure 26(B). The results are shown in Figure 26(B).

[0361] The threshold voltage fluctuations of sample 1 due to the positive BT test and the negative BT test are as follows: The positive and negative BT tests for sample 2 were 1.80V and 0.42V. The threshold voltage fluctuations due to the experiment were 0.79 V and 0.76 V, respectively. Both sample 1 and sample 2 showed small fluctuations in threshold voltage before and after the BT test, demonstrating high reliability. We can see that.

[0362] The heat treatment can be carried out in an oxygen atmosphere, but it is first necessary to use nitrogen or an inert gas, or a reducing gas. Alternatively, heat treatment may be carried out under pressure and then in an oxygen-containing atmosphere. By adding oxygen to the oxide semiconductor after dehydrogenation, the effect of the heat treatment can be further enhanced. To add oxygen later, oxygen ions can be accelerated by an electric field to form a thin film on the oxide semiconductor. A method of injecting the membrane may also be applied.

[0363] Oxygen vacancies easily cause defects in the oxide semiconductor and at the interface with the stacked film. However, by making the oxide semiconductor contain excess oxygen through such heat treatment, The oxygen vacancies that are created can be compensated for by excess oxygen. The oxygen present between them is 1×10 16 / cm 3 Over 2×10 20 / cm 3 If the above conditions are met, the compound can be contained in the oxide semiconductor without causing distortion or the like to the crystal. .

[0364] Furthermore, the heat treatment is performed so that at least a part of the oxide semiconductor contains crystals. For example, a more stable oxide semiconductor film can be obtained when the composition ratio is In:Sn:Zn= Acid film formed by sputtering using a 1:1:1 target without intentionally heating the substrate The compound semiconductor film was found to have halo patterns by X-ray diffraction (XRD). The oxide semiconductor film thus formed is crystallized by heat treatment. The heat treatment temperature can be any temperature, but for example, by performing heat treatment at 650°C, X Clear diffraction peaks can be observed by X-ray diffraction.

[0365] In fact, XRD analysis of the In-Sn-Zn oxide film was carried out. Out-of-Plane analysis was performed using the D8 ADVANCE X-ray diffractometer manufactured by Ker AXS. Measured using the e method.

[0366] Samples A and B were prepared for XRD analysis. The method for producing B will be explained.

[0367] First, a 100 nm thick In-Sn-Zn oxide film was formed on a dehydrogenated quartz substrate. The film was formed at 1000 nm.

[0368] The In-Sn-Zn oxide film was prepared by sputtering in an oxygen atmosphere at a power of 10 The target was In:Sn:Zn=1:1:1 [atomic ratio]. The substrate heating temperature during film formation was 200°C. The sample prepared in this manner was designated as sample A.

[0369] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for 1 hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to a further heat treatment at 400 K for 1 hour.

[0370] Figure 27 shows the XRD spectra of sample A and sample B. In sample A, peaks derived from crystals was not observed, but in sample B, 2θ was around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed.

[0371] Thus, oxide semiconductors containing In, Sn, and Zn as their main components are not intentionally formed during film formation. Transistor characteristics are improved by thermally heating the film and / or by heat treatment after film formation. It can be done.

[0372] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. It has the effect of preventing oxides from being included in the film or removing them from the film. High purity can be achieved by removing hydrogen, which acts as a donor impurity in semiconductors. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By doing so, the off-current can be reduced to 1 aA / μm or less. The unit indicates the current value per 1 μm of channel width.

[0373] Figure 28 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) when measuring the off-state current. For simplicity, the value is calculated by multiplying the reciprocal of the substrate temperature at the time of measurement by 1000. As shown in Figure 28, when the substrate temperature is 125°C, is 1aA / μm (1×10 -18 A / μm) or less, and at 85°C, 100zA / μm ( 1×10 -19 A / μm) or less, and at room temperature (27°C) 1zA / μm (1×10 -2 1 Preferably, it can be 0.1 aA / μm at 125°C. (1×10 -19 A / μm) or less at 85°C, -20 A / μm) or less at room temperature, -22 A / μm or less It is possible.

[0374] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during the film formation, Leaks from the nozzle and outgassing from the inner walls of the deposition chamber are sufficiently suppressed, achieving high purity of sputtering gas. For example, the sputtering gas should have a dew point of -70°C so that moisture is not contained in the film. It is preferable to use a gas that is equal to or less than the above. It is preferable to use a highly purified target so that it does not contain impurities. The oxide semiconductor containing In, Sn, and Zn as its main components can be easily removed by heat treatment. However, compared to oxide semiconductors containing In, Ga, and Zn as the main components, Since the temperature at which moisture is released is high, it is preferable to form a film that does not contain moisture from the beginning. It is preferable that:

[0375] In addition, in the transistor of Sample B, which was subjected to heat treatment at 650° C. after the formation of the oxide semiconductor film, The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0376] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and v is 0 μm and dW is 0 μm. d The voltage was set to 10 V. The substrate temperature was -40 The test was carried out at temperatures of 25°C, -25°C, 25°C, 75°C, 125°C and 150°C. In this case, the overlap width between the gate electrode and the pair of electrodes is called Lov, and The protrusion of the pair of electrodes is called dW.

[0377] In Figure 29, I d (solid line) and field-effect mobility (dotted line) g The dependency is shown in Figure 3. Fig. 30(A) shows the relationship between the substrate temperature and the threshold voltage, and Fig. 30(B) shows the relationship between the substrate temperature and the field-effect mobility. The relationship is shown below.

[0378] From FIG. 30(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The voltage range was 1.09V to -0.23V from -40℃ to 150℃.

[0379] Furthermore, it can be seen from FIG. 30(B) that the higher the substrate temperature, the lower the field-effect mobility. The temperature range is -40℃ to 150℃ and 36cm 2 / Vs~32cm 2 / Vs Therefore, it can be seen that the fluctuation of the electrical characteristics is small within the above temperature range.

[0380] The oxide semiconductor containing In, Sn, and Zn as main components is used as the channel forming region. The transistors in this region have achieved field-effect mobility while maintaining the off-state current below 1 aA / μm. degrees to 30cm 2 / Vsec or more, preferably 40cm 2 / Vsec or more, more preferably 60cm 2 / Vsec or more, and the on-current value required by the LSI can be satisfied. For example, in a FET with L / W=33nm / 40nm, the gate voltage is 2.7V and the drain voltage is At 1.0V, an on-current of 12μA or more can flow. Even in the required temperature range, sufficient electrical characteristics can be ensured. In terms of characteristics, a transistor made of oxide semiconductor in an integrated circuit made of Si semiconductor It is possible to realize an integrated circuit with new functions without sacrificing operating speed even when incorporating a microcomputer. It is possible.

[0381] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0382] By using a signal processing circuit according to one embodiment of the present invention, an electronic device with low power consumption can be provided. This is especially true for portable electronic devices that are difficult to power all the time. By adding a low-power signal processing circuit according to one embodiment of the present invention to the components thereof, This has the advantage of extending the continuous operating time. By using a transistor, redundant circuit design to compensate for high off-state current is no longer necessary. Therefore, it is possible to increase the integration density of the signal processing circuit and improve the functionality of the signal processing circuit. can.

[0383] A signal processing circuit according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, Image playback devices equipped with DVD (Digital Versatile Disc) Used for devices that have a display that can play back recording media such as SC and display the images In addition, an electronic device in which the signal processing circuit according to one embodiment of the present invention can be used Devices include mobile phones, handheld game consoles, personal digital assistants, e-books, and video cameras. , digital still camera, goggle-type display (head-mounted display), Navigation systems, audio playback devices (car audio, digital audio players) etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATM), vending machines, etc.

[0384] The signal processing circuit according to one aspect of the present invention is used in a mobile phone, a smartphone, an e-book reader, or the like. The application of this technology to a mobile electronic device will now be described.

[0385] Figure 13 is a block diagram of a portable electronic device. The portable electronic device shown in Figure 13 is a R F circuit 421, analog baseband circuit 422, digital baseband circuit 423, Battery 424, power supply circuit 425, application processor 426, flash memory 430, a display controller 431, a memory circuit 432, a display 433, It is composed of a touch sensor 439, an audio circuit 437, a keyboard 438, etc. The spray 433 is driven by a display unit 434, a source driver 435, and a gate driver 436. The application processor 426 is composed of a CPU 427, a DSP 428, and an The CPU 427 has an interface 429. The signal processing circuit shown in the above embodiment is By adopting a memory circuit, power consumption can be reduced. The memory circuit 432 is composed of an SRAM or a DRAM. By adopting the memory device shown in the above embodiment, it is possible to reduce power consumption.

[0386] FIG. 14 is a block diagram showing the configuration of the memory circuit 432. The memory circuit 432 is a storage device. a memory device 442, a memory device 443, a switch 444, a switch 445, and a memory controller It has 441.

[0387] First, some image data is received in a portable electronic device or an application. This image data is generated by the image processor 426 via the switch 444. The image data is then stored in the storage device 442. The image data is then output via the switch 444. The image data is sent to the display 433 via the display controller 431. Ray 433 uses the image data to display the image.

[0388] If the image displayed is unchanged, such as a still image, the frequency is usually around 30Hz to 60Hz. At this time, image data read from the storage device 442 is transmitted to the display via the switch 445. The image displayed on the screen is continuously sent to the play controller 431. When a change operation is performed, the application processor 426 forms new image data. The image data is stored in the storage device 443 via the switch 444. While the image data is being stored in the storage device 443, the image data is being switched from the storage device 442. Image data is periodically read out via switch 445 .

[0389] When the storage of new image data in the storage device 443 is completed, the storage device 443 starts storing the image data from the next frame period. The new image data stored in the memory device 443 is read out, and the switch 445, the display The image data is sent to the display 433 via the image controller 431. The spray 433 uses the new image data sent to display the image.

[0390] This reading of the image data is performed after the next new image data is stored in the storage device 442. In this way, the storage device 442 and the storage device 443 alternately store image data. The display 433 displays images.

[0391] The storage device 442 and the storage device 443 are not limited to separate storage devices, but may be one storage device. The memory area of ​​the device may be divided and used. By adopting the storage device shown in this embodiment, it is possible to reduce power consumption.

[0392] FIG. 15 is a block diagram of an electronic book. The electronic book has a battery 451, a power supply circuit 452, and , microprocessor 453, flash memory 454, audio circuit 455, keyboard 4 56, memory circuit 457, touch panel 458, display 459, display controller The signal processing circuit shown in the above embodiment is configured by a microprocessor. By adopting this in the processor 453, it is possible to reduce power consumption. By employing the memory device shown in the embodiment in the memory circuit 457, power consumption can be reduced. This makes it possible to:

[0393] For example, the user can change the display color of a specific part of the book data, - By drawing lines, making the letters thicker, or changing the font, you can differentiate between the relevant part and other parts. When using the highlighting function to clarify the differences between the book data and the user's The memory circuit 457 temporarily stores the data. If you want to store the above data for a long period of time, you can use a flash drive. The above data may be copied to the memory 454.

[0394] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0395] 100 memory element 101 Memory circuit 102 Memory circuit 103 Switch 104 Switch 105 Switch 106 Phase Inversion Element 107 Capacitor element 108 Capacitor 109 Transistor 110 Transistor 113 Transistor 114 transistors 150 Signal Processing Circuit 151 Arithmetic circuit 152 Arithmetic circuit 153 Storage device 154 Storage device 155 Storage device 156 Control device 157 Power supply control circuit 401 Switching element 402 Memory element 403 Memory Element Group 421 RF circuit 422 Analog Baseband Circuit 423 Digital Baseband Circuit 424 Battery 425 Power supply circuit 426 Application Processor 427 CPU 428 DSP 429 Interface 430 flash memory 431 Display Controller 432 Memory Circuit 433 Display 434 Display section 435 Source Driver 436 Gate Driver 437 Audio Circuit 438 Keyboard 439 Touch Sensor 441 Memory Controller 442 Storage device 443 Storage device 444 Switch 445 Switch 451 Battery 452 Power supply circuit 453 microprocessor 454 flash memory 455 Audio Circuit 456 keyboard 457 Memory Circuit 458 Touch Panel 459 Display 460 Display Controller 700 boards 701 Insulating film 702 Semiconductor film 703 Gate insulating film 705 Mask 707 Gate electrode 709 Impurity region 710 Channel formation region 712 insulating film 713 Insulating Film 716 Oxide semiconductor layer 719 Conductive Film 720 Conductive film 721 Gate insulating film 722 gate electrode 723 Conductive Film 724 insulating film 725 Opening 726 Wiring 727 Insulating Film 772 Semiconductor layer 773 Gate insulating layer 901 Transistor 902 insulating film 903 Oxide semiconductor layer 904 Source electrode 905 Drain electrode 906 Gate insulating film 907 Gate electrode 908 High concentration area 909 Channel formation region 911 Transistor 912 Insulating film 913 Oxide semiconductor layer 914 Source electrode 915 Drain electrode 916 Gate insulating film 917 Gate electrode 918 High concentration area 919 Channel formation region 921 Transistor 922 insulating film 923 Oxide semiconductor layer 924 Source Electrode 925 Drain electrode 926 Gate insulating film 927 Gate electrode 928 High concentration area 929 Low concentration area 930 Sidewall Insulator 931 Channel formation region 941 Transistor 942 insulating film 943 Oxide semiconductor layer 944 Source Electrode 945 Drain electrode 946 Gate insulating film 947 Gate electrode 948 High concentration area 949 Low concentration area 950 Sidewall Insulation 951 Channel formation region 1100 board 1102 insulating film 1104 insulating film 1106 Oxide semiconductor layer 1106a High resistance region 1106b Low resistance region 1108 Gate insulating film 1110 gate electrode 1112 insulating film 1114 Electrode 1116 Insulating film 1118 Wiring 1200 board 1202 insulating film 1206 Oxide semiconductor layer 1208 Gate insulating film 1210 Gate electrode 1214 Electrode 1216 Insulating film 1218 Wiring 1220 Protective film 1301 insulating film 1302 Embedded insulators 1303a Semiconductor area 1303b Semiconductor area 1303c Semiconductor field 1304 Gate insulating layer 1305 Gate electrode 1306a Sidewall insulation 1306b Sidewall insulation 1307 Insulators 1308a Source 1308b Drain 3000 boards 3001 Transistor 3004 Logic Circuit 3106 Element isolation insulating film 3303 Electrode 3503 Electrode 3505 Electrode 3003a electrode 3003b electrode 3003c electrode 3100a wiring 3100b wiring 3100c wiring 3100d wiring 3140a Insulating film 3140b insulating film 3141a Insulating film 3141b Insulating film 3142a Insulating film 3142b Insulating film 3170a Memory element 3170b Memory element 3171a transistor 3171b transistor 3501a electrode 3501b electrode 3501c electrode 3502a electrode 3502b electrode 3502c electrode 3503a electrode 3503b electrode 9900 board 9901 ALU 9902 ALU Controller 9903 Instruction Decoder 9904 Interrupt Controller 9905 Timing Controller 9906 Register 9907 Register Controller 9908 Bus·I / F 9909 ROM 9920 ROM·I / F

Claims

1. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor; one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; The other electrode of the capacitance element is electrically connected to a power supply line. a first semiconductor film having a channel formation region of the first transistor and containing polycrystalline silicon; a first conductive film having a region disposed above the first semiconductor film and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the first semiconductor film and a region facing a side surface of the first conductive film; a second semiconductor film having a region disposed above the first insulating film, a channel formation region of the second transistor, and an oxide semiconductor; a second conductive film having a region disposed above the first insulating film, a region in contact with an upper surface of the second semiconductor film, and a region in contact with an upper surface of the first conductive film, and having a function as one of a source electrode and a drain electrode of the second transistor; a third conductive film having a region disposed above the first insulating film, a region in contact with an upper surface of the second semiconductor film, and a function as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive film having a region disposed above the second semiconductor film and functioning as a gate electrode of the second transistor; a fifth conductive film having a region disposed above the second conductive film and functioning as the other electrode of the capacitor element; the fifth conductive film has a region overlapping with the first conductive film, when the power supply line and one of the source electrode or the drain electrode of the first transistor are in a conductive state via at least a channel formation region of the first transistor, a potential is applied from the power supply line to at least one of the source electrode or the drain electrode of the first transistor via the channel formation region of the first transistor; Semiconductor device.

2. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor; one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; The other electrode of the capacitance element is electrically connected to a power supply line. a first semiconductor film having a channel formation region of the first transistor and containing polycrystalline silicon; a first conductive film having a region disposed above the first semiconductor film and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the first semiconductor film and a region facing a side surface of the first conductive film; a second semiconductor film having a region disposed above the first insulating film, a channel formation region of the second transistor, and an oxide semiconductor; a second conductive film having a region disposed above the first insulating film, a region in contact with an upper surface of the second semiconductor film, and a region in contact with an upper surface of the first conductive film, and having a function as one of a source electrode and a drain electrode of the second transistor; a third conductive film having a region disposed above the first insulating film, a region in contact with an upper surface of the second semiconductor film, and a function as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive film having a region disposed above the second semiconductor film and functioning as a gate electrode of the second transistor; a fifth conductive film having a region disposed above the second conductive film and functioning as the other electrode of the capacitor element; the fifth conductive film has a region overlapping with the first conductive film, each of the second conductive film and the third conductive film includes a first titanium film, an aluminum film having a region disposed above the first titanium film, and a second titanium film having a region disposed above the aluminum film; when the power supply line and one of the source electrode or the drain electrode of the first transistor are in a conductive state via at least a channel formation region of the first transistor, a potential is applied from the power supply line to at least one of the source electrode or the drain electrode of the first transistor via the channel formation region of the first transistor; Semiconductor device.

3. a first transistor, a second transistor, a third transistor, and a capacitor; one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor; one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; The other electrode of the capacitance element is electrically connected to a power supply line, a semiconductor device in which one of a source electrode or a drain electrode of the third transistor is electrically connected to one of a source electrode or a drain electrode of the first transistor, a first semiconductor film having a channel formation region of the first transistor and containing polycrystalline silicon; a first conductive film having a region disposed above the first semiconductor film and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the first semiconductor film and a region facing a side surface of the first conductive film; a second semiconductor film having a region disposed above the first insulating film, a channel formation region of the second transistor, and an oxide semiconductor; a second conductive film having a region disposed above the first insulating film, a region in contact with an upper surface of the second semiconductor film, and a region in contact with an upper surface of the first conductive film, and having a function as one of a source electrode and a drain electrode of the second transistor; a third conductive film having a region disposed above the first insulating film, a region in contact with an upper surface of the second semiconductor film, and a function as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive film having a region disposed above the second semiconductor film and functioning as a gate electrode of the second transistor; a fifth conductive film having a region disposed above the second conductive film and functioning as the other electrode of the capacitor element; the fifth conductive film has a region overlapping with the first conductive film, when the power supply line and one of the source electrode or the drain electrode of the first transistor are in a conductive state via at least a channel formation region of the first transistor, a potential is applied from the power supply line to at least one of the source electrode or the drain electrode of the first transistor via the channel formation region of the first transistor, a potential of one of a source electrode and a drain electrode of the first transistor is applied to a first node via the third transistor having a function as a switch; Semiconductor device.

4. a first transistor, a second transistor, a third transistor, and a capacitor; one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor; one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; The other electrode of the capacitance element is electrically connected to a power supply line, a semiconductor device in which one of a source electrode or a drain electrode of the third transistor is electrically connected to one of a source electrode or a drain electrode of the first transistor, a first semiconductor film having a channel formation region of the first transistor and containing polycrystalline silicon; a first conductive film having a region disposed above the first semiconductor film and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the first semiconductor film and a region facing a side surface of the first conductive film; a second semiconductor film having a region disposed above the first insulating film, a channel formation region of the second transistor, and an oxide semiconductor; a second conductive film having a region disposed above the first insulating film, a region in contact with an upper surface of the second semiconductor film, and a region in contact with an upper surface of the first conductive film, and having a function as one of a source electrode and a drain electrode of the second transistor; a third conductive film having a region disposed above the first insulating film, a region in contact with an upper surface of the second semiconductor film, and a function as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive film having a region disposed above the second semiconductor film and functioning as a gate electrode of the second transistor; a fifth conductive film having a region disposed above the second conductive film and functioning as the other electrode of the capacitor element; the fifth conductive film has a region overlapping with the first conductive film, each of the second conductive film and the third conductive film includes a first titanium film, an aluminum film having a region disposed above the first titanium film, and a second titanium film having a region disposed above the aluminum film; when the power supply line and one of the source electrode or the drain electrode of the first transistor are in a conductive state via at least a channel formation region of the first transistor, a potential is applied from the power supply line to at least one of the source electrode or the drain electrode of the first transistor via the channel formation region of the first transistor, a potential of one of a source electrode and a drain electrode of the first transistor is applied to a first node via the third transistor having a function as a switch; Semiconductor device.

5. In any one of claims 1 to 4, the oxide semiconductor includes indium oxide; Semiconductor device.

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