Chip stack device, semiconductor module, and method of manufacturing the same

Abstract

To provide a chip lamination device of multilayer lamination capable of reducing the deviation of an electrode position from a design position in the lamination direction of a memory chip, and suppressing the deterioration of productivity.SOLUTION: A chip stack device including a first surface parallel to a first direction and a second direction intersecting the first direction and a second surface parallel to the first surface, the chip stack device comprising: a stacked body including a plurality of memory chips stacked in the first direction, each of the memory chips including a semiconductor layer, an insulating layer, and an electrode in the insulating layer, the electrode being located on the first surface; and a continuous organic film located between the memory chips of the plurality of memory chips.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a stacked chip device, a semiconductor module, and a method for manufacturing the same. [Background technology]

[0002] In recent years, data communication volume in electronic computers, such as data centers, has been increasing. Furthermore, as data communication volume increases, the power consumption of electronic computers has rapidly increased, and the memory capacity of electronic computers has also increased, leading to a growing demand for electronic computers with lower power consumption and larger capacity. For example, an electronic computer includes multiple logic chips and multiple memory chips electrically connected to the multiple logic chips. The logic chip is, for example, an IC (Integrated Circuit) chip on which a logic circuit is implemented, and the memory chip is a semiconductor chip on which a memory circuit is implemented. Data communication in an electronic computer is performed, for example, between the logic chip and the memory chip. For example, stacking logic chips and memory chips for three-dimensional implementation is one effective solution for reducing the power consumption of electronic computers and increasing the memory capacity.

[0003] Patent Document 1 discloses, as an example of a three-dimensional packaging method, a semiconductor module in which a structure (pancake-shaped memory cube) in which multiple memory chips are stacked is arranged on a substrate or logic chip so that the main surfaces of the multiple memory chips are parallel to the main surfaces of the substrate or logic chip. Patent Documents 2 to 5 disclose semiconductor modules in which a structure (sliced ​​bread-shaped memory cube) in which multiple memory chips are stacked is vertically mounted (standing vertically) on a substrate or logic chip so that the main surfaces of the multiple memory chips are perpendicular to the main surfaces of the substrate or logic chip. In this application, the main surface refers to the surface with the largest area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-156478 [Patent Document 2] Special Publication No. 3-501428 [Patent Document 3] International Publication No. 2021 / 095083 [Patent Document 4] International Publication No. 2021 / 199447 [Patent Document 5] International Publication No. 2024 / 057707 [Non-patent literature]

[0005] [Non-Patent Document 1] A. Agnesina et al., “A Novel 3D DRAM Memory Cube Architecture for Space Applications,” 2018 55th ACM / ESDA / IEEE Design Automation Conference (DAC), 2018, pp. 1-6, doi: 10.1109 / DAC.2018.8465911. Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the 3D packaging technologies disclosed in Patent Documents 1 to 5 and Non-Patent Document 1, because memory chips are stacked in multiple layers, the electrode positions of the coil that performs signal communication are likely to deviate from the designed positions in the stacking direction, which may result in a decrease in signal communication quality. Furthermore, stacking multiple memory chips in 3D packaging requires high precision stacking of the multiple memory chips, which is expected to reduce the productivity of semiconductor modules.

[0007] Therefore, there is a demand for a multi-layer stacked chip device that can reduce the deviation of electrode positions from the designed positions in the stacking direction of memory chips and can suppress a decrease in productivity. [Means for solving the problem]

[0008] The gist of the present invention is as follows. (1) A chip-stacked device including a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first surface, a stack including a plurality of memory chips stacked in the first direction, each memory chip having a semiconductor layer, an insulating layer, and an electrode in the insulating layer, the electrode being located on the first surface; and A continuous organic film positioned between each of the plurality of memory chips. 10. A chip stacking device comprising: (2) The stacked chip device according to (1), wherein the number of stacked memory chips is 16 or more. (3) The stacked chip device according to (1) or (2) above, wherein each of the memory chips has an average thickness of 1 to 300 μm. (4) The chip stacked device according to any one of (1) to (3) above, wherein the continuous organic film has an average thickness of 0.1 to 10 μm. (5) The chip-stacked device according to any one of (1) to (4) above, wherein the plurality of memory chips are bonded to one another by the adhesive force of the organic film of the continuum. (6) A semiconductor module including the stacked chip device according to any one of (1) to (5) above and a logic chip. (7) providing a semiconductor wafer including a semiconductor layer, an insulating layer, and an electrode in the insulating layer; disposing an organic film on at least one of the main surfaces of the semiconductor wafer; Cutting the semiconductor wafer on which the organic film is disposed to obtain a plurality of memory chips each having the organic film as a continuum, the semiconductor layer, the insulating layer, and an electrode in the insulating layer, and the electrode being located on a side surface of the memory chip; and stacking the plurality of memory chips to form a stack in which the continuous organic film is disposed between each of the plurality of memory chips; Including, disposing the organic film, disposing the organic film having a predetermined thickness so as to correct thickness variations relative to a design thickness of the semiconductor wafer; A method for manufacturing a chip-stacked device, comprising: (8) preparing a plurality of memory chips each having a semiconductor layer, an insulating layer, and an electrode in the insulating layer, the electrode being located on a side surface; disposing a continuous organic film on at least one of the main surfaces of the plurality of memory chips; stacking the plurality of memory chips on which the continuous organic film is disposed to form a stack having the continuous organic film between each of the plurality of memory chips; Including, disposing the continuous organic film; disposing the continuous organic film having a predetermined thickness so as to correct thickness variations with respect to a design thickness of each of the memory chips; A method for manufacturing a chip-stacked device, comprising: (9) Correcting the thickness variation relative to the design thickness includes: The total thickness variation from the design thickness and the total thickness deviation of each organic film from the reference thickness of the organic film are kept within ±3 μm. The method for producing the stacked chip device according to (7) or (8) above, comprising: (10) Correcting the thickness variation relative to the design thickness includes: In the stack, the sum of the thickness variations of two adjacent memory chips with respect to the design thickness and the sum of the thickness deviations of the organic films disposed in contact with the two adjacent memory chips with respect to the reference thickness of the organic films are kept within ±1 μm. The method for producing a compound according to (8) above, comprising: (11) The method for manufacturing a chip-stacked device according to any one of (7) to (10) above, further comprising bonding the memory chips to one another by the adhesive force of the organic film. (12) (A) subjecting the surface of the organic film disposed on the main surface of the memory chip to hydrophilic treatment; (B) depositing droplets on the surface of the hydrophilized organic film; (C) arranging an adjacent memory chip so as to come into contact with the droplet on the organic film arranged on the main surface of the memory chip, and self-aligning the adjacent memory chip with the outer shape positions of the main surfaces of each memory chip as a reference by the surface tension of the droplet; and (D) Repeating the steps (A) to (C) to form the laminate. A method for producing the stacked chip device according to any one of (7) to (11) above, comprising: (13) A method for producing a stacked chip device according to any one of (7) to (12) above, which includes heating and pressurizing the stack. (14) A method for manufacturing a semiconductor module, comprising combining a stacked chip device obtained by the manufacturing method according to any one of (7) to (13) above with a logic chip. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a low-cost multi-layer stacked chip device that can reduce the deviation of electrode positions from the designed positions. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective view showing the configuration of a semiconductor module 10 including the present stacked chip device 100. As shown in FIG. [Figure 2] FIG. 2 is a perspective view showing the configuration of the memory chip 110. As shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view showing the cross-sectional structure of the memory chip 110 taken along the line A1-A2 shown in FIG. [Figure 4] FIG. 4 is a perspective view showing the inductors 172 included in the multiple memory chips 110 of the stacked-chip device 100 and the inductors 272 included in the inductor layer 270 of the logic chip 200. As shown in FIG. [Figure 5] FIG. 5 is a perspective view showing an example of the configuration of the inductor 172 on the memory chip 110 and the inductor 272 on the logic chip 200 shown in FIG. [Figure 6]6A and 6B are schematic side views of the present chip-stacked device 100 before (FIG. 6A) and after (FIG. 6B) memory chips are stacked. [Figure 7] FIG. 7 is a schematic diagram of the present chip stacked device 100 as viewed from the first surface 146 side. [Figure 8] FIG. 8 is a schematic diagram of the present chip stacked device 100 as viewed from the first surface 146 side. [Figure 9] FIG. 9 is a schematic diagram of the present chip stacked device 100 as viewed from the first surface 146 side. [Figure 10] FIG. 10 is a schematic diagram of the present chip stacked device 100 as viewed from the first surface 146 side. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present disclosure relates to a chip stacking device including a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first surface, the stack including a plurality of memory chips stacked in the first direction, each memory chip having a semiconductor layer, an insulating layer, and an electrode in the insulating layer, the electrode being located on the first surface, and a continuous organic film located between each memory chip of the plurality of memory chips.

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. To clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual form, but these are merely examples and do not limit the interpretation of the present invention.

[0013] In one embodiment of the present invention, the D1 direction intersects with the D2 direction, and the D3 direction intersects with the D1 and D2 directions (D1D2 plane). The D1 direction is also called the first direction, the D2 direction is also called the second direction, and the D3 direction is also called the third direction.

[0014] An overview of a chip-stacked device 100 according to the present disclosure (hereinafter also referred to as the present chip-stacked device) will be described with reference to FIGS. 1 to 3. FIG. 1 is a perspective view showing the configuration of a semiconductor module 10 including the present chip-stacked device 100. FIG. 2 is a perspective view showing the configuration of a memory chip 110. FIG. 3 is a cross-sectional view showing the cross-sectional structure of the memory chip 110 taken along line A1-A2 shown in FIG. 2.

[0015] 1, the stacked chip device 100 may be included in a semiconductor module 10 together with a logic chip 200. The stacked chip device 100 may also be called a memory cube, and the logic chip 200 may also be called a semiconductor chip.

[0016] 1, the stacked-chip device 100 has a sliced ​​bread configuration in which multiple memory chips 110 are stacked in the D1 direction. The stacked-chip device 100 includes a first surface 146 that is parallel to the D1 direction and a D2 direction that intersects with the D1 direction, and a second surface 148 that is on the opposite side of the first surface 146 in the D3 direction and is parallel to the first surface.

[0017] The chip stacked device 100 also includes a third surface 145 perpendicular to the first surface 146 and the second surface 148, and a fourth surface 147 opposite to the third surface 145 in the D2 direction and parallel to the third surface 145.

[0018] The chip stacked device 100 also includes a fifth surface 142 parallel to the D2 and D3 directions, and a sixth surface 144 opposite to the fifth surface 142 in the D1 direction and parallel to the fifth surface 142.

[0019] As shown in FIGS. 1 to 3, each of the multiple memory chips 110 has a semiconductor layer 130, an insulating layer 120, and an inductor 172 including an electrode 172A in the insulating layer. The electrode 172A is located on a first surface 146 parallel to a D1 direction (first direction) and a D2 direction (second direction) intersecting the D1 direction, forming a stack including the multiple memory chips 110 stacked in the D1 direction. The semiconductor layer 130 can be a transistor layer. The insulating layer 120 can include a wiring layer 150 and an inductor layer 170. The electrode 172A only needs to be located on the first surface 146 so that the inductors can communicate with each other via magnetic field coupling, which will be described later, and may or may not be exposed to the first surface 146.

[0020] The plurality of memory chips 110 may be separated or may not be separated from one another. The plurality of memory chips 110 may have the same configuration or different configurations.

[0021] 2, the memory chip 110 includes a first surface 102 parallel to the D2 and D3 directions, and a second surface 104 opposite the first surface 102 with respect to the D1 direction. The first surface 102 is the surface of the semiconductor layer 130 opposite to the surface on which the insulating layer 120 is disposed, and the second surface 104 is the surface of the insulating layer 120 opposite to the surface on which the semiconductor layer 130 is disposed. The first surface 102 and the second surface 104 of the memory chip 110 are parallel to the fifth surface 142 and the sixth surface 144 of the chip-stacked device 100.

[0022] The memory chip 110 also includes a third surface 105 perpendicular to the first surface 102 and the second surface 104, a fourth surface 106 adjacent to the third surface 105, a fifth surface 107 adjacent to the fourth surface 106, and a sixth surface 108 adjacent to the fifth surface 107 and the third surface 105. The third surface 105 of the memory chip 110 is part of the third surface 145 of the chip stacked device 100, the fourth surface 106 of the memory chip 110 is part of the first surface 146 of the chip stacked device 100, the fifth surface 107 of the memory chip 110 is part of the fourth surface 147 of the chip stacked device 100, and the sixth surface 108 of the memory chip 110 is part of the second surface 148 of the chip stacked device 100.

[0023] 3, the semiconductor layer 130 includes, for example, a substrate 173, an isolation region 174, an active region 175, a transistor 176, an insulating layer 177, and part of a wiring 178. The substrate 173 is, for example, a Si substrate or Si-wafer.

[0024] The wiring layer 150 included in the insulating layer 120 has a multilayer wiring structure in which wiring and insulating layers are alternately stacked. The wiring layer 150 includes, for example, a part of the wiring 178, an insulating layer 179, a wiring 180, and an insulating layer 181. The number of layers of the multilayer wiring in the wiring layer 150 is not limited to two layers as shown in FIG. 3 and may be three or more layers, and can be changed as appropriate depending on the specifications and applications of the semiconductor module 10.

[0025] The memory chip 110 includes an inductor layer 170 having an electrode 172A located on the fourth surface 106. The inductor layer 170 includes, for example, an insulating layer 182 and one or more inductors 172. The inductor 172 includes the electrode 172A, which is a straight side. The inductor 172 may be disposed perpendicular to the first surface 146 of the chip stack device 100.

[0026] Electrode 172A is located on fourth surface 106 and can be close to and parallel to second surface 204 of the logic chip. Electrode 172A only needs to be located on fourth surface 106 so that communication between inductors can be achieved by magnetic field coupling, which will be described later, and may or may not be exposed to fourth surface 106.

[0027] When each inductor layer includes multiple inductors 172, the multiple inductors 172 are arranged side by side in parallel in the D2 direction. The inductor 172 may include terminals A and B. The inductor 172 is electrically connected to the transmitting and receiving circuit using terminals A and B.

[0028] Fig. 4 is a perspective view showing inductors 172 included in the multiple memory chips 110 of the present chip-stacked device 100 and inductors 272 included in the inductor layer 270 of the logic chip 200. Fig. 5 is a perspective view showing an example of the configuration of the inductors 172 on the memory chip 110 and the inductors 272 on the logic chip 200 shown in Fig. 4. As shown in Fig. 1, the first surface 146 of the present chip-stacked device 100 can be disposed on the second surface 204 of the logic chip 200.

[0029] The logic chip 200 may include, for example, a transistor layer 230, a wiring layer 250, and an inductor layer 270, and may include a first surface 202 parallel to the D1 direction and the D2 direction intersecting the D1 direction, and a second surface 204 opposite the first surface 202. The first surface 202 is the surface opposite the surface on which the wiring layer 250 is disposed relative to the transistor layer 230, and the second surface 204 is the surface opposite the surface on which the wiring layer 250 is disposed relative to the inductor layer 270. The chip-stacked device 100 and the logic chip 200 may be bonded via an adhesive layer 300. The adhesive layer 300 may be disposed between the first surface 146 of the chip-stacked device 100 and the second surface 204 of the logic chip 200, and may connect the chip-stacked device 100 and the logic chip 200.

[0030] The inductor 272 may be one or more, and may be arranged in a matrix in the directions D1 and D2 at positions corresponding to the inductor 172. The inductor 272 may include an electrode 272A. The inductor 272 may include a terminal C and a terminal D. The inductor 272 is electrically connected to the transmitting and receiving circuit using the terminals C and D.

[0031] As shown in FIG. 1, the memory chip 110 can be arranged perpendicular to the logic chip 200, and as shown in FIGS. 2 and 3, the inductor 172 can be arranged to face the inductor 272 at a 90-degree angle. When one of the inductors 172 and the inductor 272 facing each other faces the other at a 90-degree angle and magnetically couples, the inductors can communicate one-to-one. Inductors may be formed on the side surfaces of the stacked chip device 100, and the inductors of the memory chip 110 and the logic chip 200 may be arranged facing each other (in the same direction). For example, coil wiring may be formed on the first surface 146 of the stacked chip device 100 facing the logic chip 200. Communication between the inductors due to magnetic field coupling is called, for example, inductor communication, signal communication, or data communication.

[0032] The shape of inductor 172 and the shape of inductor 272 may be any shape that allows inductor communication, and is not limited to the triangular shape exemplified in Figures 2 to 5, but may be a trapezoid, a pentagon, a circle, etc. Inductor 272 may have the same configuration and function as inductor 172.

[0033] However, when the inductors are rectangular or square in shape, the distance between two adjacent inductors is constant and does not depend on the distance between the second surfaces 204. When the distance between two adjacent inductors is constant, the two adjacent inductors interfere with each other, which makes crosstalk more likely to occur. On the other hand, when the inductor 172 is triangular as illustrated in FIGS. 2 to 5, the distance between the two sides of the inductor 172 becomes shorter with increasing distance from the second surface 204, and therefore the distance between two adjacent inductors 172 becomes longer with increasing distance from the second surface 204. This makes it less likely for the two adjacent inductors 172 to interfere with each other, making it easier to suppress crosstalk.

[0034] Effective inductor communication can be achieved by electrode 172A of inductor 172 and electrode 272A of inductor 272 that overlaps electrode 172A.

[0035] As described above, the stacked-chip device 100 is disposed on the second surface 204 of the logic chip 200, and signals can be transmitted therebetween contactlessly through magnetically coupled inductor communication. Therefore, the positions of the inductors 172 of the stacked-chip device 100 and the inductors 272 of the logic chip 200 must be precisely aligned, particularly in the D1 direction, which is the stacking direction of the memory chip 110.

[0036] The position of the entire stacked chip device 100 relative to the logic chip 200 can be aligned by conventional flip-chip bonding, but the stacked chip device 100 is composed of a stack of multiple memory chips stacked in multiple layers, and if there is thickness variation (hereinafter also referred to as thickness variation) relative to the designed thickness of the memory chips, each memory chip may be misaligned with its predetermined position in the D1 direction. Therefore, even if the entire stacked chip device 100 is aligned, the position of the inductor of each memory chip in the D1 direction may be misaligned.

[0037] The present chip-stacked device 100 includes a continuous organic film (hereinafter also referred to as an organic film) positioned between each of a plurality of memory chips. The organic film may be disposed in contact with a semiconductor layer, an insulating layer, or both. The organic film may have a thickness that compensates for thickness variations relative to the designed thickness of each memory chip. Therefore, the electrodes in the present chip-stacked device 100 can be positioned accurately relative to their designed positions in the D1 direction, and strict processing control of the memory chips at the expense of productivity is not required. Therefore, the present chip-stacked device 100 is applicable to next-generation highly integrated memories, for example, those stacked in tens or more layers of thin memory chips, each approximately 10 μm thick, and can also suppress a decrease in productivity in multi-layer stacking. In this application, "compensation" refers to reducing or eliminating electrode misalignment in the present chip-stacked device 100 due to thickness variations relative to the designed thickness of the memory chips.

[0038] The organic film is positioned as a continuum between each memory chip. In this application, a continuum refers to an organic film having a substantially uniform thickness throughout the entire layer without any holes such as through-holes. By positioning the continuous organic film between each memory chip, electrodes can be obtained that are positioned with high precision relative to the design position. The organic films positioned between each memory chip may have different thicknesses.

[0039] 6A and 6B are schematic side views of the present chip-stacking device 100 before (FIG. 6A) and after (FIG. 6B) stacking of memory chips. Fig. 6 is a schematic view of the present chip-stacking device 100, which is a sliced ​​bread-type memory cube, viewed from the first surface 146 when electrodes 172A are exposed on the first surface 146. Each memory chip 110 included in the present chip-stacking device 100 has a semiconductor layer 130, an insulating layer 120, and an electrode 172A in the insulating layer 120, and has a continuous organic film 1 located between each memory chip 110.

[0040] In the stack, each memory chip 110 only needs to have an organic film 1 between adjacent memory chips 110, and the up-down orientations of the memory chips 110 may be the same or different. For example, as shown in FIG. 6, the memory chips 110 may be stacked in the same orientation, or in different orientations so that the insulating layers 120 including the electrodes 172A face each other, or so that the semiconductor layers 130 face each other. Stacking (bonding) memory chips 110 in the same orientation, as shown in FIG. 6, is called F2B bonding (face-to-back bonding). Stacking (bonding) memory chips 110 so that their insulating layers (including inductor layers) 120 face each other is called F2F bonding (face-to-face bonding), for example. Stacking (bonding) memory chips 110 so that their semiconductor layers (transistor layers) 130 face each other is called B2B bonding (back-to-back bonding), for example. In addition to being located between the memory chips 110, the organic film 1 may be located on the top surface of the stack as shown in FIG. 6, on the bottom surface of the stack, or on both surfaces thereof.

[0041] 7A, the design thickness of the semiconductor layer 130 is a, the design thickness of the insulating layer 120 is b, and the design thickness of the organic film 1 is c; the design distance from the top surface of the second-tier memory chip 110 to the reference plane (the bottom surface of the first tier) is t11; the design distance from the top surface of the third-tier memory chip 110 to the reference plane is t12; and the design distance from the top surface of the fourth-tier memory chip 110 to the reference plane is t13. FIG. 7A is a schematic diagram of the present chip-stacked device 100, which is a sliced ​​bread memory cube, viewed from the first surface 146 side when the electrode 172A is exposed on the first surface 146. FIG. 7A shows an example in which the thickness of the memory chip is as designed, and FIG. 7B shows an example in which the memory chips have thickness variations.

[0042] The thickness a of the semiconductor layer 130 and the thickness b of the insulating layer 120 may have thickness variations relative to the designed thickness. FIG. 7B shows an example in which the thickness of the second-stage semiconductor layer 130 is smaller than a by x, as an example in which thickness variations relative to the designed thickness exist in a portion of the semiconductor layer 130. In FIG. 7B, because the thickness of the second-stage semiconductor layer 130 is smaller than a by x, the distance t21 from the top surface of the second-stage memory chip 110 to the reference plane is t11=t11-x, the distance t22 from the top surface of the third-stage memory chip 110 to the reference plane is t12=t12-x, and the distance t23 from the top surface of the fourth-stage memory chip 110 to the reference plane is t13=t13-x. In other words, the influence of the thickness variations of the memory chips in the lower stage (second stage) spreads to the upper stages. In other words, as the thickness of the second-stage semiconductor layer 130 changes, the distances from the top surfaces of the memory chips 110 in the upper stages change. As a result, the distance between the electrode 172A of each memory chip 110 and the reference plane varies.

[0043] 8, for example, when the thickness of the second semiconductor layer 130 is smaller than a by x, the third layer can have an organic film 1 with a thickness c+X that is larger than the reference thickness by x. FIG. 8 is a schematic diagram of the chip-stacked device 100 when the electrode 172A is exposed on the first surface 146, viewed from the first surface 146 before (FIG. 8A) and after (FIG. 8B) memory chips are stacked.

[0044] 9(B), when a fourth-stage semiconductor layer 130 having standard dimensions is mounted on the organic film 1 having the thickness c+x, the thickness variation of the second-stage semiconductor layer 130 is corrected, and the distance t33 from the top surface of the fourth-stage memory chip 110 to the reference plane can be made the same as the designed distance t13 shown in FIG. 9(A). FIG. 9 is a schematic diagram of the present chip-stacked device 100 as viewed from the first surface 146 when the electrode 172A is exposed on the first surface 146. FIG. 9A shows an example in which the thickness of the memory chip is as designed, and FIG. 9B shows an example in which the memory chip has thickness variation.

[0045] As a method for correcting the thickness of memory chips, as described above, the correction may be made by adjusting the thickness of a single organic film disposed adjacent to a memory chip having thickness variations, or by adjusting the thickness of a single organic film disposed not adjacent to a memory chip having thickness variations, or by adjusting the total thickness of multiple organic films, as shown in FIG. 10. FIG. 10 is a schematic diagram of the present chip-stacked device 100 viewed from the first surface 146 when an electrode 172A is exposed on the first surface 146. Although the thickness of the second-stage semiconductor layer 130 is smaller than a by x, the thickness variations of the second-stage semiconductor layer 130 are corrected by two organic films 1 disposed in the third and fourth stages, each having a thickness of c+x / 2.

[0046] 7 to 10 show an example in which the second-level semiconductor layer 130 has thickness variation, but other semiconductor layers may also have thickness variation, for example, all semiconductor layers may have thickness variation. For example, when multiple memory chips are cut from the same semiconductor wafer and stacked, positive or negative thickness variations relative to the designed thickness may overlap, resulting in significant deviation of the electrode positions from the designed positions. Even in such cases, the present chip stacked device 100 can minimize the variation in the distance from the top surface of each memory chip to the reference plane relative to the designed distance.

[0047] In the present chip-stacked device 100, with regard to the thickness of the memory chips and the thickness of the organic films, the total thickness variation of each memory chip relative to the design thickness of the memory chip and the total thickness deviation of each organic film relative to the reference thickness of the organic film are preferably within ±3 μm, more preferably within ±1 μm, and even more preferably substantially zero. This allows the overall thickness of the present chip-stacked device 100 to be substantially the same as the designed position, and allows the position of each electrode included in the stack to be positioned close to the designed position.

[0048] In the present chip-stacked device 100, with regard to the thickness of the memory chips and the thickness of the organic films, the total thickness variation of two adjacent memory chips and the total thickness deviation of each organic film, which is disposed in contact with the two adjacent memory chips and is relative to the reference thickness, are preferably within ±1 μm, more preferably within ±0.5 μm, and even more preferably substantially zero. This allows the overall thickness of the present chip-stacked device 100 to be substantially the same as the designed position, and allows the position of each electrode included in the stack to be positioned exactly as designed with greater precision.

[0049] Each electrode 172A in the present chip stacked device 100 can be positioned preferably within ±3 μm or less, more preferably within ±1 μm, even more preferably within ±0.5 μm, and even more preferably substantially at the designed position relative to the designed position in the D1 direction. If the electrode 172A is exposed on the first surface 146, the position of the electrode 172A can be confirmed with a camera. If the electrode 172A is not exposed on the first surface 146, the electrode 172A can be confirmed with an X-ray monitor. Alternatively, a mark for confirming the position of the electrode 172A may be formed on the insulating layer separately from the electrode 172A, and the position of the mark may be confirmed with a camera.

[0050] To compensate for thickness variations in memory chips, an organic film of a predetermined thickness can be disposed on the semiconductor layer, the insulating layer, or both. For example, an organic film of a predetermined thickness can be disposed on the semiconductor layer or the insulating layer, or an organic film of a predetermined thickness can be disposed on the semiconductor layer or the insulating layer by a spin coating method, a spray method, or the like.

[0051] As such, according to this chip stacking device, an organic film having a predetermined thickness is provided between the memory chips, making it possible to adjust the distance between the memory chips, adjust the position of the memory chip in the stacking direction (D1 direction) of the stack, adjust the position of the electrodes in the stacking direction (D1 direction) of the stack, and adjust the overall thickness of the stack.

[0052] Furthermore, when memory chips are stacked in multiple layers, the memory chips are relatively hard, which increases the internal stress of the stack, potentially resulting in defects such as chip cracking. With this stacked-chip device, because the organic film is provided between the memory chips, even when memory chips are stacked in multiple layers, the organic film can alleviate the stress and prevent the internal stress from increasing, thereby reducing defects such as chip cracking.

[0053] The number of stacked memory chips is 2 or more, preferably 4 or more, more preferably 12 or more, even more preferably 8 or more, still more preferably 16 or more, still more preferably 24 or more, still more preferably 64 or more, and still more preferably 128 or more. The number of stacked memory chips can be, for example, 16 to 1024, 64 to 512, or 128 to 256. According to the present chip stacked device 100, even in the above-described multi-layer stacked structure of memory chips, the electrodes can be positioned with high precision.

[0054] Conventionally, pancake-shaped memory cubes have been commercialized with up to 12 stacked layers, but heat dissipation becomes an issue with multi-layer stacked structures with 16 or more stacked layers. In contrast, sliced ​​bread-shaped memory cubes have semiconductor layers made of Si or the like extending above and below the memory cube, allowing for better heat dissipation and a greater number of stacked layers, making it possible to stack memory chips in multiple layers as described above. The present chip stacking device 100 makes it possible to obtain a multi-layer stacked memory cube, thereby enabling a large-capacity memory without increasing the size of the memory chips.

[0055] However, because memory chips can have thickness variations relative to their designed thickness, in sliced ​​bread memory cubes, the greater the number of stacked memory chips, the more likely electrodes are to be misaligned relative to their designed positions in the D1 direction (stacking direction). This can result in low yields, and productivity issues arise, such as the need to prepare memory chips that are precisely processed to have the designed thickness. The present stacked chip device 100 includes a continuous organic film between each memory chip. Even if thickness variations relative to the designed thickness of each memory chip occur, the organic film can compensate for the thickness variations of each memory chip. Therefore, even if a large number of memory chips are stacked, electrodes can be obtained that are positioned with high precision relative to their designed positions in the D1 direction.

[0056] Each memory chip has an average thickness THI (see FIG. 3) of, for example, 1 to 800 μm, 3 to 300 μm, or 5 to 100 μm. Each memory chip may have an average thickness of 50 μm or less, 40 μm or less, 30 μm or less, 20 μm or less, or 10 μm or less.

[0057] Although the thickness of each memory chip is substantially constant within the memory chip, it has an average thickness variation of greater than ±0 to about ±10 μm relative to the design thickness, and by strictly controlling the thickness processing of the memory chips over a long period of time at the expense of productivity, it can have an average thickness variation of greater than ±0 to about ±1.3 μm.

[0058] Therefore, in the past, the positions of electrodes included in a stack of sliced ​​bread type memory cubes, for example, in a memory cube with 64 layers of stacked memory chips, had a deviation of more than ±0 to ±20 μm from the designed position in the stacking direction (D1 direction), and by strict control of the thickness processing of the memory chips over time at the expense of productivity, the deviation can be reduced to more than ±0 to ±4 μm.

[0059] In the present chip-stacked device 100, thickness variations relative to the design thickness of the memory chips can be corrected by the thickness of the organic film, so even when memory chips with a small average thickness and thickness variations relative to the design thickness are stacked in multiple layers, as described above, electrodes can be formed with high positional accuracy relative to the design position, and strict thickness processing control of the memory chips at the expense of productivity is not required. Therefore, the present chip-stacked device 100 can be applied to next-generation highly integrated memories, for example, those in which thin memory chips with thicknesses of about 10 μm are stacked in tens or more layers, and productivity declines can be suppressed.

[0060] The continuous organic film may have a thickness that allows one or more organic films to compensate for thickness variations relative to the design thickness of the memory chip, for example, an average thickness of 0.1 to 10 μm. Since thickness variations relative to the design thickness of the memory chip are greater than ±0 to about ±10 μm, the organic films may have different thicknesses that allow compensation for this thickness variation.

[0061] The continuous organic film can have thickness variations in increments of 0.1 μm, 0.2 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 5 μm, 10 μm, etc. within the average thickness range of 0.1 to 10 μm.

[0062] An organic film of a predetermined thickness for correcting thickness variations relative to the design thickness of a memory chip may be prepared on an individual basis. Alternatively, for example, organic films with different thickness variations may be prepared in advance, and an organic film capable of correcting thickness variations relative to the design thickness of a memory chip may be selected and placed on the memory chip. An organic film of a predetermined thickness for correcting thickness variations may be formed by applying an organic solution to the memory chip to correct thickness variations relative to the design thickness of the memory chip. Alternatively, an organic film capable of correcting thickness variations relative to the design thickness of a semiconductor wafer before it is cut into memory chips may be selected and placed on the semiconductor wafer. An organic film of a predetermined thickness for correcting thickness variations may be applied to the semiconductor wafer to correct thickness variations relative to the design thickness of the semiconductor wafer.

[0063] The organic film may be any polymer film having elasticity, and may be, for example, a polyimide-based, epoxy-based, acrylic-based, silicone-based, or urethane-based organic film.

[0064] The multiple memory chips are preferably bonded to each other by the adhesive strength of a continuous organic film. By bonding the multiple memory chips to each other using the adhesive strength of the organic film, adhesive is not required, and the multiple memory chips can be positioned with high positional accuracy. The organic film may have adhesive strength before the formation of the laminate, or may have adhesive strength by subjecting the laminate to heat treatment or ultraviolet treatment after formation. Because the organic film may have tack before curing, multiple memory chips can be temporarily bonded by placing the organic film between them even without the adhesive strength of the organic film during stacking. Furthermore, because the surfaces of the multiple memory chips facing each other have high flatness, they have high adhesion to each other and are easily temporarily bonded even without the adhesive strength of the organic film during stacking.

[0065] The organic film is preferably a thermoplastic organic film. Since a thermoplastic organic film is easily deformed by heat treatment, the laminate can be adjusted to a predetermined thickness by heating and pressurizing the laminate after formation.

[0066] The semiconductor layer may be made of a semiconductor, such as silicon (Si).

[0067] The insulating film is one that has been conventionally used in semiconductor integrated circuits, and can be a silicon oxide film (SiO2), a silicon nitride film (SiN), a silicon carbonitride film (SiCN), a low-k film, or the like.

[0068] The electrodes can be made of materials conventionally used in semiconductor integrated circuits, such as Al, Cu, and the like.

[0069] The overall dimensions of the present chip stacked device 100 are not particularly limited, but for example, the length MCBZ in the D1 direction (see FIG. 1) is 1 to 25 mm, the length MCBY in the D2 direction (see FIG. 1) is 1 to 25 mm, and the length MCBX in the D3 direction (see FIG. 1) is 1 to 10 mm.

[0070] The present disclosure is also directed to a semiconductor module 10 including the above-described chip stack device 100 and a logic chip 200. As shown in FIG. 1 , the first surface 146 of the chip stack device 100 can be disposed on the second surface 204 of the logic chip 200.

[0071] In the semiconductor module 10, signals are transmitted and received using non-contact inductor communication between the inductor 172 included in the memory chip 110 and the inductor 272 included in the logic chip 200. In the semiconductor module 10, the positional accuracy of the electrodes of the inductor 172 included in the present chip stacked device 100 is high, so that excellent communication quality can be obtained between the inductor 272.

[0072] The semiconductor module 10 may include a configuration that allows one-to-one inductor communication between an inductor 172 and an inductor 272 that are arranged opposite each other at 90 degrees. Furthermore, multiple inductors 172 are arranged in parallel on the first surface 146 of the present chip-stacked device 100, and multiple inductors 272 are arranged in parallel on the second surface 204 of the logic chip 200, allowing one-to-one communication between the inductors. As a result, large-capacity signals (data) can be easily communicated in parallel.

[0073] Each inductor 172 may perform inductor communication with its one-to-one corresponding inductor 272 in response to (synchronous with) a clock received by clock communication, or each inductor 172 may perform inductor communication with its one-to-one corresponding inductor 272 without synchronizing (asynchronously) with the clock received by clock communication. Each inductor 172 may perform inductor communication with its one-to-one corresponding inductor 272 asynchronously.

[0074] The present disclosure also relates to a method for manufacturing a stacked-chip device (hereinafter also referred to as the present manufacturing method), including: preparing a semiconductor wafer including a semiconductor layer, an insulating layer, and electrodes in the insulating layer; disposing an organic film on at least one of the main surfaces of the semiconductor wafer; slicing the semiconductor wafer with the organic film to obtain a plurality of memory chips each having a continuous organic film, the semiconductor layer, the insulating layer, and electrodes in the insulating layer, the electrodes being located on their side surfaces; and stacking the plurality of memory chips to form a stack in which the continuous organic film is disposed between each of the plurality of memory chips, wherein disposing the organic film includes disposing the organic film to a predetermined thickness to compensate for thickness variations relative to the designed thickness of the semiconductor wafer. The side surface is the fourth surface 106 of the memory chip 110 described above with respect to the present stacked-chip device.

[0075] The semiconductor wafer containing the semiconductor layer, the insulating layer, and the electrodes in the insulating layer can be prepared by methods conventionally used in the manufacture of semiconductor integrated circuits.

[0076] Semiconductor wafers produced in the front-end of semiconductor processing typically have a diameter of approximately 200 to 450 mm and a thickness of approximately 500 to 1000 μm. After forming minute nanometer devices on the semiconductor wafer and applying a protective film, the semiconductor wafer is thinned from the back to a desired thickness, for example, approximately 10 μm, and then cut into pieces for use as memory chips. Semiconductor wafers can be processed to the desired thickness either before or after the organic film is deposited. It is difficult to process a semiconductor wafer to a desired thickness, for example, exactly 10 μm, and thickness variations (tolerances) can occur between semiconductor wafers.

[0077] An organic film is disposed on at least one of the main surfaces of a semiconductor wafer. The main surface of a semiconductor wafer refers to a first surface, which is the surface of a semiconductor layer or an insulating layer included in the semiconductor wafer, and a second surface on the opposite side. The organic film disposed on at least one of the main surfaces of the semiconductor wafer need only be continuous when the semiconductor wafer is cut into memory chips, and the cut portions may be discontinuous, but a continuous organic film is preferred.

[0078] By disposing an organic film on the semiconductor wafer before cutting it into memory chips, it is possible to dispose the organic film on the upper surface of a plurality of memory chips at once. Furthermore, since the semiconductor wafer has substantially the same thickness within its plane, the thickness variation relative to the design thickness is the same within the plane. Therefore, it is sufficient to dispose an organic film having a predetermined thickness on at least one of the main surfaces of the semiconductor wafer so as to correct the thickness variation relative to the design thickness of the semiconductor wafer.

[0079] The organic film can be formed, for example, by applying an organic solution to at least one of the main surfaces of the semiconductor wafer. The method for applying the organic solution is not particularly limited as long as it can form an organic film of substantially uniform thickness, and can be performed using, for example, a spin coating method, a spray method, a doctor blade method, or the like.

[0080] The organic film can also be formed by disposing an organic film on at least one of the main surfaces of a semiconductor wafer. If the organic film has adhesive properties, it can be directly bonded to a memory chip. Even if the organic film does not have adhesive properties, it can be directly bonded to a semiconductor wafer if it has tackiness.

[0081] The semiconductor wafer on which the organic film is disposed is cut in a direction parallel to the stacking direction of the semiconductor wafer (a direction perpendicular to the main surface of the semiconductor wafer) to obtain a plurality of memory chips each having a semiconductor layer, an insulating layer, and an electrode in the insulating layer and with the electrode located on the side surface. The main surface of the semiconductor wafer becomes the main surface of the memory chips obtained by cutting the semiconductor wafer, and therefore a continuous organic film is disposed on at least one of the main surfaces of each of the plurality of memory chips obtained by cutting.

[0082] The memory chips obtained by cutting are stacked to form a stack in which a continuous organic film is disposed between each of the memory chips. The memory chips may be obtained from a single semiconductor wafer or from multiple semiconductor wafers.

[0083] The disposing of the organic film includes disposing an organic film having a predetermined thickness to compensate for thickness variations relative to a design thickness of the semiconductor wafer, and the organic film having a predetermined thickness can be prepared and disposed as described above with respect to the present chip stacking device.

[0084] The present disclosure also relates to a method for manufacturing a stacked-chip device (hereinafter also referred to as the present manufacturing method), which includes: preparing a plurality of memory chips each having a semiconductor layer, an insulating layer, and electrodes in the insulating layer, the electrodes being located on a side surface; disposing a continuous organic film on at least one of the main surfaces of the plurality of memory chips; and stacking the plurality of memory chips with the continuous organic film disposed thereon to form a stack having the continuous organic film between each of the plurality of memory chips, wherein disposing the continuous organic film includes disposing the continuous organic film having a predetermined thickness to compensate for thickness variations relative to the designed thickness of each of the memory chips. The side surface is the fourth surface 106 of the memory chip 110 described above with respect to the present stacked-chip device.

[0085] A plurality of memory chips having a semiconductor layer, an insulating layer, and electrodes in the insulating layer, with the electrodes located on the side surfaces, can be obtained from the semiconductor wafer described above.

[0086] A continuous organic film is disposed on at least one of the main surfaces of the memory chip. The main surface of the memory chip refers to the first surface, which is the surface of the semiconductor layer or the surface of the insulating layer of the memory chip, and the second surface on the opposite side. The main surface of the memory chip is part of the main surface of the semiconductor wafer.

[0087] Disposing the continuous organic film includes disposing a continuous organic film having a predetermined thickness so as to correct thickness variations relative to the design thickness of the memory chip. By disposing the continuous organic film on the memory chip, it is possible to correct thickness variations relative to the design thickness of each memory chip used to form the stack.

[0088] In this manufacturing method, correcting thickness variations relative to the design thickness preferably includes reducing the total thickness variation relative to the design thickness and the total thickness deviation of each organic film relative to the reference thickness of the organic film to within ±3 μm, more preferably within ±1 μm, and even more preferably to substantially zero. For example, if the total thickness deviation relative to the design thickness of a semiconductor wafer or memory chip is −5 μm, using organic films with a total thickness of +5 μm above the reference thickness will reduce the total thickness deviation relative to the design thickness and the total thickness deviation of each organic film to zero. This allows the dimensions of this chip-stacking device in the stacking direction (D1 direction) to approach the design dimensions, and the positions of the electrodes in the stacking direction (D1 direction) included in this chip-stacking device to approach their design positions.

[0089] In this manufacturing method, correcting thickness variations relative to the design thickness preferably includes reducing the sum of the thickness variations relative to the design thickness of two adjacent memory chips in the stack and the sum of the thickness deviations of each organic film relative to the reference thickness of the organic film disposed adjacent to the adjacent two memory chips to within ±1 μm, more preferably within ±0.5 μm, and even more preferably to substantially zero. For example, if the sum of the thickness deviations relative to the design thickness of two adjacent memory chips is -5 μm, using an organic film with a total thickness of +5 μm from the reference thickness in contact with the two adjacent memory chips will reduce the sum of the thickness deviations relative to the design thickness and the sum of the thickness deviations of each organic film to zero. This allows the electrode positions in the stacking direction (D1 direction) of this chip-stacked device to be closer to the design positions for each two memory chips in the stacking direction (D1 direction). By focusing on the thickness deviations between two adjacent memory chips, thickness deviations can be reduced even when the number of stacked chips is small.

[0090] Conventionally, memory chips are stacked (bonded) together using techniques such as fusion bonding, silicon direct bonding (SDB), or thermo-compression bonding using microbumps and sealing resin. In this manufacturing method, an organic film is placed between each memory chip in the stack, allowing stacking (bonding) to be achieved by utilizing the tackiness or adhesiveness of the organic film.

[0091] This manufacturing method preferably includes bonding multiple memory chips to each other using the adhesive strength of an organic film. By bonding multiple memory chips to each other using the adhesive strength of the organic film, adhesive is not required and multiple memory chips can be positioned with high positional accuracy. The organic film may have adhesive strength before the formation of the stack, or it may have adhesive strength by subjecting the stack to heat treatment or UV treatment after formation. Because the organic film may have tackiness before curing, multiple memory chips can be temporarily bonded by placing the organic film between them even without the adhesive strength of the organic film during stacking. The organic film can be cured by heat treatment or UV treatment. The curing treatment atmosphere may be atmospheric pressure or an inert gas atmosphere. Furthermore, since the opposing surfaces of the multiple memory chips have high flatness, they have high adhesion to each other and are easily temporarily bonded even without the adhesive strength of the organic film during stacking.

[0092] This manufacturing method preferably includes (A) hydrophilizing the surface of the organic film disposed on the main surface of the memory chip, (B) depositing a droplet on the hydrophilized surface of the organic film, (C) arranging an adjacent memory chip so that the adjacent memory chip contacts the droplet on the organic film disposed on the main surface of the memory chip, and self-aligning the adjacent memory chips using the surface tension of the droplet as a reference for the outer contour positions of the main surfaces of the memory chips, and (D) repeating steps (A) to (C) to form the stack. Use of this self-alignment technique enables high-speed stacking of memory chips and high-precision positioning.

[0093] The order in which steps (A) to (C) are repeated in step (D) does not matter, and steps (A) to (C) may be repeated in order, or only step (A) may be repeated first to prepare multiple memory chips having an organic film whose surface has been hydrophilically treated, and then steps (B) and (C) may be repeated, or only steps (A) and (B) may be repeated first to prepare multiple memory chips having an organic film whose surface has droplets attached, and then step (C) may be repeated.

[0094] The surface of an organic film is generally hydrophobic, but can be modified to become hydrophilic by performing a hydrophilic treatment, which allows droplets to wet the entire surface of the organic film.

[0095] The hydrophilization treatment can be a treatment method that does not substantially change the thickness of the organic film, and for example, ultraviolet irradiation treatment, plasma treatment, chemical treatment, etc. can be used.

[0096] Since the organic film to be hydrophilized and the semiconductor layer of the memory chip have the same external shape, adjacent memory chips can be self-aligned with high precision using the external positions of the main surfaces of each memory chip as a reference.

[0097] Arranging the adjacent memory chips includes contacting the hydrophilic surfaces of the adjacent memory chips with the droplets. The semiconductor layer of the memory chip is made of a semiconductor material such as Si, so the surface is hydrophilic, allowing the droplets to wet the entire surface of the semiconductor layer. The insulating layer of the memory chip is made of a ceramic material such as silicon dioxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), or low-k film, so the surface is hydrophilic, allowing the droplets to wet the entire surface of the insulating layer. If the surface of the adjacent memory chip is hydrophobic or not sufficiently hydrophilic, the surface of the adjacent memory chip may also be subjected to a hydrophilization treatment.

[0098] The droplets may be any liquid that easily wets the hydrophilic surface, such as water, or may be other inorganic or organic liquids such as glycerin, acetone, alcohol, or SOG (Spin-On-Glass) materials.

[0099] The present manufacturing method preferably includes heating and pressurizing the laminate. By heating and pressurizing the laminate, the organic film can be softened and the bonding strength between the memory chips can be improved. The temperature for heating and pressurizing is, for example, 100 to 350°C, 150 to 300°C, or 200 to 300°C. By heating and pressurizing at such a temperature, the bonding strength between the memory chips can be more effectively improved.

[0100] Furthermore, by applying heat and pressure to the laminate, the organic film can be softened and the thickness of the laminate in the stacking direction (D1 direction) can be adjusted. This allows the thickness of the present chip-stacked device in the stacking direction (D1 direction) to be adjusted, thereby bringing the electrode positions closer to the designed positions. The pressure for heating and pressing is, for example, 0 (only the weight of the memory chips) to 10 MPa, 1 to 8 MPa, or 2 to 6 MPa. By applying heat and pressure at such a pressure, the thickness of the present chip-stacked device in the stacking direction (D1 direction) can be more effectively adjusted, bringing the electrode positions closer to the designed positions.

[0101] The organic film is preferably a thermoplastic organic film. Since a thermoplastic organic film is easily deformed by heat treatment, the laminate can be more effectively adjusted to a predetermined thickness by heating and pressurizing the laminate after formation.

[0102] After forming this stacked chip device in which a predetermined number of memory chips are stacked, the first surface 146, the second surface 148, the third surface 145, and the fourth surface 147 may be polished and flattened by, for example, chemical mechanical polishing (CMP).

[0103] The present disclosure also relates to a method for manufacturing a semiconductor module, which includes combining the chip-stacked device obtained by the above-described manufacturing method with a logic chip. The chip-stacked device 100 can be disposed on a logic chip 200 using, for example, an adhesive layer 300. For example, the first surface 146 of the chip-stacked device 100 is connected to the adhesive layer 300, and the first surface 146 of the chip-stacked device 100 and the adhesive layer 300 are adhered onto the second surface 204 of the logic chip 200. The adhesive layer 300 may be, for example, an adhesive containing an epoxy resin or an acrylic polymer, a die bonding film containing an epoxy resin or an acrylic polymer, or an adhesive film such as a die attached film.

[0104] A heat dissipation layer may be arranged so as to be in contact with the second surface 148, the fifth surface 142, and the sixth surface 144 of the chip-stacked device 100 and the second surface 204 of the logic chip 200 on which the adhesive layer 300 is not arranged. The second surface 148 is the surface opposite the first surface 146 in the direction D2. [Explanation of symbols]

[0105] 1 Organic film 10 Semiconductor Module 100 Chip stacked device 102 memory chip first side 104 Second side of memory chip 105 Third side of memory chip 106 Memory Chip Fourth Side 107 Fifth side of memory chip 108 Memory Chip 6th Side 110 memory chips 120 insulating layer 130 Semiconductor layer 142 Fifth side of stacked chip device 144 Sixth side of stacked chip device 145 Third side of stacked chip device 146 First side of stacked chip device 147 Fourth side of stacked chip device 148 Second side of stacked chip device 150 Wiring layers of stacked chip devices 170 Inductor layer of stacked chip device 172 Inductors in stacked chip devices 172A Electrode for inductor of chip stacked device 173 PCB 174 isolation region 175 Activation area 176 transistors 177 Insulating Layer 178 Wiring 179 Insulating Layer 180 Wiring 181 Insulating layer 182 Insulating layer 200 logic chips 202 Logic Chip First Side 204 Second side of logic chip 230 Logic chip transistor layer 250 logic chip wiring layers 270 Logic chip inductor layer 272 Logic chip inductors 272A Logic chip inductor electrode 300 adhesive layer

Claims

1. A chip-stacked device including a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first surface, a stack including a plurality of memory chips stacked in the first direction, the memory chips having a semiconductor layer, an insulating layer, and electrodes in the insulating layer, the electrodes being located on the first surface; and A continuous organic film positioned between each of the plurality of memory chips.

10. A chip stacking device comprising:

2. The stacked chip device according to claim 1 , wherein the number of stacked memory chips is 16 or more.

3. The chip stacking device according to claim 1 , wherein each of the memory chips has an average thickness of 1 to 300 μm.

4. 2. The chip stacking device according to claim 1, wherein the continuous organic film has an average thickness of 0.1 to 10 μm.

5. The chip stacking device according to claim 1 , wherein the plurality of memory chips are adhered to one another by adhesive strength of the organic film of the continuous body.

6. A semiconductor module comprising the stacked chip device according to any one of claims 1 to 5 and a logic chip.

7. providing a semiconductor wafer including a semiconductor layer, an insulating layer, and an electrode in the insulating layer; disposing an organic film on at least one of the main surfaces of the semiconductor wafer; Cutting the semiconductor wafer on which the organic film is disposed to obtain a plurality of memory chips each having the organic film as a continuum, the semiconductor layer, the insulating layer, and an electrode in the insulating layer, and the electrode being located on a side surface of the memory chip; and stacking the plurality of memory chips to form a stack in which the continuous organic film is disposed between each of the plurality of memory chips; Including, disposing the organic film, disposing the organic film having a predetermined thickness so as to correct thickness variations relative to a design thickness of the semiconductor wafer; A method for manufacturing a chip-stacked device, comprising:

8. providing a plurality of memory chips each having a semiconductor layer, an insulating layer, and an electrode in the insulating layer, the electrode being located on a side surface; disposing a continuous organic film on at least one of the main surfaces of the plurality of memory chips; stacking the plurality of memory chips on which the continuous organic film is disposed to form a stack having the continuous organic film between each of the plurality of memory chips; Including, disposing the continuous organic film; disposing the continuous organic film having a predetermined thickness so as to correct thickness variations with respect to a design thickness of each of the memory chips; A method for manufacturing a chip-stacked device, comprising:

9. The step of correcting thickness variations relative to the design thickness includes: The total thickness variation with respect to the design thickness and the total thickness deviation of each organic film with respect to the reference thickness of the organic film are kept within ±3 μm. The method for manufacturing the chip-stacked device according to claim 7 or 8, comprising:

10. The step of correcting thickness variations relative to the design thickness includes: In the stack, the sum of the thickness variations of two adjacent memory chips with respect to the design thickness and the sum of the thickness deviations of the organic films disposed in contact with the two adjacent memory chips with respect to the reference thickness of the organic films are kept within ±1 μm. The method of claim 8, comprising:

11. The method for manufacturing a chip-stacked device according to claim 7 or 8, further comprising: bonding the plurality of memory chips to each other by the adhesive force of the organic film.

12. (A) subjecting the surface of the organic film disposed on the main surface of the memory chip to hydrophilic treatment; (B) depositing droplets on the surface of the hydrophilically treated organic film; (C) arranging an adjacent memory chip so as to come into contact with the droplet on the organic film arranged on the main surface of the memory chip, and self-aligning the adjacent memory chip with the outer shape positions of the main surfaces of the memory chips as a reference by the surface tension of the droplet; and (D) Repeating the steps (A) to (C) to form the laminate. The method for manufacturing the chip-stacked device according to claim 7 or 8, comprising:

13. The method for manufacturing a stacked chip device according to claim 7 or 8, further comprising heating and pressurizing the stack.

14. A method for manufacturing a semiconductor module, comprising combining a stacked chip device obtained by the manufacturing method according to claim 7 or 8 with a logic chip.

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