Test method

Abstract

To provide a test method for accurately evaluating the processing performance of a device to be tested when a load is generated.SOLUTION: A method of testing a control program stored in a storage unit and executed by an arithmetic unit in a test target device includes an acquiring step S2 of acquiring a predetermined processing time required for predetermined processing performed by the arithmetic unit in each predetermined cycle according to the control program, a determining step S3 of determining a load processing time for which load processing is performed according to a difference between the predetermined cycle and the predetermined processing time, a load processing step S4 of causing the arithmetic unit to execute the load processing according to a load program, and an evaluating step S5 of evaluating processing performances of the arithmetic unit that performs the predetermined processing and the load processing.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to testing methods. [Background technology]

[0002] Japanese Patent Application Laid-Open Publication No. 2018-81479 discloses a load control method capable of generating a desired load on a device under test. The load is, for example, the number of instruction execution steps executed by a load generation program. The number of instruction execution steps is related to the load processing time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-81479 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the disclosure of JP 2018-81479 A, ​​an operator must set the time and amount of load to be generated on the device under test. When the device under test is to be subjected to load processing while a predetermined process is being performed by executing a control program, the operator must appropriately determine the load processing time, which is not easy. Therefore, it is difficult to accurately evaluate the processing performance of the device under test when a load is generated.

[0005] The present disclosure aims to solve the above-mentioned problems. [Means for solving the problem]

[0006] An aspect of the present disclosure is a method for testing a control program executed by a calculation unit, comprising: a determination step for determining a load processing time for load processing based on the difference between a predetermined processing time required for a predetermined processing performed by the calculation unit at a predetermined period in accordance with the control program and the predetermined period; a load processing step for causing the calculation unit to execute the load processing in accordance with the load program; and an evaluation step for evaluating the processing performance of the calculation unit that performs the predetermined processing and the load processing. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to accurately evaluate the processing performance of a test target device when a load is applied. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram schematically illustrating the configuration of a test target device. [Figure 2] FIG. 2 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 3] FIG. 3 is a flowchart illustrating a processing procedure related to a control program testing method. [Figure 4] FIG. 4 is a diagram showing a schematic configuration of the test target device and the test execution device. [Figure 5] FIG. 5 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 6] FIG. 6 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 7] FIG. 7 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 8] FIG. 8 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 9] FIG. 9 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 10]FIG. 10 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 11] FIG. 11 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 12] FIG. 12 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 13] FIG. 13 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. [Figure 14] FIG. 14 is a diagram for explaining the relationship between the predetermined processing time, the load processing time, and the predetermined cycle. DETAILED DESCRIPTION OF THE INVENTION

[0009] 1 is a diagram schematically illustrating the configuration of a test target device 10. The test target device 10 has a calculation unit 20 and a storage unit 22. The calculation unit 20 is a computer and includes a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). In other words, the calculation unit 20 includes processing circuitry.

[0010] The storage unit 22 is a computer-readable recording medium. The storage unit 22 includes a volatile memory such as a random access memory (RAM) and a non-volatile memory such as a read-only memory (ROM) or flash memory. The volatile memory is used as a working memory for the processor. The non-volatile memory stores the control program 40 and the load program 42 executed by the processor, as well as other necessary data. In other words, the test target device 10 has a program product of the program executed by the processor.

[0011] The calculation unit 20 has a control unit 50, a timing unit 52, an acquisition unit 54, a determination unit 56, a load processing unit 58, and an evaluation unit 60. The calculation unit 20 executes the control program 40 stored in the storage unit 22 to realize the control unit 50, the timing unit 52, the acquisition unit 54, the determination unit 56, the load processing unit 58, and the evaluation unit 60. The calculation unit 20 executes the load program 42 stored in the storage unit 22 to cause the load processing unit 58 to cause the control unit 50 to execute load processing Lp.

[0012] At least some of the control unit 50, the timing unit 52, the acquisition unit 54, the determination unit 56, the load processing unit 58, and the evaluation unit 60 may be realized by an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array), or an electronic circuit including a discrete device.

[0013] The control unit 50 performs a predetermined process Pp at predetermined intervals Tc to enable the test target device 10 to perform its intended functions in accordance with the control program 40. If the test target device 10 is, for example, an ECU (Electronic Control Unit) for fuel injection control mounted on a vehicle, the control unit 50 performs the predetermined process Pp to control fuel injection into an internal combustion engine equipped in the vehicle.

[0014] The timing unit 52 measures the start time and end time of the above-mentioned predetermined process Pp using a clock signal supplied to the calculation unit 20. The acquisition unit 54 acquires the predetermined processing time TP required for the predetermined process Pp performed by the control unit 50 at each predetermined cycle Tc. The acquisition unit 54 acquires the predetermined processing time TP by calculating it based on the start time and end time of the predetermined process Pp measured by the timing unit 52. This allows for a highly accurate predetermined processing time TP to be obtained.

[0015] The determination unit 56 calculates a reference value Ds according to the difference between a predetermined period Tc and a predetermined processing time TP. The reference value Ds is calculated, for example, as follows. First, a ratio r of the time load imposed on the arithmetic unit 20 is determined in advance (for example, r = 0.9). The reference value Ds is the difference between a value r·Tc obtained by multiplying the predetermined period Tc by the ratio r of the time load and the predetermined processing time TP (Ds = r·Tc - TP).

[0016] The ratio r of the time load is a value greater than a minimum ratio rm1 and less than or equal to a maximum ratio rm2 (rm1 < r ≤ rm2). In the present embodiment, the minimum ratio rm1 is equal to 0 and the maximum ratio rm2 is less than 1. The ratio r of the time load may vary every predetermined period Tc. The ratio r of the time load is determined in advance according to the test purpose of the control program 40. Thereby, since the load processing time TL is appropriately determined, the processing performance of the test target device 10 at the time of load generation can be accurately evaluated.

[0017] The determination unit 56 determines a load processing time TL during which the load processing Lp is performed, using the calculated reference value Ds. The larger the reference value Ds is, the larger the load processing time TL is. In the present embodiment, the load processing time TL is equal to the reference value Ds.

[0018] The load processing unit 58 causes the control unit 50 to execute the load processing Lp according to the load program 42. The load processing Lp is composed of, for example, repetition of operations that are standardly defined in the control program 40, such as reading and writing of dummy data, incrementing of a counter, output of a count value, or numerical calculation. The load processing unit 58 instructs the control unit 50 to execute such operations as the load processing Lp.

[0019] The evaluation unit 60 evaluates the processing performance of the calculation unit 20, which has a control unit 50 that performs a predetermined process Pp and a load process Lp. The processing performance of the calculation unit 20 is evaluated, for example, using the utilization rate of the calculation unit 20. If the predetermined process Pp and the load process Lp are performed within a predetermined cycle Tc, and the total processing time of the predetermined processing time TP and the load processing time TL reaches a time equal to or longer than the predetermined cycle Tc, the utilization rate of the calculation unit 20 theoretically reaches 100%. The evaluation unit 60 evaluates the processing performance of the calculation unit 20 by acquiring an actual measurement value of the utilization rate of the calculation unit 20.

[0020] 2 is a diagram illustrating the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In the example shown in FIG. 2, both the predetermined processing Pp and the load processing Lp are performed at every predetermined cycle Tc starting from time t1. In this embodiment, the proportion r of the temporal load imposed on the calculation unit 20 is predetermined to a constant value.

[0021] The constant value r·Tc obtained by multiplying the predetermined period Tc by the temporal load ratio r is the sum of the reference value Ds and the predetermined processing time TP, as described above. When the load processing time TL is set to a value equal to the reference value Ds, the sum of the predetermined processing time TP and the load processing time TL is equal to the constant value r·Tc described above. In other words, the sum of the predetermined processing time TP and the load processing time TL is a predetermined constant time Ts (Ts = r·Tc). The load processing time TL in each period of the predetermined period Tc is determined as the difference between the constant time Ts and the predetermined processing time TP.

[0022] In this way, it is possible to accurately evaluate the processing performance of the test target device 10 when the total processing time of the predetermined processing time TP and the load processing time TL is a fixed time Ts.

[0023] In the example shown in FIG. 2, within a predetermined period Tc starting from time t1, a predetermined process Pp is performed by the control unit 50 between time t1 and time t2. That is, time t1 is the start time of the predetermined process Pp measured by the timer unit 52, and time t2 is the end time of the predetermined process Pp measured by the timer unit 52. The acquisition unit 54 acquires a predetermined process time TP = TP1 from time t1 to time t2.

[0024] The determination unit 56 determines a load processing time TL = TL1 obtained as the difference between a fixed time Ts and the predetermined process time TP = TP1. As described above, the fixed time Ts is equal to a fixed value r·Tc obtained by multiplying the predetermined period Tc by the time load ratio r. The time load ratio r is greater than 0 and less than or equal to the maximum ratio rm2 (0 < r ≤ rm2). In this embodiment, the maximum ratio rm2 is less than 1. That is, the load processing time TL = TL1 is determined so as not to exceed the difference between the predetermined period Tc and the predetermined process time TP = TP1. In this way, the processing performance of the test target device 10 in a high load state can be accurately evaluated.

[0025] In this embodiment, following the predetermined process Pp corresponding to the predetermined process time TP = TP1 acquired by the acquisition unit 54, a load process Lp is performed within the same predetermined period Tc as the predetermined process Pp. In that case, the load processing unit 58 causes the control unit 50 to execute the load process Lp for the load processing time TL = TL1 from time t2 to time t3. Thereby, it is possible to prevent an overload state in which the total processing time of the predetermined process time TP and the load processing time TL exceeds the predetermined period Tc during the test.

[0026] At time t4, after both the predetermined process Pp and the load process Lp have finished, the predetermined cycle Tc that began at time t1 ends and a new predetermined cycle Tc begins. Within the predetermined cycle Tc that begins at time t4, the control unit 50 performs the predetermined process Pp from time t4 to time t5. That is, time t4 is the start time of the predetermined process Pp measured by the timing unit 52, and time t5 is the end time of the predetermined process Pp measured by the timing unit 52. The acquisition unit 54 acquires the predetermined processing time TP=TP2 from time t4 to time t5.

[0027] The determination unit 56 determines a load processing time TL=TL2, which is obtained as the difference between the fixed time Ts and the predetermined processing time TP=TP2. The load processing time TL=TL2 is determined so as not to exceed the difference between the predetermined cycle Tc and the predetermined processing time TP=TP2. Following the predetermined processing Pp corresponding to the predetermined processing time TP=TP2 acquired by the acquisition unit 54, a load processing Lp is performed within the same predetermined cycle Tc as the predetermined processing Pp. In this case, the load processing unit 58 causes the control unit 50 to execute the load processing Lp during the load processing time TL=TL2, from time t5 to time t6.

[0028] At time t7 after both the predetermined process Pp and the load process Lp have been completed, the predetermined process Pp and the load process Lp are performed again in the same manner. After that, the predetermined process Pp and the load process Lp are performed periodically.

[0029] As shown in Figure 2, both the predetermined process Pp and the load process Lp are performed within the same predetermined cycle Tc. The load process time TL is determined so as not to exceed the difference between the predetermined cycle Tc and the predetermined processing time TP. Therefore, the total processing time of the predetermined processing time TP and the load process time TL is expected to be less than the predetermined cycle Tc. However, the actual processing time may differ from the expected value, and the time when both the predetermined process Pp and the load process Lp end may be longer than the predetermined cycle Tc.

[0030] For example, the load processing Lp may end at a time after time t3 within the predetermined cycle Tc starting from time t1. In this case, the actual measured value of the utilization rate of the calculation unit 20 acquired by the evaluation unit 60 approaches 100%. If the load processing Lp ends after time t4, when the predetermined cycle Tc starting from time t1 ends, the actual measured value of the utilization rate of the calculation unit 20 acquired by the evaluation unit 60 reaches 100%.

[0031] 3 is a flowchart illustrating a processing procedure relating to a test method for the control program 40. This processing procedure is performed by the calculation unit 20 executing the load program 42 while executing the control program 40. When this processing procedure is started, in step S1 (timing step), the timing unit 52 times the start time and end time of a predetermined process Pp in conjunction with the start of a predetermined period Tc.

[0032] In step S2 (acquisition step), the acquisition unit 54 acquires the predetermined processing time TP required for the predetermined process Pp performed by the control unit 50 at each predetermined cycle Tc. In step S3 (determination step), the determination unit 56 determines the load processing time TL for performing the load process Lp according to the difference between the predetermined cycle Tc and the predetermined processing time TP. In step S4 (load processing step), the load processing unit 58 causes the control unit 50 to perform the load process Lp in accordance with the load program 42.

[0033] In step S5 (evaluation step), the evaluation unit 60 evaluates the processing performance of the calculation unit 20, which has the control unit 50 that performs the predetermined processing Pp and the load processing Lp. In step S6, the load processing unit 58 determines whether or not a test end instruction has been issued. The test end instruction is issued, for example, when an operator inputs an instruction to stop the load program 42 into the test target device 10.

[0034] If the result of step S6 is YES, the procedure proceeds to step S7. If the result of step S6 is NO, the procedure returns to step S1. In step S7, the load processing unit 58 stops the load processing Lp that has been executed by the control unit 50. When the processing of step S7 is completed, the procedure ends.

[0035] The above-described embodiment may be modified as follows: In the following modifications, explanations that overlap with the above-described embodiment will be omitted.

[0036] (Variation 1) In the above-described embodiment, the storage unit 22 of the test target device 10 stores both the control program 40 and the load program 42. However, the load program 42 may be stored in a storage unit of a device different from the storage unit 22 of the test target device 10.

[0037] 4 is a diagram showing a schematic configuration of the test target device 10 and the test execution device 70. The test target device 10 performs a predetermined process Pp and also performs a load process Lp in accordance with instructions from the test execution device 70. The test execution device 70 is, for example, a personal computer. In FIG. 4, the same reference numerals are used for components common to FIG. 1. A description of this configuration will be omitted.

[0038] 4, the test target device 10 further includes a communication unit 80 in addition to the calculation unit 20 and the storage unit 22. The communication unit 80 enables communication between the test target device 10 and the test execution device 70. The storage unit 22 stores a control program 40. The calculation unit 20 includes a control unit 50 and a timing unit 52.

[0039] The test execution device 70 has a calculation unit 90, a memory unit 92, and a communication unit 94. The calculation unit 90 is a computer and includes a processor such as a CPU or GPU. In other words, the calculation unit 90 includes a processing circuit. The communication unit 94 enables communication between the test execution device 70 and the test target device 10.

[0040] The storage unit 92 is a computer-readable recording medium. The storage unit 92 includes volatile memory such as RAM and non-volatile memory such as ROM or flash memory. The volatile memory is used as the working memory of the processor. The non-volatile memory stores the control program 100 and load program 42 executed by the processor, as well as other necessary data. In other words, the test execution device 70 has a program product of the program executed by the processor.

[0041] The calculation unit 90 has an acquisition unit 54, a determination unit 56, a load processing unit 58, and an evaluation unit 60. When the calculation unit 90 executes a control program 100 stored in the storage unit 92, the acquisition unit 54, the determination unit 56, the load processing unit 58, and the evaluation unit 60 are realized.

[0042] The load processing unit 58 causes the control unit 50 of the test target device 10 to execute the load processing Lp in accordance with the load program 42. The load processing Lp is composed of a repetition of operations that are standardly defined in the control program 40, as described above. The load processing unit 58 instructs the control unit 50 via the communication unit 94 of the test execution device 70 and the communication unit 80 of the test target device 10 to cause the control unit 50 to execute these operations as the load processing Lp.

[0043] With this configuration, it is possible to accurately evaluate the processing performance of the test target device 10 when a load is applied, using the test execution device 70 provided at a location distant from the test target device 10. Furthermore, since the calculation unit 20 of the test target device 10 does not have the acquisition unit 54, the determination unit 56, the load processing unit 58, or the evaluation unit 60, it is possible to more accurately evaluate the processing performance of the calculation unit 20 having the control unit 50 that performs the predetermined processing Pp and the load processing Lp.

[0044] (Variation 2) In the above-described embodiment, the load processing time TL determined by the determination unit 56 may vary for each predetermined period Tc. However, the load processing time TL may also be constant. FIG. 5 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined period Tc. In FIG. 5, the same symbols as in FIG. 2 are used. A description of this configuration will be omitted. Note that even if the same symbols are used in FIG. 5 and FIG. 2, they do not necessarily represent the same timing. In FIG. 5, unlike FIG. 2, the load processing time TL is constant.

[0045] 5, similarly to FIG. 2, the control unit 50 performs both the predetermined process Pp and the load process Lp at predetermined intervals Tc. The determination unit 56 determines the load process time TL to be a predetermined fixed time TL0. Therefore, the determination unit 56 determines a predetermined maximum process time TPmax, which is the longest predetermined process time TP, from among past predetermined process times TP.

[0046] The determination unit 56 determines the fixed time TL0, which is the difference between the fixed time Ts and the maximum predetermined processing time TPmax, as the load processing time TL. Since it is not necessary to determine the load processing time TL for each predetermined cycle Tc, the load processing unit 58 can cause the control unit 50 to execute the load processing Lp immediately after the predetermined processing Pp ends.

[0047] The predetermined processing time TP required for the predetermined process Pp performed in each predetermined cycle Tc is not necessarily the maximum predetermined processing time TPmax. As shown in Figure 5, within the predetermined cycle Tc starting at time t1, the load process Lp begins at time t2 after the predetermined process Pp performed from time t1 for the predetermined processing time TP = TP1 ends. The load processing time TL during which the load process Lp is performed is the above-mentioned fixed time TL0. The same applies within the predetermined cycle Tc starting at time t4.

[0048] (Variation 3) In the above-described embodiment, the sum of the predetermined processing time TP and the load processing time TL is a predetermined constant time Ts. However, the sum of the predetermined processing time TP and the load processing time TL does not have to be constant. FIG. 6 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In FIG. 6, the same symbols as in FIGS. 2 and 5 are used. A description of this configuration will be omitted. Note that even if the same symbols are used in FIG. 6, FIG. 2, and FIG. 5, they do not necessarily represent the same timing.

[0049] In the example shown in Fig. 6, similarly to Fig. 2, the control unit 50 performs both the predetermined processing Pp and the load processing Lp at predetermined cycles Tc. The sum of the predetermined processing time TP and the load processing time TL is not constant. The determination unit 56 determines the load processing time TL so that the load processing time TL varies at each predetermined cycle Tc. However, the load processing time TL is determined so that it does not exceed the difference between the predetermined cycle Tc and the predetermined processing time TP.

[0050] As shown in Fig. 6, within a predetermined cycle Tc starting at time t1, a predetermined process Pp is performed for a predetermined processing time TP = TP1 from time t1 to time t2. After the predetermined process Pp is completed, a load process Lp is performed for a load processing time TL = TL1 from time t2 to time t3. Within a predetermined cycle Tc starting at time t4, a predetermined process Pp is performed for a predetermined processing time TP = TP2 from time t4 to time t5. After the predetermined process Pp is completed, a load process Lp is performed for a load processing time TL = TL2 from time t5 to time t6.

[0051] Within the predetermined cycle Tc starting at time t7, a predetermined process Pp is performed for a predetermined processing time TP=TP3 from time t7 to time t8. After the predetermined process Pp is completed, a load process Lp is performed for a load processing time TL=TL3 from time t8 to time t9. In the example shown in FIG. 6, the load processing time TL varies for each predetermined cycle Tc. This makes it possible to accurately evaluate the processing performance of the test target device 10 under more realistic high-load conditions where the load processing time TL varies.

[0052] (Variation 4) In the above-described embodiment, the load processing time TL determined by the determination unit 56 may vary for each predetermined period Tc. The load processing time TL may vary monotonically for each predetermined period Tc. That is, the load processing time TL may increase or decrease monotonically for each predetermined period Tc. FIG. 7 is a diagram for explaining the relationship between the predetermined processing time TP and the load processing time TL and the predetermined period Tc. In FIG. 7, the same symbols as those in FIGS. 2, 5, and 6 are used. A description of this configuration will be omitted. Note that even if the same symbols are used for times in FIG. 7, 2, 5, and 6, they do not necessarily represent the same timing.

[0053] In the example shown in Fig. 7, similar to Fig. 2, the control unit 50 performs both the predetermined process Pp and the load process Lp at every predetermined cycle Tc. The determination unit 56 determines the load process time TL so that the load process time TL increases monotonically at every predetermined cycle Tc. As shown in Fig. 7, within the predetermined cycle Tc starting from time t1, the predetermined process Pp is performed for a predetermined processing time TP = TP1 from time t1 to time t2. After the predetermined process Pp is completed, the load process Lp is performed for a load processing time TL = TL1 from time t2 to time t3.

[0054] Within the predetermined cycle Tc starting at time t4, a predetermined process Pp is performed for a predetermined processing time TP=TP2 from time t4 to time t5. After the predetermined process Pp is completed, a load process Lp is performed for a load processing time TL=TL2 from time t5 to time t6. The load processing time TL=TL2 within the predetermined cycle Tc starting at time t4 is longer than the load processing time TL=TL1 within the predetermined cycle Tc starting at time t1.

[0055] Within the predetermined cycle Tc starting at time t7, a predetermined process Pp is performed for a predetermined processing time TP=TP3 from time t7 to time t8. After the predetermined process Pp is completed, a load process Lp is performed for a load processing time TL=TL3 from time t8 to time t9. The load processing time TL=TL3 within the predetermined cycle Tc starting at time t7 is longer than the load processing time TL=TL2 within the predetermined cycle Tc starting at time t4.

[0056] In the fourth modification, the load processing time TL varies monotonically for each predetermined period Tc. This makes it possible to verify the load level at which the processing durability of the test target device 10 is maintained and the load level at which the processing durability is impaired. In the example shown in FIG. 7, the load processing time TL increases monotonically for each predetermined period Tc. This makes it possible to identify the boundary of the load level at which the processing durability of the test target device 10, which has been maintained, is subsequently impaired. It is possible.

[0057] FIG. 8 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In FIG. 8, the same symbols as in FIG. 2 and FIGS. 5 to 7 are used. Explanation of the relevant configuration will be omitted. Note that even when the same symbols are used in FIG. 8, FIG. 2, and FIGS. 5 to 7, they do not necessarily represent the same timing.

[0058] In the example shown in Fig. 8, similarly to Fig. 2, the control unit 50 performs both the predetermined process Pp and the load process Lp at each predetermined cycle Tc. The determination unit 56 determines the load process time TL so that the load process time TL decreases monotonically at each predetermined cycle Tc. As shown in Fig. 8, within the predetermined cycle Tc starting from time t1, the predetermined process Pp is performed during the predetermined processing time TP=TP1 from time t1 to time t2. After the predetermined process Pp is completed, the load process Lp is performed during the load process time TL=TL1 from time t2 to time t3.

[0059] Within the predetermined cycle Tc starting at time t4, a predetermined process Pp is performed for a predetermined processing time TP=TP2 from time t4 to time t5. After the predetermined process Pp is completed, a load process Lp is performed for a load processing time TL=TL2 from time t5 to time t6. The load processing time TL=TL2 within the predetermined cycle Tc starting at time t4 is shorter than the load processing time TL=TL1 within the predetermined cycle Tc starting at time t1.

[0060] Within the predetermined cycle Tc starting at time t7, a predetermined process Pp is performed for a predetermined processing time TP=TP3 from time t7 to time t8. After the predetermined process Pp is completed, a load process Lp is performed for a load processing time TL=TL3 from time t8 to time t9. The load processing time TL=TL3 within the predetermined cycle Tc starting at time t7 is shorter than the load processing time TL=TL2 within the predetermined cycle Tc starting at time t4.

[0061] 8, the load processing time TL decreases monotonically at each predetermined period Tc. In this way, it is possible to identify the boundary of the load level at which the processing durability of the test target device 10, which has been impaired, turns around and returns to normal.

[0062] (Variation 5) In the above-described embodiment, the load processing time TL is determined so as not to exceed the difference between the predetermined cycle Tc and the predetermined processing time TP. However, the load processing time TL may also be determined so as to exceed the difference between the predetermined cycle Tc and the predetermined processing time TP. FIG. 9 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In FIG. 9, the same symbols as in FIG. 2, and FIGS. 5 to 8 are used. A description of this configuration will be omitted. Note that even when the same symbols are used in FIG. 9, FIG. 2, and FIGS. 5 to 8, the same timing is not necessarily represented.

[0063] In the example shown in FIG. 9, within a predetermined period Tc starting from time t1, a predetermined process Pp is performed by the control unit 50 for a predetermined process time TP = TP1 from time t1 to time t2. For a load processing time TL = TL1 from time t2 to time t3 after the completion of the predetermined process Pp, a load process Lp is performed by the control unit 50. At the time t4 when the predetermined period Tc starting from time t1 ends, the load process Lp has not yet ended. The time t3 when the load process Lp ends is a time after the time t4 when the predetermined period Tc starting from time t1 ends.

[0064] This is realized as follows. First, the above-mentioned ratio r of the time load is determined in advance (for example, r = 1.2). The ratio r of the time load is a value greater than the minimum ratio rm1 and less than or equal to the maximum ratio rm2 (rm1 < r ≦ rm2). In this modification 5, the minimum ratio rm1 is equal to 1, and the maximum ratio rm2 is greater than 1. That is, the ratio r of the time load is at least greater than 1 (1 < r).

[0065] As described above, the fixed time Ts is equal to a fixed value r·Tc obtained by multiplying the predetermined period Tc by the ratio r of the time load. The determination unit 56 determines the load processing time TL = TL1 obtained as the difference between the fixed time Ts and the predetermined processing time TP = TP1. That is, the load processing time TL = TL1 is determined so as to exceed the difference between the predetermined period Tc and the predetermined processing time TP = TP1.

[0066] FIG. 9 shows that an overload state occurs in which the total processing time of the predetermined processing time TP and the load processing time TL exceeds the predetermined period Tc. In a new predetermined period Tc starting from time t4, the control unit 50 requests the start of the predetermined process Pp at time t4. However, since the load process Lp has not yet ended, the predetermined process Pp is not started. That is, the start request for the predetermined process Pp at time t4 fails. In that case, for example, a start error of the predetermined process Pp is detected by the control unit 50.

[0067] In this way, the processing performance of the test target device 10 in an overload state can be evaluated with high accuracy. Also, it can be verified whether the test target device 10 behaves unexpectedly due to the occurrence of an overload state. If the test target device 10 is the fuel injection control ECU described above, it is possible that the test target device 10 in an overload state will be unable to perform appropriate fuel injection control and will behave unexpectedly. Examples of unexpected behavior of the fuel injection control ECU include an operation that triggers a reset process for the fuel injection control ECU, as well as an operation that affects other ECUs or the vehicle.

[0068] (Variation 6) In the above-described embodiment, the control unit 50 performs the predetermined process Pp at every predetermined cycle Tc. The control unit 50 may perform a plurality of processes as the predetermined process Pp. In this case, the predetermined processing time TP required for the predetermined process Pp is the time required for all of the plurality of processes performed as the predetermined process Pp. Therefore, the load processing time TL determined using the predetermined processing time TP can be determined with high accuracy. Note that a plurality of control programs 40 executed by the calculation unit 20 may be provided, and each control program 40 may correspond to a respective one of the plurality of processes.

[0069] Furthermore, among the multiple processes performed as the predetermined process Pp, a portion of the process Ppa may have a lower processing priority than the remaining portion of the process Ppb. When the remaining portion of the process Ppb is started, the portion of the process Ppa is completed after the remaining portion of the process Ppb is completed. The predetermined processing time TP required for the predetermined process Pp is the time required for the portion of the process Ppa and the remaining portion of the process Ppb. Therefore, the load processing time TL determined using the predetermined processing time TP can be determined with high accuracy.

[0070] If the remaining processing Ppb has already started when a request to start a partial processing Ppa is made, the partial processing Ppa will be performed after the remaining processing Ppb. That is, the remaining processing Ppb, which has a relatively high processing priority, will be performed first, and then the partial processing Ppa, which has a relatively low processing priority, will be performed. In this case, the predetermined processing time TP required for the predetermined processing Pp is the time from when the remaining processing Ppb starts to when the partial processing Ppa ends.

[0071] Fig. 10 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In Fig. 10, the same symbols as in Fig. 2 and Figs. 5 to 9 are used. Explanation of the relevant configuration will be omitted. Note that even when the same symbols are used in Fig. 10, Fig. 2, and Figs. 5 to 9, they do not necessarily represent the same timing.

[0072] 10, similarly to FIG. 2, the control unit 50 performs both a predetermined process Pp and a load process Lp at predetermined cycles Tc. As the predetermined process Pp, a plurality of processes including a partial process Ppa and a remaining process Ppb are performed. The partial process Ppa has a lower processing priority than the remaining process Ppb.

[0073] As shown in Figure 10, within a predetermined cycle Tc starting at time t1, a remaining process Ppb, which has a relatively high processing priority, is performed from time t1 to time t2b. After the remaining process Ppb, a partial process Ppa, which has a relatively low processing priority, is performed from time t2b to time t2a. The predetermined processing time TP = TP1 required for the predetermined process Pp is the time from time t1, when the remaining process Ppb starts, to time t2a, when the partial process Ppa ends. After the partial process Ppa ends, a load process Lp is performed during a load processing time TL = TL1, from time t2a to time t3.

[0074] At time t4, the predetermined cycle Tc that started at time t1 ends, and a new predetermined cycle Tc begins. Within the predetermined cycle Tc that starts at time t4, the remaining processing Ppb, which has a relatively high processing priority, is performed from time t4 to time t5b. After the remaining processing Ppb, a portion of the processing Ppa, which has a relatively low processing priority, is performed from time t5b to time t5a.

[0075] The predetermined processing time TP=TP2 required for the predetermined process Pp is the time from time t4 when the remaining process Ppb starts to time t5a when the partial process Ppa ends. After the partial process Ppa ends, the load process Lp is performed during the load processing time TL=TL2 from time t5a to time t6. After time t7 when the predetermined cycle Tc that started at time t4 ends, the predetermined process Pp including the partial process Ppa and the remaining process Ppb and the load process Lp are similarly performed periodically.

[0076] Suppose that after a portion of a process Ppa with a relatively low processing priority has started but before it has finished, a request is made to start a remaining portion of a process Ppb with a relatively high processing priority. In this case, the portion of the process Ppa is interrupted and the remaining portion of the process Ppb is started. After the remaining portion of the process Ppb has finished, the portion of the process Ppa is resumed. In this case, the predetermined processing time TP required for the predetermined process Pp is the time from when the portion of the process Ppa has started, until the remaining portion of the process Ppb is performed while the portion of the process Ppa is interrupted, and until the resumed portion of the process Ppa finishes after the remaining portion of the process Ppb has finished.

[0077] FIG. 11 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In FIG. 11, the same symbols as in FIG. 2 and FIG. 5 to FIG. 10 are used. Explanation of the relevant configuration will be omitted. Note that even when the same symbols are used in FIG. 11, FIG. 2, and FIG. 5 to FIG. 10, they do not necessarily represent the same timing.

[0078] 11, similarly to FIG. 2, the control unit 50 performs both a predetermined process Pp and a load process Lp at predetermined cycles Tc. As the predetermined process Pp, a plurality of processes including a partial process Ppa and a remaining process Ppb are performed. The partial process Ppa has a lower processing priority than the remaining process Ppb.

[0079] As shown in Figure 11, within a predetermined cycle Tc starting at time t1, a portion of the process Ppa, which has a relatively low processing priority, is performed from time t1 to time t2as. If a request to start the remaining process Ppb, which has a relatively high processing priority, is made at time t2as before the completion of the portion of the process Ppa, the portion of the process Ppa is suspended. The remaining process Ppb is performed from time t2as to time t2b. After the remaining process Ppb is completed, the suspended portion of the process Ppa is resumed at time t2b. The portion of the process Ppa is performed from time t2b to time t2ae.

[0080] The predetermined processing time TP=TP1 required for the predetermined process Pp is the time from time t1 when the partial process Ppa starts, to time t2ae when the remaining process Ppb is performed while the partial process Ppa is suspended, and to time t2ae when the partial process Ppa resumes and finishes after the remaining process Ppb has finished. After the partial process Ppa finishes, the load process Lp is performed during the load processing time TL=TL1 from time t2ae to time t3.

[0081] At time t4, the predetermined cycle Tc that began at time t1 ends, and a new predetermined cycle Tc begins. Within the predetermined cycle Tc that begins at time t4, a portion of the processing Ppa, which has a relatively low processing priority, is performed from time t4 to time t5as. If a request is made to start the remaining processing Ppb, which has a relatively high processing priority, at time t5as before the completion of the portion of the processing Ppa, the portion of the processing Ppa is suspended. The remaining processing Ppb is performed from time t5as to time t5b. After the remaining processing Ppb is completed, the suspended portion of the processing Ppa is resumed at time t5b. The portion of the processing Ppa is performed from time t5b to time t5ae.

[0082] The predetermined processing time TP=TP2 required for the predetermined process Pp is the time from time t4 when the partial process Ppa is started, when the remaining process Ppb is performed while the partial process Ppa is suspended, to time t5ae when the partial process Ppa resumes after the remaining process Ppb is completed. The load process Lp is performed during the load processing time TL=TL2 from time t5ae after the partial process Ppa is completed to time t6. From time t7 when the predetermined cycle Tc that started at time t4 ends, the predetermined process Pp including the partial process Ppa and the remaining process Ppb and the load process Lp are similarly performed periodically.

[0083] (Variation 7) In the embodiment described above, the load processing Lp is performed within the same predetermined cycle Tc as the predetermined processing Pp, following the predetermined processing Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54. However, the load processing Lp may be performed within the predetermined cycle Tc following the predetermined cycle Tc in which the predetermined processing Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54 is performed.

[0084] Fig. 12 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In Fig. 12, the same symbols as in Fig. 2 and Figs. 5 to 11 are used. Explanation of the relevant configuration will be omitted. Note that even when the same symbols are used in Fig. 12, Fig. 2, and Figs. 5 to 11, they do not necessarily represent the same timing.

[0085] As described above, the acquisition unit 54 acquires the predetermined processing time TP required for the predetermined process Pp to be performed within the predetermined cycle Tc. The determination unit 56 determines the load processing time TL during which the load process Lp is performed, depending on the difference between the predetermined cycle Tc and the predetermined processing time TP. In the present seventh modification, the load processing time TL determined by the determination unit 56 is applied to the load process Lp to be performed within the predetermined cycle Tc following the predetermined cycle Tc during which the predetermined process Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54 is performed.

[0086] 12, a load processing time TL=TL1 determined using a predetermined processing time TP=TP1 required for a predetermined process Pp performed within a predetermined cycle Tc starting from time t1 is applied to a load processing Lp performed within a predetermined cycle Tc starting from time t4. That is, the load processing Lp is performed following the predetermined process Pp performed for a predetermined processing time TP=TP2 from time t4 to time t5. The load processing Lp is performed during a load processing time TL=TL1 from time t5 to time t6.

[0087] Furthermore, the load processing time TL=TL2 determined using the predetermined processing time TP=TP2 required for the predetermined process Pp performed within the predetermined cycle Tc starting at time t4 is applied to the load processing Lp performed within the predetermined cycle Tc starting at time t7. That is, the load processing Lp is performed following the predetermined processing Pp performed during the predetermined processing time TP=TP3 from time t7 to time t8. The load processing Lp is performed during the load processing time TL=TL2 from time t8 to time t9.

[0088] With this configuration, even if it takes time for the acquisition unit 54 to acquire the predetermined processing time TP and for the determination unit 56 to determine the load processing time TL, the load processing Lp can be performed following the predetermined processing Pp. If the predetermined processing time TP does not fluctuate significantly for each predetermined period Tc, the load processing time TL can be determined so as not to exceed the difference between the predetermined period Tc and the predetermined processing time TP by appropriately adjusting the temporal load ratio r. Therefore, the processing performance of the test target device 10 can be evaluated with high accuracy.

[0089] (Variation 8) In the above-described embodiment, the load processing Lp is performed within the same predetermined cycle Tc as the predetermined processing Pp, following the predetermined processing Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54. However, the predetermined processing Pp may also be performed within the predetermined cycle Tc following the predetermined cycle Tc in which the predetermined processing Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54 is performed. In other words, the load processing Lp is performed before the predetermined processing Pp.

[0090] Fig. 13 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In Fig. 13, the same symbols as in Fig. 2 and Figs. 5 to 12 are used. Explanation of the relevant configuration will be omitted. Note that even if the same symbols are used in Fig. 13, Fig. 2, and Figs. 5 to 12, they do not necessarily represent the same timing.

[0091] As described above, the acquisition unit 54 acquires the predetermined processing time TP required for the predetermined process Pp to be performed within the predetermined cycle Tc. The determination unit 56 determines the load processing time TL during which the load process Lp is performed, depending on the difference between the predetermined cycle Tc and the predetermined processing time TP. In the present modification 8, as in modification 7, the load processing time TL determined by the determination unit 56 is applied to the load process Lp to be performed within the predetermined cycle Tc following the predetermined cycle Tc during which the predetermined process Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54 is performed.

[0092] 13, a load processing time TL=TL1 determined using a predetermined processing time TP=TP1 required for a predetermined process Pp performed within a predetermined cycle Tc starting at time t1 is applied to a load processing Lp performed within a predetermined cycle Tc starting at time t4. Following the load processing Lp, a predetermined process Pp is performed within the same predetermined cycle Tc starting at time t4. That is, the load processing Lp is performed during the load processing time TL=TL1 from time t4 to time t6, before the predetermined process Pp is performed during the predetermined processing time TP=TP2 from time t6 to time t5.

[0093] Furthermore, a load processing time TL=TL2 determined using the predetermined processing time TP=TP2 required for the predetermined process Pp performed within the predetermined cycle Tc starting at time t4 is applied to the load processing Lp performed within the predetermined cycle Tc starting at time t7. Following this load processing Lp, a predetermined process Pp is performed within the same predetermined cycle Tc starting at time t7. That is, the load processing Lp is performed during the load processing time TL=TL2 from time t7 to time t9, before the predetermined process Pp is performed during the predetermined processing time TP=TP3 from time t9 to time t8.

[0094] With this configuration, even if it takes time for the acquisition unit 54 to acquire the predetermined processing time TP and for the determination unit 56 to determine the load processing time TL, the predetermined processing Pp can be performed following the load processing Lp. If the predetermined processing time TP does not fluctuate significantly for each predetermined period Tc, the load processing time TL can be determined so as not to exceed the difference between the predetermined period Tc and the predetermined processing time TP by appropriately adjusting the temporal load ratio r described above. Therefore, the processing performance of the test target device 10 can be evaluated with high accuracy.

[0095] (Variation 9) In the embodiment described above, the load processing Lp is performed within the same predetermined cycle Tc as the predetermined processing Pp, following the predetermined processing Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54. However, the predetermined processing Pp and the load processing Lp may be performed within the predetermined cycle Tc following the predetermined cycle Tc in which the predetermined processing Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54 is performed.

[0096] The predetermined processing Pp may be a plurality of processings including a partial processing Ppa and a remaining processing Ppb, in which case the remaining processing Ppb of the plurality of processings is followed by a load processing Lp, and the partial processing Ppa of the plurality of processings is followed by the load processing Lp.

[0097] Fig. 14 is a diagram for explaining the relationship between the predetermined processing time TP, the load processing time TL, and the predetermined cycle Tc. In Fig. 14, the same symbols as in Fig. 2 and Figs. 5 to 13 are used. Explanation of the relevant configuration will be omitted. Note that even if the same symbols are used in Fig. 14, Fig. 2, and Figs. 5 to 13, they do not necessarily represent the same timing.

[0098] As described above, the acquisition unit 54 acquires the predetermined processing time TP required for the predetermined process Pp to be performed within the predetermined cycle Tc. The determination unit 56 determines the load processing time TL during which the load process Lp is performed, depending on the difference between the predetermined cycle Tc and the predetermined processing time TP. In the present modification 9, as in the modification 7 and modification 8, the load processing time TL determined by the determination unit 56 is applied to the load process Lp to be performed within the predetermined cycle Tc following the predetermined cycle Tc during which the predetermined process Pp corresponding to the predetermined processing time TP acquired by the acquisition unit 54 is performed.

[0099] 14, within a predetermined cycle Tc starting at time t1, a remaining process Ppb, which has a relatively high processing priority, is performed from time t1 to time t2b. After the remaining process Ppb, a partial process Ppa, which has a relatively low processing priority, is performed from time t2b to time t2a. The predetermined processing time TP=TP1 required for the predetermined process Pp is the time from time t1 when the remaining process Ppb starts to time t2a when the partial process Ppa ends.

[0100] As shown in Fig. 14, a load processing time TL = TL1 determined using a predetermined processing time TP = TP1 required for a predetermined process Pp performed within a predetermined cycle Tc starting at time t1 is applied to a load processing Lp performed within a predetermined cycle Tc starting at time t4. The remaining process Ppb is performed during a processing time TP2b from time t4 to time t5b, followed by the load processing Lp. The load processing Lp is performed during a load processing time TL = TL1 from time t5b to time t6. Following the load processing Lp, a portion of the process Ppa is performed during a processing time TP2a from time t6 to time t5a.

[0101] The predetermined processing time TP=TP2 required for the predetermined process Pp performed within the predetermined cycle Tc starting from time t4 is acquired by the acquisition unit 54. The predetermined processing time TP=TP2 is the sum of the processing time TP2b from time t4 to time t5b during which the remaining process Ppb is performed, and the processing time TP2a from time t6 to time t5a during which part of the process Ppa is performed.

[0102] Furthermore, the load processing time TL=TL2 determined using the predetermined processing time TP=TP2 required for the predetermined process Pp performed within the predetermined cycle Tc starting at time t4 is applied to the load processing Lp performed within the predetermined cycle Tc starting at time t7. The load processing Lp is performed following the remaining process Ppb, which is performed during the processing time TP3b from time t7 to time t8b. The load processing Lp is performed during the load processing time TL=TL2 from time t8b to time t9. Following the load processing Lp, a portion of the process Ppa is performed during the processing time TP3a ​​from time t9 to time t8a.

[0103] The predetermined processing time TP=TP3 required for the predetermined process Pp performed within the predetermined cycle Tc starting from time t7 is acquired by the acquisition unit 54. The predetermined processing time TP=TP3 is the sum of the processing time TP3b from time t7 to time t8b during which the remaining process Ppb is performed, and the processing time TP3a ​​from time t9 to time t8a during which part of the process Ppa is performed.

[0104] With this configuration, even if it takes time for the acquisition unit 54 to acquire the predetermined processing time TP and for the determination unit 56 to determine the load processing time TL, the load processing Lp can be performed following the predetermined processing Pp. If the predetermined processing time TP does not fluctuate significantly for each predetermined period Tc, the load processing time TL can be determined so as not to exceed the difference between the predetermined period Tc and the predetermined processing time TP by appropriately adjusting the temporal load ratio r. Therefore, the processing performance of the test target device 10 can be evaluated with high accuracy.

[0105] Furthermore, the load processing Lp can be regarded as an interrupt processing that interrupts a predetermined processing Pp that is made up of multiple processes, and in this case, the processing performance of the test target device 10 in a state where an interrupt processing has occurred can be evaluated with high accuracy.

[0106] The following additional notes are disclosed regarding the above-described embodiment and modifications.

[0107] (Appendix 1) The testing method disclosed herein is a method for testing a control program (40) stored in a storage unit (22) and executed by a computing unit (20), and includes an acquisition step (S2) of acquiring a predetermined processing time (TP) required for a predetermined process (Pp) performed by the computing unit at a predetermined cycle (Tc) in accordance with the control program, a determination step (S3) of determining a load processing time (TL) for performing a load process (Lp) based on the difference between the predetermined cycle and the predetermined processing time, a load processing step (S4) of causing the computing unit to perform the load process in accordance with a load program (42), and an evaluation step (S5) of evaluating the processing performance of the computing unit that performs the predetermined process and the load processing. This configuration makes it possible to accurately evaluate the processing performance of a test target device operating in accordance with the control program when a load is applied.

[0108] (Appendix 2) In the test method according to Supplementary Note 1, when a plurality of processes are performed as the predetermined process at each predetermined period, the predetermined processing time may be the time required for all of the plurality of processes. With this configuration, the load processing time determined using the predetermined processing time can be determined with high accuracy.

[0109] (Appendix 3) In the test method described in Supplementary Note 2, a part of the processes (Ppa) among the plurality of processes may have a lower processing priority than the remaining processes (Ppb), and when the processing of the remaining processes is started, the part of the processes may be completed after the processing of the remaining processes, and the predetermined processing time may be the time required for the part of the processes and the processing of the remaining processes. With this configuration, it is possible to accurately determine the load processing time determined using the predetermined processing time.

[0110] (Appendix 4) The testing method according to Supplementary Note 1 may further include a timing step (S1) of timing a start time and an end time of the predetermined processing, and the predetermined processing time may be acquired in the acquisition step based on the start time and the end time measured in the timing step. With this configuration, a highly accurate predetermined processing time can be obtained.

[0111] (Appendix 5) In the testing method according to Supplementary Note 1, when the predetermined processing and the load processing are both performed at the predetermined cycle in the determining step, the load processing time in each cycle of the predetermined cycle may be determined to be a time obtained by subtracting a predetermined fixed time (Ts) from the predetermined processing time. With this configuration, it is possible to accurately evaluate the processing performance of the device under test when the total processing time of the predetermined processing time and the load processing time is the fixed time.

[0112] (Appendix 6) In the test method according to Supplementary Note 1, when the predetermined processing and the load processing are both performed at the predetermined cycle, the load processing time in each cycle of the predetermined cycle may be determined to be a predetermined fixed time (TL0). With this configuration, the load processing can be executed immediately after the predetermined processing is completed.

[0113] (Appendix 7) In the testing method according to Supplementary Note 1, when the predetermined processing and the load processing are both performed at the predetermined cycle, the load processing time may be determined so that the load processing time varies at the predetermined cycle. With this configuration, it is possible to accurately evaluate the processing performance of the test target device under a more realistic high-load condition.

[0114] (Appendix 8) In the testing method according to Supplementary Note 1, in the determining step, the load processing time may be determined so as not to exceed the difference between the predetermined cycle and the predetermined processing time. With this configuration, it is possible to accurately evaluate the processing performance of the test target device under high load conditions.

[0115] (Appendix 9) In the testing method according to Supplementary Note 1, the load processing time may be determined to exceed the difference between the predetermined cycle and the predetermined processing time in the determining step. With this configuration, the processing performance of the test target device in an overloaded state can be evaluated with high accuracy.

[0116] (Appendix 10) In the testing method according to Supplementary Note 1, in the determining step, the load processing time may be determined so as to vary monotonically for each predetermined period. With this configuration, it is possible to verify a load level at which the processing durability of the test target device is maintained and a load level at which the processing durability is impaired.

[0117] (Appendix 11) In the testing method according to Supplementary Note 10, in the determining step, the load processing time may be determined so as to monotonically increase for each of the predetermined cycles. With this configuration, it is possible to identify the boundary of the load level at which the processing durability of the device under test is eventually impaired.

[0118] (Appendix 12) In the testing method according to Supplementary Note 10, in the determining step, the load processing time may be determined so as to monotonically decrease for each of the predetermined cycles. With this configuration, it is possible to identify a boundary of a load level at which the processing durability of the device under test that has been impaired turns around and returns to normal.

[0119] (Appendix 13) In the test method according to Supplementary Note 1, in the load processing step, the load processing may be performed following the predetermined processing corresponding to the predetermined processing time acquired in the acquisition step, or the load processing may be performed following the predetermined processing within the predetermined period after the predetermined period in which the predetermined processing is performed. With this configuration, the processing performance of the test target device can be evaluated with high accuracy.

[0120] (Appendix 14) In the testing method according to Supplementary Note 1, in the load processing step, the predetermined processing may be performed following the load processing within a predetermined period after the predetermined period in which the predetermined processing corresponding to the predetermined processing time acquired in the acquisition step is performed. With this configuration, the processing performance of the test target device can be evaluated with high accuracy.

[0121] (Appendix 15) In the test method according to Supplementary Note 3, in the load processing step, the load processing may be performed following the remaining processing, and the part of the processing may be performed following the load processing, within the predetermined period after the predetermined period in which the predetermined processing corresponding to the predetermined processing time acquired in the acquisition step is performed. With this configuration, it is possible to accurately evaluate the processing performance of the device under test when interrupt processing occurs.

[0122] Although the present disclosure has been described in detail, the present disclosure is not limited to the individual embodiments described above. Various additions, substitutions, modifications, partial deletions, etc. are possible in these embodiments without departing from the gist of the present disclosure or the spirit of the present disclosure derived from the content of the claims and their equivalents. These embodiments can also be implemented in combination. For example, in the above-described embodiments, the order of each operation and the order of each process are shown as examples and are not limited to these. The same applies when numerical values ​​or mathematical expressions are used in the description of the above-described embodiments. [Explanation of symbols]

[0123] 10... Test target device 20, 90... Calculation unit 22, 92... Storage unit 40, 100... Control program 42... Load program 50... Control unit 52... Time counting unit 54... Acquisition unit 56... Determination unit 58... Load processing unit 60... Evaluation unit 70... Test execution device 80, 94... Communication unit

Claims

1. A method for testing a control program stored in a storage unit and executed by a calculation unit, comprising: an acquisition step of acquiring a predetermined processing time required for a predetermined process performed by the calculation unit at predetermined intervals in accordance with the control program; a determining step of determining a load processing time during which the load processing is performed according to a difference between the predetermined cycle and the predetermined processing time; a load processing step of causing the calculation unit to execute the load processing in accordance with a load program; an evaluation step of evaluating the processing performance of the calculation unit that performs the predetermined processing and the load processing; A test method comprising:

2. 2. The test method according to claim 1, A testing method, wherein, when a plurality of processes are performed as the predetermined process at each predetermined period, the predetermined processing time is the time required for all of the plurality of processes.

3. 3. The test method according to claim 2, Some of the processes have a lower processing priority than the remaining processes, When the processing of the remaining part is started, the processing of the part is completed after the processing of the remaining part, The predetermined processing time is the time required to process the part and the remaining part.

4. 2. The test method according to claim 1, a timing step of timing a start time and an end time of the predetermined process, A testing method, wherein in the obtaining step, the predetermined processing time is obtained based on the start time and the end time measured in the timing step.

5. 2. The test method according to claim 1, A testing method in which, in the determination step, when the specified processing and the load processing are both performed at the specified cycle, the load processing time in each cycle of the specified cycle is determined to be a time obtained as the difference between a predetermined constant time and the specified processing time.

6. 2. The test method according to claim 1, A testing method in which, in the determination step, when the specified processing and the load processing are both performed at the specified cycle, the load processing time in each cycle of the specified cycle is determined to be a fixed time that is set in advance.

7. 2. The test method according to claim 1, In the determining step, when the predetermined processing and the load processing are both performed at the predetermined cycle, the load processing time is determined so that the load processing time varies at the predetermined cycle.

8. 2. The test method according to claim 1, A testing method, wherein in the determining step, the load processing time is determined so as not to exceed the difference between the predetermined cycle and the predetermined processing time.

9. 2. The test method according to claim 1, A testing method, wherein in the determining step, the load processing time is determined to exceed the difference between the predetermined cycle and the predetermined processing time.

10. 2. The test method according to claim 1, A testing method, wherein in the determining step, the load processing time is determined so as to vary monotonically for each predetermined period.

11. 11. The test method of claim 10, A testing method, wherein in the determining step, the load processing time is determined so as to monotonically increase for each predetermined period.

12. 11. The test method of claim 10, A testing method, wherein in the determining step, the load processing time is determined so as to monotonically decrease for each predetermined period.

13. 2. The test method according to claim 1, A testing method in which, in the load processing step, the load processing is performed following the specified processing corresponding to the specified processing time acquired in the acquisition step, or the load processing is performed following the specified processing within the specified period after the specified period in which the specified processing is performed.

14. 2. The test method according to claim 1, A testing method in which, in the load processing step, the specified processing is performed following the load processing within a specified period after the specified period in which the specified processing corresponding to the specified processing time acquired in the acquisition step is performed.

15. 4. The test method according to claim 3, A testing method in which, in the load processing step, the load processing is performed following the remaining processing within a predetermined period after the predetermined period in which the predetermined processing corresponding to the predetermined processing time acquired in the acquisition step is performed, and the partial processing is performed following the load processing.

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