Semiconductor device

Abstract

To generalize wiring design of a semiconductor system.SOLUTION: A semiconductor device according to an embodiment includes a first semiconductor module and a second semiconductor module in each of which one or more semiconductor chips are stacked, and the first and second semiconductor modules are mounted on a first surface. A first signal line connecting a first electrode provided on a second surface opposite to the first surface and the first semiconductor module, a second signal line connecting a second electrode provided on the second surface and the second semiconductor module, a third signal line connected to the first signal line and having an end portion exposed to the third surface, and a fourth signal line connected to the second signal line, A wiring substrate including a fourth signal line having an end portion exposed to a third surface, and a cross-linking wiring connecting the end portions of the third and fourth signal lines to each other, A first signal is input to and output from the first and second semiconductor modules through the first and second signal lines.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] A semiconductor system has multiple semiconductor devices mounted on a mounting board. The semiconductor device may contain multiple semiconductor modules, each of which is made up of stacked semiconductor chips. Various signals are input and output to and from each of the multiple semiconductor modules via the mounting board.

[0003] Depending on the product application, signal lines transmitting the same signals may be shared among multiple semiconductor modules, or signal lines may be connected individually to each of the multiple semiconductor modules. This means that the wiring design of the semiconductor system must be changed for each application. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2023 / 0230956 [Patent Document 2] US Patent Application Publication No. 2018 / 0053738 [Patent Document 3] US Patent Application Publication No. 2008 / 0012150 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a semiconductor device that allows the wiring design of a semiconductor system to be generalized. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes a first semiconductor module and a second semiconductor module, each having one or more stacked semiconductor chips; a wiring substrate having the first and second semiconductor modules mounted on a first surface, a first signal line connecting the first semiconductor module to a first electrode provided on a second surface opposite the first surface, a second signal line connecting the second electrode provided on the second surface to the second semiconductor module, a third signal line connected to the first signal line and having an end exposed on the third surface, a fourth signal line connected to the second signal line and having an end exposed on the third surface, and a bridging wiring connecting the ends of the third and fourth signal lines, and a first signal is input / output to / from the first and second semiconductor modules via the first and second signal lines. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram showing an example of the configuration of a semiconductor system according to a first embodiment. [Figure 2] FIG. 1 is a diagram showing a detailed configuration of a semiconductor device according to a first embodiment. [Figure 3] 1A to 1C are diagrams illustrating in order some of the steps of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing a detailed configuration of the semiconductor device according to the first embodiment, illustrating a state after conversion from a first specification to a second specification. [Figure 5] FIG. 1 is a diagram illustrating a semiconductor system according to a comparative example. [Figure 6] FIG. 10 is a diagram illustrating a first modification of the first embodiment. [Figure 7] FIG. 10 is a diagram illustrating a second modification of the first embodiment. [Figure 8] FIG. 10 is a schematic diagram showing an example of the configuration of a semiconductor system according to a second embodiment. [Figure 9] FIG. 10 is a diagram showing a detailed configuration of a semiconductor device according to a second embodiment. [Figure 10] 10A to 10C are diagrams illustrating in order some of the steps of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 11]FIG. 10 is a diagram showing the detailed configuration of the semiconductor device according to the second embodiment, showing a state after conversion from a second specification to a first specification. [Figure 12] FIG. 10 is a diagram illustrating a modification of the second embodiment. [Figure 13] FIG. 10 is a diagram illustrating a modification of the second embodiment. [Figure 14] 10A and 10B are diagrams illustrating other modified examples. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0009] [Embodiment 1] Hereinafter, the first embodiment will be described in detail with reference to FIGS.

[0010] (Configuration example of semiconductor device) Fig. 1 is a schematic diagram showing an example of the configuration of a semiconductor system SA according to embodiment 1. More specifically, Fig. 1(a) is a cross-sectional view of the semiconductor system SA along the XZ direction, and Fig. 1(b) is a plan view of a semiconductor device 1a included in the semiconductor system SA when viewed from the negative Z direction (the bottom surface side of the semiconductor device 1a).

[0011] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, in Fig. 1(a), components that do not necessarily exist on the same cross section are shown.

[0012] In this specification, the side on which the semiconductor device 1a is mounted as viewed from the mounting substrate 2a is defined as the upper side, and the side of the mounting substrate 2a is defined as the lower side, with the vertical direction being defined as the Z direction. The X and Y directions are both directions along the surface of the mounting substrate 2a, and are perpendicular to each other. The direction indicated by the arrow on each axis is defined as the positive direction, and the direction opposite to the arrow on each axis is defined as the negative Z direction.

[0013] The semiconductor system SA of the first embodiment is, for example, an SSD (Solid State Drive), etc. As shown in Fig. 1(a), the semiconductor system SA includes a semiconductor device 1a, a semiconductor device 1b, and a mounting board 2a.

[0014] The semiconductor device 1b has a wiring substrate 30b and a controller chip 10b sealed on the wiring substrate 30b. The semiconductor device 1a has semiconductor chips CP1 to CP8 and CP11 to CP18 configured as nonvolatile memories or the like, as will be described later, and the controller chip 10b is configured as a memory controller incorporating an integrated circuit capable of controlling the operation of the semiconductor device 1a. A plurality of electrode terminals 40b are provided on the underside of the wiring substrate 30b. Each of the plurality of electrode terminals 40b functions as an external connection terminal of the semiconductor device 1b by being connected to the mounting substrate 2a.

[0015] The mounting substrate 2a is a printed circuit board (PCB) or the like in which insulating layers and conductive layers are alternately stacked multiple times. Each of the multiple conductive layers, including the conductive layer 21 shown in FIG. 1(a), is formed of a metal such as Cu. One end of each of the multiple conductive layers is connected to a corresponding one of multiple electrode terminals 40b of the semiconductor device 1b, and the other end is connected to a corresponding one of multiple electrode terminals included in a ball grid array 40a of the semiconductor device 1a, which will be described later. Each of the multiple conductive layers functions as a signal line for transmitting and receiving various signals between the semiconductor device 1b and the semiconductor device 1a.

[0016] Of the multiple conductive layers, conductive layer 21 is a signal line for transmitting and receiving a first signal between semiconductor device 1b and semiconductor device 1a. The first signal is, for example, a command signal, such as a command latch enable signal (CLE signal), an address latch enable signal (ALE signal), or a write enable signal (WE signal). The length of conductive layer 21 is, for example, approximately 200 mm. The first signal is transmitted and received through conductive layer 21 between semiconductor device 1b and semiconductor device 1a in, for example, approximately 1.4 ns.

[0017] The semiconductor device 1a is configured as a semiconductor package in which a first semiconductor module 10a and a second semiconductor module 11a are sealed on a wiring substrate 30a.

[0018] The wiring board 30a includes a core layer 32a, solder resist layers 31a and 33a, and a plurality of conductive layers including a conductive layer 35a.

[0019] The core layer 32a is disposed at the center of the wiring board 30a and is made of a prepreg or the like made of carbon fiber, glass fiber, aramid fiber, or the like impregnated with a thermosetting resin such as epoxy resin before curing.

[0020] The plurality of conductive layers have wiring patterns that extend in the X and Y directions on the core layer 32a, and vias that connect these wiring patterns in the Z direction. The plurality of conductive layers are formed of, for example, Cu.

[0021] The plurality of conductive layers extend in the Z direction through the core layer 32a, connect to either the first semiconductor module 10a or the second semiconductor module 11a on the upper surface of the core layer 32a, and connect to any electrode terminal of the ball grid array 40a on the lower surface of the core layer 32a. The plurality of conductive layers function as signal lines that transmit a plurality of signals transmitted from the plurality of conductive layers of the mounting substrate 2a to the first and second semiconductor modules 10a, 11a between the first semiconductor module 10a and the second semiconductor module 11a and the ball grid array 40a.

[0022] For example, among the multiple conductive layers, conductive layer 35a is a signal line that transmits a first signal transmitted from conductive layer 21 of the above-mentioned mounting substrate 2a to the first and second semiconductor modules 10a, 11a, and is composed of a first conductive layer 36a, a second conductive layer 37a, etc.

[0023] The first conductive layer 36a is connected to the first semiconductor module 10a on the upper surface of the core layer 32a, and is connected to the ball grid array 40a on the lower surface of the core layer 32a. That is, the first conductive layer 36a is a signal line that transmits and receives a first signal between the first semiconductor module 10a and the ball grid array 40a. Hereinafter, the first conductive layer 36a may be referred to as the first signal line 36a.

[0024] The second conductive layer 37a is connected to the second semiconductor module 11a on the upper surface of the core layer 32a, and is connected to the ball grid array 40a on the lower surface of the core layer 32a. That is, the second conductive layer 37a is a signal line that transmits and receives a first signal between the second semiconductor module 11a and the ball grid array 40a. Hereinafter, the second conductive layer 37a may be referred to as the second signal line 37a.

[0025] In addition, a bridge wiring 100a is provided between the first signal line 36a and the second signal line 37a to electrically connect the first signal line 36a and the second signal line 37a. As will be described later, the bridge wiring 100 is configured to be added as needed to the semiconductor device 1a that has been completed through a predetermined manufacturing process before being mounted on the mounting substrate 2a. The details of the bridge wiring 100a will be described later.

[0026] The solder resist layers 31a and 33a are formed of, for example, an insulating resin. The solder resist layer 31a covers the upper surface of the core layer 32a, and the solder resist layer 33a covers the lower surface of the core layer 32a. The solder resist layer 33a has an opening 330a on the lower surface of the core layer 32b between the electrode terminal to which the first signal line 36a is connected and the electrode terminal to which the second signal line 37a is connected, among the multiple electrode terminals of the ball grid array 40a. The bridge wiring 100a is exposed in the opening 330a. The solder resist layer 33a is an example of an insulating layer.

[0027] Hereinafter, the upper surface of wiring board 30a, i.e., the surface on which solder resist layer 31a is provided, may be referred to as surface 310a, which is the first surface, and the lower surface of wiring board 30a, i.e., the surface on which solder resist layer 33a is provided, may be referred to as surface 320a, which is the second surface. Surface 320a is also an example of the third surface.

[0028] A first semiconductor module 10a and a second semiconductor module 11a are mounted on a surface 310a of the wiring substrate 30a. Each of the first semiconductor module 10a and the second semiconductor module 11a has a configuration in which one or more semiconductor chips are stacked. The semiconductor chip is a small piece of a silicon substrate or the like on which a semiconductor element is mounted. The semiconductor element mounted on the semiconductor chip is, for example, a nonvolatile memory such as a NAND flash memory.

[0029] More specifically, the first semiconductor module 10a has, for example, semiconductor chips CP1 to CP8, and the second semiconductor module 11a has, for example, semiconductor chips CP11 to CP18. Spacers 70 are provided between the semiconductor chips CP4 and CP5, and between the semiconductor chips CP14 and CP15. The spacers 70 are small pieces of Si substrate or the like.

[0030] The semiconductor chips CP1 to CP8 and CP11 to CP18 are stacked so as to be shifted relative to each other in a predetermined direction along the surface 310a of the wiring substrate 30a. As a result, portions of the upper surface of each of the semiconductor chips CP1 to CP7 and CP11 to CP17 do not overlap with the semiconductor chips CP2 to CP8 and CP12 to CP18 directly above them. Electrodes (not shown) are provided on these portions and on the upper surfaces of the semiconductor chips CP8 and CP18. These electrodes are connected to, for example, the first signal line 36a and the second signal line 37a, respectively, by bonding wires 60 on the surface 310a of the wiring substrate 30a.

[0031] The surface 320a of the wiring substrate 30a is provided with the ball grid array 40a described above. The ball grid array 40a includes a plurality of electrode terminals. The ball grid array 40a functions as an external connection terminal of the semiconductor device 1a by connecting to electrode pads (not shown) of the mounting substrate 2a.

[0032] More specifically, as shown in FIG. 1(b), the ball grid array 40a includes a plurality of electrode terminals 41a provided in an area R10 that overlaps in the Z direction with the mounting position of the first semiconductor module 10a mounted on the surface 310a of the wiring board 30a, and a plurality of electrode terminals 42a provided in an area R11 that overlaps in the Z direction with the mounting position of the second semiconductor module 11a mounted on the surface 310a of the wiring board 30a.

[0033] The plurality of electrode terminals 41a provided in the region R10 are electrically connected to the first semiconductor module 10a via the plurality of conductive layers 35a. For example, the first electrode 411 of the plurality of electrode terminals 41a is connected to the first signal line 36a, and is electrically connected to the first semiconductor module 10a via the first signal line 36a.

[0034] The electrode terminals 42a provided in the region R11 are electrically connected to the second semiconductor module 11a via the conductive layers 35a. For example, the second electrode 421 of the electrode terminals 42a is connected to the second signal line 37a and is electrically connected to the second semiconductor module 11a via the second signal line 37a.

[0035] 1(a), the surface of the first electrode 411 facing the mounting substrate 2a is connected to the conductive layer 21 of the mounting substrate 2a. As a result, a first signal is input / output from the semiconductor device 1b to the first semiconductor module 10a via the conductive layer 21, the first electrode 411, and the first signal line 36a.

[0036] As described above, the first signal line 36a and the second signal line 37a are electrically connected via the bridging wiring 100a, so that the first signal is input to and output from the second semiconductor module 11a via the first signal line 36a and the second signal line 37a.

[0037] Fig. 2 is a diagram showing a detailed configuration of the semiconductor device 1a according to embodiment 1. Fig. 2(a) is an enlarged cross-sectional view of the semiconductor device 1a taken along line AA in Fig. 1(b), and Fig. 2(b) is an enlarged plan view of the semiconductor device 1a as viewed from the negative Z direction.

[0038] 2(a) and 2(b) show the state of the semiconductor device 1a before it is mounted on the mounting substrate 2a. Therefore, the semiconductor device 1a in FIGS. 2(a) and 2(b) does not yet have some components, such as the bridging wiring 100a. Also, in FIGS. 2(a) and 2(b), the description will mainly focus on the configuration of the wiring substrate 30a of the semiconductor device 1a. Therefore, some components, such as the configuration of the first semiconductor module 10a and the second semiconductor module 11a, may not be described.

[0039] As described above, the wiring board 30a includes the core layer 32a, the first signal line 36a and the second signal line 37a extending through the core layer 32a, and the solder resist layers 31a and 33a.

[0040] The first signal line 36a includes a wiring layer L1 extending along the surface 310a and connected to the first semiconductor module 10a via the bonding wire 60 (see FIG. 1(a)) described above, and a wiring layer L2 extending along the surface 320a and connected to the first electrode 411 and the third signal line 38a. The core layer 32a also includes a wiring layer L3 and via layers V0 and V1 that connect the wiring layers L1 and L2. The wiring layer L3 extends, for example, in the X and Y directions between the wiring layers L1 and L2. The via layer V0 extends in the Z direction in the core layer 32a between the wiring layers L1 and L3 to connect the wiring layers L1 and L3, and the via layer V1 extends in the Z direction in the core layer 32a between the wiring layers L3 and L2 to connect the wiring layers L3 and L2. However, the number and arrangement of the wiring layer L3 and via layers V0, V1, etc., which connect the wiring layers L1 and L2, are arbitrary.

[0041] The third signal line 38a is formed of a conductive material such as Cu. The third signal line 38a includes a wiring portion 383a connected to the wiring layer L2 and an end portion 381a connected to the wiring portion 383a. The wiring portion 383a and the end portion 381a are connected to the wiring layer L2 and extend in the positive direction of X along the surface 320a. The end portion 381a is exposed through an opening 330a in the solder resist layer 33a. In other words, the end portion 381a of the third signal line 38a reaches the surface 320a. Alternatively, the end portion 381a of the third signal line 38a may be said to be drawn out to the surface 320a.

[0042] The second signal line 37a includes a wiring layer L11 extending along the surface 310a and connected to the second semiconductor module 11a via the bonding wire 60 (see FIG. 1(a)), and a wiring layer L12 extending along the surface 320a and connected to the second electrode 421 and the fourth signal line 39a. The core layer 32a also includes a wiring layer L13 and via layers V10 and V11 that connect the wiring layers L11 and L12. The wiring layer L13 extends, for example, in the X and Y directions between the wiring layers L11 and L12. The via layer V10 extends in the Z direction in the core layer 32a between the wiring layers L11 and L13 to connect the wiring layers L11 and L13, and the via layer V11 extends in the Z direction in the core layer 32a between the wiring layers L13 and L12 to connect the wiring layers L13 and L12. However, the number and arrangement of the wiring layer L13 and via layers V10, V11, etc. that connect the wiring layers L11 and L12 are arbitrary.

[0043] The fourth signal line 39a is formed of a conductive material such as Cu. The fourth signal line 39a includes a wiring portion 393a connected to the wiring layer L12 and an end portion 391a connected to the wiring portion 393a. The wiring portion 393a and the end portion 391a are connected to the wiring layer L12 and extend in the negative X direction along the surface 320a. The end portion 391a is exposed through an opening 330a in the solder resist layer 33a. In other words, the end portion 391a of the fourth signal line 39a reaches the surface 320a. Alternatively, the end portion 391a of the fourth signal line 39a may be said to be drawn out to the surface 320a.

[0044] With this configuration, the first signal line 36a and the second signal line 37a can be electrically connected by later forming a bridging wire 100a that connects the end 381a and the end 391a as needed. That is, the end 381a and the end 391a are configured as bridging terminals 382a and 392a, respectively, when the bridging wire 100a is later formed.

[0045] As shown in FIG. 2(a), the bridging terminals 382a and 392a are each provided on the lower surface of the core layer 32a. That is, the bridging terminals 382a and 392a are each provided at the same height as the wiring layer L2 and the wiring layer L12, which extend along the lower surface of the core layer 32a. Furthermore, the bridging terminals 382a and 392a are not covered with the solder resist layer 33a and are therefore exposed on the surface 320a. The surface 320a is the surface that faces the mounting board 2a when the semiconductor device 1a is mounted on the mounting board 2a (see FIG. 1). That is, the bridging terminals 382a and 392a are each exposed on the surface 320a of the semiconductor device 1a that faces the mounting board 2a. Since the bridging terminals 382a and 392a are exposed on the surface 320a of the semiconductor device 1a, it is easy to form the bridging wire 100a bridging between the bridging terminals 382a and 392a. Furthermore, as will be described later, it is possible to form the bridging wire 100a bridging between the bridging terminals 382a and 392a after the semiconductor device 1a is manufactured and before the semiconductor device 1a is mounted on the mounting substrate 2a.

[0046] 2(b), when viewed from the Z direction, each of the bridging terminals 382a and 392a is preferably formed in a rectangular shape with one side along the Y direction longer than the width along the Y direction of the wiring portions 383a and 393a extending along the X direction. The bridging terminals 382a and 392a are also arranged side by side in a predetermined direction, with an interval of, for example, 1 mm or less between them. This facilitates the formation of the bridging wiring 100a that bridges between the bridging terminals 382a and 392a.

[0047] Furthermore, the bridging terminals 382a and 392a reach positions on the surface 320a on the line connecting the first electrode 411 and the second electrode 421 at the shortest distance. Specifically, as shown in FIG. 2(b), the bridging terminals 382a and 392a are disposed opposite each other across the line BB, which connects the first electrode 411 and the second electrode 421 in a straight line. As described above, the third signal line 38a extends from the wiring layer L2 connected to the first electrode 411, and the fourth signal line 39a extends from the wiring layer L12 connected to the second electrode 412. Therefore, by disposing the bridging terminals 382a and 392a opposite each other on the line BB, the lengths of the third signal line 38a and the fourth signal line 39a can be further shortened.

[0048] In this case, in the example of FIG. 2(b), the bridging terminals 382a and 392a are arranged to face each other in the direction along the X direction, but the bridging terminals 382a and 392a may be arranged to face each other in the direction along the Y direction, or may be arranged to face each other on a line connecting the first electrode 411 and the second electrode 421.

[0049] (Semiconductor system manufacturing method) Next, a method for manufacturing the semiconductor system SA, including a method for manufacturing the semiconductor device 1a of the first embodiment, will be described with reference to FIGS.

[0050] First, a method for manufacturing the semiconductor device 1a will be described with reference to Fig. 3. The manufacturing process for the semiconductor device 1a shown in Fig. 3 is carried out as part of the manufacturing process for the semiconductor system SA.

[0051] 3 is a diagram illustrating, in order, some steps of the method for manufacturing the semiconductor device 1a according to the first embodiment. However, in FIG. 3, the description will mainly focus on the steps related to forming the wiring substrate 30a among the manufacturing steps of the semiconductor device 1a. Therefore, the description of some steps, such as the manufacturing steps of the first semiconductor module 10a and the second semiconductor module 11a, may be omitted.

[0052] As shown in FIG. 3(a), a first signal line 36a and a second signal line 37a are formed on a wiring substrate 30a.

[0053] As shown in FIG. 3(b), a third signal line 38a is formed, connected to the first signal line 36a and extending along the surface 320a, and a fourth signal line 39a is formed, connected to the second signal line 37a and extending along the surface 320a. When the third signal line 38a and the fourth signal line 39a are formed, bridging terminals 382a and 392a are also formed. However, the third signal line 38a and the bridging terminal 382a may be formed together, and the fourth signal line 39a and the bridging terminal 392a may be formed together. Furthermore, the third signal line 38a, the fourth signal line 39a, and the bridging terminals 382a and 392a may all be formed together.

[0054] 3(c), the surface 320a is covered with a solder resist layer 33a. At this time, openings 330a for exposing the bridging terminals 382a and 392a and an opening 360a for forming the ball grid array 40a are formed in the solder resist layer 33a.

[0055] 3(d), a ball grid array 40a including the first electrode 411 and the second electrode 421 is formed in the opening 360a. This completes the manufacture of the semiconductor device 1a of the first embodiment.

[0056] The semiconductor device 1a manufactured in this manner is then mounted on a mounting substrate 2a, completed as a semiconductor system SA, and shipped as a product. Depending on the application of the product, various specifications may be required for the semiconductor system SA.

[0057] For example, a first specification may require that the same signal from the semiconductor device 1b be input / output to / from the first semiconductor module 10a and the second semiconductor module 11a via different signal lines, while a second specification may require that the same signal from the semiconductor device 1b be input / output to / from the first semiconductor module 10a and the second semiconductor module 11a via a common signal line.

[0058] For example, when the number of modules, such as the first semiconductor module 10a and the second semiconductor module 11a, included in the semiconductor device 1a is small, the second specification is often adopted. On the other hand, when the number of modules included in the semiconductor device 1a is large, the first specification is often adopted. That is, the first specification can be applied, for example, when it is desired to increase the capacity of the SSD of the semiconductor system SA. This is because by dividing the signal lines transmitting the same signal for each individual module, it is possible to suppress a decrease in signal transmission speed that accompanies an increase in the number of modules, which are units for signal input / output.

[0059] In this embodiment, as described above, the semiconductor device 1a is manufactured in advance so that the bridge wiring 100a (described later) can be added later, thereby enabling the semiconductor device 1a for the first specification to be converted to a semiconductor device for the second specification.

[0060] When the second specification is required, the manufacturing process of the semiconductor system SA includes a process for forming a bridging wire 100a that connects the bridging terminals 382a and 392a of the semiconductor device 1a. The process for forming the bridging wire 100a is performed after it has been determined that the semiconductor device 1a will comply with the second specification, that is, before the semiconductor device 1a, which has been stocked as a finished product, is mounted on the mounting substrate 2a. Note that when the second specification is not required, the following process does not need to be performed.

[0061] 4A and 4B are diagrams showing the detailed configuration of the semiconductor device according to the first embodiment, illustrating a state after conversion from a first specification to a second specification. Fig. 4A is an enlarged cross-sectional view of the semiconductor device 1a corresponding to Fig. 2A, and Fig. 4B is an enlarged plan view of the semiconductor device 1a corresponding to Fig. 2B.

[0062] As shown in FIGS. 4(a) and 4(b), a bridge wire 100a is formed to connect the bridge terminals 382a and 392a of the semiconductor device 1a so as to straddle the surfaces of the bridge terminals 382a and 392a. The bridge wire 100a is formed, for example, using an inkjet method. The bridge wire 100a is formed by including a conductive material such as Cu, which is sprayed from an inkjet head. For example, the conductive material may be Ag or Au. By forming the bridge wire 100a, the bridge terminals 382a and 392a are electrically connected. As a result, the first signal line 36a and the second signal line 37a are electrically connected via the third signal line 38a and the fourth signal line 39a.

[0063] Next, although not shown, the semiconductor device 1a with the bridge wiring 100a formed thereon is mounted on a mounting substrate 2a. As a result, the first signal input / output from the semiconductor device 1b is input / output to the first semiconductor module 10a and the second semiconductor module 11a via the conductive layer 21, the first electrode 411, the first signal line 36a, and the second signal line 37a, respectively. This completes the manufacturing of the semiconductor system SA of Embodiment 1.

[0064] [Comparative Example] 5A and 5B are diagrams illustrating a semiconductor system according to a comparative example, in which (a) and (b) show configuration examples of semiconductor systems SX and SY, respectively, of the comparative example.

[0065] As described above, various specifications are required of semiconductor systems depending on the application of the product.

[0066] For example, as a first technique for obtaining a semiconductor system having the second specification described above, a semiconductor device 1x is manufactured for the first specification, and then the semiconductor system is adapted to the second specification by changing the wiring layout of the mounting substrate 2a. Specifically, as shown in FIG. 5(a), a conductive layer 21 connecting the semiconductor device 1b and the first electrode 411 and a conductive layer 22 having one end connected to the conductive layer 21 and the other end connected to the second electrode 421 are provided in the mounting substrate 2a to obtain the mounting substrate 2x. This allows a semiconductor system SX to be obtained in which a first signal can be input / output from the semiconductor device 1b to the first semiconductor module 10a and the second semiconductor module 11a via the conductive layers 21 and 22, respectively.

[0067] As a second method for obtaining a semiconductor system having the second specification, a method of adapting the semiconductor system to the second specification by changing the wiring layout within the semiconductor device 1x may be used. Specifically, as shown in FIG. 5B, a conductive layer 200x connecting the first signal line 36a and the second signal line 37a is formed in advance on the surface 310a. This makes it possible to obtain a semiconductor device 1y and a semiconductor system SY that can input and output a first signal from the semiconductor device 1b to the first semiconductor module 10a and the second semiconductor module 11a via the first signal line 36a and the conductive layer 200x without changing the wiring layout of the mounting substrate 2a.

[0068] However, in order to be able to support either the first or second specifications, the first method requires the preparation of both a mounting board 2x that complies with the first specifications and a mounting board 2a that complies with the second specifications, whereas the second method requires the preparation of both a semiconductor device 1x that complies with the first specifications and a semiconductor device 1y that complies with the second specifications.

[0069] Furthermore, in the first method, the wiring length increases because a new conductive layer 22 branching from the conductive layer 21 is provided, which increases the amount of power loss and may result in a deterioration in the electrical characteristics of the semiconductor system SX.

[0070] [Summary] The wiring substrate 30a of the semiconductor device 1a of the first embodiment includes a first signal line 36a, a second signal line 37a, a third signal line 38a connected to the first signal line 36a and having an end 381a reaching the surface 320a, and a fourth signal line 39a connected to the second signal line 37a and having an end 391a reaching the surface 320a. The first signal line 36a and the second signal line 37a input and output first signals to and from the first semiconductor module 10a and the second semiconductor module 11a.

[0071] As a result, for example, before mounting the semiconductor device 1a on the mounting substrate 2a, the end 381a and end 391a that have reached the surface 320a can be connected as needed to electrically connect the first signal line 36a and the second signal line 37a. Since the signal line connections can be flexibly changed depending on the application required for the semiconductor system SA, it is no longer necessary to prepare multiple semiconductor devices 1x, 1y, etc. with different specifications in advance. This means that the versatility of the semiconductor device 1a in the design of the semiconductor system SA is enhanced.

[0072] Furthermore, since the first signal line 36a and the second signal line 37a can be connected without changing the wiring layout of the mounting board 2a, it is possible to suppress degradation of the electrical characteristics of the semiconductor system SA due to, for example, extending the wiring length of the mounting board 2a.

[0073] In the semiconductor device 1a of the first embodiment, the end 381a and the end 391a reach the position of the surface 320a on the line connecting the first electrode 411 and the second electrode 421 at the shortest distance.

[0074] This allows the lengths of the third signal line 38a and the fourth signal line 39a to be shorter, thereby reducing the amount of power loss and suppressing degradation of the electrical characteristics of the semiconductor system SA.

[0075] [Variation 1] FIG. 6 is a diagram illustrating a first modification of the first embodiment.

[0076] Modification 1 of Embodiment 1 differs from Embodiment 1 in the configuration of the bridge wiring. Note that, in the following, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0077] 6, the bridging wiring of Modification 1 includes a bonding wire 100aa. Specifically, one end of the bonding wire 100aa, which is made of a conductive material such as Cu, is bonded to a bridging terminal 382a, and the other end is bonded to a bridging terminal 392a. As a result, the bridging terminals 382a and 392a are connected via the bonding wire 100aa, and the first signal line 36a and the second signal line 37a are electrically connected.

[0078] [Variation 2] FIG. 7 is a diagram illustrating a second modification of the first embodiment.

[0079] Modification 2 of Embodiment 1 differs from Embodiment 1 and Modification 1 in the configuration of the bridge wiring. Note that, in the following, configurations similar to those in the above-described embodiments are denoted by the same reference numerals, and descriptions thereof may be omitted.

[0080] As shown in FIG. 7, the bridging wiring of Modification 2 includes a low-resistance component 100aaa. Specifically, one end of the low-resistance component 100aaa is connected to the bridging terminal 382a, and the other end is connected to the bridging terminal 392a. This connects the bridging terminals 382a and 392a via the low-resistance component 100aaa, electrically connecting the first signal line 36a and the second signal line 37a. The low-resistance component 100aaa has a resistance value of approximately 0 Ω, which further reduces power loss in the bridging wiring. The low-resistance component 100aaa may be, for example, a passive component.

[0081] [Embodiment 2] Hereinafter, the second embodiment will be described with reference to FIGS.

[0082] In the second embodiment, a semiconductor device for the second specification is configured to be adaptable to the first specification. As described above, the first specification is a specification in which different signals are input and output from the semiconductor device 1b to the first semiconductor module 10a and the second semiconductor module 11a, respectively.

[0083] The semiconductor device 1a of the first embodiment described above is a semiconductor device for a first specification that can be converted to a second specification, whereas the semiconductor device of the second embodiment is a semiconductor device for a second specification that can be converted to the first specification. When it becomes necessary to convert a semiconductor device for the second specification to the first specification, the bridging wiring connecting the bridging end portions of the semiconductor device may be cut. Note that, in the following, the same reference numerals are used for the same configurations as those of the above-described embodiments, and their description may be omitted.

[0084] (Configuration example of semiconductor device) Fig. 8 is a schematic diagram showing an example of the configuration of the semiconductor system SB according to embodiment 2. More specifically, Fig. 8 is a cross-sectional view of the semiconductor system SB along the XZ direction.

[0085] However, hatching is omitted in Fig. 8 to make the drawing easier to read. Also, Fig. 8 shows components that do not necessarily exist on the same cross section, and some wiring and the like are omitted.

[0086] 8, the semiconductor system SB of the second embodiment includes a mounting substrate 2aa, a semiconductor device 1b, and a semiconductor device 1aa. Conductive layers 21 and 22 are formed on the mounting substrate 2aa. The conductive layer 21 is a signal line for transmitting and receiving a first signal between the semiconductor device 1b and the semiconductor device 1aa. The conductive layer 22 is a signal line for transmitting and receiving a second signal between the semiconductor device 1b and the semiconductor device 1aa. The second signal is the same command signal as the first signal, and is, for example, one of a command latch enable signal (CLE signal), an address latch enable signal (ALE signal), a write enable signal (WE signal), etc.

[0087] The wiring board 30aa includes a core layer 32a, solder resist layers 31a and 33a, a first conductive layer 36a, and a second conductive layer 37a.

[0088] The first conductive layer 36a is connected to the first semiconductor module 10a on the surface 310a of the wiring substrate 30a and to the first electrode 411 on the surface 320a of the wiring substrate 30a. The second conductive layer 37a is connected to the second semiconductor module 11a on the surface 310a of the wiring substrate 30a and to the second electrode 421 on the surface 320a of the wiring substrate 30a. As described below, the bridge wire 110a provided between the first signal line 36a and the second signal line 37a to connect them is cut near its center. As a result, in the semiconductor device 1aa of the second embodiment, the first signal line 36a and the second signal line 37a are electrically separated. The cut portion of the bridge wire 110a is exposed in the opening 330aa of the solder resist layer 33a. Details of the bridge wire 110a will be described later.

[0089] The surface of the first electrode 411 facing the mounting board 2aa is connected to the conductive layer 21 of the mounting board 2aa, and the surface of the second electrode 421 facing the mounting board 2aa is connected to the conductive layer 22 of the mounting board 2aa. As described above, the first signal line 36a and the second signal line 37a are electrically isolated from each other. Therefore, a first signal input / output from the semiconductor device 1b is input / output to the first semiconductor module 10a via the conductive layer 21, and a second signal input / output from the semiconductor device 1b is input / output to the second semiconductor module 11a via the conductive layer 22.

[0090] Fig. 9 is a diagram showing a detailed configuration of the semiconductor device 1aa of embodiment 2. Fig. 9(a) is an enlarged cross-sectional view of the semiconductor device 1aa corresponding to Fig. 2(a), and Fig. 9(b) is an enlarged plan view of the semiconductor device 1aa corresponding to Fig. 2(b).

[0091] 9(a) and 9(b) show the semiconductor device 1aa in a state before being mounted on the mounting substrate 2aa. Therefore, the semiconductor device 1aa in FIGS. 9(a) and 9(b) shows the state before the bridging wiring 110a is cut. Also, in FIGS. 9(a) and 9(b), the configuration of the semiconductor device 1aa will be mainly described, focusing on the configuration of the wiring substrate 30aa. Therefore, the description of some of the configurations, such as the configurations of the first semiconductor module 10a and the second semiconductor module 11a, may be omitted.

[0092] As described above, the wiring board 30aa includes the core layer 32a, the first signal line 36a and the second signal line 37a extending through the core layer 32a, and the solder resist layers 31a and 33a.

[0093] The first signal line 36a includes a wiring layer L1 extending along the surface 310a and connected to the first semiconductor module 10a via the bonding wire 60 (see FIG. 1(a)) described above, and a wiring layer L2 extending along the surface 320a and connected to the first electrode 411 and the third signal line 38a. The core layer 32a also includes a wiring layer L3 and via layers V0 and V1 that connect the wiring layers L1 and L2. The wiring layer L3 extends, for example, in the X and Y directions between the wiring layers L1 and L2. The via layer V0 extends in the Z direction in the core layer 32a between the wiring layers L1 and L3 to connect the wiring layers L1 and L3, and the via layer V1 extends in the Z direction in the core layer 32a between the wiring layers L3 and L2 to connect the wiring layers L3 and L2.

[0094] The third signal line 38a is formed of a conductive material such as Cu. The third signal line 38a is connected to the wiring layer L2 and extends in the positive direction of X along the surface 320a. As a result, an end 381aa of the third signal line 38a is exposed through an opening 330aa in the solder resist layer 33a. In other words, the end 381aa of the third signal line 38a reaches the surface 320a.

[0095] The second signal line 37a includes a wiring layer L11 extending along the surface 310a and connected to the second semiconductor module 11a via the bonding wire 60 (see FIG. 1(a)), and a wiring layer L12 extending along the surface 320a and connected to the second electrode 421 and the fourth signal line 39a. The core layer 32a also includes a wiring layer L13 and via layers V10 and V11 that connect the wiring layers L11 and L12. The wiring layer L13 extends, for example, in the X and Y directions between the wiring layers L11 and L12. The via layer V10 extends in the Z direction in the core layer 32a between the wiring layers L11 and L13 to connect the wiring layers L11 and L13, and the via layer V11 extends in the Z direction in the core layer 32a between the wiring layers L13 and L12 to connect the wiring layers L13 and L12.

[0096] The fourth signal line 39a is formed of a conductive material such as Cu. The fourth signal line 39a is connected to the wiring layer L12 and extends in the negative X direction along the surface 320a. As a result, an end 391aa of the fourth signal line 39a is exposed through an opening 330aa in the solder resist layer 33a. That is, the end 391aa of the fourth signal line 39a reaches the surface 320a.

[0097] The surface 320a is covered with a solder resist layer 33a except for the opening 330aa and the regions where the first electrode 411 and the second electrode 421 are formed. The bridge wiring 110a is exposed in the opening 330aa. To convert the semiconductor device 1aa configured for the second specification to the first specification, the bridge wiring 110a exposed in the opening 330aa can be subsequently cut. This electrically separates the first signal line 36a and the second signal line 37a.

[0098] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor system SB, including a method for manufacturing the semiconductor device 1aa of the second embodiment, will be described with reference to FIGS.

[0099] First, a method for manufacturing the semiconductor device 1aa will be described with reference to Fig. 10. The manufacturing process for the semiconductor device 1aa shown in Fig. 10 is performed as part of the manufacturing process for the semiconductor system SB.

[0100] 10 is a diagram illustrating, in order, some steps of the method for manufacturing the semiconductor device 1aa according to the second embodiment. However, in FIG. 10, the description will mainly focus on the steps related to forming the wiring substrate 30aa among the manufacturing steps of the semiconductor device 1aa. Therefore, the description of some steps, such as the manufacturing steps of the first semiconductor module 10a and the second semiconductor module 11a, may be omitted.

[0101] As shown in FIG. 10(a), a first signal line 36a and a second signal line 37a are formed on a wiring substrate 30aa.

[0102] 10(b), a third signal line 38a is formed to be connected to the first signal line 36a, and a fourth signal line 39a is formed to be connected to the second signal line 37a. A bridging wire 110a is formed to connect an end 381aa of the third signal line 38a to an end 391aa of the fourth signal line 39a.

[0103] 10(c), the surface 320a is covered with a solder resist layer 33a. At this time, openings 330aa for exposing the bridge wiring 110a and openings 360a for forming the first electrode 411 and the second electrode 421 are formed in the solder resist layer 33a.

[0104] 10(d), the first electrode 411 and the second electrode 421 are formed in the opening 360a. This completes the manufacturing process of the semiconductor device 1aa of the first embodiment.

[0105] When the first specification is required, the manufacturing process of the semiconductor system SB involves cutting the bridging wire 110a connecting the bridging terminals 382aa and 392aa of the semiconductor device 1aa. The cutting process of the bridging wire 110a is performed after it is decided to apply the first specification, that is, immediately before the semiconductor device 1aa is mounted on the mounting board 2aa.

[0106] 11A and 11B are diagrams showing the detailed configuration of the semiconductor device 1aa according to the second embodiment, illustrating a state after conversion from the second specification to the first specification. Fig. 11A is an enlarged cross-sectional view of the semiconductor device 1a corresponding to Fig. 9A, and Fig. 11B is an enlarged plan view of the semiconductor device 1aa corresponding to Fig. 9B.

[0107] 11(a) and 11(b), the central portion of the bridging wire 110a connecting the end 381aa of the third signal wire 38a and the end 391aa of the fourth signal wire 39a is cut by, for example, dry etching, thereby separating the third signal wire 38a and the fourth signal wire 39a, and electrically separating the first signal wire 36a and the second signal wire 37a.

[0108] Next, although not shown, the semiconductor device 1aa with the bridging wiring 110a cut is mounted on a mounting board 2aa. As a result, a first signal input / output from the semiconductor device 1b is input / output to the first semiconductor module 10a via the first signal line 36a, and a second signal is input / output to the second semiconductor module 11a via the second signal line 37a. In other words, different signals are input / output from the semiconductor device 1b to the first semiconductor module 10a and the second semiconductor module 11a, respectively. This completes the manufacture of the semiconductor system SB of embodiment 2.

[0109] [Summary] The semiconductor device 1aa of the second embodiment includes a wiring substrate 30aa having a first signal line 36a, a second signal line 37a, a third signal line 38a connected to the first signal line 36a and having an end reaching the surface 320a, and a fourth signal line 39a connected to the second signal line 37a and having an end reaching the surface 320a. The first signal line 36a and the second signal line 37a input and output first signals to the first semiconductor module 10a and the second semiconductor module 11a. The semiconductor device 1aa also includes a bridge wiring 110a connecting an end 381aa of the third signal line 38a to an end 391aa of the fourth signal line 39a.

[0110] As a result, for example, immediately before mounting the semiconductor device 1a on the mounting substrate 2a, if necessary, the bridge wiring 110a connecting the end 381a and the end 391a drawn out to the surface 320a can be cut to electrically separate the first signal line 36a and the second signal line 37a. This makes it possible to convert the semiconductor device 1aa for the second specification into a device for the first specification. In other words, the versatility of the semiconductor device 1aa in the design of the semiconductor system SA is increased.

[0111] [Variations] 12 and 13 are diagrams illustrating a modification of the second embodiment.

[0112] The modified example of the second embodiment differs from the second embodiment in the configuration of the bridge wiring. In the following, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0113] Figures 12 and 13 are diagrams showing the detailed configuration of a semiconductor device 1aaa according to a modified example of embodiment 2. More specifically, Figures 12(a) and 13(a) are enlarged cross-sectional views of the semiconductor device 1aaa corresponding to Figure 11(a), and Figures 12(b) and 13(b) are enlarged plan views of the semiconductor device 1aaa corresponding to Figure 11(b).

[0114] 12(a) and 12(b) are diagrams showing the semiconductor device 1aaa in a state before being mounted on a mounting substrate 2a.

[0115] As described above, the wiring board 30aaa includes the core layer 32a, the first signal line 36a and the second signal line 37a extending through the core layer 32a, and the solder resist layers 31a and 33a.

[0116] The first conductive layer 36a includes wiring layers L1 to L3 and via layers V0 to V1, and the second conductive layer 37a includes wiring layers L11 to L13 and via layers V10 to V11.

[0117] 12(a), the third signal line 38aa is connected to the wiring layer L3 and extends through the core layer 32a in the positive direction of X. The fourth signal line 39aa is connected to the wiring layer L13 and extends through the core layer 32a in the negative direction of X.

[0118] An end 381aaa of the third signal line 38aa and an end 391aaa of the fourth signal line 39aa are connected via a bridging via 120a. The end 381aaa of the third signal line 38aa is the other end of the connection end with the wiring layer L3, and the end 391aaa of the fourth signal line 39aa is the other end of the connection end with the wiring layer L13. The bridging via 120a extends through the core layer 32a in the negative Z direction, and its end 123a is exposed in an opening 330aaa in the solder resist layer 33a.

[0119] 12(b), the bridging via 120a includes a conductive layer 121a made of a conductive material such as Cu, and an insulating layer 122a formed inside the conductive layer 121a. An end 381aaa of the third signal line 38aa and an end 391aaa of the fourth signal line 39aa are connected to the conductive layer 121a, thereby electrically connecting the third signal line 38aa and the fourth signal line 39aa.

[0120] As described above in the description of the second embodiment, when conversion of the semiconductor device 1aaa configured to be applicable to the second specification to the first specification is required, the bridging vias 120a of the semiconductor device 1aaa are cut after it is decided to apply the first specification, that is, before the semiconductor device 1aaa is mounted on the mounting substrate 2a.

[0121] 13(a) and 13(b) are diagrams showing the state of the semiconductor device 1aaa immediately before it is mounted on the mounting substrate 2a.

[0122] 13(a) and 13(b), a bridging via 120a connecting an end 381aaa of the third signal line 38a and an end 391aaa of the fourth signal line 39a is cut, for example, by back drilling. This electrically separates the third signal line 38aa from the fourth signal line 39aa, and electrically separates the first signal line 36a from the second signal line 37a. A recess 124a extending in the Z direction on the wiring substrate 30aaa is formed in the portion where the bridging via 120a has been cut.

[0123] [Other variations] FIG. 14 is a diagram illustrating another modified example.

[0124] 14(a) and 14(b) show a semiconductor device without a bridging wiring, where Fig. 14(a) is an enlarged cross-sectional view of the semiconductor device 1aaaaa, and Fig. 14(b) is a plan view of the semiconductor device 1aaaaa as viewed from the positive Z direction (the top surface side of the semiconductor device 1aaaaaa).

[0125] For example, as shown in FIG. 14(a), an end 381aaa of a third signal line 38aaa and an end 391aaa of a fourth signal line 39aaa may be extended to a side surface of a wiring substrate 30a of a semiconductor device 1aaaa. A bridge wiring may then be formed on the side surface of the wiring substrate 30a to connect the end 381aaa and the end 391aaa. Because the side surface of the wiring substrate 30a does not include a dense structure such as a ball grid array, the bridge wiring can be easily formed and cut. The side surface of the wiring substrate 30a is an example of a third surface.

[0126] Alternatively, as shown in FIG. 14(b), the ends 381aaaa and 391aaaa may reach the top surface of the semiconductor device 1aaaaa. Then, a bridge wiring connecting the ends 381aaaa and 391aaaaa may be formed on the top surface of the semiconductor device 1aaaaa. Because the top surface of the semiconductor device 1aaaaa does not include a ball grid array or other configuration, the bridge wiring can be easily formed and cut. The top surface of the semiconductor device 1aaaaa is an example of a third surface.

[0127] In the above embodiment, an example has been described in which one semiconductor device 1a and one semiconductor device 1b are mounted on the mounting substrate 2 in the semiconductor system, but the present invention is not limited to this. The number of semiconductor devices 1a mounted on the mounting substrate 2 may be any number, such as two, four, or eight.

[0128] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0129] DESCRIPTION OF SYMBOLS 1a, 1aa, 1aaa, 1b...semiconductor device, 2a, 2aa...mounting substrate, 10a...first semiconductor module, 11a...second semiconductor module, 30a, 30aa, 30aaa, 30b...wiring substrate, 31a, 33a...solder resist layer, 32a...core layer, 36a...first signal line, 37a...second signal line, 38a, 38aa...third signal line, 39a, 39aa...fourth signal line, 40a...ball grid array, 100a...bridged wiring, 100a a...bonding wire, 100aaa...low resistance component, 110a...bridged wiring, 120a...bridged via, 310a, 320a...surface, 330a, 330aa...opening, 381a, 381aa, 381aaa, 391a, 391aa, 391aaa...end, 382a, 382aa, 392a, 392aa...bridged terminal, 411...first electrode, 421...second electrode, CP1 to CP8, CP11 to CP18...semiconductor chip, SA, SB...semiconductor system.

Claims

1. a first semiconductor module and a second semiconductor module, each of which has one or more semiconductor chips stacked thereon; a wiring board having the first and second semiconductor modules mounted on a first surface, a first signal line connecting the first semiconductor module to a first electrode provided on a second surface opposite to the first surface, a second signal line connecting the second electrode provided on the second surface to the second semiconductor module, a third signal line connected to the first signal line and having an end exposed on a third surface, and a fourth signal line connected to the second signal line and having an end exposed on the third surface; a bridging wiring that connects the ends of the third and fourth signal lines; Equipped with The first and second semiconductor modules include: a first signal is input / output from the first and second signal lines; Semiconductor device.

2. The ends of the third and fourth signal lines are exposed at a position on the third surface on a line connecting the first and second electrodes at the shortest distance; The semiconductor device according to claim 1 .

3. the bridging wiring is formed by including a conductive material ejected from an inkjet head; The semiconductor device according to claim 1 .

4. The bridge wiring is a bonding wire. The semiconductor device according to claim 1 .

5. The bridge wiring is a passive component. The semiconductor device according to claim 1 .

6. the third surface is the second surface of the wiring substrate; The semiconductor device according to claim 1 .

7. The wiring board is an insulating layer provided on the third surface side of the wiring substrate, the insulating layer having openings through which the ends of the third and fourth signal lines are exposed; The semiconductor device according to claim 1 .

8. a first semiconductor module and a second semiconductor module, each of which has one or more semiconductor chips stacked thereon; a wiring board having first and second semiconductor modules mounted on a first surface, a first signal line connecting a first electrode provided on a second surface opposite to the first surface to the first semiconductor module, a second signal line connecting a second electrode provided on the second surface to the second semiconductor module, a third signal line connected to the first signal line, a fourth signal line connected to the second signal line, and bridging vias connected to the other ends of the connection ends of the third and fourth signal lines with the first and second signal lines, and having ends exposed on a third surface; Equipped with The first and second semiconductor modules include: a first signal is input / output from the first and second signal lines; Semiconductor device.

Images