Controller circuit, step-up / step-down DC / DC converter, and vehicle equipped with the same

Abstract

To provide a controller circuit capable of achieving an appropriate operation of a step-up / down DC / DC converter even when a peak voltage of a ramp voltage for generating a PWM signal changes.SOLUTION: The controller circuit 10 includes a ramp voltage generation circuit 140 for generating a ramp voltage, an intermediate voltage generation circuit 150 for generating an intermediate voltage of the ramp voltage based on the ramp voltage generated by the ramp voltage generation circuit, and an error amplifier circuit for generating an error signal. The control circuit includes an inverting amplifier that generates an inversion signal, a first comparator that compares a ramp voltage and an error signal to generate a first PWM signal, a second comparator that compares a ramp voltage and the inversion signal to generate a second PWM signal, and a logic circuit 100 that generates a control signal for controlling operations of a high-side transistor and a low-side transistor based on the first PWM signal and the second PWM signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a controller circuit, a step-up / step-down DC / DC converter, and a vehicle equipped with the same. [Background technology]

[0002] A step-up / step-down DC / DC converter capable of both stepping up and stepping down is known (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-153080

[0004] [overview] However, the inventors have come to recognize the following problem. There are various control methods for buck-boost DC / DC converters. One of these methods generates a ramp voltage based on a clock signal, and uses the intermediate voltage of that ramp voltage to generate a PWM (Pulse Width Modulation) signal for PWM control. However, with this method, if the peak voltage of the ramp voltage changes due to changes in the frequency of the clock signal, the intermediate voltage of the ramp voltage also changes, and this can prevent the buck-boost DC / DC converter from operating properly.

[0005] The present disclosure has been made in light of these circumstances, and one of its exemplary purposes is to provide a controller circuit that can achieve appropriate operation of a step-up / step-down DC / DC converter even when the peak voltage of the ramp voltage for generating a PWM signal changes.

[0006] A controller circuit according to an embodiment of the present disclosure generates an output voltage according to an input voltage. The controller circuit includes: a step-down switch circuit including a high-side transistor and receiving an input voltage; a step-up switch circuit including a low-side transistor and outputting an output voltage; a ramp voltage generation circuit generating a ramp voltage based on a clock signal; an intermediate voltage generation circuit generating an intermediate voltage of the ramp voltage based on the ramp voltage generated by the ramp voltage generation circuit; an error amplifier circuit generating an error signal based on an error between a feedback voltage of the output voltage and a reference voltage; an inverting amplifier inverting the error signal based on the intermediate voltage generated by the intermediate voltage generation circuit to generate an inverted signal; a first comparator comparing the ramp voltage with the error signal to generate a first PWM signal; a second comparator comparing the ramp voltage with the inverted signal to generate a second PWM signal; and a logic circuit generating control signals for controlling the operation of the high-side transistor and the low-side transistor based on the first PWM signal and the second PWM signal.

[0007] Any combination of the above components and conversion of the expressions of the present disclosure into methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a step-up / step-down DC / DC converter according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a timing chart showing an example of ramp voltages generated by the first ramp voltage generator and the second ramp voltage generator according to the embodiment. [Figure 3] FIG. 3 is a timing chart showing an example of operation in the buck mode of the buck-boost DC / DC converter according to the embodiment. [Figure 4] FIG. 4 is a timing chart showing an example of operation in the step-up mode of the step-up / step-down DC / DC converter according to the embodiment. [Figure 5]FIG. 5 is a timing chart for explaining an example of the operation of the intermediate voltage generating circuit according to the embodiment. [Figure 6] FIG. 6 is a timing chart showing an example of a ramp voltage that is affected by the operation of the intermediate voltage generating circuit according to the embodiment. [Figure 7] FIG. 7 is a timing chart showing another example of operation of the step-up / step-down DC / DC converter according to the same embodiment.

[0009] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0010] A controller circuit according to one embodiment generates an output voltage according to an input voltage. The controller circuit includes: a step-down switch circuit including a high-side transistor and receiving an input voltage; a step-up switch circuit including a low-side transistor and outputting an output voltage; a ramp voltage generation circuit generating a ramp voltage based on a clock signal; an intermediate voltage generation circuit generating an intermediate voltage of the ramp voltage based on the ramp voltage generated by the ramp voltage generation circuit; an error amplifier circuit generating an error signal based on an error between a feedback voltage of the output voltage and a reference voltage; an inverting amplifier inverting the error signal based on the intermediate voltage generated by the intermediate voltage generation circuit to generate an inverted signal; a first comparator comparing the ramp voltage with the error signal to generate a first PWM signal; a second comparator comparing the ramp voltage with the inverted signal to generate a second PWM signal; and a logic circuit generating control signals for controlling the operation of the high-side transistor and the low-side transistor based on the first PWM signal and the second PWM signal.

[0011] According to this configuration, the intermediate voltage generation circuit generates an intermediate voltage of the ramp voltage based on the ramp voltage generated by the ramp voltage generation circuit. As a result, even if the peak voltage of the ramp voltage for generating the PWM signal changes, the intermediate voltage of the ramp voltage can be generated in accordance with the change, thereby realizing proper operation of the step-up / step-down DC / DC converter.

[0012] In one embodiment, the ramp voltage generating circuit may include a first ramp voltage generator and a second ramp voltage generator, each generating a ramp voltage. The second ramp voltage generator may be configured to synchronize with the first ramp voltage generator and generate a ramp voltage having the same shape as the ramp voltage generated by the first ramp voltage generator. The intermediate voltage generating circuit may generate an intermediate voltage of the ramp voltages based on the ramp voltage generated by the first ramp voltage generator. The first comparator may compare the ramp voltage generated by the second ramp voltage generator with an error signal to generate a first PWM signal. The second comparator may compare the ramp voltage generated by the second ramp voltage generator with an inverted signal to generate a second PWM signal.

[0013] In one embodiment, the first ramp voltage generator and the second ramp voltage generator may each generate a ramp voltage based on a common clock signal. The intermediate voltage generation circuit may include a phase adjustment circuit that generates a clock signal by adjusting the phase of the common clock signal, and a sample-and-hold circuit that samples and holds the ramp voltage generated by the first ramp voltage generator. The phase adjustment circuit may generate a clock signal by adjusting the phase of the common clock signal so that the sample-and-hold circuit can sample and hold an intermediate voltage of the ramp voltage generated by the first ramp voltage generator based on the phase-adjusted clock signal.

[0014] In one embodiment, the sample-and-hold circuit may include a switch that operates in response to the clock signal whose phase is adjusted by the phase adjustment circuit, and a capacitor that samples and holds the ramp voltage generated by the first ramp voltage generator. The capacitor may be configured to sample the ramp voltage generated by the first ramp voltage generator when the switch is on and to hold the sampled voltage when the switch is off.

[0015] In one embodiment, the ramp voltage generating circuit may change the peak voltage of the ramp voltage that it generates in response to changes in the frequency of the input clock signal.

[0016] In one embodiment, the ramp voltage generating circuit may change the peak voltage of the ramp voltage in response to a change in the input voltage.

[0017] In one embodiment, it may be monolithically integrated on a single semiconductor chip.

[0018] A step-up / step-down DC / DC converter according to one embodiment may include the controller circuit.

[0019] A vehicle according to an embodiment may be equipped with the above-described step-up / step-down DC / DC converter.

[0020] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0021] In this specification, "component A is connected to component B" includes not only a case where component A and component B are directly physically connected, but also a case where component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0022] Similarly, "component C is connected (provided) between component A and component B" includes not only a case where component A and component C, or component B and component C, are directly connected, but also a case where they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0023] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0024] In this specification, "mono-integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are mono-integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate to adjust the circuit constants.

[0025] 1 is a block diagram of a buck-boost DC / DC converter 1 according to an embodiment of the present disclosure. IN Output voltage V according toOUT The step-up / step-down DC / DC converter 1 may be mounted on a vehicle, for example. The step-up / step-down DC / DC converter 1 according to this embodiment includes a semiconductor circuit 10 and peripheral circuits 20a and 20b.

[0026] The semiconductor circuit 10 is a controller circuit that controls the operation of the step-up / step-down DC / DC converter 1. The semiconductor circuit 10 according to this embodiment mainly includes a logic circuit 100, a step-down driver 102, a step-up driver 104, a step-down switch circuit 110, a step-up switch circuit 112, an error amplifier circuit 120, a clock signal generation circuit 130, a ramp voltage generation circuit 140, an intermediate voltage generation circuit 150, an inverting amplifier 160, a first comparator 162, a second comparator 164, transistors MP1 and MP2, and diodes D1 and D2. The semiconductor circuit 10 may be monolithically integrated on a single semiconductor substrate.

[0027] The semiconductor circuit 10 of this embodiment further includes various pins to be connected to the circuit elements of the peripheral circuits 20a and 20b, respectively, and specifically includes a feedback pin FB, pins COMP, SYNC, and SS, an input pin IN, an output pin OUT, a ground pin GND, switching pins LX1 and LX2, and bootstrap pins BS1 and BS2.

[0028] The step-down switch circuit 110 receives an input voltage V through an input pin IN. INis input. The step-down switch circuit 110 includes a first high-side transistor MH1 and a first low-side transistor ML1. The first high-side transistor MH1 and the first low-side transistor ML1 are each configured as an N-channel MOS (Metal Oxide Semiconductor) transistor. The first low-side transistor ML1 may be replaced with another switch element such as a diode. The drain of the first high-side transistor MH1 is connected to the input pin IN. The source of the first low-side transistor ML1 is connected to the ground pin GND. A switching pin LX1 is connected to a node N1 between the first high-side transistor MH1 and the first low-side transistor ML1.

[0029] The boost switch circuit 112 outputs the output voltage V OUT The boost switch circuit 112 includes a second high-side transistor MH2 and a second low-side transistor ML2. The second high-side transistor MH2 and the second low-side transistor ML2 are each configured as an N-channel MOS transistor. The second high-side transistor MH2 may be replaced with another switch element, such as a diode. The drain of the second high-side transistor MH2 is connected to the output pin OUT. The source of the second low-side transistor ML2 is connected to the ground pin GND. A switching pin LX2 is connected between the second high-side transistor MH2 and the second low-side transistor ML2.

[0030] The logic circuit 100 generates a first PWM signal S PWM1 and the second PWM signal S PWM2Based on these, control signals SH1, SL1, SH2, and SL2 are generated to control the operations of the transistors in the step-down switch circuit 110 and the transistors in the step-up switch circuit 112. The control signals SH1, SL1, SH2, and SL2 are signals to control the operations of the first high-side transistor MH1, the first low-side transistor ML1, the second high-side transistor MH2, and the second low-side transistor ML2, respectively.

[0031] The logic circuit 100 may generate the control signals SH1, SL1, SH2, and SL2 so that the step-down switch circuit 110 and the step-up switch circuit 112 operate in conjunction with each other, specifically, so that when the step-down switch circuit 110 operates at a certain duty ratio, the step-up switch circuit 112 operates at a duty ratio corresponding to the duty ratio of the step-down switch circuit 110. More specifically, the logic circuit 100 generates the control signals SH1 and SL2 so that the first high-side transistor MH1 and the second low-side transistor ML2 operate complementarily, i.e., so that when one transistor is high, the other transistor is low.

[0032] The logic circuit 100 according to this embodiment generates a first PWM signal S PWM1 and the second PWM signal S PWM2 The logic circuit 100 generates the control signal SH1 by taking the XNOR of the first PWM signal S PWM1 and the second PWM signal S PWM2 The control signal SL2 is generated by taking an XOR of these signals. This generates the control signal SL2 which is an inversion of the control signal SH1.

[0033] The step-down driver 102 and the step-up driver 104 are connected to an internal power supply V REGThe step-down driver 102 drives the first high-side transistor MH1 and the first low-side transistor ML1 of the step-down switch circuit 110 based on control signals SH1 and SL1. The step-up driver 104 drives the second high-side transistor MH2 and the second low-side transistor ML2 of the step-up switch circuit 112 based on control signals SH2 and SL2.

[0034] The transistors MP1 and MP2 are each configured as a P-channel MOS transistor. The drains of the transistors MP1 and MP2 are connected to the internal power supply voltage V REG The source of transistor MP1 is connected to bootstrap pin BS1, and the source of transistor MP2 is connected to bootstrap pin BS2. The anodes of diodes D1 and D2 are connected to the internal power supply voltage V REG The cathode of diode D1 is connected to bootstrap pin BS1, and the cathode of diode D2 is connected to bootstrap pin BS2.

[0035] The error amplifier circuit 120 outputs an output voltage V OUT The feedback voltage V FB and the reference voltage V REF Based on the error between ERR2 The error amplifier circuit 120 according to this embodiment generates an output voltage V OUT and configured to feed back a current I1 flowing between the node N1 and the ground pin GND. The error amplifier circuit 120 includes a first error amplifier 122, a second error amplifier 124, a soft start circuit 126, and a current detection circuit 128.

[0036] The soft start circuit 126 is connected to the pin SS. The soft start circuit 126 generates a soft start voltage V SS Generates the soft start voltage V SS is input to the first error amplifier 122.

[0037] The first error amplifier 122 outputs a feedback voltage VFB and the reference voltage V REF The error signal S ERR1 Generates an error signal S ERR1 is input to the inverting input terminal of the second error amplifier 124. The inverting input terminal of the first error amplifier 122 receives the feedback voltage V via the feedback pin FB. FB The non-inverting input terminal of the first error amplifier 122 receives a reference voltage V REF The output terminal of the first error amplifier 122 is connected to a pin COMP.

[0038] The current detection circuit 128 detects the current I1 flowing between the node N1 and the ground pin GND, and outputs a detection signal S according to the detection result. SNS A detection signal S SNS is input to the non-inverting input terminal of the second error amplifier 124.

[0039] The second error amplifier 124 outputs the error signal S ERR1 and the detection signal S SNS The error signal S ERR2 Generates an error signal S ERR2 is input to the inverting input terminal of the inverting amplifier 160 and the non-inverting input terminal of the first comparator 162.

[0040] The clock signal generating circuit 130 generates a clock signal CL1. The clock signal generating circuit 130 includes an oscillator 132 and an OR circuit 134. The oscillator 132 generates a clock signal S CLK The OR circuit 134 generates the signal S input via the pin SYNC. SY and clock signal S CLK The clock signal CL1 is input to the ramp voltage generating circuit 140 and the intermediate voltage generating circuit 150. The signal S SY When is high, clock signal CL1 is synchronized with clock signal S CLK Then, the signal S SY When is low, the clock signal CL1 is low.

[0041] The ramp voltage generating circuit 140 generates a ramp voltage V based on the clock signal CL1. RAMP1 ,V RAMP2 Hereafter, the lamp voltage V RAMP1 and lamp voltage V RAMP2 When there is no particular distinction between these, they are simply referred to as "lamp voltage V RAMP Lamp voltage V RAMP may be, for example, a periodic sawtooth wave, a triangular wave, etc. The ramp voltage generating circuit 140 according to this embodiment includes a first ramp voltage generator 142 and a second ramp voltage generator 144.

[0042] The first ramp voltage generator 142 generates a ramp voltage V based on the clock signal CL1. RAMP1 The second ramp voltage generator 144 synchronizes with the first ramp voltage generator 142 to generate the ramp voltage V RAMP1 and the same shape as the lamp voltage V RAMP2 The second ramp voltage generator 144 is configured to generate a ramp voltage V. The second ramp voltage generator 144 is synchronized with the first ramp voltage generator 142 by receiving a clock signal CL1 common to both the first ramp voltage generator 142 and the second ramp voltage generator 144. RAMP2 is input to the inverting input terminals of the first comparator 162 and the second comparator 164.

[0043] The ramp voltage generating circuit 140 according to this embodiment generates a ramp voltage V in response to a change in the frequency of the input clock signal CL1. RAMP The peak voltage is changed by the lamp voltage V RAMP In this embodiment, the first ramp voltage generator 142 generates the ramp voltage V according to the change in the frequency of the clock signal CL1. RAMP1 The second ramp voltage generator 144 varies the peak voltage of the ramp voltage V in response to changes in the frequency of the clock signal CL1. RAMP2 Specifically, the peak voltage of the lamp voltage V RAMP The higher the frequency of the clock signal CL1, the smaller the peak voltage of the clock signal CL1.

[0044] The ramp voltage generating circuit 140 according to this embodiment receives an input voltage V IN In response to the change in the lamp voltage V RAMP For example, the ramp voltage generating circuit 140 is configured to change the peak voltage of the input voltage V IN Signal S according to VIN Based on the lamp voltage V RAMP In this embodiment, the first ramp voltage generator 142 may vary the peak voltage of the input voltage V IN Depending on the change in the lamp voltage V RAMP1 The second ramp voltage generator 144 varies the peak voltage of the input voltage V IN Depending on the change in the lamp voltage V RAMP2 For example, the peak voltage of the lamp voltage V RAMP The peak voltage of IN The larger the value, the larger the value can be.

[0045] FIG. 2 shows the ramp voltages V generated by the first ramp voltage generator 142 and the second ramp voltage generator 144 according to this embodiment. RAMP 2 is a timing chart showing an example of the lamp voltage V RAMP is a periodic sawtooth wave. The ramp voltage V RAMP is a period during which the clock signal CL1 having a predetermined frequency is high (hereinafter referred to as the "high period T H1 ) is 0V. Also, the lamp voltage V RAMP is the period T when the clock signal CL1 is low. L1 (hereinafter referred to as "Low Period T L1 ) at the initial voltage V INIT (>0) to peak voltage V PEAK rises linearly up to

[0046] When the frequency of the clock signal CL1 changes, the low period T L1 The initial voltage V INIT and low period T L1 Lamp voltage V RAMPIf the slope of the L1 The longer the peak voltage V PEAK As a result, the lamp voltage V RAMP The intermediate voltage V MID (i.e., the initial voltage V INIT and peak voltage V PEAK The voltage between the low and high voltages is L1 The longer the lamp voltage V RAMP The intermediate voltage V MID can change in response to changes in the frequency of the clock signal CL1.

[0047] In this embodiment, the input voltage V IN Depending on the change in the low period T L1 Lamp voltage V RAMP For example, the slope of the input voltage V IN The larger the low period T L1 Lamp voltage V RAMP When the slope of the input voltage V IN The larger the peak voltage V PEAK As a result, the intermediate voltage V MID In this way, the lamp voltage V RAMP The intermediate voltage V MID is the input voltage V IN may change depending on changes in

[0048] 1, the intermediate voltage generating circuit 150 will be described. The intermediate voltage generating circuit 150 generates the ramp voltage V RAMP Based on the lamp voltage V RAMP In this embodiment, the intermediate voltage generating circuit 150 generates an intermediate voltage V RAMP1 Based on the lamp voltage V RAMP1 Generates an intermediate voltage.

[0049] The intermediate voltage generating circuit 150 according to this embodiment includes a phase adjusting circuit 152 and a ramp voltage V generated by the first ramp voltage generator 142. RAMP1and a sample-and-hold circuit 154 that samples and holds the signal.

[0050] The phase adjustment circuit 152 adjusts the phase of the clock signal CL1 to generate a phase-adjusted clock signal CL2. Specifically, the phase adjustment circuit 152 may adjust the timing of the rising edge of the clock signal CL1. More specifically, the phase adjustment circuit 152 may generate a clock signal CL3 whose rising edge is the same as that of the clock signal CL1 and whose pulse width is adjusted from the clock signal CL1. The phase adjustment circuit 152 can generate a clock signal CL2 that rises at the timing of the falling edge of the clock signal CL3. This generates a clock signal CL2 whose phase is delayed by the pulse width of the clock signal CL3.

[0051] The phase adjustment circuit 152 is configured such that the sample-and-hold circuit 154 generates a ramp voltage V RAMP1 In this embodiment, the phase adjustment circuit 152 generates the clock signal CL2 by adjusting the phase of the clock signal CL1 so that the intermediate voltage of the ramp voltage V can be sampled and held. In this embodiment, the phase adjustment circuit 152 generates the clock signal CL2 by delaying the phase of the clock signal CL1 by 180°. RAMP1 Since the waveform of is a sawtooth wave, the ramp voltage V occurs 180° behind the rising edge of the clock signal CL1. RAMP1 By sampling the lamp voltage V RAMP1 This makes it possible to sample the intermediate voltage.

[0052] The magnitude of the phase adjusted by the phase adjustment circuit 152 is determined by the lamp voltage V RAMP1 For example, the waveform of the lamp voltage V RAMP1 When the clock signal CL1 is a triangular wave, the phase adjustment circuit 152 may delay the phase of the clock signal CL1 by 90° to generate the clock signal CL2. In this case as well, the sample-and-hold circuit 154 generates the ramp voltage V RAMP1 The intermediate voltage can be sampled and held.

[0053] The sample-and-hold circuit 154 according to this embodiment generates the ramp voltage V when the clock signal CL2 is high. RAMP1 The voltage sampled when the clock signal CL2 is low (hereinafter referred to as the hold voltage V SH The sample-and-hold circuit 154 is configured to hold the ramp voltage V generated by the first ramp voltage generator 142 and the clock signal CL2 whose phase has been adjusted by the phase adjustment circuit 152. RAMP1 The capacitor C that samples and holds SH Includes:

[0054] The switch SW1 is provided between the output terminal of the first ramp voltage generator 142 and the non-inverting input terminal of the inverting amplifier 160. The switch SW1 operates in response to a clock signal CL2. Specifically, the switch SW1 is turned on when the clock signal CL2 is high, and turned off when the clock signal CL2 is low.

[0055] Capacitor C SH is the ramp voltage V generated by the first ramp voltage generator 142 when the switch SW1 is on. RAMP1 The capacitor C is provided to sample the voltage and hold the sampled voltage when the switch SW1 is off. SH One end of the capacitor C is connected between the switch SW1 and the non-inverting input terminal of the inverting amplifier 160. SH The other end is connected to ground.

[0056] When switch SW1 is on, the lamp voltage V RAMP1 is connected to the capacitor C SH is supplied to the capacitor C SH is the lamp voltage V RAMP1 When switch SW1 is on, the lamp voltage V RAMP1 The intermediate voltage of capacitor C SH is supplied to the capacitor C SH is the lamp voltage V RAMP1The intermediate voltage of the capacitor C SH holds the sampled voltage, and the hold voltage V SH is input to the non-inverting input terminal of the inverting amplifier 160.

[0057] The inverting amplifier 160 outputs the intermediate voltage (hold voltage V SH ) as the reference, the error signal S ERR2 is inverted, and the inverted signal S INV Specifically, the inverting amplifier 160 generates S ERR2 <V SH In the case of S INV -V SH =V SH -S ERR2 (S INV >V SH ) so that the inverted signal S INV The inverting amplifier 160 generates S ERR2 >V SH In the case of V SH -S INV =S ERR2 -V SH (S INV <V SH ) so that the inverted signal S INV Furthermore, the inverting amplifier 160 generates S ERR2 =V SH In the case of S INV =S ERR2 So, the inverted signal S INV Generates an inverted signal S INV is input to the non-inverting input terminal of the second comparator 164.

[0058] The first comparator 162 detects the lamp voltage V RAMP and the error signal S ERR2 and the first PWM signal S PWM1 The first comparator 162 according to this embodiment generates the ramp voltage V RAMP2 and the error signal S ERR2 and the first PWM signal S PWM1 The first PWM signal S PWM1 is SERR2 >V RAMP2 It becomes high when S ERR2 <V RAMP2 It goes low when

[0059] The second comparator 164 detects the lamp voltage V RAMP and inverted signal S INV and the second PWM signal S PWM2 The second comparator 164 according to this embodiment generates the ramp voltage V generated by the second ramp voltage generator 144. RAMP2 and inverted signal S INV and the second PWM signal S PWM2 The second PWM signal S PWM2 is S INV >V RAMP2 It becomes high when S INV <V RAMP2 It goes low when

[0060] The peripheral circuit 20a includes a resistor R1 and capacitors C1 and C2. The resistor R1 and capacitor C1 are connected in series. One end of the capacitor C1 opposite the resistor R1 is grounded, and the other end of the capacitor C1 opposite the resistor R1 is connected to the pin COMP. One end of the capacitor C2 is grounded, and the other end of the capacitor C2 is connected to the pin SS.

[0061] The peripheral circuit 20b includes a variable voltage source 22 and a resistor R FB1 ,R FB2 , capacitors C3 to C6 and an inductor L1.

[0062] The variable voltage source 22 receives an input voltage V IN is supplied to the input pin IN. One end of the capacitor C3 is connected to the input pin IN, and the other end of the capacitor C3 is grounded. One end of the capacitor C4 is connected to the output pin OUT, and the other end of the capacitor C4 is grounded. Resistor R FB1 ,R FB2 are connected in series and the output voltage V OUT is divided to generate the feedback voltage V FB where V FB =V OUT×R FB2 / (R FB1 +R FB2 )

[0063] One end of inductor L1 is connected to switching pin LX1, and the other end of inductor L1 is connected to switching pin LX2. One end of capacitor C5 is connected to bootstrap pin BS1, and the other end of capacitor C5 is connected to one end of inductor L1. One end of capacitor C6 is connected to bootstrap pin BS2, and the other end of capacitor C6 is connected to the other end of inductor L1.

[0064] 3 is a timing chart showing an example of operation in the buck mode of the buck-boost DC / DC converter 1 according to this embodiment. SH is the lamp voltage V RAMP2 The intermediate voltage V MID (V SH =V MID ) The same applies to Figure 4. The mode is the error signal S ERR2 and hold voltage V SH2 As shown in Figure 3, in the step-down mode, the error signal S ERR2 is the hold voltage V SH is smaller than (S ERR2 <V SH ).

[0065] 1st PWM signal S PWM1 is the error signal S ERR2 and hold voltage V SH The second PWM signal S PWM2 is the inverted signal S INV and hold voltage V SH The first PWM signal S is generated according to the magnitude relationship between PWM1 and the second PWM signal S PWM2 The first high-side transistor MH1 is driven in response to the control signal SH1 generated by the XNOR of the input voltage V IN The output voltage V OUTIn the step-down mode, the control signal SL2 for controlling the operation of the second low-side transistor ML2 is low, and the second low-side transistor ML2 is off.

[0066] 4 is a timing chart showing an example of the operation in the boost mode of the step-up / step-down DC / DC converter 1 according to this embodiment. As shown in FIG. 4, in the boost mode, the error signal S ERR2 is the hold voltage V SH greater than (S ERR2 >V SH ). 1st PWM signal S PWM1 and the second PWM signal S PWM2 The second low-side transistor ML2 is driven in response to a control signal SL2 generated by XORing the input voltage V IN The output voltage V OUT is generated. In the boost mode, the control signal SH1 for controlling the operation of the first high-side transistor MH1 is low, and the first high-side transistor MH1 is off. Although FIGS. 3 and 4 show an example in which one of the first high-side transistor MH1 and the second low-side transistor ML2 is switched on, both may be operated.

[0067] 5 is a timing chart for explaining an example of the operation of the intermediate voltage generating circuit 150 according to this embodiment. H1 The clock signal CL3 is generated by adjusting the pulse width (pulse width) to half the period of the clock signal CL1. Therefore, if the period of the clock signal CL1 is T1, the high period of the clock signal CL3 is T H3 is T1 / 2.

[0068] The phase adjustment circuit 152 generates a clock signal CL2 that rises at the timing of the falling edge of the clock signal CL3. This generates a clock signal CL2 that rises with a delay of half a cycle (T1 / 2) compared to the clock signal CL1. That is, the clock signal CL2 is generated with a phase delay of 180° compared to the clock signal CL1. Here, the pulse width of the clock signal CL2 may be smaller than the pulse width of the clock signal CL1.

[0069] The sample-and-hold circuit 154 generates the ramp voltage V RAMP1 The sample-and-hold circuit 154 samples and holds the signal T H2 At the lamp voltage V RAMP1 and the clock signal CL2 is sampled during the low period T L2 The sampled voltage is held at

[0070] In the example shown in FIG. 5, the lamp voltage V RAMP1 The slope of the ramp voltage V changes, and the peak voltage changes. Before time t1, RAMP1 The peak voltage of is V PEAK1 After the timing t1, the lamp voltage V RAMP1 The peak voltage of is V PEAK2 is.

[0071] Figure 5 shows the true midpoint voltage V MID is shown by a dashed line, and the hold voltage V SH As shown in FIG. 5, after timing t1, the ramp voltage V RAMP1 By sampling the true intermediate voltage V MID As can be seen, according to this embodiment, the lamp voltage V RAMP1 Even if the peak voltage of the ramp voltage V changes, it is possible to obtain an intermediate voltage by following the change. In particular, if the intermediate voltage can be obtained by following the change faster than the bands of the first error amplifier 122 and the second error amplifier 124, RAMP1This can substantially eliminate the influence of fluctuations in the peak voltage on PWM control.

[0072] FIG. 6 shows the ramp voltage V RAMP1 6 is a timing chart showing an example of the lamp voltage V RAMP1 is the high period T of the clock signal CL2 during which sampling by the sample-and-hold circuit 154 is performed. H2 Therefore, if the lamp voltage V RAMP1 is input to the first comparator 162 and the second comparator 164, the first PWM signal S PWM1 and the second PWM signal S PWM2 This causes jitter and makes the PWM control unstable.

[0073] In the semiconductor circuit 10 according to this embodiment, the ramp voltage V RAMP1 , but the ramp voltage V generated by the second ramp voltage generator 144 RAMP2 is input to the first comparator 162 and the second comparator 164. Therefore, the first PWM signal S PWM1 and the second PWM signal S PWM2 This suppresses jitter from occurring in the PWM signal, making it possible to stabilize the PWM control.

[0074] The configuration and operation of the step-up / step-down DC / DC converter 1 and its semiconductor circuit 10 according to this embodiment have been described above. According to the semiconductor circuit 10 according to this embodiment, the intermediate voltage generation circuit 150 converts the ramp voltage V generated by the ramp voltage generation circuit 140 into a voltage V RAMP2 Based on the lamp voltage V RAMP2 This generates an intermediate voltage between the PWM signal (first PWM signal S PWM1 and the second PWM signal S PWM2 ) to generate the lamp voltage V RAMP Even if the peak voltage of V changes, the lamp voltage V RAMP Therefore, the step-up / step-down DC / DC converter 1 can operate properly.

[0075] (Other examples of operation) 7 is a timing chart showing another operation example of the step-up / step-down DC / DC converter 1 according to the above embodiment. In this operation example, the input voltage V IN is V before timing t2. IN1 and increases linearly from timing t2 to t3, and V IN2 (>V IN1 ) shall be maintained.

[0076] In the example shown in Figure 7, the lamp voltage V RAMP The slope of the input voltage V IN Specifically, from timing t2 to t3, the lamp voltage V RAMP The slope of the ramp voltage V gradually increases and becomes constant after timing t3. RAMP The peak voltage of V PEAK3 From V PEAK4 (>V PEAK3 )

[0077] When feedforward control is performed in the buck-boost DC / DC converter 1, the ramp voltage V RAMP The peak voltage V PEAK is the input voltage V IN This allows duty control to be performed faster than the response of the first error amplifier 122 and the second error amplifier 124, thereby controlling the input voltage V IN The output voltage V OUT For example, as shown in Figure 7, the fluctuation of the input voltage V IN When becomes larger, the first PWM signal S PWM1 The duty ratio can be reduced.

[0078] Even in such a case, the intermediate voltage generating circuit 150 generates the ramp voltage V RAMP The lamp voltage V RAMPTherefore, by using feedforward control, it is possible to more reliably achieve proper operation of the step-up / step-down DC / DC converter 1.

[0079] (Application example) In the above embodiment, an example in which the clock signal CK1 is generated inside the semiconductor circuit 10 has been described. However, a clock signal may be generated externally and used. In this case, the first ramp voltage generator 142 and the second ramp voltage generator 144 can each generate a ramp voltage based on a clock signal input from an external source. Furthermore, the intermediate voltage generation circuit 150 can generate an intermediate voltage of the ramp voltages based on the clock signal input from an external source and the ramp voltage generated by the first ramp voltage generator 142. Therefore, even if the semiconductor circuit does not have information about the clock signal input from an external source, it is possible to appropriately generate an intermediate voltage of the ramp voltages. As a result, the buck-boost DC / DC converter can operate appropriately even when a clock signal is input from an external source.

[0080] An in-vehicle step-up / step-down DC / DC converter is sometimes required to have an external synchronization function that inputs an external clock signal and performs switching in synchronization with the clock signal. By applying the step-up / step-down DC / DC converter 1 according to the above embodiment, such a requirement can be met.

[0081] In the above embodiment, the frequency of the clock signal CL1 input to the ramp voltage generation circuit 140 and the intermediate voltage generation circuit 150 is mainly constant. However, the frequency of the clock signal CL1 may be varied as necessary. For example, the frequency of the clock signal CL1 may be varied to achieve the function of a spread spectrum clock generator (SSCG), which suppresses noise concentration at a specific frequency.

[0082] In the case of an in-vehicle buck-boost DC / DC converter, it is undesirable for the clock signal frequency to overlap with the AM (Amplitude Modulation) band of radio. To prevent the clock signal frequency from being fixed to a specific frequency in the AM band, it is preferable to periodically vary the frequency using the SSCG function. In this case, the intermediate voltage of the ramp voltage also changes in response to changes in frequency, but the intermediate voltage generation circuit 150 can generate the intermediate voltage in response to these changes. This allows for both the SSCG function and proper operation of the buck-boost DC / DC converter.

[0083] If the semiconductor circuit 10 can generate a clock signal CL1 with a high frequency accuracy, it is possible to ensure that the frequency of the clock signal CL1 does not overlap with the AM band. However, if the frequency accuracy of the clock signal CL1 is low, variations in frequency occur. In the semiconductor circuit 10 according to this embodiment, the intermediate voltage generation circuit 150 generates the ramp voltage V RAMP Therefore, even if there is a variation in the frequency of the clock signal CL1, the step-up / step-down DC / DC converter 1 can operate properly.

[0084] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0085] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0086] (Item 1) A controller circuit for a step-up / step-down DC / DC converter that generates an output voltage according to an input voltage, a step-down switch circuit including a high-side transistor and receiving the input voltage; a boost switch circuit including a low-side transistor and outputting the output voltage; a ramp voltage generating circuit that generates a ramp voltage based on a clock signal; an intermediate voltage generating circuit that generates an intermediate voltage of the ramp voltage based on the ramp voltage generated by the ramp voltage generating circuit; an error amplifier circuit that generates an error signal based on an error between a feedback voltage of the output voltage and a reference voltage; an inverting amplifier that inverts the error signal based on the intermediate voltage generated by the intermediate voltage generating circuit to generate an inverted signal; a first comparator that compares the ramp voltage with the error signal to generate a first PWM signal; a second comparator that compares the ramp voltage with the inverted signal to generate a second PWM signal; a logic circuit that generates a control signal for controlling operations of the high-side transistor and the low-side transistor based on the first PWM signal and the second PWM signal. Controller circuit.

[0087] (Item 2) the ramp voltage generating circuit includes a first ramp voltage generator and a second ramp voltage generator, each of which generates a ramp voltage; the second ramp voltage generator is configured to synchronize with the first ramp voltage generator and generate a ramp voltage having the same shape as a ramp voltage generated by the first ramp voltage generator; the intermediate voltage generating circuit generates an intermediate voltage of the ramp voltage based on the ramp voltage generated by the first ramp voltage generator; the first comparator compares the ramp voltage generated by the second ramp voltage generator with the error signal to generate a first PWM signal; the second comparator compares the ramp voltage generated by the second ramp voltage generator with the inverted signal to generate a second PWM signal; Item 1. The controller circuit of item 1.

[0088] (Item 3) the first ramp voltage generator and the second ramp voltage generator each generate a ramp voltage based on a common clock signal; the intermediate voltage generation circuit includes a phase adjustment circuit that generates a clock signal by adjusting the phase of the common clock signal, and a sample-and-hold circuit that samples and holds the ramp voltage generated by the first ramp voltage generator, the phase adjustment circuit generates a clock signal obtained by adjusting the phase of the common clock signal so that the sample-and-hold circuit can sample and hold an intermediate voltage of the ramp voltage generated by the first ramp voltage generator based on the phase-adjusted clock signal. Item 2. The controller circuit of item 2.

[0089] (Item 4) the sample-and-hold circuit includes a switch that operates in response to the clock signal whose phase has been adjusted by the phase adjustment circuit, and a capacitor that samples and holds the ramp voltage generated by the first ramp voltage generator; the capacitor is configured to sample the ramp voltage generated by the first ramp voltage generator when the switch is on, and to hold the sampled voltage when the switch is off. Item 3. The controller circuit of item 3.

[0090] (Item 5) the ramp voltage generating circuit changes the peak voltage of the ramp voltage to be generated in response to a change in the frequency of the input clock signal; 5. The controller circuit of any one of items 1 to 4.

[0091] (Item 6) the ramp voltage generating circuit changes a peak voltage of the ramp voltage in response to a change in the input voltage; 6. The controller circuit of any one of items 1 to 5.

[0092] (Item 7) Integrated on a single semiconductor chip 7. The controller circuit of any one of items 1 to 6.

[0093] (Item 8) Item 8: A controller circuit according to any one of items 1 to 7, Step-up / step-down DC / DC converter.

[0094] (Item 9) The step-up / step-down DC / DC converter described in item 8 is mounted. vehicle. [Explanation of symbols]

[0095] 1 Buck-boost DC / DC converter, 10 semiconductor circuit, 20a, 20b peripheral circuit, 22 variable voltage source, 100 logic circuit, 102 buck driver, 104 boost driver, 110 buck switch circuit, 112 boost switch circuit, 120 error amplifier circuit, 122 first error amplifier, 124 second error amplifier, 126 soft start circuit, 128 current detection circuit, 130 clock signal generation circuit, 132 oscillator, 134 OR circuit, 140 ramp voltage generation circuit, 142 first ramp voltage generator, 144 second ramp voltage generator, 150 intermediate voltage generation circuit, 152 phase adjustment circuit, 154 sample and hold circuit, 160 inverting amplifier, 162 first comparator, 164 second comparator, MP1, MP2 transistor, MH1 first high-side transistor, ML1 first low-side transistor, MH2 Second high-side transistor, ML2 Second low-side transistor, D1, D2 Diode, SW1 Switch, R1, R FB1 ,R FB2 Resistance, C1~C6,C SH Capacitor, L1 inductor.

Claims

1. A controller circuit for a step-up / step-down DC / DC converter that generates an output voltage according to an input voltage, a step-down switch circuit including a high-side transistor and receiving the input voltage; a boost switch circuit including a low-side transistor and outputting the output voltage; a ramp voltage generating circuit that generates a ramp voltage based on a clock signal; an intermediate voltage generating circuit that generates an intermediate voltage of the ramp voltage based on the ramp voltage generated by the ramp voltage generating circuit; an error amplifier circuit that generates an error signal based on an error between a feedback voltage of the output voltage and a reference voltage; an inverting amplifier that inverts the error signal based on the intermediate voltage generated by the intermediate voltage generating circuit to generate an inverted signal; a first comparator that compares the ramp voltage with the error signal to generate a first PWM signal; a second comparator that compares the ramp voltage with the inverted signal to generate a second PWM signal; a logic circuit that generates a control signal for controlling operations of the high-side transistor and the low-side transistor based on the first PWM signal and the second PWM signal. Controller circuit.

2. the ramp voltage generating circuit includes a first ramp voltage generator and a second ramp voltage generator, each of which generates a ramp voltage; the second ramp voltage generator is configured to generate a ramp voltage having the same shape as a ramp voltage generated by the first ramp voltage generator in synchronization with the first ramp voltage generator; the intermediate voltage generating circuit generates an intermediate voltage of the ramp voltage based on the ramp voltage generated by the first ramp voltage generator; the first comparator compares the ramp voltage generated by the second ramp voltage generator with the error signal to generate a first PWM signal; the second comparator compares the ramp voltage generated by the second ramp voltage generator with the inverted signal to generate a second PWM signal; 2. The controller circuit of claim 1.

3. the first ramp voltage generator and the second ramp voltage generator each generate a ramp voltage based on a common clock signal; the intermediate voltage generation circuit includes a phase adjustment circuit that generates a clock signal by adjusting the phase of the common clock signal, and a sample-and-hold circuit that samples and holds the ramp voltage generated by the first ramp voltage generator, the phase adjustment circuit generates a clock signal obtained by adjusting the phase of the common clock signal so that the sample-and-hold circuit can sample and hold an intermediate voltage of the ramp voltage generated by the first ramp voltage generator based on the phase-adjusted clock signal.

3. The controller circuit of claim 2.

4. the sample-and-hold circuit includes a switch that operates in response to the clock signal whose phase has been adjusted by the phase adjustment circuit, and a capacitor that samples and holds the ramp voltage generated by the first ramp voltage generator; the capacitor is configured to sample the ramp voltage generated by the first ramp voltage generator when the switch is on, and to hold the sampled voltage when the switch is off.

4. The controller circuit of claim 3.

5. the ramp voltage generating circuit changes the peak voltage of the ramp voltage to be generated in response to a change in the frequency of the input clock signal; 2. The controller circuit of claim 1.

6. the ramp voltage generating circuit changes a peak voltage of the ramp voltage in response to a change in the input voltage; 2. The controller circuit of claim 1.

7. Integrated on a single semiconductor chip 2. The controller circuit of claim 1.

8. A controller circuit according to any one of claims 1 to 7, Step-up / step-down DC / DC converter.

9. A step-up / step-down DC / DC converter according to claim 8 is mounted on the device. vehicle.

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