Semiconductor memory device

Abstract

To reduce the area of a staircase region.SOLUTION: In a semiconductor memory device of an embodiment, a plurality of conductive layers WL are stacked apart from each other, and a memory region MR is sandwiched between first and second staircase regions SR in which the plurality of conductive layers WL are processed into a staircase shape. A stacked body LM disposed at each of both ends of the plurality of conductive layers WL in a first direction intersecting a stacking direction of the plurality of conductive layers WL; The stacked body LM includes the first plate-shaped portion LIx that divides the memory region MR into the first and second sub memory regions MR adjacent to each other in the second direction intersecting the stacking direction and the first direction, and the second plate-shaped portion LIy that extends in the stacked body LM in the second direction and the stacking direction and divides the first sub memory region MR and the first staircase region SR, and the second plate-shaped portion LIy is connected to the side surface of the first plate-shaped portion LIx in the second direction via the insulating metal-element-containing layer 55.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices such as three-dimensional nonvolatile memories, memory cells are arranged three-dimensionally in a stack of multiple conductive layers spaced apart from one another. These conductive layers are processed into a stepped pattern at the edge regions of the stack. As the number of stacked conductive layers increases, the area occupied by the stepped conductive layer regions in the semiconductor memory device also increases. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2017 / 0098658 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device that can reduce the area of ​​a staircase region. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment comprises a stack in which a plurality of conductive layers are stacked at a distance from each other, and first and second staircase regions in which the plurality of conductive layers are processed into a staircase shape are disposed at both ends of a first direction intersecting with the stacking direction of the plurality of conductive layers, with a memory region sandwiched between them; a first plate-shaped portion extending within the stack in the first direction and the stacking direction and dividing the memory region into first and second sub-memory regions adjacent in a second direction intersecting with the stacking direction and the first direction; and a second plate-shaped portion extending within the stack in the second direction and the stacking direction and dividing the first sub-memory region from the first staircase region, and the second plate-shaped portion is connected to the side of the first plate-shaped portion in the second direction via an insulating metal element-containing layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 2] FIG. 2 is an XY cross-sectional view showing an example of a detailed layout of the semiconductor memory device according to the embodiment. [Figure 3] 3 is a schematic perspective view of a staircase region that a stack of the semiconductor memory device according to the embodiment has on one side in the X direction. FIG. [Figure 4] 1 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to an embodiment. [Figure 5] 1 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views illustrating a part of a procedure for replacing a word line in a semiconductor memory device according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views illustrating a part of a procedure for replacing a word line in a semiconductor memory device according to an embodiment. [Figure 15] 1A to 1C are cross-sectional views illustrating a part of a procedure for replacing a word line in a semiconductor memory device according to an embodiment. [Figure 16] 1A to 1C are cross-sectional views illustrating a part of a procedure for replacing a word line in a semiconductor memory device according to an embodiment. [Figure 17] 10A to 10C are cross-sectional views illustrating in order some steps of a method for forming a plate-shaped portion in a semiconductor memory device according to a modified example of the embodiment. [Figure 18] 10A to 10C are cross-sectional views illustrating in order some steps of a method for forming a plate-shaped portion in a semiconductor memory device according to a modified example of the embodiment. [Figure 19] FIG. 10 is a schematic perspective view of a staircase region on one side in the X direction of a stack of a semiconductor memory device according to another modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] (Example of overall configuration of semiconductor memory device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 1A is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1B is a schematic plan view illustrating the layout of the semiconductor memory device 1.

[0009] However, hatching is omitted in Fig. 1(a) for ease of viewing, and some upper layer wiring is also omitted in Fig. 1(a).

[0010] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0011] As shown in FIG. 1(a), the semiconductor memory device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which a peripheral circuit CBA is provided.

[0012] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical continuity is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from the outside to the semiconductor memory device 1 are provided in the same layer as the electrode film EL. A select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order on the source line SL to form a stacked body LM.

[0013] 1(a) and 1(b), a memory region MR is disposed in the center of the laminate LM in the X direction, and staircase regions SR are disposed at both ends of the laminate LM in the X direction. These staircase regions SR are used as lead-out portions for the word lines WL and select gate lines SGD and SGS in the laminate LM to electrically connect the word lines WL and select gate lines SGD and SGS to the peripheral circuit CBA via contacts CC (described later). The memory region MR and staircase region SR are divided into multiple regions by multiple plate-like portions LIx that extend in the X direction through the laminate LM.

[0014] The area arranged between adjacent plate-like portions LIx in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK serves as the erase unit for this data.

[0015] In one block region BLK, a plate-like portion LIy extending in the Y direction is arranged on one side of the staircase regions SR on both sides in the X direction, dividing the staircase region SR and the memory region MR on one side of the laminate LM. Also, when viewed from one side in the X direction, the plate-like portion LIy is arranged, for example, every two block regions BLK.

[0016] That is, in the example of Figure 1(b), when looking at the staircase region SR on the right side of the paper, the plate-shaped portion LIy is not arranged in the block regions BLK at the top and bottom of the paper, and in each of these block regions BLK, the memory region MR is electrically connected to the staircase region SR on the right side of the paper.

[0017] On the other hand, in the second and third block regions BLK from the top of the paper, a plate-like portion LIy is arranged that extends in the Y direction through the staircase region SR on the right side of the paper. Therefore, in these block regions BLK, the memory region MR is not electrically connected to the staircase region SR on the right side of the paper.

[0018] However, the plate-shaped portion LIx that separates the block region BLK at the top of the page from the second block region BLK has a gap between the memory region MR side and the staircase region SR side, sandwiched between the plate-shaped portion LIy, on both sides of the stack LM in the X direction.

[0019] Therefore, the staircase region SR on the right side of the paper, which is aligned in the X direction with the memory region MR belonging to the second block region BLK sandwiched between the plate-like portion LIy and the memory region MR belonging to the block region BLK at the top of the paper, is electrically connected to the memory region MR belonging to the block region BLK at the top of the paper. Also, the staircase region SR on the left side of the paper, which is aligned in the X direction with the memory region MR belonging to the first block region BLK sandwiched between the plate-like portion LIy and the memory region MR belonging to the second block region BLK from the top of the paper, is electrically connected to the memory region MR belonging to the block region BLK at the top of the paper.

[0020] Similarly, the plate-like portion LIx that separates the block region BLK at the bottom of the paper from the third block region BLK from the top of the paper has a gap between the memory region MR side and the staircase region SR side, sandwiching the plate-like portion LIy on both sides of the laminate LM in the X direction.

[0021] Therefore, the staircase region SR on the right side of the paper, which is aligned in the X direction with the plate-like portion LIy sandwiched between the memory region MR belonging to the third block region BLK from the top of the paper, is electrically connected to the memory region MR belonging to the block region BLK at the bottom of the paper. Also, the staircase region SR on the left side of the paper, which is aligned in the X direction with the plate-like portion LIy sandwiched between the memory region MR belonging to the block region BLK at the bottom of the paper, is electrically connected to the memory region MR belonging to the third block region BLK from the top of the paper.

[0022] The individual memory regions MR belonging to the plurality of block regions BLK are electrically isolated from each other by the plate-like portions LIx and LIy.

[0023] Between the plate-like portions LIx adjacent in the Y direction, a plurality of isolation layers SHE are arranged, which extend in the X direction and penetrate the select gate lines SGD. The isolation layers SHE extend in the X direction throughout the memory region MR and reach parts of the staircase regions SR at both ends in the X direction.

[0024] In the memory region MR, a plurality of pillars PL are arranged, penetrating the stack LM in the stacking direction. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0025] In the staircase region SR, the word lines WL and select gate lines SGD, SGS constituting the stack LM are terminated in a staircase shape so as not to overlap with the upper conductive layers in the stacking direction. At this time, as one moves away from the memory region MR in the X direction, the terminations of the word lines WL and select gate lines SGD, SGS move from the upper layer side to the lower layer side, and therefore the height position of each terrace portion where the word lines WL and select gate lines SGD, SGS are provided so as not to overlap with the upper conductive layers in the stacking direction decreases toward the source line SL side.

[0026] The isolation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the isolation layer SHE penetrates the portions above the multiple word lines WL, dividing these upper portions into the patterns of multiple select gate lines SGD.

[0027] Moreover, the above-mentioned plate-like portion LIy is disposed on the terrace portion of the select gate line SGD in the staircase region SR.

[0028] Contacts CC connected to the word lines WL and select gate lines SGD, SGS of each layer are arranged in the terrace portion of each stage formed by multiple word lines WL and select gate lines SGD, SGS. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each select gate line SGD per layer for each section separated by a separation layer SHE.

[0029] Here, in one block region BLK, the contacts CC connected to the select gate lines SGD are arranged on one of the staircase regions SR on both sides in the X direction. Also, in the staircase region SR on one side in the X direction, these contacts CC connected to the select gate lines SGD are arranged, for example, every two block regions BLK.

[0030] 1(b), in the block regions BLK at the top and bottom of the page, contacts CC connected to the select gate line SGD are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the right side of the page.Furthermore, in the second and third block regions BLK from the top of the page, contacts CC connected to the select gate line SGD are arranged in the staircase region SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page.

[0031] 1(a), the contacts CC in the staircase regions SR at both ends in the X direction are connected to memory cells belonging to different block regions BLK. In addition, in one of the staircase regions SR at both ends in the X direction, a plate-like portion LIy is arranged, and no contacts CC connected to the select gate line SGD are arranged.

[0032] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0033] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components.

[0034] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0035] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers the stacked body LM, etc., a semiconductor memory device 1 is formed that includes a configuration of multiple word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0036] Next, the detailed layout of the semiconductor memory device 1 will be described with reference to FIG.

[0037] 2 is an XY cross-sectional view showing an example of a detailed layout of the semiconductor memory device 1 according to the embodiment. More specifically, FIG. 2 is an XY cross-sectional view at the height of the select gate line SGD, and includes a part of the staircase region SR on one side of the stacked body LM in the X direction and a part of the memory region MR.

[0038] As shown in Figure 2, the staircase region SR on one side of the laminate LM in the X direction has, in order from the side closest to the memory region MR, either a portion where the select gate line SGD is processed in a staircase shape, a portion where the multiple word lines WL are processed in a staircase shape, or a staircase portion SPa or SPb where the select gate line SGS is processed in a staircase shape, in each region between adjacent plate-shaped portions LIx in the Y direction.

[0039] More specifically, in the staircase region SR, the region separated by the isolation layer SHE extending from the memory region MR corresponds to the portion where the select gate lines SGD are processed in a staircase shape. The region beyond the end of the isolation layer SHE in the X direction is the portion where the word lines WL and the select gate lines SGS are processed in a staircase shape.

[0040] As described above, a plurality of contacts CC are arranged in the staircase region SR, which are connected to a plurality of word lines WL and select gate lines SGD, SGS, respectively.

[0041] Of the above-mentioned staircase portions SPa and SPb, in staircase portion SPa, multiple contacts CC are arranged throughout the entire area where multiple word lines WL and select gate lines SGD, SGS are processed in a staircase shape, and are connected to these word lines WL and select gate lines SGD, SGS, respectively.

[0042] In the stepped portion SPb, no contacts CC are arranged in the portion where the select gate line SGD is processed in a stepped shape. A plurality of contacts CC are arranged in the portion where the word lines WL and select gate lines SGS are processed in a stepped shape, and are connected to these word lines WL and select gate lines SGS, respectively.

[0043] 2, two contacts CC are arranged in each section of the select gate line SGD separated by the separation layer SHE. That is, in the example of FIG. 2, the stacked body LM has two layers of select gate lines SGD.

[0044] In addition, in each of the stepped portions SPa and SPb, in the portions where the word lines WL and select gate lines SGS are processed in a stepped shape, three rows of contacts CC are arranged along the X direction in each individual region divided by the plate-shaped portion LIx.

[0045] In the example of Figure 2, as one moves away from the memory region MR, the word lines WL and select gate lines SGS that make up the terrace surfaces of the staircase sections SPa and SPb transition to lower layers as described above, and the staircase sections SPa and SPb are also configured so that the layers transition in the Y direction.

[0046] A staircase structure in which layers such as word lines WL constituting the terrace surface change not only in the X direction but also in the Y direction is also called a multi-row staircase. In other words, the above staircase structure in which layers change in three stages in the Y direction is a triple-row staircase. In a multi-row staircase, one step of the staircase can be configured to include word lines WL of multiple layers in at least one of the X and Y directions.

[0047] That is, the layers of the word lines WL and select gate lines SGS that form the terrace surfaces aligned at the same position in the X direction may be different from each other in the Y direction to form the staircase portions SPa and SPb. Figure 2 shows an example of a three-row staircase in which the terrace surfaces of three layers that are continuous in the stacking direction of the word lines WL and select gate lines SGS are aligned at the same position in the X direction in the Y direction. In the example shown in Figure 2 with such a configuration, contacts CC are also aligned in the Y direction, three at the same position in the X direction, to connect to the word lines WL and select gate lines SGS of each layer.

[0048] The multi-column staircase structure shown in FIG. 2 will be described in detail later.

[0049] Regardless of whether or not the staircase is a multi-row staircase, the staircase portions SPa and SPb may include staircase portions in which each step descends toward the memory region MR, so as to face a staircase portion in which each step descends as it moves away from the memory region MR. As described above, the contacts CC are connected to the staircase portions descending in the direction away from the memory region MR, whereas the word lines WL and the like in the staircase portions descending toward the memory region MR are, for example, in a floating state, and the contacts CC are not connected.

[0050] The staircase portions SPa and SPb configured as described above are alternately arranged for every two block regions BLK divided by the plate-like portions LIx.

[0051] Among these, the staircase portions SPb adjacent to each other in the Y direction are divided by a plate-like portion LIx that extends continuously in the X direction and are electrically isolated from each other. The staircase portions SPa and SPb adjacent to each other in the Y direction are electrically connected to each other through a gap formed by the plate-like portion LIx disposed between them, and each includes a portion where the word lines WL and the select gate lines SGS in a layer different from the other staircase portions SPa and SPb are processed into a staircase shape.

[0052] As an example, the staircase portion SPa may include a portion in which the lower-layer word lines WL and select gate lines SGS are processed in a staircase shape, and the staircase portion SPb may include a portion in which the upper-layer word lines WL are processed in a staircase shape. In this case, the number of layers of the staircase-shaped word lines WL and select gate lines SGS included in the staircase portion SPa may be approximately equal to the number of layers of the staircase-shaped word lines WL included in the staircase portion SPb.

[0053] As a result, the select gate line SGD included in the laminate LM has a terrace surface on both of the staircase sections SPa and SPb adjacent to each other in the Y direction, and the multiple word lines WL and select gate lines SGS included in the laminate LM have a terrace surface on either of the staircase sections SPa and SPb adjacent to each other in the Y direction.

[0054] That is, the word lines WL and select gate lines SGD and SGS included in the stacked body LM are drawn out across the entire staircase portions SPa and SPb adjacent to each other in the Y direction. In view of this, the semiconductor memory device 1 of the embodiment can also be said to have a six-column staircase structure that combines the three columns of staircase portion SPa and the three columns of staircase portion SPb adjacent thereto.

[0055] Of the staircase portions SPa and SPb, a plate-like portion LIy extending in the Y direction and penetrating the stacked body LM is disposed in the portion of the staircase portion SPb where the select gate line SGD is processed into a staircase shape. The plate-like portion LIy extends across two block regions BLK adjacent in the Y direction, including the staircase portion SPb. In this case, the plate-like portion LIy is divided by a plate-like portion LIx disposed between the two block regions BLK.

[0056] Furthermore, both ends of the plate-shaped portion LIy in the Y direction reach the plate-shaped portion LIx that divides the plate-shaped portion LIy between the two block regions BLK and the adjacent plate-shaped portions LIx on both sides in the Y direction. In the example of FIG. 2, both ends of the plate-shaped portion LIy are divided by these plate-shaped portions LIx. In this way, by crossing the ends of the plate-shaped portions LIx and LIy, a slight misalignment is allowed when forming these plate-shaped portions LIx and LIy. However, one end of these plate-shaped portions LIx and LIy may be connected to the side surface of the other, or these plate-shaped portions LIx and LIy may be connected to each other at their ends.

[0057] By arranging the plate-like portions LIx and LIy as described above, the memory regions MR belonging to different block regions BLK are electrically isolated from each other. Furthermore, these memory regions MR are connected to the step portions SPa and SPb on one side of each block region BLK.

[0058] That is, in the example of Fig. 2, the memory regions MR belonging to the block regions BLK at the top and bottom of the page, respectively, are electrically connected to the staircase portions SPa and SPb shown in Fig. 2. As a result, transistors such as memory cells included in these memory regions MR are electrically operated via contacts CC arranged in the staircase portion SPa and connected to the select gate line SGD, and contacts CC arranged in the staircase portions SPa and SPb and connected to the word lines WL and select gate lines SGS of different layers.

[0059] On the other hand, the memory regions MR belonging to the two block regions BLK in the center of the page are electrically isolated from the staircase portion SPb shown in Figure 2 by the plate-like portions LIy arranged in these block regions BLK. These memory regions MR are electrically connected to the staircase portions SPa and SPb (not shown) on the other side in the X direction of the laminated body LM. As a result, transistors such as memory cells included in these memory regions MR are electrically operated via contacts CC arranged in the staircase portions SPa and SPb on the other side in the X direction.

[0060] The plate-like portion LIy only needs to be able to electrically separate the portion of the staircase portion SPb where the word lines WL and select gate lines SGS are processed in a staircase shape from the memory region MR. Therefore, the plate-like portion LIy can be placed at any position in the X direction within the range of the portion of the staircase portion SPb where the select gate lines SGD are processed in a staircase shape.

[0061] However, in order to suppress the influence of the plate-shaped portion LIy on the memory region MR, it is preferable to position the plate-shaped portion LIy as far away as possible from the memory region MR, such as near the boundary between the portion where the select gate line SGD is processed in a stepped manner and the portion where the multiple word lines WL are processed in a stepped manner.

[0062] A plurality of bridge portions BRx and BRy are disposed on the upper ends of the plate-like portions LIx and LIy.

[0063] The bridge portions BRx at the upper ends of the plate-like portions LIx are arranged at intervals in the X direction. As will be described later, the bridge portions BRx are used as a countermeasure against stress when the laminate LM is formed from a laminate in which sacrificial layers and insulating layers are stacked. As will be described later, when the laminate LM is formed from a laminate including a sacrificial layer, slits that will later become the plate-like portions LIx are formed through the laminate. At this time, stress may be generated on both sides of the slit in the Y direction. By providing the bridge portions BRx at the upper ends of the slits, deformation of the slit due to stress on both sides in the Y direction can be suppressed.

[0064] The bridge portions BRy at the upper ends of the plate-shaped portions LIy are arranged at intervals in the Y direction. When the plate-shaped portions LIy are arranged near the boundary between a portion where the select gate line SGD is processed in a stepped shape and a portion where the plurality of word lines WL are processed in a stepped shape, the bridge portions BRy can function as a stopper layer, for example, when the separation layer SHE is formed.

[0065] The memory region MR includes a plurality of pillars PL in which a plurality of memory cells are formed, and the staircase region SR includes a plurality of columnar portions HR. As will be described later, the columnar portions HR support the sacrificial layer and the insulating layer when forming the stacked body LM from the stacked body, but do not contribute to the function of the semiconductor memory device 1.

[0066] In the example of Fig. 2, the pillars PL and columnar portions HR are both arranged in a staggered pattern. However, the pillars PL and columnar portions HR may be arranged in a pattern other than a staggered pattern, such as in a grid pattern.

[0067] At the same height position of the laminate LM, the cross-sectional area of ​​the columnar portions HR in the direction along the XY plane is larger than, for example, the cross-sectional area of ​​the pillars PL in the direction along the XY plane. Also, the pitch between the columnar portions HR is larger than, for example, the pitch between the pillars PL, and the arrangement density of the columnar portions HR per unit area of ​​the word line WL in the laminate LM is lower than the arrangement density of the pillars PL per unit area of ​​the word line WL.

[0068] In this way, for example, by configuring the cross-sectional area of ​​the pillars PL to be smaller and by setting a narrower pitch than the columnar portions HR, it is possible to form a large number of memory cells at a high density within the stacked body LM of a given size, thereby increasing the storage capacity of the semiconductor memory device 1. On the other hand, since the columnar portions HR are used solely to support the stacked body LM, for example, by setting the cross-sectional area and pitch to be larger than those of the pillars PL, it is possible to relax the processing precision when forming the columnar portions HR.

[0069] The above-mentioned multi-stage structure will now be described in more detail with reference to FIG.

[0070] 3 is a schematic perspective view showing an example of a staircase region SR that the stack LM of the semiconductor memory device 1 according to the embodiment has on one side in the X direction. More specifically, FIG. 3 shows a staircase region SR that corresponds to eight block regions BLK. The stack LM shown in FIG. 3 also has, as an example, 16 layers of word lines WL, and above and below these word lines WL, two select gate lines SGD0 and SGD1, and two select gate lines SGS0 and SGS1, in that order from the top layer in the stacking direction.

[0071] 3 mainly shows the shapes of the word lines WL etc. in the staircase region SR, and omits some components such as contacts CC etc. Also, each word line WL etc. is stacked and spaced apart from each other by an insulating layer (not shown).

[0072] 3, each of the staircase sections SPa and SPb has, for example, a three-column staircase structure. Furthermore, of the staircase sections SPa and SPb adjacent to each other in the Y direction, in the staircase section SPb, terrace portions of the select gate lines SGS0 and SGS1, which are the lowest layer of the stacked body LM, are arranged on the opposite side of the staircase section SPa in the Y direction. Furthermore, in the staircase section SPa, terrace portions of the word lines WL, which are the highest layer belonging to the column in the Y direction, are arranged on the opposite side of the staircase section SPb in the Y direction.

[0073] That is, in the staircase portions SPa and SPb adjacent to each other in the Y direction, the terrace portions of the word lines WL or the select gate lines SGS rise one layer at a time from the staircase portion SPb side to the staircase portion SPa side in the Y direction. As a result, in terrace portions adjacent to each other in the Y direction, the total number of layers of the word lines WL and the select gate lines SGS included in the stacking direction of one terrace portion is, for example, 2n layers, and the total number of layers of the word lines WL and the select gate lines SGS included in the stacking direction of the adjacent terrace portion is, for example, (2n+1) layers.

[0074] In the above-mentioned stepped portions SPa and SPb, the layers of the select gate lines SGD0 and SGD1 having terrace portions in the region closest to the memory region MR do not change in the Y direction.

[0075] On the other hand, in a pair of staircase sections SPa and SPb adjacent to each other in the Y direction, the terrace portions of the word lines WL and the like each rise six levels in the X direction toward the memory region MR, whereas the terrace portions of the select gate lines SGD0 and SGD1 rise one level in the X direction toward the memory region MR.

[0076] In this way, the word lines WL and other elements constituting the terrace portions change layer by layer in the Y direction and change six layers by six layers in the X direction, so that the word lines WL and select gate lines SGS included in the laminate LM all have terrace portions in either one of these stepped portions SPa, SPb. As described above, a pair of stepped portions SPa, SPb adjacent in the Y direction is connected to the memory region MR belonging to one block region BLK. Therefore, multiple word lines WL and select gate lines SGD, SGS in the laminate LM can be extracted by these pairs of stepped portions SPa, SPb.

[0077] Similarly to the above pair, a pair of staircase portions SPa, SPb adjacent in the Y direction also has terrace portions of word lines WL or select gate lines SGS that rise one layer at a time from the staircase portion SPb side in the Y direction toward the staircase portion SPa side, and rise six layers at a time in the X direction toward the memory region MR. In this case, these staircase portions SPa, SPb are arranged so that the arrangement of the terrace portions of the multiple pairs of staircase portions SPa, SPb is line-symmetrical in the Y direction.

[0078] As a result, when the YZ cross section of the staircase portions SPa adjacent to each other in the Y direction is viewed from the X direction, the boundary portions of these staircase portions SPa have a mountain-like shape with a higher elevation, and when the YZ cross section of the staircase portions SPb adjacent to each other in the Y direction is viewed from the X direction, the boundary portions of these staircase portions SPb have a valley-like shape with a lower elevation.

[0079] It should be noted that the staircase region SR on the other side of the laminate LM in the X direction can be configured in the same manner as the staircase portions SPa and SPb shown in Fig. 3. In this case, the shapes of the staircase regions SR on both sides of the laminate SR in the X direction may be configured to be line-symmetrical in the X direction, or the arrangement of the terrace portions of each layer may be reversed in the Y direction at both ends in the X direction.

[0080] In other words, if the shapes of a pair of staircase portions SPa and SPb adjacent in the Y direction on both sides of the laminate LM in the X direction are configured to be line-symmetric in the X direction, the direction of ascending layer by layer in the Y direction from the staircase portion SPb side to the staircase portion SPa side will be opposite in the staircase regions SR at both ends of the laminate LM in the X direction, because the positions where the plate-like portions LIy are arranged are different for every two block regions BLK on both sides of the X direction.

[0081] Therefore, when the shapes of a pair of staircase sections SPa and SPb adjacent in the Y direction on both sides of the laminate LM in the X direction are inverted in the Y direction, the direction of ascending one layer at a time in the Y direction from the staircase section SPb side to the staircase section SPa side coincides in the staircase regions SR at both ends of the laminate LM in the X direction.

[0082] 3 has been described above as a case where the staircase section SPa or staircase section SPb belonging to one block region BLK each has a three-row staircase structure. However, as mentioned above, the number of staircase rows that each of the staircase sections SPa and SPb has in the Y direction is not limited to three rows, and may be one row, two rows, or four or more rows.

[0083] It is also possible to change the arrangement order in the Y direction of the multiple staircase sections SPa and SPb shown in Fig. 3. For example, in Fig. 3, these staircase sections SPa and SPb are arranged in the following order from one side in the Y direction: SPa, SPb, SPb, SPa, SPa, SPb, SPb, SPa. Alternatively, these staircase sections SPa and SPb may be arranged in the following order: SPb, SPa, SPa, SPb, SPb, SPa, SPa, SPb.

[0084] Even in such an arrangement order, each pair of staircase portions SPa, SPb adjacent to each other in the Y direction can be arranged so that the arrangement of the terrace portions between these pairs is line-symmetrical in the Y direction.

[0085] 3, each pair of staircase sections SPa, SPb adjacent in the Y direction is arranged so that the arrangement of the terrace portions between these pairs is line-symmetrical in the Y direction. However, the arrangement of these pairs does not have to be line-symmetrical in the Y direction.

[0086] As an example, in one pair of staircase sections SPa, SPb, the pair can be configured so that the terrace portions of the word lines WL, etc. rise one layer at a time from one side in the Y direction to the other, and in the next pair adjacent in the Y direction to the terrace portion of the top word line WL belonging to the same column in the Y direction of the above pair, the next pair can also be configured so that the terrace portions of the word lines WL, etc. rise one layer at a time in the same direction in the Y direction as the first pair.

[0087] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Figures 4 and 5. Figures 4 and 5 are cross-sectional views showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0088] More specifically, Figure 4(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 4(a), the structure below the insulating layer 60 and above the insulating layer 53 described below are omitted.

[0089] 4(b) is an enlarged cross-sectional view of a pillar PL at the height of the word line WL, and FIG. 4(c) is an enlarged cross-sectional view of a pillar PL at the height of the select gate lines SGD and SGS.

[0090] Fig. 4(d) is an enlarged cross-sectional view of the plate-shaped portion LIx in the Y direction at the height of the word lines WL and the select gate lines SGD, SGS. Fig. 4(e) is an enlarged cross-sectional view of the plate-shaped portion LIy in the X direction at the height of the word lines WL and the select gate lines SGD, SGS.

[0091] Fig. 4(f) is an XY cross-sectional view showing an intersection of the plate-shaped portions LIx and LIy at the height position of an arbitrary insulating layer OL. Fig. 4(g) is an XY cross-sectional view showing an intersection of the plate-shaped portions LIx and LIy at the height position of an arbitrary word line WL.

[0092] Fig. 5(a) is a cross-sectional view along the X direction of a staircase portion SPa included in the staircase region SR of the semiconductor memory device 1. Fig. 5(b) is a cross-sectional view along the X direction of a staircase portion SPb included in the staircase region SR of the semiconductor memory device 1. Structures below insulating layer 60 and above insulating layer 53, which will be described later, are omitted in Figs. 5(a) and 5(b).

[0093] FIG. 5C is a schematic perspective view showing another example of the staircase region SR that the stacked body LM of the semiconductor memory device 1 according to the embodiment has on one side in the X direction.

[0094] In this specification, the direction in which the terrace surface of the word line WL of each step in the staircase region SR faces is defined as the upward direction in the semiconductor memory device 1.

[0095] 4(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The intermediate source line BSL is disposed below the memory region MR of the stack LM.

[0096] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the intermediate source line BSL may be a conductive polysilicon layer or the like in which impurities are diffused.

[0097] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA through the insulating layer 50 on the outside of the laminated body LM.

[0098] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0099] The stacked body LMa is disposed above the source line SL. Below the word line WL in the lowest layer of the stacked body LMa, a plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the stacked body LMa, with an insulating layer OL interposed between them. The stacked body LMb is disposed on the stacked body LMa. Above the word line WL in the top layer of the stacked body LMb, a plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the stacked body LMb, with an insulating layer OL interposed between them.

[0100] However, the number of stacked word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0101] The upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53, together with an insulating layer 51 described later, each constitute a part of the insulating layer 50 shown in FIG.

[0102] As described above, the laminate LM is divided in the Y direction by a plurality of plate-like portions LIx. That is, the plate-like portions LIx are aligned in the Y direction and extend in the stacking direction and the X direction of the laminate LM.

[0103] In this way, the plate-shaped portion LIx extends substantially continuously within the stacked body LM from one end to the other end in the X direction of the stacked body LM, except for the gap portion. The plate-shaped portion LIx also penetrates the stacked body LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0104] The plate-like portion LIx has a tapered shape in which the width in the Y direction decreases from the upper end to the lower end, or a bowing shape in which the width in the Y direction is maximized at a predetermined position between the upper end and the lower end.

[0105] Each of the plate-shaped portions LIx includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, etc. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0106] The insulating layer 54 covers the side walls of the plate-shaped portion LIx facing each other in the Y direction. The conductive layer 24 is filled inside the insulating layer 54 and is electrically connected to the source lines SL including the intermediate source line BSL.

[0107] However, instead of the plate-like portions LIx, plate-like members filled with an insulating layer may penetrate the laminate LM and extend in the X direction, thereby dividing the laminate LM in the Y direction.

[0108] A plurality of bridge portions BRx are arranged at the upper end of the plate-like portion LIx at predetermined intervals in the X direction. As will be described later, the bridge portions BRx are formed so as to be embedded in the upper end of the plate-like portion LIx located on the upper surface of the uppermost insulating layer OL of the laminate LM. Therefore, in the area where the bridge portions BRx are arranged, part of the upper end of the plate-like portion LIx is replaced with the constituent material of the bridge portions BRx.

[0109] The bridge portion BRx is, for example, a polysilicon layer or a silicon oxide layer. By arranging multiple bridge portions BRx at predetermined intervals on the upper end of the plate-like portion LIx, as described above, deformation of the slit due to stress generated on both sides in the Y direction of the slit that will later become the plate-like portion LIx is suppressed. For example, if the width of the slit in the Y direction changes due to stress deformation, there is a risk of misalignment in the Y direction occurring between the pillar PL already formed in the memory region MR at this point and the plug CH that will be connected above the pillar PL thereafter. By suppressing deformation of the slit width using the bridge portion BRx, it is possible to suppress connection failures due to misalignment between the pillar PL and the plug CH, as well as malfunctions of the memory cell MC due to these connection failures.

[0110] 4(a), in order to show the shapes of both the plate-like portion LIx in the portion having the cross-linking portion BRx and the portion not having the cross-linking portion BRx, the cross-linking portion BRx is shown on only one of the plate-like portions LIx arranged on both the left and right sides of the paper. In this way, the cross-linking portions BRx may be arranged at different positions in the X direction in the plate-like portions LIx adjacent in the Y direction, or may be arranged so that the positions in the X direction coincide in the plurality of plate-like portions LIx, as shown in FIG. 2 above.

[0111] Between the plate-like portions LIx adjacent in the Y direction, a plurality of isolation layers SHE are arranged, which extend in the X direction and penetrate the upper layer portion of the laminated body LMb. These isolation layers SHE are insulating layers 56, such as silicon oxide layers, which penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL immediately below the select gate line SGD1.

[0112] In other words, these separation layers SHE that penetrate the upper part of the laminate LMb extend in the X direction between the plate-shaped portions LIx through the memory region MR and part of the staircase region SR, thereby dividing the upper part of the laminate LMb into the above-mentioned select gate lines SGD0 and SGD1.

[0113] In the memory region MR, a plurality of pillars PL are distributed and arranged, passing through the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0114] As described above, the pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval shape, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0115] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0116] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0117] 4(b) and 4(c), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is arranged on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also arranged on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0118] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa. More specifically, the channel layer CN is arranged on the side and bottom surfaces of the pillar PL via the memory layer ME. However, a portion of the channel layer CN contacts the intermediate source line BSL on the side, thereby electrically connecting to the source line SL including the intermediate source line BSL. A core layer CR is filled further inside the channel layer CN.

[0119] Each of the pillars PL has a cap layer CP at its upper end. The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. The cap layer CP is connected to a bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction so as to intersect with the leading direction of the word line WL.

[0120] 4(a), plugs CH are connected only to three of the six pillars PL that penetrate the three separated select gate lines SGD and are electrically connected to the bit lines BL shown in Fig. 4(a). The other pillars PL are connected to other bit lines BL that extend in the Y direction parallel to the bit lines BL shown in Fig. 4(a) at positions different from the cross section shown in Fig. 4(a) via plugs CH not shown in Fig. 4(a).

[0121] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN and cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0122] As shown in Figure 4(b), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL in portions facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0123] 4(c), select gates STD are formed on the side surfaces of the pillars PL facing select gate lines SGD0 and SGD1 above the word lines WL, and select gates STS are formed on the side surfaces of the pillars PL facing select gate lines SGS0 and SGS1 below the word lines WL.

[0124] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0125] As shown in Figures 4(b) and 4(c), a conductive metal element-containing layer 25 and an insulating metal element-containing layer 55 are arranged in this order on both sides of each of the word lines WL and select gate lines SGD, SGS in the stacking direction of the laminate LM.

[0126] When the word lines WL are tungsten layers or the like, the metal element-containing layer 25 is at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer, for example, and functions as a barrier metal layer that suppresses the diffusion of tungsten atoms into structures near the word lines WL.When the word lines WL are molybdenum layers or the like, the metal element-containing layer 25 is a molybdenum nitride layer or the like and functions as a precursor when the word lines WL are formed.

[0127] The metal element-containing layer 55 is, for example, an aluminum oxide (Al2O3) layer, and functions as a block insulating layer in the memory cell MC.

[0128] As described above, these metal element-containing layers 25, 55 are disposed on both sides of the word lines WL in the stacking direction, and also on the end faces of the word lines WL opposing the side walls of the pillars PL in this order.

[0129] As shown in Figures 5(a) and 5(b), the staircase region SR has staircase portions SPa and SPb in which a plurality of word lines WL and select gate lines SGD and SGS are processed in a staircase shape. For convenience of explanation, Figures 5(a) and 5(b) show an example of a two-row staircase having two rows of stairs per block region BLK, unlike the three-row staircase example shown in Figure 2 and the like.

[0130] As shown in Figure 5(c), even when the staircase region SR has a two-stage staircase structure, the arrangement of the terrace portions of each layer in the staircase portions SPa and SPb is the same as in the three-stage staircase structure described above in Figure 3. That is, in the staircase portions SPa and SPb adjacent to each other in the Y direction, the terrace portions of the word lines WL or select gate lines SGS rise one layer at a time from the staircase portion SPb side to the staircase portion SPa side in the Y direction. On the other hand, the word lines WL and select gate lines SGS constituting the terrace portions change in steps of four layers in the X direction.

[0131] The staircase portion SPa shown in Fig. 5(a) is a cross section of a row including terrace portions of the lower word lines WL belonging to the same row in the Y direction of the two staircases of the staircase portion SPa shown in Fig. 5(c). The staircase portion SPb shown in Fig. 5(b) is also a cross section of a row including terrace portions of the lower word lines WL belonging to the same row in the Y direction of the two staircases of the staircase portion SPb shown in Fig. 5(c).

[0132] The stepped portions SPa and SPb are covered with an insulating layer 51. The insulating layer 51 reaches, for example, the height position of the uppermost layer of the laminated body LM, and the insulating layers 52 and 53 also cover the upper surface of the insulating layer 51. As described above, the insulating layer 51 also constitutes a part of the insulating layer 50 in FIG.

[0133] In the staircase region SR, the source lines SL include an intermediate insulating layer SCO interposed between the upper source line DSLb and the lower source line DSLa instead of the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0134] Therefore, in the staircase region SR, the plate-like portion LIx (not shown in FIG. 5) penetrates the insulating layer 51, the stacked body LM, and the upper source line DSLb to reach the intermediate insulating layer SCO.

[0135] 5(a), the staircase portion SPa includes a plurality of contacts CC connected to some of the word lines WL and select gate lines SGD, respectively. Each contact CC penetrates the insulating layer 51 and the like and is connected to a word line WL or select gate line SGD immediately below the insulating layer OL that constitutes each step of the staircase portion SPa.

[0136] 5(b), the stepped portion SPb includes a plate-like portion LIy in a portion where the select gate line SGD is processed into a stepped shape. The plate-like portion LIy is a single insulating layer 57 such as a silicon oxide layer. The stepped portion SPb also includes a plurality of contacts CC that are respectively connected to some of the word lines WL and the select gate line SGS.

[0137] That is, in the staircase portion SPb, the contacts CC are connected to word lines WL that belong to a layer different from the word lines WL connected to the contacts CC in the staircase portion SPa adjacent in the Y direction.

[0138] In the staircase portion SPb, each contact CC penetrates the insulating layer 51 etc. and is connected to a word line WL or a select gate line SGS immediately below the insulating layer OL that constitutes each step of the staircase portion SPb. As described above, no contact CC connected to a select gate line SGD is arranged in the staircase portion SPb.

[0139] In the stepped portions SPa and SPb, each contact CC has a tapered shape in which the diameter and cross-sectional area decrease from the upper end to the lower end, or a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper end and the lower end.

[0140] The contact CC also has an insulating layer 59 that covers the outer periphery of the contact CC, and a conductive layer 29 such as a tungsten layer or a copper layer that fills the inside of the insulating layer 59.

[0141] The insulating layer 59 is a liner layer of the contact CC. The conductive layer 29 is the core of the contact CC and is connected to an upper layer wiring MX disposed in the insulating layer 53 via a plug V0 disposed in the insulating layer 52. This upper layer wiring MX is electrically connected to the peripheral circuit CBA described above (see FIG. 1).

[0142] With this configuration, the word lines WL of each layer and the select gate lines SGD, SGS above and below the word lines WL can be electrically drawn out on both sides of the stacked body LM in the X direction. That is, with the above configuration, a predetermined voltage can be applied to the memory cells MC from the peripheral circuit CBA via the upper layer wiring MX, contacts CC, word lines WL, etc., to operate the memory cells MC as storage elements.

[0143] Furthermore, in the staircase region SR including the staircase portions SPa and SPb, a plurality of pillar-shaped portions HR are dispersedly arranged, penetrating the stacked body LM, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa. Each of the plurality of pillar-shaped portions HR is a single piece of insulating layer 58 such as a silicon oxide layer extending in the stacking direction within the stacked body LM.

[0144] As described above, the multiple columns HR are arranged, for example, in a staggered or grid pattern when viewed from the stacking direction of the laminate LM. Each column HR has a cross-sectional shape, such as a circle, an ellipse, or an oval, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0145] The columnar portion HR has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the columnar portion HR has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0146] 4(d) to 4(g) show the arrangement of the metal element-containing layers 25, 55 around the plate-shaped portions LIx, LIy.

[0147] 4(e) to 4(g), around the plate-shaped portion LIy, the metal element-containing layers 25, 55 are arranged in the same manner as around the pillar PL. That is, the metal element-containing layers 25, 55 are arranged in this order on both sides of the word lines WL etc. in the stacking direction, and also on the end faces of the word lines WL etc. facing the side faces of the plate-shaped portion LIy in the X direction.

[0148] As shown in Figures 4(d) and (g), around the plate-shaped portion LIx, the metal element-containing layers 25, 55 are not arranged on the Y-direction side surfaces of the plate-shaped portion LIx at the height of the word lines WL, etc., and the end faces of the word lines WL, etc. that face the Y-direction side surfaces of the plate-shaped portion LIx are in direct contact with each other.

[0149] 4(g), at the intersection with the plate-shaped portion LIy, a metal element-containing layer 55 is interposed between the plate-shaped portion LIx and the plate-shaped portion LIy at the height of the word line WL, etc. The metal element-containing layer 55 interposed between the plate-shaped portion LIx and the plate-shaped portion LIy may protrude inward of the plate-shaped portion LIx by, for example, the thickness of the metal element-containing layer 55, and as a result, the insulating layer 54 on the side wall of the plate-shaped portion LIx may also protrude slightly inward of the plate-shaped portion LIx at the intersection with the plate-shaped portion LIy.

[0150] 4(d) and 4(f), in the periphery of the plate-shaped portion LIx, the side surface in the Y direction of the plate-shaped portion LIx at the height position of the insulating layer OL is opposed to the end face of the insulating layer OL via the metal element-containing layer 55. In this way, the metal element-containing layer 55 extends from both sides in the stacking direction of the word line WL, etc., to the end face of the insulating layer OL adjacent to the word line WL in the stacking direction, facing the plate-shaped portion LIx, and is interposed between the end face of the insulating layer OL and the side surface of the plate-shaped portion LIx.

[0151] 4(f), the metal element-containing layer 55 extends continuously in the X direction on the Y-direction side surface of the plate-shaped portion LIx at the height of the insulating layer OL. As a result, at the intersection with the plate-shaped portion LIy, the metal element-containing layer 55 is interposed between the plate-shaped portion LIx and the plate-shaped portion LIy even at the height of the insulating layer OL.

[0152] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 6 to 16. Figures 6 to 12 among Figures 6 to 16 are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0153] 6 shows the laminate LMsa, which is the lower layer of the laminate LM before the word lines WL are formed, and how various components are formed in the laminate LMsa. Fig. 6 is a cross-sectional view along the X direction of the region that will later become the memory region MR and the staircase region SR.

[0154] As shown in FIG. 6(a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are formed in this order on a support substrate SS.

[0155] The support substrate SS may be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate, etc. The above-mentioned insulating layer 60 (see FIGS. 4 and 5, etc.) may be formed on the upper surface side of the support substrate SS.

[0156] The intermediate sacrificial layer SCN is formed in a region on the support substrate SS that will later become the memory region MR, and the intermediate insulating layer SCO is formed in a region on the support substrate SS that will later become the staircase region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL. As described above, the intermediate insulating layer SCO is, for example, a silicon oxide layer or the like.

[0157] Furthermore, a stacked body LMsa is formed on the upper source line DSLb, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers that will later be replaced with a conductive material to become word lines WL or select gate lines SGS.

[0158] 6(b), the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsa. Such processing can be performed by repeatedly slimming a mask pattern such as a photoresist layer and etching the insulating layers NL and OL of the laminate LMsa.

[0159] That is, a mask pattern is formed on the upper surface of the laminate LMsa, and the exposed insulating layers NL and OL are etched away layer by layer, for example, as a pair. Furthermore, the edges of the mask pattern are retracted by a process such as oxygen plasma to newly expose the upper surface of the laminate LMsa, and the insulating layers NL and OL are further etched away layer by layer. By repeating this process multiple times, the above-mentioned stepped shape is formed.

[0160] In this case, the number of insulating layers NL and OL removed in one etching process corresponds to the number of staircase rows that the staircase sections SPa and SPb will ultimately have. That is, when forming a pair of staircase sections SPa and SPb, each having a two-row staircase structure, four pairs of insulating layers NL and OL are removed in one etching process.

[0161] 6(c), an insulating layer 51 is formed to cover the stepped portion and reach the height of the upper surface of the laminated body LMsa. The insulating layer 51 is also formed in the outer region of the laminated body LMsa.

[0162] As shown in Fig. 6(d), a plurality of memory holes MHa and holes HLa are formed in the stacked body LMsa, extending in the stacking direction. The memory holes MHa are parts that will later become the lower structure of the pillars PL, and are arranged in the region that will later become the memory regions MR. The holes HLa are parts that will later become the lower structure of the columnar portions HR, and are arranged in the region that will later become the staircase regions SR.

[0163] These memory holes MHa and holes HLa pass through the stacked body LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN or the intermediate insulating layer SNO to reach the lower source line DSLa.

[0164] 6(e), the memory holes MHa and holes HLa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer. As a result, in the region that will later become the memory region MR, pillars PLc are formed in which the sacrificial layer 26 is filled in the memory holes MHa. Also, in the region that will later become the staircase region SR, columnar portions HRc are formed in which the sacrificial layer 26 is filled in the holes HLa.

[0165] 7 shows the formation of a laminate LMsb, which is the upper layer of the laminate LM before the word lines WL are formed, and the formation of various components in the laminates LMsa and LMsb. Similar to the above-described FIG. 6, FIG. 7 is a cross-sectional view along the X direction of the region that will later become the memory region MR and the staircase region SR.

[0166] 7(a), a laminate LMsb is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL, covering the laminate LMsa including the stepped portion, and the end portion in the X direction is processed to have a stepped shape. The sacrificial layer NL of the laminate LMsb will later be replaced with a conductive layer to become the word line WL or the select gate line SGD.

[0167] More specifically, after forming the laminate LMsb that covers the entire laminate LMsa, the insulating layers NL and OL are processed to have a stepped shape in a partial region of the laminate LMsb. This processing can be performed by repeating the slimming of a mask pattern such as a photoresist layer and the etching of the insulating layers NL and OL of the laminate LMsb multiple times, similar to the process shown in FIG. 6(b) above.

[0168] At this time, the top step of the staircase portion already formed in the laminate LMsa and the bottom step of the staircase portion formed in the laminate LMsb are brought close together, and these are formed so that they are continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb.

[0169] 7(b), an insulating layer 51 is formed that covers the upper surface of the insulating layer 51 that covers the staircase portion of the laminate LMsa and the newly formed staircase portion of the laminate LMsb, and reaches the height of the upper surface of the laminate LMsb. The insulating layer 51 is also formed in the outer regions of the laminates LMsa and LMsb.

[0170] As shown in Fig. 7(c), a plurality of memory holes MHb and holes HLb are formed in the stacked body LMsb, extending in the stacking direction. The memory holes MHb are later to become the upper structure of the pillar PL and are arranged in the region that will later become the memory region MR. The holes HLb are later to become the upper structure of the columnar portion HR and are arranged in the region that will later become the staircase region SR.

[0171] These memory holes MHb and holes HLb penetrate the stacked body LMsb and reach the upper ends of the pillar PLc and columnar portion HRc formed in the stacked body LMsa, respectively.

[0172] Thereafter, the sacrificial layer 26 filling the pillars PLc and the columnar portions HRc is removed via the memory holes MHb and holes HLb. However, if the sacrificial layer 26 is a CVD-carbon layer or the like, the sacrificial layer 26 may also be removed all at once when removing the resist pattern or the like used to process the memory holes MHb and holes HLb.

[0173] Furthermore, holes HLa and HLb, which are connected at their upper and lower ends, are filled with an insulating layer 58 such as a silicon oxide layer to form a plurality of columnar portions HR. Note that the insulating layer 58 may be filled into each of the columnar portions HR separately for each of the holes HLa and HLb. That is, after forming the hole HLa in the laminate LMsa, the insulating layer 58 may be filled in place of the sacrificial layer 26, and after forming the hole HLb in the laminate LMsb, the insulating layer 58 may be further filled into the hole HLb.

[0174] Furthermore, in the stepped portion of the upper layer side of the laminated body LMsb, a plurality of slits (not shown) are formed that penetrate the laminated bodies LMsa and LMsb and extend in the Y direction through areas that will become two block regions BLK. An insulating layer 57 such as a silicon oxide layer is then filled into these slits to form a plurality of plate-like portions LIy. At this time, the memory holes MHa and MHb, whose upper and lower ends are connected, are protected by being covered with a photoresist layer or the like.

[0175] As will be described below, memory layers ME, channel layers CN, and core layers CR are then stacked in the memory holes MHa and MHb to form multiple pillars PL. These memory layers ME, channel layers CN, and core layers CR generate stress in the stacked bodies LMsa and LMsb.

[0176] As described above, by completing the formation of the plate-like portion LIy before these multilayer structures are formed in the memory holes MHa and MHb, it is possible to prevent misalignment of each part, including the pillar PL, due to the influence of stress generated by the multilayer structure of the pillar PL, for example, when forming a slit that becomes the plate-like portion LIy.

[0177] Furthermore, as described above, by forming the plate-like portion LIy in a position as far as possible in the X direction from the region where the memory holes MHa, MHb are formed in the portion where the upper insulating layer NL that becomes the select gate line SGD is processed into a stepped shape, it is possible to further suppress misalignment of the memory holes MHa, MHb, etc. when forming the slit that becomes the plate-like portion LIy and when filling the slit with the insulating layer 57.

[0178] 8 and 9 show how a pillar PL is formed by forming a multilayer structure in the memory hole MH. Figures 8 and 9 are cross-sectional views along the Y direction of a region that will later become the memory region MR.

[0179] As shown in FIG. 8(a), a plurality of memory holes MH including memory holes MHa and MHb each connected at the upper end and the lower end are formed in a region that will later become the memory region MR.

[0180] 8(b), a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are formed in this order in the memory hole MH, whereby the multilayer insulating layer MEb and the semiconductor layer CNb are disposed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0181] The multilayer insulating layer MEb is an insulating layer with a multilayer structure that will later become the memory layer ME. The semiconductor layer CNb is a layer that will later become the channel layer CN. The insulating layer CRb is a silicon oxide layer or the like that will later become the core layer CR.

[0182] The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also formed in this order on the upper surface of the laminated body LMsb.

[0183] As shown in Figure 8(c), in the region that will later become the memory region MR, the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb are sequentially etched back to remove them from the top surface of the laminated body LMsb, and a recess DN is formed at the top end of the memory hole MH from which the insulating layer CRb and the semiconductor layer CNb have been removed.

[0184] As a result, the memory layer ME, the channel layer CN, and the core layer CR are formed in the memory hole MH in this order from the outer periphery.

[0185] 9(a), in the region that will later become the memory region MR, a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb is a layer that will later become the cap layer CP. The semiconductor layer CPb is also formed on the upper surface of the stacked body LMsb.

[0186] As shown in FIG. 9(b), in the region that will later become the memory region MR, the semiconductor layer CPb on the top surface of the stacked body LMsb is removed by CMP or the like, and a cap layer CP is formed at the upper end of the memory hole MH.

[0187] As shown in FIG. 9(c), an insulating layer OL is deposited on the top layer of the laminated body LMsb that has been thinned by the above-described process such as CMP.

[0188] As a result, a pillar PL is formed in which the cap layer CP is buried in the uppermost insulating layer OL. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and a part of the side surface of the channel layer CN is not exposed from the memory layer ME.

[0189] Next, the formation of the slit STx and the bridge portion BRx at the upper end of the slit STx will be shown using Figure 10. The slit STx will later become the plate-like portion LIx. The following figures show the formation of the bridge portion BRx only in the slit STx on one side in the left-right direction of the paper.

[0190] FIG. 10 is a cross-sectional view along the Y direction of a region that will later become the memory region MR.

[0191] As shown in FIG. 10(a), a slit STx is formed that passes through the stacked bodies LMsb, LMsa and the upper source line DSLb and reaches the intermediate sacrificial layer SCN.

[0192] The slits STx have a tapered or bowed cross section in the Y direction, and extend in the X direction within the stacks LMsa and LMsb. Therefore, in the staircase region SR (not shown), the lower ends of the slits STx reach the intermediate insulating layer SCO.

[0193] As shown in FIG. 10(b), the slit STx is filled with a sacrificial layer 27 such as an amorphous silicon layer.

[0194] 10(c), a portion of the sacrificial layer 27 at the upper end of the slit STx is removed. As a result, multiple recesses are formed at the upper end of the slit STx, lined up in the X direction at predetermined intervals. The slit STx on one side in the left-right direction of the paper is a cross section of a portion where recesses are formed, and the slit STx on the other side in the left-right direction of the paper is a cross section of a portion where no recesses are formed.

[0195] 10(d), the recesses at the upper ends of the slits STx are filled with a polysilicon layer or the like to form multiple bridge portions BRx. The slits STx on one side in the left-right direction of the paper are cross sections of the portions where the bridge portions BRx are formed, and the slits STx on the other side in the left-right direction of the paper are cross sections of the portions where the bridge portions BRx are not formed.

[0196] Thereafter, the sacrificial layer 27 in the slit STx is removed. The sacrificial layer 27 is removed from the upper end side of the slit STx where the bridge portion BRx is not formed.

[0197] In addition, in parallel with the formation of the bridge portions BRx in the slits STx, the bridge portions BRy may be formed on the already formed plate-like portion LIy. When forming the bridge portions BRy on the plate-like portion LIy, the insulating layer 57 on the upper end portion of the plate-like portion LIy is removed to form multiple recesses, and these recesses are filled with a polysilicon layer or the like. In this way, the bridge portions BRy are formed on the plate-like portion LIy.

[0198] However, the bridge portions BRy may be formed at other times, such as when the plate-like portions LIy are formed.

[0199] Next, the formation of the source lines SL and word lines WL will be shown with reference to Figures 11 and 12. Figures 11 and 12 are cross-sectional views along the Y direction of a region that will later become the memory region MR, similar to Figure 10 described above.

[0200] 11(a), an insulating layer 54s is formed on the side walls of the slit STx facing each other in the Y direction. The insulating layer 54s is formed through the upper end of the slit STx where the bridge portion BRx is not formed.

[0201] As shown in FIG. 11(b), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit STx whose sidewalls are protected by the insulating layer 54s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0202] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Also, a part of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPs.

[0203] At this time, since the sidewalls of the slits STx are protected by the insulating layer 54s, the insulating layer NL in the stacked bodies LMsa and LMsb is prevented from being removed as well. In addition, in the staircase region SR (not shown), there is no intermediate sacrificial layer SCN between the lower source line DSLa and the upper source line DSLb, and therefore no gap layer GPs is formed.

[0204] 11(c), a chemical solution is appropriately poured into the gap layer GPs through the slit STx to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see FIGS. 4(b) and 4(c)) of the memory layer ME exposed in the gap layer GPs. As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPs.

[0205] 11(d), a raw material gas such as amorphous silicon is injected through the slit STx whose sidewalls are protected by the insulating layer 54s, and the gap layer GPs is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0206] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0207] At this time, in the staircase region SR (not shown), no gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb, and no intermediate source line BSL is formed either.

[0208] As shown in FIG. 12(a), the insulating layer 54s on the sidewall of the slit STx is temporarily removed.

[0209] 12(b), a remover for the insulating layers NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits STx to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0210] The stacked bodies LMga and LMgb, each including a plurality of gap layers GP, have a fragile structure. In the region that will later become the memory region MR, a plurality of pillars PL support the fragile stacked bodies LMga and LMgb. In the region that will later become the staircase region SR, a plurality of columnar portions HR support the fragile stacked bodies LMga and LMgb.

[0211] Such a support structure by the pillars PL and the columnar portions HR prevents the remaining insulating layer OL from bending and the laminated bodies LMga and LMgb from being distorted or collapsed.

[0212] Furthermore, the bridge portions BRx formed at the upper ends of the slits STx can prevent the slits STx from being deformed by stress on both sides of the slits STx in the Y direction, and prevent misalignment of the various parts including the pillars PL.

[0213] 12(c), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminates LMga, LMgb through the slits STx to fill the gap layers GP of the laminates LMga, LMgb with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one layer at a time.

[0214] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0215] When forming the word lines WL in the gap layers GP of the laminated bodies LMga and LMgb, the above-mentioned metal element containing layers 55 and 25 are formed in this order in advance. Below, Figures 13 to 16 show the state around the slits STx and the plate-shaped portions LIy during the replacement process of the word lines WL.

[0216] 13 to 16 are cross-sectional views illustrating in order part of the procedure for replacing the word lines WL in the semiconductor memory device 1 according to the embodiment.

[0217] In Figures 13 to 16, (Aa) and (Ab) are enlarged cross-sectional views along the Y direction of the slit STx at the height position of any word line WL, and (Ba) and (Bb) are enlarged cross-sectional views along the X direction of the plate-shaped portion LIy at the height position of any word line WL.

[0218] In addition, (Ca) and (Cb) are XY cross-sectional views of the slit STx and the plate-shaped portion LIy at a height position of any insulating layer OL, and (Da) and (Db) are XY cross-sectional views of the slit STx and the plate-shaped portion LIy at a height position of any insulating layer NL.

[0219] 13(Aa) to 13(Da), a slit STx and a plate-shaped portion LIy are already formed in the stacked bodies LMsa and LMsb before the replacement process of the word lines WL, etc. As shown in Fig. 13(Ca) and 13(Da), the Y-direction end of the plate-shaped portion LIy is divided by a slit STx extending in the X-direction.

[0220] By positioning the slit STx and the plate-like portion LIy so that their ends cross each other, even if there is a misalignment between the plate-like portion LIy that has already been formed and the slit STx that is formed later, the ends of the plate-like portion LIy and the slit STx can be more reliably connected, and electrical isolation between specified areas within the block region BLK can be more reliably achieved.

[0221] 13(Ab) to 13(Db), a remover such as hot phosphoric acid is poured through the slit STx to remove the insulating layers NL from the laminates LMsa and LMsb, thereby forming gap layers GP in the areas where the insulating layers NL have been removed.

[0222] 14(Aa) to 14(Da), a raw material gas such as aluminum oxide is supplied to form a metal element-containing layer 55 in the gap layer GP. The metal element-containing layer 55 is formed on the upper and lower surfaces of the insulating layer OL exposed on both sides of the gap layer GP in the stacking direction.

[0223] The metal element-containing layer 55 is also formed on the end face of the insulating layer OL facing the Y-direction side face of the slit STx and on the X-direction side face of the plate-shaped portion LIy. At this time, the Y-direction end face of the plate-shaped portion LIy, which is divided by the slit STx and faces the Y-direction side face of the slit STx, is on a plane continuous with the end face of the insulating layer OL facing the Y-direction side face of the slit STx at the height position of the insulating layer OL. Therefore, the metal element-containing layer 55 is also formed on the Y-direction end face of the plate-shaped portion LIy facing the Y-direction side face of the slit STx.

[0224] Furthermore, the metal element-containing layer 55 is also formed on the Y-direction end face of the plate-shaped portion LIy facing the Y-direction side face of the slit STx at the height position of the gap layer GP. In this case, the metal element-containing layer 55 formed on the Y-direction end face of the plate-shaped portion LIy may protrude into the inside of the slit STx by, for example, the layer thickness of the metal element-containing layer 55.

[0225] 14(Ab) to 14(Db), a raw material gas such as titanium, titanium nitride, tantalum, tantalum nitride, or molybdenum nitride is supplied to form a metal element-containing layer 25 in the gap layer GP. As a result, the metal element-containing layer 25 is formed in each portion of the gap layer GP with the metal element-containing layer 55 interposed therebetween.

[0226] That is, the metal element containing layer 25 is formed via the metal element containing layer 55 on the upper and lower surfaces of the insulating layer OL exposed on both sides of the gap layer GP in the stacking direction.

[0227] The metal element-containing layer 25 is also formed on the end face of the insulating layer OL facing the Y-direction side surface of the slit STx and the Y-direction end face of the plate-shaped portion LIy via the metal element-containing layer 55. In this case, the metal element-containing layer 25 formed on the Y-direction end face of the plate-shaped portion LIy may be in a state of further protruding inward of the slit STx, for example.

[0228] At the height position of the gap layer GP, the metal element containing layer 25 is also formed on the side surface of the plate-shaped portion LIy in the X direction with the metal element containing layer 55 interposed therebetween.

[0229] 15(Aa) to 15(Da), a source gas such as tungsten is supplied into the gap layer GP on which the metal element-containing layers 55 and 25 are formed in this order, and the gap layer GP is filled with a conductive material. As a result, the word lines WL and the like are formed in the gap layer GP. At this time, a tungsten layer and the like may also be formed in the slits STx.

[0230] As shown in Figures 15(Ab) to 15(Db), the tungsten layer and the like in the slit STx are removed. Also, the metal element-containing layer 25 formed on the end face of the insulating layer OL facing the side face of the slit STx in the Y direction is removed. This is to prevent the word lines WL arranged on both sides of the insulating layer OL in the stacking direction from becoming electrically connected to each other through the metal element-containing layer 25 on the end face of the insulating layer OL. The metal element-containing layer 55 on the end face of the insulating layer OL is insulating, so it may be left without being removed.

[0231] As shown in Figures 16(Aa) to 16(Da), an insulating layer 54 is formed to cover the side walls of the slits STx, and as shown in Figures 16(Ab) to 16(Db), the inside of the slits STx is further filled with a conductive layer 24. This forms the plate-shaped portion LIx.

[0232] The insulating layer 54 of the plate-shaped portion LIx may protrude slightly into the plate-shaped portion LIx at the connection portion with the plate-shaped portion LIy due to the metal element-containing layers 25, 55 protruding into the plate-shaped portion LIx.

[0233] Alternatively, the insulating layer 54 or the like may be filled in the slit STx without forming the conductive layer 24, thereby forming a plate-like member.

[0234] In addition, a trench is formed through one or more conductive layers including the topmost conductive layer of the laminated body LMb, and an insulating layer 56 is filled in the trench to form a separation layer SHE that divides these conductive layers into the pattern of the select gate line SGD.

[0235] At this time, the bridge portion BRy formed on the plate-like portion LIy prevents the separation layer SHE from exceeding the target depth and reaching the lower layer of the laminate LM. Furthermore, when the X-direction end of the separation layer SHE is positioned so as to terminate on the side surface of the plate-like portion LIy, the bridge portion BRy of the plate-like portion LIy prevents the separation layer SHE from being formed in the portion where the word line WL or the like is processed in a stepped shape. In this way, the bridge portion BRy of the plate-like portion LIy functions as a stopper layer when the separation layer SHE is formed.

[0236] After this, a plurality of contact holes are formed through the insulating layer 51 covering the staircase region SR, an insulating layer 59 is formed to cover the side walls of the contact holes, and the contact holes are further filled with a conductive layer 29 to form a plurality of contacts CC.

[0237] An insulating layer 52 is formed on the upper surface of the insulating layer 51 covering the upper surface of the stacked body LM and the staircase region SR, and a plug V0 is formed through the insulating layer 52 to be connected to the contact CC. A plug CH is formed through the insulating layer 52 to be connected to the pillar PL. An insulating layer 53 is then formed on the insulating layer 52, and upper layer wiring MX and bit lines BL, etc., connected to the plugs V0 and CH are formed. Electrode pads, etc., for electrical conduction with the peripheral circuit CBA are formed on the upper surface of the insulating layer 53.

[0238] It should be noted that the plugs V0, CH, upper layer wiring MX, bit line BL, etc. may be formed all at once by using, for example, a dual damascene method.

[0239] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads, etc. formed on the upper surface of the insulating layer 40.

[0240] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0241] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0242] (Overview) A semiconductor memory device such as a three-dimensional nonvolatile memory is configured such that multiple word lines, etc. are stacked, some of which are formed in a staircase shape, and contacts are connected to these staircase portions, thereby enabling voltage application to the multiple word lines, etc. Therefore, as the number of stacked word lines, etc. increases, the length of the staircase portion in the X direction, i.e., the staircase length, also increases.

[0243] Furthermore, since the staircase regions are arranged on both sides of the stack in the X direction, for example, a memory region belonging to one block region is operated by contacts connected to the staircase region on one side in the X direction. In this case, no contacts are connected to the staircase region on the other side in the X direction, which becomes dead space. This also contributes to an increase in the area occupied by the staircase regions in the semiconductor memory device.

[0244] According to the embodiment of the semiconductor memory device 1, there is provided a plate-shaped portion LIx that divides the memory region MR so that each memory region belongs to a block region BLK aligned in the Y direction, and a plate-shaped portion LIy that extends within the stack LM in the direction along the Y direction and the stacking direction of the stack LM and divides one memory region MR and a staircase region SR among the memory regions MR that each belong to a block region BLK aligned in the Y direction.

[0245] In this way, by electrically isolating the staircase region SR on one side in the X direction of the laminate LM from the memory region MR belonging to one of the two block regions BLK, the staircase region SR on one side in the X direction, which corresponds to two block regions BLK, can be used for memory cell operation of the memory region MR belonging to the other of the two block regions BLK. This makes it possible to reduce the area of ​​the staircase region SR in the entire semiconductor memory device 1, i.e., the staircase length.

[0246] According to the semiconductor memory device 1 of the embodiment, the plate-shaped portion LIy is in contact with the Y-direction side surface of the plate-shaped portion LIx via the insulating metal-element-containing layer 55. Furthermore, the metal-element-containing layer 55 extends continuously along the Y-direction side surface of the plate-shaped portion LIx, including the portion in contact with the plate-shaped portion LIy, at the height position of each of the multiple insulating layers OL of the laminate LM.

[0247] According to the semiconductor memory device 1 of the embodiment, the word lines WL and the select gate lines SGD, SGS are in direct contact with the Y-direction side surface of the plate-shaped portion LIx, and are in contact with the X-direction side surface of the plate-shaped portion LIy via at least the metal element-containing layer 55. Furthermore, the insulating layers OL are in contact with the Y-direction side surface of the plate-shaped portion LIx via the metal element-containing layer 55, and are in direct contact with the X-direction side surface of the plate-shaped portion LIy.

[0248] These are all evidences that the plate-shaped portions LIx and LIy were formed at different times. More specifically, since the plate-shaped portion LIy was already formed before the replacement process of the word lines WL, etc., the metal element-containing layer 55 has the above-described arrangement around the plate-shaped portions LIx and LIy.

[0249] In order to reduce the overall staircase length of the staircase sections SPa and SPb, when the plate-shaped sections LIx and LIy are used to electrically separate specific areas within the block region BLK, if the plate-shaped sections LIx and LIy are formed at the same time, for example, the laminates LMsa and LMsb may be divided at multiple points, which may result in a large amount of positional misalignment between the components formed in the laminates LMsa and LMsb.

[0250] As in the semiconductor memory device 1 of the embodiment, by forming the plate-shaped portions LIx and LIy at different times, the number of places where the stacks LMsa and LMsb are divided at one time can be reduced, and misalignment between each component within the stacks LMsa and LMsb can be suppressed.

[0251] According to the semiconductor memory device 1 of the embodiment, in the staircase portions SPa and SPb that are aligned in the X direction with the memory region MR adjacent in the Y direction, a plurality of contacts CC are arranged that are connected to a plurality of memory cells MC included in the memory region MR that are aligned in the X direction with the staircase portion SPa.

[0252] More specifically, the contacts CC of the staircase portions SPa and SPb arranged in the staircase regions SR at both ends of the block region BLK so as to correspond to two block regions BLK adjacent in the Y direction are used on one side in the X direction for the operation of the memory cells MC in the memory region MR belonging to one block region BLK, while on the other side in the X direction they are used for the operation of the memory cells MC in the memory region MR belonging to the other block region BLK. This makes it possible to prevent dead space from being generated in the staircase region SR, and in principle, the area of ​​the staircase region SR that the semiconductor memory device 1 occupies and the staircase length of the staircase portions SPa and SPb can be reduced to about half of the area when the configuration of the embodiment is not adopted.

[0253] (Variation) Next, a semiconductor memory device according to a modification of the embodiment will be described with reference to Figures 17 and 18. In the semiconductor memory device according to the modification, the method of forming the plate-like portion LIr extending in the Y direction is different from that of the plate-like portion LIy in the above-described embodiment.

[0254] In the following drawings, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0255] 17 and 18 are cross-sectional views illustrating in order some steps of a method for forming plate-shaped portions LIx and LIr in a semiconductor memory device according to a modified example of the embodiment. More specifically, FIGS. 17 and 18 are XY cross-sectional views at a height position of an arbitrary insulating layer NL.

[0256] 17(a), it is assumed that the stacked bodies LMsa and LMsb before replacement have already been formed with a staircase shape, a plurality of memory holes MH, and a plurality of holes HL. These memory holes MH and holes HL are periodically arranged, such as in a staggered arrangement.

[0257] However, these memory holes MH and holes HL are not arranged in the region where the slits STx will be formed later and the region where the contacts CC connected to the word lines WL and the select gate lines SGS will be formed. Note that the region shown in Figure 17(a) is the part that will later become the stepped portion SPb, so there is no space for the contacts CC to be formed in the part where the insulating layer NL on the upper side of the stacked body LMsb is processed into a stepped shape.

[0258] In addition, between the stepped portion of the upper insulating layer NL, which will later become the select gate line SGD, and the stepped portion of the lower insulating layer NL, which will later become the word line WL, etc., a plurality of holes HLy, each having a larger diameter than the other holes HL, are arranged in a line along the Y direction.

[0259] In this case, it is preferable that the diameters of the holes HLy are set within a range that allows them to be formed together with the memory holes MH and holes HL. Also, it is preferable that the formation positions of the holes HL and HLy are adjusted so that the holes HL and HLy are arranged periodically as a whole. This makes it easy to form the memory holes MH and holes HL and HLy together.

[0260] 17(b), the diameters of the holes HLy are enlarged by wet processing or the like. At this time, it is sufficient that the diameters of the holes HLy are enlarged at least at the height positions of the insulating layers NL, so that the holes HLy are connected to each other in the Y direction at least at the height positions of the insulating layers NL.

[0261] However, the diameter of the plurality of holes HLy may be expanded over the entirety in the stacking direction, and the entire side surfaces of these holes HLy in the Y direction may be connected to each other.

[0262] 17(c), a plurality of holes HLy connected to each other in the Y direction are filled with an insulating layer such as a silicon oxide layer to form a plate-like portion LIr to which a plurality of columnar portions HRy are connected. At this time, a plurality of holes HL can also be filled with an insulating layer to form a plurality of columnar portions HR.

[0263] During the process shown in FIG. 17(c), the memory holes MH are protected by a photoresist layer or the like that covers them.

[0264] As shown in FIG. 18(a), a memory layer ME, a channel layer CN, a core layer CR, etc. are sequentially formed in the memory hole MH to form a plurality of pillars PL.

[0265] 18(b), a plurality of slits STx are formed extending in the X direction through the regions between the pillars PL and the columnar portions HR. At this time, for example, the slit STx in the center of the paper extends in the X direction from the region between the pillars PL to the region between the columnar portions HR, dividing the approximate center of the plate-like portion LIr in the Y direction. Furthermore, the slits STx at the top and bottom of the paper extend in the X direction through the regions between the pillars PL, intersect both ends of the plate-like portion LIr in the Y direction, and then extend further in the X direction through the regions between the columnar portions HR with gaps.

[0266] 18(c), a plurality of bridge portions BRx are formed at the upper end of the slit STx at predetermined intervals in the X direction, and a plurality of bridge portions BRy are formed at the upper end of the plate-like portion LIr at predetermined intervals in the Y direction.

[0267] The cross-linking portions BRy of the plate-shaped portion LIr may not be formed at the same time as the cross-linking portions BRx of the plate-shaped portion LIx, but may be formed, for example, when the plate-shaped portion LIr is formed.

[0268] The subsequent processing is performed in the same manner as the processing in the above-described embodiment from Figure 11 onwards, for example. In this way, the plate-like portions LIx and LIr are formed by the method of the modified example.

[0269] According to the semiconductor memory device of the modified example, the plate-shaped portion LIr extends in the stacking direction within the stacked body LM and includes a plurality of columnar portions HRy connected in the Y direction at the height positions of at least a plurality of word lines WL and select gate lines SGD, SGS. This allows many of the processes for forming the plate-shaped portion LIr to be performed collectively with the processes for forming the columnar portions HR, making it possible to form the plate-shaped portion LIr more easily.

[0270] According to the semiconductor memory device of the modified example, the plurality of columnar portions HR, HRy are periodically arranged as a whole when viewed from the stacking direction of the laminate LM. By arranging the columnar portions HR, HRy in this manner, it is possible to perform high-precision processing when collectively forming these columnar portions HR, HRy.

[0271] (Other variations) In the above-described embodiment and modified examples, a two-tier staircase or a three-tier staircase has been mainly described, in which terrace portions formed by word lines WL etc. ascend one layer at a time from one side in the Y direction of a pair of staircase portions SPa and SPb adjacent in the Y direction to the other side. However, the configuration of the staircase portions SPa and SPb is not limited to this.

[0272] For example, in each staircase section SPa, SPb having a multi-row staircase structure of three or more rows, the word lines WL, etc. constituting the terrace portion belonging to the row in the center of the Y direction may be word lines WL at a lower level than the word lines WL, etc. of the terrace portions of other rows.

[0273] That is, for example, in a three-column staircase structure, if the X-direction positions of the terrace portions included in the first to third columns of stairs aligned in the Y direction are equal, the number of layers of word lines WL, etc. included in the stacking direction in the terrace portion of the first column may be greater than the number of layers of word lines WL, etc. included in the stacking direction in the terrace portion of the second column < the number of layers of word lines WL, etc. included in the stacking direction in the terrace portion of the third column.

[0274] Furthermore, for example, in a four-column staircase structure, if the X-direction positions of the terrace portions included in the first to fourth columns of stairs aligned in the Y direction are equal, the number of layers of word lines WL, etc. included in the stacking direction in the terrace portion of the first column may be greater than the number of layers of word lines WL, etc. included in the stacking direction in the terrace portion of the second column, and the number of layers of word lines WL, etc. included in the stacking direction in the terrace portion of the third column may be less than the number of layers of word lines WL, etc. included in the stacking direction in the terrace portion of the fourth column.

[0275] As another example, in the stacks LMa and LMb that are the upper and lower structures of the stack LM, terrace portions of the word lines WL and select gate lines SGS included in the stack LMa may be arranged on one of the pair of stepped portions SPa and SPb, and terrace portions of the word lines WL included in the stack LMb may be arranged on the other. Such an example is shown in FIG.

[0276] 19 is a schematic perspective view of a staircase region SR2 that a stack of a semiconductor memory device according to another modification of the embodiment has on one side in the X direction. Note that, in FIG. 19 as well, an example of a three-row staircase will be described.

[0277] 19, of the staircase portions SPa and SPb adjacent to each other in the Y direction, terrace portions of the word lines WL and select gate lines SGS included in the stacked body LMa are arranged in the staircase portion SPb. Also, of the staircase portions SPa and SPb, terrace portions of the word lines WL included in the stacked body LMb are arranged in the staircase portion SPa.

[0278] In this case, too, the terrace portions of the word lines WL or select gate lines SGS rise in the Y direction from the staircase portion SPb side to the staircase portion SPa side. Within the staircase portion SPa or within the staircase portion SPb, these terrace portions rise one layer at a time. Meanwhile, at the boundary between the staircase portions SPa and SPb, the total number of layers of the word lines WL and select gate lines SGS included in the stacking direction between the terrace portion of the staircase portion SPb and the terrace portion of the staircase portion SPa differs by the total number of layers of the word lines WL and select gate lines SGS that have terrace portions in the staircase portion SPb.

[0279] In the example of FIG. 19, in each pair of staircase portions SPa, SPb adjacent to each other in the Y direction, the terrace portions of the word lines WL etc. ascend by three layers in the X direction toward the memory region MR.

[0280] Even with this configuration, both the word lines WL and the select gate lines SGS included in the laminate LM have terrace portions in either one of these staircase sections SPa, SPb, and multiple word lines WL and select gate lines SGD, SGS in the laminate LM can be drawn out by these pairs of staircase sections SPa, SPb.

[0281] In the above-described embodiment and modified examples, the plate-like portion LIy extending in the Y direction extends across two block regions BLK and separates the memory region MR and the staircase region SR in these block regions BLK. However, the number of block regions BLK separated by one plate-like portion LIy is not limited to this. For example, one plate-like portion LIy may extend in the Y direction to separate one block region BLK. Even in this configuration, it is possible to pair the staircase portions SPa and SPb arranged in the staircase regions SR at both ends of the block region BLK corresponding to the two block regions BLK, and to extract multiple word lines WL and select gate lines SGD and SGS in the stack LM.

[0282] In the above-described embodiment and modified examples, the plate-shaped portions LIx, LIy, and LIr have bridges BRx and BRy at their upper ends, respectively. However, at least one of the plate-shaped portions LIx, LIy, and LIr may also have a bridge at a height position between the stacks LMa and LMb.

[0283] To form a bridge portion at a height position between the upper and lower ends of the plate-like portion LIr, a hole for the lower structure of the columnar portion HRy can be formed in the laminate LMsa, and then a bridge portion can be formed at the upper end of the hole, and a hole for the upper structure of the columnar portion HRy can be formed in the laminate LMsb, and then a bridge portion can be formed at the upper end of the hole.

[0284] To form a bridge portion at a height between the upper and lower ends of the plate-like portions LIx and LIy, a slit STx may be formed in each of the laminates LMa and LMb. That is, a slit penetrating the laminate LMsa is formed at a predetermined timing to form a bridge portion at the upper end. After the laminate LMsb is formed, a slit penetrating the laminate LMsb is formed at a predetermined timing to form a bridge portion at the upper end.

[0285] At this time, for example, the memory holes MHa of the laminated body LMa may be formed separately, and the holes HLa and the slits that become the lower structures of the plate-like portions LIx and LIy may be formed at the same time.

[0286] In the above-described embodiment and modified example, the plate-shaped portions LIx and LIy have substantially the same depth in the source line SL, but the depths of these plate-shaped portions LIx and LIy may be different from each other. Note that, since the plate-shaped portion LIx has a lower aspect ratio than the plate-shaped portion LIy, the depth of the plate-shaped portion LIx may be deeper than that of the plate-shaped portion LIy.

[0287] In addition, in the above-described embodiment and modified examples, the laminate LM has a two-tier structure. However, the configuration of the laminate LM may be one-tier, or may be three or more tiers.

[0288] In the above-described embodiment and modified examples, the pillar PL is connected to the source line SL at the side of the channel layer CN, but this is not limiting. For example, the pillar may be configured so that the memory layer at the bottom of the pillar is removed and the lower end of the channel layer is connected to the source line.

[0289] In the above-described embodiment and modified example, the peripheral circuit CBA is arranged above the stack LM, but the peripheral circuit may be arranged below the stack or on the same layer as the stack.

[0290] When the peripheral circuit is disposed below the stack, the source line and the stack can be formed on an insulating layer of a semiconductor substrate having the peripheral circuit covered with the insulating layer, for example. When the peripheral circuit is disposed on the same layer as the stack, the stack can be formed at a different position from the peripheral circuit on the semiconductor substrate on which the peripheral circuit is formed.

[0291] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0292] 1...semiconductor memory device, CC...contact, LIr, LIx, LIy...plate-shaped portion, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb...laminated body, MC...memory cell, MR...memory region, NL, OL...insulating layer, 51...insulating layer, PL...pillar, SGD, SGS...select gate line, SPa, SPb...staircase portion, SR, SR2...staircase region, WL...word line.

Claims

1. a stacked body in which a plurality of conductive layers are stacked apart from each other, and first and second staircase regions in which the plurality of conductive layers are processed into a staircase shape are disposed at both ends in a first direction intersecting with a stacking direction of the plurality of conductive layers, with a memory region sandwiched therebetween; a first plate-shaped portion extending within the stack in the first direction and the stacking direction and dividing the memory area into first and second sub-memory areas adjacent to each other in a second direction intersecting the stacking direction and the first direction; a second plate-shaped portion extending within the stack in the second direction and the stacking direction and dividing the first sub-memory region and the first staircase region, The second plate-shaped portion includes: the first plate-shaped portion is connected to a side surface of the first plate-shaped portion in the second direction via an insulating metal element-containing layer; Semiconductor memory device.

2. the laminate is formed by stacking the plurality of conductive layers and the plurality of insulating layers alternately one by one in the first direction, The metal element-containing layer is At each height position of the plurality of insulating layers, the insulating layers extend continuously along a side surface of the first plate-shaped portion in the second direction, including a portion connected to the second plate-shaped portion.

2. The semiconductor memory device according to claim 1.

3. The plurality of conductive layers are The stack includes a first group and a second group that are stacked at different positions within the stack, The first staircase region includes: a first sub-staircase region arranged alongside the first sub-memory region in the first direction, in which the conductive layers belonging to the first group among the plurality of conductive layers are processed into a staircase shape; a second sub-staircase region arranged alongside the second sub-memory region in the first direction, in which conductive layers belonging to the second group among the plurality of conductive layers are processed into a staircase shape; The first and second sub-staircase regions include: a plurality of first contacts are arranged, the first contacts being electrically connected to a plurality of memory cells included in the second sub-memory region; 2. The semiconductor memory device according to claim 1.

4. a separation layer that penetrates a conductive layer belonging to a third group stacked above the conductive layers of the first and second groups, extends within the memory region in the first direction, and divides the conductive layers belonging to the third group in the first and second sub-memory regions in the second direction; The second plate-shaped portion includes: Between the first sub-memory region and the first sub-staircase region, a lowermost conductive layer among the conductive layers belonging to the third group through which the isolation layer penetrates is disposed in a terrace portion provided so as not to overlap with an upper conductive layer in the stacking direction.

4. The semiconductor memory device according to claim 3.

5. a stacked body in which a plurality of conductive layers are stacked apart from each other, and first and second staircase regions in which the plurality of conductive layers are processed into a staircase shape are disposed at both ends in a first direction intersecting with a stacking direction of the plurality of conductive layers, with a memory region sandwiched therebetween; a first plate-shaped portion extending within the stack in the first direction and the stacking direction and dividing the memory area into first and second sub-memory areas adjacent to each other in a second direction intersecting the stacking direction and the first direction; a second plate-shaped portion extending within the stack in the second direction and the stacking direction and dividing the first sub-memory region and the first staircase region, The plurality of conductive layers are directly connected to a side surface of the first plate-shaped portion in the second direction, the first metal element-containing layer is connected to the side surface of the second plate-shaped portion in the first direction via at least a first metal element-containing layer; Semiconductor memory device.

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