Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device in which a channel stopper layer having a stable pattern can be formed easily through a simple process with high productivity.SOLUTION: The semiconductor device includes a P type semiconductor layer (P +) 13 disposed on a first N type semiconductor layer (N -) 11, a groove side 11b located on the outer periphery of the P type semiconductor layer 13 in a plan view and formed on the upper surface side of the first N type semiconductor layer 11, and a second N type semiconductor layer (N -) 14 formed on the first N type semiconductor layer 11 and disposed outside the groove side 11b in a plan view. An N-type channel stopper layer (N +) 14 having an impurity concentration higher than that of a first N-type semiconductor layer 11, a passivation layer 21 disposed in a groove side 11b, and a second N-type semiconductor layer (N +) 12 formed under the first N-type semiconductor layer 11 and having an impurity concentration higher than that of the first N-type semiconductor layer 11 are provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] To achieve high reliability, it is effective to provide a channel stopper CS on the periphery of the semiconductor chip, and the introduction of the channel stopper CS into a mesa diode requires cutting a mesa groove and then performing laser diffusion or the like (see Figure 2). This makes the process complicated and reduces productivity. Note that a related technology is described in Patent Document 1.

[0003] Furthermore, even if a channel stopper CS is formed in the groove by a photolithography process, the depth of the groove exceeds 100 μm, making it difficult to form a stable pattern of the channel stopper CS.

[0004] Therefore, there is a demand for a method for easily forming a channel stopper layer with a stable pattern, which does not require complicated processes and has good productivity. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-118585 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of various aspects of the present invention is to provide a semiconductor device and a method for manufacturing the same, which does not require complicated processes, has good productivity, and allows for easy formation of a channel stopper layer with a stable pattern. [Means for solving the problem]

[0007] Various aspects of the present invention are described below.

[0008] [1] A first N-type semiconductor layer; a P-type semiconductor layer disposed on the first N-type semiconductor layer; a groove located on the outer periphery of the P-type semiconductor layer in a plan view and formed on the upper surface side of the first N-type semiconductor layer; an N-type channel stopper layer formed on the first N-type semiconductor layer, arranged outside the trench in a plan view, and having an impurity concentration higher than that of the first N-type semiconductor layer; a passivation layer disposed within the groove; a second N-type semiconductor layer formed under the first N-type semiconductor layer and having a higher impurity concentration than the first N-type semiconductor layer; and the N-type channel stopper layer is separated from the P-type semiconductor layer, A semiconductor device, wherein an upper portion of the P-type semiconductor layer is located below a lower portion of the N-type channel stopper layer.

[0009] According to the semiconductor device of the above [1] of one aspect of the present invention, the N-type channel stopper layer is formed outside the trench, resulting in a mesa planar structure in which the trench is located within a single chip. Furthermore, because the upper portion of the P-type semiconductor layer serving as the anode layer is located below the lower portion of the N-type channel stopper layer and separated by the trench, the distance from the PN junction between the P-type semiconductor layer and the first N-type semiconductor layer to the N-type channel stopper layer can be increased. As a result, the peripheral invalid region can be narrowed in the horizontal direction, thereby reducing the chip area.

[0010] [2] A step (a) of introducing N-type impurities into the upper and lower surfaces of an N-type semiconductor wafer to form a first N-type semiconductor layer having a higher impurity concentration than the N-type semiconductor wafer on the upper surface side of the N-type semiconductor wafer, and to form a second N-type semiconductor layer having a higher impurity concentration than the N-type semiconductor wafer on the lower surface side of the N-type semiconductor wafer; a step (b1) of forming a first groove in the first N-type semiconductor layer and the N-type semiconductor wafer, the first groove being deeper than the thickness of the first N-type semiconductor layer, and leaving the first N-type semiconductor layer outside the first groove in a plan view; a step (b2) of introducing a P-type impurity into the semiconductor wafer from the bottom surface of the first trench and performing a heat treatment to form a P-type semiconductor layer on the upper surface side of the N-type semiconductor wafer and below the bottom surface of the first trench, forming an N-type channel stopper layer outside the first trench and on the outer periphery of the P-type semiconductor layer, and forming a third N-type semiconductor layer having an impurity concentration higher than that of the N-type semiconductor wafer on the lower surface side of the N-type semiconductor wafer; (c) forming a second groove between the N-type channel stopper layer and the P-type semiconductor layer to separate the N-type channel stopper layer and the P-type semiconductor layer; (d) forming a passivation layer in the second trench; 1. A method for manufacturing a semiconductor device, comprising:

[0011] According to the semiconductor device of [2] above, an N-type channel stopper layer is formed outside the first and second trenches. This structure prevents contact between adjacent chips, resulting in a mesa planar structure in which the second trenches are located within a single chip. Furthermore, because the second trench is shallower than that of a typical mesa diode, wafer warpage during manufacturing is suppressed, making the device applicable to large-diameter wafers of 6 inches or more. Furthermore, because the second trench separates the N-type semiconductor layer and the first N-type semiconductor layer, the distance from the PN junction to the N-type channel stopper layer can be increased. As a result, the peripheral ineffective region can be narrowed laterally, resulting in a smaller chip area. Furthermore, as in steps (a) and (b2), the N-type channel stopper layer is formed simultaneously with the third N-type semiconductor layer that serves as the cathode layer on the underside of the N-type semiconductor wafer, so that the photolithography process and impurity diffusion process for forming the N-type channel stopper layer are not required, thereby simplifying the process.

[0012] [3] In [2] above, A method for manufacturing a semiconductor device, wherein the second grooves in the step (c) are formed in the N-type semiconductor wafer.

[0013] According to the method for manufacturing a semiconductor device [3] above, which relates to one aspect of the present invention, the second groove is formed in the N-type semiconductor wafer, thereby reliably separating the N-type channel stopper layer and the P-type semiconductor layer.

[0014] [4] In [2] or [3] above, A method for manufacturing a semiconductor device, wherein the first groove in the step (b1) and the second groove in the step (c) are each formed by etching.

[0015] [5] In [2] or [3] above, 10. A method for manufacturing a semiconductor device, wherein the passivation layer in step (d) is a glass layer. [Effects of the Invention]

[0016] According to various aspects of the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same, in which a channel stopper layer having a stable pattern can be easily formed without complex processes and with good productivity. [Brief explanation of the drawings]

[0017] [Figure 1] 5(a) to 5(d) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a cross-sectional view showing a conventional mesa diode. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0019] (First embodiment) 1(a) to 1(d) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0020] As shown in Figure 1(a), an N-type semiconductor wafer (N - N-type impurities are introduced into the upper and lower surfaces of the N-type semiconductor wafer (N - ) 11 on the upper surface of the N-type semiconductor wafer (N - ) 11 has a higher impurity concentration than the first N-type semiconductor layer (N + ) 14a and an N-type semiconductor wafer (N - ) 11 on the bottom side of the N-type semiconductor wafer (N - ) 11 has a higher impurity concentration than the second N-type semiconductor layer (N + 1(a) to 1(d) show the cross section of one chip, and the N-type semiconductor wafer (N - ) 11 has a state in which a large number of chips shown in FIG. 1 are formed adjacent to each other.

[0021] Next, as shown in FIG. 1(b), a first N-type semiconductor layer (N + ) 14a and N-type semiconductor wafer (N - ) 11, a first N-type semiconductor layer (N + The first groove 11a is formed to be deeper than the thickness of the first N-type semiconductor layer (N + ) 14a remains (step (b1)). The first grooves 11a are preferably formed by etching.

[0022] In detail, the first N-type semiconductor layer (N + A resist pattern having an opening is formed on the first N-type semiconductor layer (N + ) 14a and N-type semiconductor wafer (N - The upper part of the first N-type semiconductor layer (N + ) 14a and N-type semiconductor wafer (N - ) 11, a first N-type semiconductor layer (N +The first groove 11a is formed to be deeper than the thickness of the first N-type semiconductor layer (N + )14a is left.

[0023] Next, the semiconductor wafer (N - ) 11 is doped with P-type impurities and then heat-treated. - A P-type semiconductor layer (anode P) 11 is formed on the upper surface side of the first groove 11a and below the bottom surface of the first groove 11a. + and a P-type semiconductor layer (anode P) 13 is formed outside the first groove 11a. + An N-type channel stopper layer (N + ) 14 and an N-type semiconductor wafer (N - ) 11 on the bottom side of the N-type semiconductor wafer (N - ) 11 has a higher impurity concentration than the third N-type semiconductor layer (cathode N + The layer 12 is formed (step (b2)).

[0024] Next, as shown in FIG. 1(c), an N-type channel stopper layer (N + ) 14 and a P-type semiconductor layer (P + ) 13, the second groove 11b is formed between the N-type channel stopper layer (N + ) 14 and a P-type semiconductor layer (P + The second grooves 11b are preferably formed by etching. The second grooves 11b are formed by separating the N-type semiconductor wafer (N - ) 11. This allows the N-type channel stopper layer (N + ) 14 and a P-type semiconductor layer (P + )13 can be reliably separated.

[0025] In detail, the N-type channel stopper layer (N + ) 14 and a P-type semiconductor layer (P + A resist pattern having an opening is formed on the N-type channel stopper layer (N + ) 14, the outer periphery of the P-type semiconductor layer (P+ ) 13 and the inner periphery of the N-type semiconductor wafer (N - ) 11 is wet-etched. + ) 14 and a P-type semiconductor layer (P + ) 13. As a result, a second groove 11b is formed between the N-type channel stopper layer (N + ) 14 and a P-type semiconductor layer (P + )13 is isolated.

[0026] Next, as shown in Fig. 1(d), a passivation layer 21 is formed in the second groove 11b (step (d)). The passivation layer 21 is preferably a glass layer.

[0027] Specifically, a glass paste is applied to the entire inner surface of the second groove 11b by printing, and the glass paste is then baked to form the glass passivation layer 21. Although the printing method is used in this embodiment, it is also possible to form the passivation film by electrodeposition.

[0028] In this embodiment, the anode P + On layer 13 and cathode N + Although no electrode layer is formed on each of the layers 12, the anode P + On layer 13 and cathode N + An electrode layer may be formed on each of the layers 12 .

[0029] According to this embodiment, an N-type channel stopper layer (N + ) 14, the second grooves 11b of adjacent chips do not come into contact with each other, and a mesa planar structure can be achieved in which the groove is located within a single chip. Furthermore, the second grooves 11b are formed shallower than those of ordinary mesa-type diodes, which reduces wafer warpage during manufacturing and makes it possible to apply the diodes to large-diameter wafers of 6 inches or more. In addition, because they are separated by the second grooves 11b, the anode P + layer 13 and the first N-type semiconductor layer (N - ) 11 from the PN junction with the N-type channel stopper layer (N+ ) 14 can be made wider. As a result, the peripheral invalid area can be narrowed in the horizontal direction, and the chip area can be reduced.

[0030] Furthermore, according to this embodiment, as in the above steps (a) and (b2), the N-type channel stopper layer 14 is formed on the cathode N of the lower surface of the N-type semiconductor wafer 11. + Since the N-type channel stopper layer 14 is formed simultaneously with the layer 12, the photolithography process and the impurity diffusion process for forming the N-type channel stopper layer 14 are not required. This simplifies the process. Therefore, the process is not complicated, productivity is good, and a channel stopper layer with a stable pattern can be easily formed.

[0031] (Second embodiment) FIG. 1D is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

[0032] As shown in FIG. 1(d), this semiconductor device has a first N-type semiconductor layer (N - ) 11, and a first N-type semiconductor layer (N - On top of 11 is a P-type semiconductor layer (anode P + In plan view, the anode P + The first N-type semiconductor layer (N - A groove 11b is formed on the upper surface of the anode P + The first N-type semiconductor layer (N - ) 11 is provided with an N-type channel stopper layer (N + ) 14 is formed, and an N-type channel stopper layer (N + ) 14 is a first N-type semiconductor layer (N - ) 11. In plan view, the N-type channel stopper layer (N + ) 14 is disposed outside the groove 11b, and the anode P + It is formed so as to surround the outer periphery of layer 13 .

[0033] A passivation layer 21 is disposed in the groove 11b. The passivation layer 21 is a glass layer. A first N-type semiconductor layer (N - ) 11 is provided with a first N-type semiconductor layer (N - ) 11 has a higher impurity concentration than the second N-type semiconductor layer (cathode N + An N-type channel stopper layer (N + ) 14 is a P-type semiconductor layer (P + ) 13. + The upper part of the N-type channel stopper layer (N + )It is recommended that it be located below the bottom of 14.

[0034] In this embodiment, the anode P + On layer 13 and cathode N + Although no electrode layer is formed on each of the layers 12, the anode P + On layer 13 and cathode N + An electrode layer may be formed on each of the layers 12 .

[0035] According to this embodiment, an N-type channel stopper layer (N + ) 14, a mesa planar structure can be formed in which the groove is located within a single chip. + The upper part of the layer 13 is an N-type channel stopper layer (N + ) 14 and separated by the groove 11b, + layer 13 and the first N-type semiconductor layer (N - ) 11 from the PN junction with the N-type channel stopper layer (N + ) 14 can be made wider. As a result, the peripheral invalid area can be narrowed in the horizontal direction, and the chip area can be reduced. [Explanation of symbols]

[0036] 11 First N-type semiconductor layer (N - ) 11a First Groove 11b Groove, second groove 12 Third N-type semiconductor layer (N + ), cathode N + layer 12a second N-type semiconductor layer (N + ) 13 P-type semiconductor layer (P + ), anode P + layer 14 N-type channel stopper layer (N + ) 14a First N-type semiconductor layer (N + ) 21 Passivation Layer

Claims

1. a first N-type semiconductor layer; a P-type semiconductor layer disposed on the first N-type semiconductor layer; a groove located on the outer periphery of the P-type semiconductor layer in a plan view and formed on the upper surface side of the first N-type semiconductor layer; an N-type channel stopper layer formed on the first N-type semiconductor layer, arranged outside the trench in a plan view, and having an impurity concentration higher than that of the first N-type semiconductor layer; a passivation layer disposed within the groove; a second N-type semiconductor layer formed under the first N-type semiconductor layer and having a higher impurity concentration than the first N-type semiconductor layer; and the N-type channel stopper layer is separated from the P-type semiconductor layer; The semiconductor device is characterized in that an upper portion of the P-type semiconductor layer is located below a lower portion of the N-type channel stopper layer.

2. (a) introducing N-type impurities into the upper and lower surfaces of an N-type semiconductor wafer to form a first N-type semiconductor layer having a higher impurity concentration than the N-type semiconductor wafer on the upper surface side of the N-type semiconductor wafer, and to form a second N-type semiconductor layer having a higher impurity concentration than the N-type semiconductor wafer on the lower surface side of the N-type semiconductor wafer; a step (b1) of forming a first groove in the first N-type semiconductor layer and the N-type semiconductor wafer, the first groove being deeper than the thickness of the first N-type semiconductor layer, and leaving the first N-type semiconductor layer outside the first groove in a plan view; a step (b2) of introducing a P-type impurity into the semiconductor wafer from the bottom surface of the first groove and performing a heat treatment to form a P-type semiconductor layer on the upper surface side of the N-type semiconductor wafer and below the bottom surface of the first groove, forming an N-type channel stopper layer outside the first groove and on the outer periphery of the P-type semiconductor layer, and forming a third N-type semiconductor layer having an impurity concentration higher than that of the N-type semiconductor wafer on the lower surface side of the N-type semiconductor wafer; (c) forming a second groove between the N-type channel stopper layer and the P-type semiconductor layer to separate the N-type channel stopper layer and the P-type semiconductor layer; (d) forming a passivation layer in the second trench; 1. A method for manufacturing a semiconductor device, comprising:

3. In claim 2, The method for manufacturing a semiconductor device, wherein the second groove in the step (c) is formed in the N-type semiconductor wafer.

4. In claim 2 or 3, A method for manufacturing a semiconductor device, wherein the first groove in the step (b1) and the second groove in the step (c) are each formed by etching.

5. In claim 2 or 3, 10. A method for manufacturing a semiconductor device, wherein the passivation layer in the step (d) is a glass layer.

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