Semiconductor device and method of manufacturing the same

Abstract

To provide a technique capable of suppressing reduction in breakdown voltage in a semiconductor device composed of a nitride semiconductor.SOLUTION: The n-type drift region 22, the n-type buried region 23, the n-type current spreading region 24, and the p-type region 25 are arranged in this order from the first main surface 10a toward the second main surface 10b. The current spreading region is in contact with the p-type region. A carrier concentration of an n-type impurity contained in the current spreading region is higher than a carrier concentration of an n-type impurity contained in the drift region. A carrier concentration of an n-type impurity contained in the n-type buried region is lower than a carrier concentration of an n-type impurity contained in the drift region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device made of a nitride semiconductor. This semiconductor device includes an n-type region with a high concentration of n-type impurities surrounding a p-type region called a body region or base region. This n-type region can function as a current spreading region. Therefore, a semiconductor device with an n-type region can have low on-resistance characteristics. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-40952 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, high-temperature heat treatment is required to activate p-type impurities contained in nitride semiconductors. For example, heat treatment at 1300°C or higher is required to activate magnesium, an example of a p-type impurity. FIG. 12 shows the concentration profiles of magnesium contained in a nitride semiconductor layer before and after heat treatment at 1400°C. As shown in FIG. 12, when magnesium is activated by high-temperature heat treatment, the magnesium thermally diffuses. In the semiconductor device of Patent Document 1, when heat treatment is performed to activate the p-type impurities contained in the p-type region, the p-type impurities diffuse into the n-type region surrounding the p-type region. To prevent the n-type region from disappearing due to this thermal diffusion of the p-type impurities, it is necessary to increase the concentration of the n-type impurities contained in the n-type region. However, increasing the concentration of the n-type impurities in the n-type region causes electric field concentration at the p-n junction between the p-type region and the n-type region, raising concerns about a decrease in the breakdown voltage of the semiconductor device.

[0005] The present specification provides a technique capable of suppressing a decrease in breakdown voltage in a semiconductor device made of a nitride semiconductor. [Means for solving the problem]

[0006] The semiconductor device disclosed herein may include a nitride semiconductor layer (10), a drain electrode (32) provided on a first major surface (10a) of the nitride semiconductor layer, and a source electrode (34) provided on a second major surface (10b) of the nitride semiconductor layer opposite the first major surface. The nitride semiconductor layer may have a portion in which an n-type drift region (22), an n-type buried region (23), an n-type current diffusion region (24), and a p-type region (25) are arranged in this order from the first major surface toward the second major surface. The current diffusion region and the p-type region may be in contact with each other. The carrier concentration of the n-type impurity contained in the current diffusion region may be higher than the carrier concentration of the n-type impurity contained in the drift region. The carrier concentration of the n-type impurity contained in the n-type buried region may be lower than the carrier concentration of the n-type impurity contained in the drift region.

[0007] In the semiconductor device, an n-type buried region with a low carrier concentration of n-type impurities is provided facing the p-n junction surface between the p-type region and the n-type region. With this configuration, electric field concentration at the p-n junction between the p-type region and the n-type region is alleviated, and a decrease in the breakdown voltage of the semiconductor device is suppressed.

[0008] The method for manufacturing a semiconductor device disclosed herein may include the steps of forming an n-type first epitaxial layer (14) on a nitride semiconductor substrate (12), forming a second epitaxial layer (16) on the first epitaxial layer, the second epitaxial layer having a higher concentration of n-type impurities than the first epitaxial layer, ion-implanting p-type impurities into a portion of an upper layer of the second epitaxial layer, and diffusing at least a portion of the p-type impurities into the first epitaxial layer using a heat treatment technique. In the second epitaxial layer, a p-type region may be formed in a region containing p-type impurities at a concentration higher than the concentration of n-type impurities, and a current diffusion region may be formed in a region excluding the p-type region. In the first epitaxial layer, an n-type buried region may be formed in a region containing the diffused p-type impurities and having a lower concentration of p-type impurities than the n-type impurities, and a drift region may be formed in a region excluding the n-type buried region.

[0009] According to the above manufacturing method, a drift region is formed in the first epitaxial layer by decreasing the concentration of n-type impurities contained in the first epitaxial layer, and a current spreading region is formed in the second epitaxial layer by increasing the concentration of n-type impurities contained in the second epitaxial layer. Furthermore, a p-type region is formed in a part of the second epitaxial layer by diffusing p-type impurities implanted into a part of the upper layer of the second epitaxial layer, and an n-type buried region is formed in a part of the first epitaxial layer. According to the above manufacturing method, it is possible to manufacture a semiconductor device having a part in which the drift region, n-type buried region, current spreading region, and p-type region are arranged in this order, and in which a decrease in breakdown voltage is suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view of a main part of an embodiment of a semiconductor device; [Figure 2] 2 is a schematic cross-sectional view of a main part of a modified example of the semiconductor device of FIG. 1. [Figure 3] 2 shows a partial manufacturing flow of a method for manufacturing the semiconductor device of FIG. [Figure 4] 2 is a schematic cross-sectional view of a main part in one manufacturing process of the manufacturing method of the semiconductor device of FIG. 1. [Figure 5] 2 is a schematic cross-sectional view of a main part in one manufacturing process of the manufacturing method of the semiconductor device of FIG. 1. [Figure 6] 2 is a schematic cross-sectional view of a main part in one manufacturing process of the manufacturing method of the semiconductor device of FIG. 1. [Figure 7] 2 is a schematic cross-sectional view of a main part in one manufacturing process of the manufacturing method of the semiconductor device of FIG. 1. [Figure 8] The impurity concentration profile corresponding to the line AA in FIG. 6 is shown schematically. [Figure 9] 2 is a schematic cross-sectional view of a main part of a modified example of the semiconductor device of FIG. 1. [Figure 10] 10A and 10B show schematic views of impurity concentration profiles of the semiconductor device of FIG. [Figure 11] FIG. 10 is a cross-sectional view of a main part of another embodiment of a semiconductor device; [Figure 12] 1 shows the concentration profiles of magnesium contained in the nitride semiconductor layer before and after heat treatment at 1400° C. DETAILED DESCRIPTION OF THE INVENTION

[0011] The semiconductor device and the manufacturing method thereof disclosed in this specification will be described below with reference to the drawings. In each drawing, common components may be designated by a reference numeral only for one of the components.

[0012] 1, the semiconductor device 1 includes a nitride semiconductor layer 10 made of a nitride semiconductor. The nitride semiconductor layer 10 is a stack of a nitride semiconductor substrate 12, a first epitaxial layer 14, and a second epitaxial layer 16, and has a first main surface 10a (i.e., a lower surface) and a second main surface (i.e., an upper surface). The semiconductor device 1 further includes a drain electrode 32 provided to cover the first main surface 10a of the nitride semiconductor layer 10, a source electrode 34 provided to cover a portion of the second main surface 10b of the nitride semiconductor layer 10, and a planar-type insulated gate portion 40 provided to cover a portion of the second main surface 10b of the nitride semiconductor layer 10.

[0013] The nitride semiconductor substrate 12 is not particularly limited, and may be, for example, a gallium nitride substrate (i.e., a GaN substrate). As will be described later, the nitride semiconductor substrate 12 is a base substrate for growing crystals of the first epitaxial layer 14. The nitride semiconductor substrate 12 also contains a high concentration of n-type impurities and functions as the drain region 21. The n-type impurity is not particularly limited, and may be, for example, silicon. The drain region 21 is in ohmic contact with the drain electrode 32.

[0014] The first epitaxial layer 14 is a gallium nitride epitaxial layer formed by crystal growth from the upper surface of the nitride semiconductor substrate 12, and includes a drift region 22 and an n-type buried region 23. The first epitaxial layer 14 is formed so as to contain n-type impurities during crystal growth. The n-type impurities are not particularly limited, but may be, for example, silicon.

[0015] The drift region 22 is an n-type region formed in the first epitaxial layer 14 except for the n-type buried region 23, and contains a certain concentration of n-type impurities introduced during crystal growth.

[0016] The n-type buried region 23 is an n-type region formed in a region including a part of the surface of the first epitaxial layer 14 that contacts the second epitaxial layer 16, and as will be described later, contains p-type impurities diffused from the p-type region 25. Therefore, the carrier concentration of the n-type impurities in the n-type buried region 23 is the concentration obtained by subtracting the concentration of the p-type impurities diffused into the n-type buried region 23 from the concentration of the n-type impurities contained in the first epitaxial layer 14.

[0017] The second epitaxial layer 16 is a gallium nitride epitaxial layer formed by crystal growth on the upper surface of the first epitaxial layer 14, and includes a current spreading region 24, a p-type region 25, and a source region 26. The second epitaxial layer 16 is formed so as to contain n-type impurities during crystal growth. The n-type impurities are not particularly limited, but may be, for example, silicon.

[0018] The current spreading region 24 is an n-type region formed in a portion of the second epitaxial layer 16 excluding the p-type region 25 and the source region 26. The n-type impurity carrier concentration of the current spreading region 24 is higher than that of the drift region 22. The current spreading region 24 is in contact with the bottom and side surfaces of the p-type region 25 and surrounds the p-type region 25. A portion of the current spreading region 24 adjacent to the side surfaces of the p-type region 25, i.e., a portion of the current spreading region 24 located between adjacent p-type regions 25, is also referred to as a JFET region and is also formed in a position exposed to the second main surface 10b of the nitride semiconductor layer 10. The portion of the current spreading region 24 in contact with the bottom surface of the p-type region 25, i.e., a portion of the current spreading region 24 located between the n-type buried region 23 and the p-type region 25, contains p-type impurities diffused from the p-type region 25, as described below. Therefore, the carrier concentration of the n-type impurity contained in the part of the current spreading region 24 in contact with the bottom surface of the p-type region 25 is the concentration obtained by subtracting the concentration of the p-type impurity diffused in the part of the current spreading region 24 from the concentration of the n-type impurity contained in the second epitaxial layer 16.

[0019] The p-type region 25 is a p-type region formed in a region including a part of the second main surface 10b of the nitride semiconductor layer 10, and is formed by ion implantation of p-type impurities into the upper layer portion of the second epitaxial layer 16, as will be described later. The p-type impurity is not particularly limited, but may be magnesium, for example. The p-type region 25 is in ohmic contact with the source electrode 34 at a portion exposed at the second main surface 10b of the nitride semiconductor layer 10.

[0020] The source region 26 is an n-type region formed in a region including a portion of the second main surface 10b of the nitride semiconductor layer 10, and is formed by ion-implanting n-type impurities into the upper portion of the second epitaxial layer 16, as described below. The n-type impurity is not particularly limited, but may be silicon, for example. The source region 26 is separated from the current spreading region 24 by the p-type region 25. The source region 26 is in ohmic contact with the source electrode 34 at a portion exposed at the second main surface 10b of the nitride semiconductor layer 10.

[0021] The insulated gate portion 40 is provided so as to be in contact with a part of the second main surface 10b of the nitride semiconductor layer 10, and has a gate insulating film 42 and a gate electrode 44. The gate insulating film 42 is disposed between the nitride semiconductor layer 10 and the gate electrode 44, and insulates the gate electrode 44 from the nitride semiconductor layer 10. The gate electrode 44 faces a portion of the p-type region 25 that separates the current spreading region 24 and the source region 26, with the gate insulating film 42 interposed therebetween.

[0022] Next, the operation of the semiconductor device 1 will be described. During use, a voltage that makes the drain electrode 32 more positive than the source electrode 34 is applied between the drain electrode 32 and the source electrode 34. When a voltage higher than the gate threshold voltage is applied to the gate electrode 44, an inversion layer is formed in the p-type region 25 separating the current diffusion region 24 and the source region 26, i.e., in the channel region. Electrons flow from the source region 26 into the current diffusion region 24 through the inversion layer formed in the channel region. The electrons that flow into the current diffusion region 24 flow vertically between the p-type regions 25 and laterally in the region adjacent to the bottom surface of the p-type region 25. The current diffusion region 24 surrounding the p-type region 25 thus ensures a wide current path, thereby enabling the semiconductor device 1 to have low on-resistance characteristics. When a voltage lower than the gate threshold voltage is applied to the gate electrode 44, the inversion layer disappears, and the semiconductor device 1 turns off. In this way, the semiconductor device 1 can perform a switching operation that controls the current between the drain electrode 32 and the source electrode 34 based on the voltage applied to the gate electrode 44.

[0023] When the semiconductor device 1 is turned off, a depletion layer extends from the pn junction between the current spreading region 24 and the p-type region 25, generating an electric field in the depletion layer in response to the voltage applied between the drain electrode 32 and the source electrode 34. As shown in FIG. 1 , when the semiconductor device 1 is turned off, the electric field is most concentrated at the corner 50 of the p-type region 25. This electric field concentration is thought to be caused by the equipotential lines bending upward in a convex shape toward a portion of the current spreading region 24 located between adjacent p-type regions 25, resulting in closer spacing of the equipotential lines at the corner 50 of the p-type region 25. For example, when the n-type buried region 23 is not provided, the bending of the equipotential lines is greater. On the other hand, in the semiconductor device 1 with the n-type buried region 23, the convex bending of the equipotential lines is suppressed compared to when the n-type buried region 23 is not provided, thereby mitigating the electric field concentration at the corner 50 of the p-type region 25. This suppresses a decrease in breakdown voltage in the semiconductor device 1.

[0024] As shown in FIG. 2 , the n-type buried region 23 may extend to a position inside the side surface of the p-type region 25. More specifically, when the nitride semiconductor layer 10 is viewed in plan, the n-type buried region 23 may extend beyond the pn junction surface at the side surface of the current spreading region 24 and the p-type region 25 and may be arranged so as to overlap with the current spreading region 24 located between adjacent p-type regions 25. The n-type buried region 23 configured in this manner can effectively alleviate electric field concentration at the corner portion 50 of the p-type region 25. Note that the n-type buried region 23 does not have to be arranged continuously, and may be divided by the drift region 22 at least in a portion below the current spreading region 24 located between adjacent p-type regions 25. Because the low-concentration n-type buried region 23 does not completely block the current path, an increase in the on-resistance of the semiconductor device 1 can be suppressed.

[0025] (Method of manufacturing semiconductor device 1) 3 is a manufacturing flow showing a flow of some of the steps for manufacturing the semiconductor device 1. FIGS. 4 to 7 are cross-sectional views of the main part in the manufacturing process corresponding to the manufacturing flow of FIG.

[0026] 4, a crystal growth technique is used to grow a first epitaxial layer 14 on the upper surface of a nitride semiconductor substrate 12, and then a second epitaxial layer 16 is grown on the upper surface of the first epitaxial layer 14, thereby forming a stack of the nitride semiconductor substrate 12, the first epitaxial layer 14, and the second epitaxial layer 16 (Step S1 in FIG. 3). The first epitaxial layer 14 is grown to contain an n-type impurity, and the concentration of the n-type impurity is adjusted to a concentration desired for the drift region 22. The second epitaxial layer 16 is grown to contain a higher concentration of n-type impurity than the first epitaxial layer 14, and the concentration of the n-type impurity is adjusted to a concentration desired for the current spreading region 24.

[0027] 5, p-type impurities and n-type impurities are implanted into predetermined regions in the upper part of the second epitaxial layer 16 using ion implantation technology to form a p-type region 25 and a source region 26 (step S2 in FIG. 3). The order in which these semiconductor regions 25 and 26 are formed is not particularly limited.

[0028] Next, as shown in FIG. 6, a heat treatment is performed to activate these semiconductor regions 25 and 26 (step S3 in FIG. 3). The heat treatment temperature is not particularly limited, but may be, for example, 1300°C or higher, 1350°C or higher, or 1400°C or higher. Such high-temperature heat treatment can effectively activate the implanted impurities, particularly the p-type impurity magnesium. The higher the heat treatment temperature, the more effectively the p-type impurity magnesium can be activated. Furthermore, some of the p-type impurities diffuse from the second epitaxial layer 16 to the first epitaxial layer 14, forming an n-type buried region 23 in the upper portion of the first epitaxial layer 14. FIG. 8 shows an impurity concentration profile along line AA in FIG. 6. In this way, part of the carrier concentration of the n-type impurity contained in the first epitaxial layer 14 is offset by the p-type impurity, forming the n-type buried region 23 in the first epitaxial layer 14.

[0029] 7, a gate insulating film 42 is formed on the second epitaxial layer 16 (Step S4 in FIG. 3). Specifically, using a vapor deposition technique, the gate insulating film 42 is formed so as to cover the upper surface of the second epitaxial layer 16. Next, using a known manufacturing technique, the drain electrode 32, the source electrode 34, and the gate electrode 44 are formed (Step S5 in FIG. 3), thereby manufacturing the semiconductor device 1 shown in FIG.

[0030] According to the above manufacturing method, a drift region 22 is formed in the first epitaxial layer 14 by reducing the concentration of n-type impurities contained in the first epitaxial layer 14, and a current spreading region 24 is formed in the second epitaxial layer 16 by increasing the concentration of n-type impurities contained in the second epitaxial layer 16. Furthermore, a p-type region 25 is formed in a part of the second epitaxial layer 16 by diffusing p-type impurities implanted into a part of the surface of the second epitaxial layer 16, and an n-type buried region 23 is formed in a part of the first epitaxial layer 14. According to the above manufacturing method, it is possible to manufacture a semiconductor device 1 having a part where the drift region 22, the n-type buried region 23, the current spreading region 24, and the p-type region 25 are arranged in this order, and in which a decrease in breakdown voltage is suppressed.

[0031] As shown in FIG. 9 , a p-type buried region 27 may be provided between the n-type buried region 23 and the current diffusion region 24. As shown in FIG. 10 , the p-type buried region 27 is a region in which the concentration of p-type impurities diffused from the p-type region 25 is higher than the concentration of n-type impurities contained in the first epitaxial layer 14. The p-type buried region 27 can be formed using the same process as the manufacturing method described above by adjusting the concentration of the n-type impurities contained in the first epitaxial layer 14, the concentration and depth of the p-type impurities ion-implanted into the second epitaxial layer 16, the heat treatment conditions, and the like. The provision of such a p-type buried region 27 can more effectively alleviate electric field concentration at the corners of the p-type region 25. It is desirable that the thickness T1 of the p-type buried region 27 be sufficiently thin. For example, the thickness T1 of the p-type buried region 27 may be smaller than the thickness T2 of the n-type buried region 23. In this way, if the thickness T1 of the p-type buried region 27 is sufficiently thin, it is possible to alleviate the electric field concentration at the corners of the p-type region 25 while suppressing an increase in the on-resistance.

[0032] Although the technology disclosed in this specification has been described above with reference to a semiconductor device 1 including a planar-type insulated gate portion 40, the technology disclosed in this specification is also applicable to a JFET-type semiconductor device 2, as shown in Fig. 11. Note that in Fig. 11, components having the same functions as those in the semiconductor device 1 of Fig. 1 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0033] In the semiconductor device 2, the gate electrode 44 is in contact with the p-type region 25, and the source region 26 is located between adjacent p-type regions 25 and in contact with the current diffusion region 24. In the semiconductor device 2, the width of the depletion layer extending into the current diffusion region 24 located between adjacent p-type regions 25 is controlled in accordance with the voltage applied to the gate electrode 44, thereby controlling the current between the drain electrode 32 and the source electrode 34. In the semiconductor device 2, the n-type buried region 23 is also provided, thereby mitigating electric field concentration at the corners of the p-type region 25.

[0034] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0035] 1, 2: semiconductor device, 10: nitride semiconductor layer, 12: nitride semiconductor substrate, 14: first epitaxial layer, 16: second epitaxial layer, 21: drain region, 22: drift region, 23: n-type buried region, 24: current diffusion region, 25: p-type region, 26: source region, 32: drain electrode, 34: source electrode, 40: insulated gate portion, 42: gate insulating film, 44: gate electrode

Claims

1. A nitride semiconductor layer (10), a drain electrode (32) provided on a first major surface (10a) of the nitride semiconductor layer; a source electrode (34) provided on a second major surface (10b) of the nitride semiconductor layer opposite to the first major surface, the nitride semiconductor layer has a portion in which an n-type drift region (22), an n-type buried region (23), an n-type current diffusion region (24), and a p-type region (25) are arranged in this order from the first main surface toward the second main surface, the current spreading region and the p-type region are in contact with each other, a carrier concentration of n-type impurities contained in the current diffusion region is higher than a carrier concentration of n-type impurities contained in the drift region; a carrier concentration of the n-type impurity contained in the n-type buried region is lower than a carrier concentration of the n-type impurity contained in the drift region.

2. 2. The semiconductor device according to claim 1, wherein said current spreading region surrounds said p-type region.

3. an insulated gate portion provided on the second main surface of the nitride semiconductor layer, the nitride semiconductor layer further includes an n-type source region separated from the current spreading region by the p-type region; 3. The semiconductor device according to claim 2, wherein said insulated gate portion faces a portion of said p-type region that separates said source region and said current diffusion region.

4. The nitride semiconductor layer has a first epitaxial layer (14) and a second epitaxial layer (16) stacked on the first epitaxial layer, the drift region and the n-type buried region are included in the first epitaxial layer; 2. The semiconductor device according to claim 1, wherein said current spreading region and said p-type region are included in said second epitaxial layer.

5. 5. The semiconductor device according to claim 1, wherein the nitride semiconductor layer further comprises a p-type buried region (27) provided between the n-type buried region and the current spreading region.

6. forming an n-type first epitaxial layer (14) on a nitride semiconductor substrate (12); forming a second epitaxial layer (16) on the first epitaxial layer, the second epitaxial layer having a higher concentration of n-type impurities than the first epitaxial layer; ion-implanting a p-type impurity into a portion of an upper layer portion of the second epitaxial layer; and diffusing at least a portion of the p-type impurity into the first epitaxial layer using a heat treatment technique, In the second epitaxial layer, a p-type region is formed in a region containing the p-type impurity at a concentration higher than a concentration of the n-type impurity, and a current spreading region is formed in a region excluding the p-type region; a first epitaxial layer including a first epitaxial layer and a second epitaxial layer having a first epitaxial layer and a second epitaxial layer and a second epitaxial layer having a second epitaxial layer and a second epitaxial layer and a third epitaxial layer and a fourth epitaxial layer, the third epitaxial layer including a first epitaxial layer and a second epitaxial layer and a fourth epitaxial layer, the third epitaxial layer including a first epitaxial layer and a second epitaxial layer, the fourth ... second epi

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