Data receiving system, display device, data receiving circuit, and data receiving method

Abstract

To provide a data reception system, a display device, a data reception circuit, and a data reception method for preventing data from being missed.SOLUTION: The data receiving system 100 includes a clock source 30 for generating an operation clock, a data transmission circuit 20 for transmitting read data, and a data receiving circuit 10. The data receiving circuit 10 includes a recording unit 12 for recording the read data transmitted from the data transmission circuit 20, a storage unit 14 for storing predetermined data in advance, a comparison unit 16 for comparing the predetermined data stored in the storage unit 14 with the retrieved data recorded in the recording unit 12, and a control unit 18 for selecting a retrieval clock, which is a timing for retrieving the read data from the data transmission circuit, from among the operation clocks generated by the clock source, while maintaining the phase of the operation clock, based on a comparison result between the predetermined data and the retrieved data by the comparison unit 16.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a data receiving system, a display device, a data receiving circuit, and a data receiving method. [Background technology]

[0002] Display devices with multiple display elements arranged in a matrix are used for railway signs, road signs, etc. Such display devices are equipped with a memory that stores correction data to cancel out brightness variations among the display elements. The control IC on the master side reads the correction data from the memory on the slave side and controls the lighting of the display unit.

[0003] Such display devices use dynamic lighting and high-speed scanning to improve display quality, which means that memory readout is limited to the lighting time per line.

[0004] However, in conventional data receiving circuits, it takes a long time to determine the optimal data acquisition timing, which may make it incompatible with faster dynamic scanning. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-10042 Summary of the Invention [Problem to be solved by the invention]

[0006] One object of the present disclosure is to provide a data receiving system, a display device, a data receiving circuit, and a data receiving method that prevent data loss. Another object of the present disclosure is to provide a data receiving system, a display device, a data receiving circuit, and a data receiving method that improve the reliability of display. Note that the description of these objects and objects of the present disclosure does not preclude the existence of other objects and objects. Furthermore, it is not necessary for one embodiment of the present disclosure to solve all of these objects. Furthermore, other objects can be extracted from the description of the specification, drawings, and claims of the present disclosure. [Means for solving the problem]

[0007] A data receiving system according to one embodiment of the present disclosure comprises a data receiving circuit including a clock source that generates an operating clock, a data sending circuit that sends read data, a recording unit that records the read data sent from the data sending circuit, a storage unit that stores predetermined data in advance, a comparison unit that compares the predetermined data stored in the storage unit with captured data recorded in the recording unit, and a control unit that, based on the comparison result of the comparison unit between the predetermined data and the captured data, selects an capture clock from the operating clocks generated by the clock source that is the timing for capturing the read data from the data sending circuit while maintaining the phase of the operating clock.

[0008] A display device according to another aspect of the present disclosure is a display device comprising the above-described data receiving system and a display unit composed of a plurality of light-emitting elements, wherein the data receiving circuit converts the specified data stored in the storage unit into display data to be displayed on the display unit, and the plurality of light-emitting elements are configured to have their brightness controlled by the data transmission circuit.

[0009] In addition, a data receiving circuit according to another aspect of the present disclosure is a data receiving circuit for capturing read data sent from a data sending circuit based on an operating clock generated by a clock source, and is provided with a recording unit for recording the captured read data, a storage unit for pre-saving predetermined data, a comparison unit for comparing the predetermined data saved in the storage unit with the captured data recorded in the recording unit, and a control unit for selecting an capture clock from the operating clocks that is the timing for capturing the read data, while maintaining the phase of the operating clock, based on the comparison result between the predetermined data and the captured data by the comparison unit.

[0010] Furthermore, a data receiving method according to another aspect of the present disclosure is a data receiving method in which read data sent from a data sending circuit is captured by a data receiving circuit based on an operating clock generated by a clock source, and includes the steps of: a step in which a control unit of the data receiving circuit generates an capture enable signal; a step in which the data receiving circuit captures the read data from the data sending circuit based on the capture enable signal generated by the control unit and records the captured capture data in a recording unit; a step in which a comparison unit of the data receiving circuit compares predetermined data stored in advance in a storage unit with the capture data recorded in the recording unit, and based on the comparison result, the control unit selects an capture clock from the operating clock that is the timing for capturing the read data.

[0011] Furthermore, a data receiving method according to another aspect of the present disclosure is a data receiving method in which read data transmitted from a data transmission circuit is captured by a data receiving circuit based on an operating clock generated by a clock source, and includes the steps of: a control unit of the data receiving circuit generating a first temporary capture enable; the data receiving circuit provisionally capturing the read data from the data transmission circuit based on the first temporary capture enable generated by the control unit, and recording the captured temporary capture data in a recording unit; a comparison unit of the data receiving circuit comparing predetermined data previously stored in a storage unit with the temporary capture data recorded in the recording unit, and based on the comparison result, the control unit selecting a capture clock from the operating clock that is the timing for capturing the read data; a control unit generating a final capture enable based on the capture clock selected by the control unit; and the data receiving circuit capturing the read data from the data transmission circuit based on the final capture enable generated by the control unit, and recording the captured final capture data in the recording unit. [Effects of the Invention]

[0012] According to the data receiving system of the above embodiment, it is possible to select an appropriate acquisition clock from among a plurality of operation clocks, thereby preventing read data from being missed. In addition, it is possible to shorten the time required to determine the appropriate timing for acquiring read data, thereby realizing high-speed dynamic scanning.

[0013] Furthermore, according to the data display device of the above aspect, when dynamic scanning is performed on the display device that displays the display data stored in the data receiving circuit, it is possible to avoid missing data and to speed up the display.

[0014] Furthermore, with the data receiving circuit and data receiving method according to the above aspects, it is possible to select an appropriate capture clock from among multiple operating clocks, thereby preventing read data from being missed. Furthermore, it is possible to shorten the time required to determine the appropriate timing for capturing read data, thereby achieving faster dynamic scanning. In particular, by performing dummy communication using the first temporary capture enable before normal communication using this capture enable, it is possible to deal with changes in signal propagation delay over time by updating the selected capture clock position accordingly. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a block diagram showing a display device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing the data receiving system of FIG. 1. [Figure 3] 3 is a timing chart showing details of the propagation delay time in FIG. 2. [Figure 4] FIG. 4A is a timing chart showing the case where the propagation delay time is small, and FIG. 4B is a timing chart showing the case where the propagation delay time is large. [Figure 5] 10 is a timing chart showing how read data is taken in when the difference in propagation delay time is small. [Figure 6] 10 is a timing chart showing how read data is taken in when there is a large difference in propagation delay time. [Figure 7] 10 is a timing chart showing how the timing of capturing data is changed in accordance with the propagation delay time. [Figure 8] FIG. 3 is a block diagram showing details of the data receiving circuit of FIG. 2. [Figure 9] FIG. 10 is a block diagram showing a data receiving circuit according to a modified example. [Figure 10] 3 is a flowchart showing a data receiving method according to the first embodiment. [Figure 11] 10 is a flowchart showing a data receiving method according to a third embodiment. [Figure 12] 4 is a timing chart of dummy communication in the data receiving circuit according to the first embodiment. [Figure 13] 4 is a timing chart of normal communication in the data receiving circuit according to the first embodiment. [Figure 14] FIG. 14A is a timing chart showing an example of changing the edge, and FIG. 14B is a timing chart showing an example of changing the phase. [Figure 15] 10 is a timing chart of dummy communication in the data receiving circuit according to the second embodiment. [Figure 16] 10 is a timing chart of normal communication in the data receiving circuit according to the second embodiment. [Figure 17] 10 is a timing chart of dummy communication in the data receiving circuit according to the third embodiment. [Figure 18] 10 is a timing chart of normal communication in the data receiving circuit according to the third embodiment. [Figure 19] 19 is a timing chart showing details of normal communication in the data reception method of FIG. 18. [Figure 20] 19 is a timing chart showing details of normal communication in the data reception method of FIG. 18. DETAILED DESCRIPTION OF THE INVENTION

[0016] The present invention will be described in more detail below with reference to the drawings. In the following description, terms indicating specific directions or positions (e.g., "upper," "lower," and other terms including these terms) will be used as necessary. However, the use of these terms is intended to facilitate understanding of the invention with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention. Furthermore, parts that appear with the same reference numerals in multiple drawings indicate the same or equivalent parts or members.

[0017] Furthermore, the embodiments shown below are specific examples of the technical concept of the present invention and are not intended to limit the present invention thereto. Furthermore, unless otherwise specified, the dimensions, materials, shapes, relative positions, etc. of the components described below are intended as examples and are not intended to limit the scope of the present invention thereto. Furthermore, the content described in one embodiment or example can also be applied to other embodiments or examples. Furthermore, the sizes and positional relationships of components shown in the drawings may be exaggerated for clarity of explanation. (display device)

[0018] The display device according to the present disclosure can be used for traffic information signs, character display boards, displays, etc. Below, an example in which the display device is applied to a traffic information display board will be described, but the present disclosure is not limited to this. [Embodiment 1]

[0019] FIG. 1 shows a block diagram of a display device 100 according to a first embodiment. The display device 100 shown in this figure includes a display unit 2 and a data receiving system 100. The display unit 2 is composed of a plurality of light-emitting elements 1. A large display, a liquid crystal monitor, or the like can be used as the display unit 2. The data receiving system 100 transmits display data, such as still images and videos, to the display unit 2. The display device 100 performs dynamic lighting of the display unit 2. During dynamic lighting, it is preferable to perform a high-speed scanning operation to improve display quality. For example, the dynamic scanning speed is set to 240 Hz to 960 Hz. This makes it possible to display, for example, smoothly flowing characters. (Data Receiving System 100)

[0020] A block diagram of the data receiving system 100 is shown in FIG. 2. The data receiving system 100 shown in this figure includes a clock source 30, a data transmission circuit 20, and a data receiving circuit 10. In this data receiving system 100, the data transmission circuit 20 acts as a slave, and the data receiving circuit 10 acts as a master. The data receiving circuit 10 controls the lighting of the display unit 2. Meanwhile, the clock source 30 generates an operation clock and sends it to the data receiving circuit 10. In accordance with the operation clock, the data receiving circuit 10 receives correction data from the data transmission circuit 20 for correcting variations in brightness among the light-emitting elements 1 that constitute the display device 100. The data receiving circuit 10 controls the lighting of the light-emitting elements 1, such as their brightness, in accordance with the lighting control data. The data receiving circuit 10 also holds correction data for correcting variations in brightness among the light-emitting elements 1 that constitute the display device 100. Meanwhile, the clock source 30 generates an operation clock and sends it to the data receiving circuit 10. Correction data is sent from the data receiving circuit 10 to the data sending circuit 20 in accordance with the operating clock, thereby correcting the display content of the display unit 2. The sending and receiving of this data is performed via a shift register or the like.

[0021] Here, we will explain the data exchanged between the master data receiving circuit 10 and the slave data sending circuit 20. As shown in Figure 2, input data from the data receiving circuit 10 is read data, and output data is write data. The master data receiving circuit 10 uses the write data and control clock to input a read command and a starting address to the slave data sending circuit 20. After that, as the data receiving circuit 10 continues to receive the control clock, the data sending circuit 20 returns the memory contents from the starting address for the number of control clocks to the data receiving circuit 10 as read data.

[0022] Display devices that perform dynamic lighting perform scanning at high speeds to improve display quality. Therefore, memory readout is limited to the lighting time per line. However, conventional data reception systems require dummy communications for the number of patterns with shifted clock phases, which lengthens the time required to determine the optimal data capture timing, making it incompatible with faster dynamic scanning. Specifically, the signal propagation delay time T varies depending on the distance between the data reception circuit and the data transmission circuit, the operating voltage, the ambient temperature, and other factors. As a result, the timing at which the data reception circuit captures read data from the data transmission circuit is not constant and varies depending on the environment. As a result, the scanning speed must be slowed down to prevent read data from being missed even when the environment changes. Here, the propagation delay time T is the time from a data request to a response. This will be described in detail with reference to Figures 2 to 6. (propagation delay time)

[0023] 2 shows how the data receiving circuit 10 sends data such as correction data to the data sending circuit 20. As shown in this figure, a propagation delay time T occurs from the time the data receiving circuit 10 sends the control clock and write data to the data sending circuit 20 until it receives the read data from the data sending circuit 20. This propagation delay time T is the sum of the time t1 for the control clock to reach the data sending circuit 20 from the data receiving circuit 10, the time t2 for the data sending circuit 20 to output read data in response to the input of the control clock, and the time t3 for the read data to reach the data receiving circuit 10 from the data sending circuit 20.

[0024] This process will be explained using the timing chart in Figure 3. The data receiving circuit 10 generates a control clock based on the operating clock. As an example, the following case is shown: read data D0 is read using a control clock that is a quarter of the operating clock. The control clock arrives from the data receiving circuit 10 to the data sending circuit 20, and the data receiving circuit 10 retrieves the read data D0 returned to the data receiving circuit 10 according to the operating clock. This procedure will be explained in order. First, the data receiving circuit 10 initiates a request to the data sending circuit 20. That is, it outputs a control clock to the data sending circuit 20 in response to the rising edge of the operating clock. The data sending circuit 20 receives this control clock t1 after the request. Upon receiving the control clock, the data sending circuit 20 outputs read data D0 t2 after the request. The data receiving circuit 10 receives this read data D0 t3 after the request. This timing is the time at which the data receiving circuit 10 receives a response. The sum of the times t1, t2, and t3 from the request to the response is the propagation delay time T. The period during which the data receiving circuit 10 can receive the read data D0 is the period of the read data D0 (master input) shown at the bottom of FIG.

[0025] As shown in Figures 4A and 4B, this propagation delay time T varies depending on conditions, which can result in read data being dropped. Specifically, if the maximum propagation delay time T is TMax and the minimum propagation delay time T is TMin, a large difference between TMax and TMin can result in read data being dropped. The timing at which the data receiving circuit 10 can capture read data D0 is the period during which the master input D0 exists, as shown in Figures 4A and 4B. Therefore, if the master input D0 periods no longer overlap due to fluctuations in the propagation delay time T, the data receiving circuit 10 will be unable to capture read data D0. This situation will be explained with reference to Figures 5 and 6. For simplicity's sake, the master output and slave output have been omitted from each figure, as compared to Figure 3. Figure 5 shows the case where the difference between TMax and TMin is small, while Figure 6 shows the case where the difference between TMax and TMin is large. In Figures 5 and 6, the timing at which read data D0 can be captured at the rising edge of the operating clock is indicated by thin dashed lines. As shown in FIG. 5, when the difference in propagation delay time TMax-TMin is small, there is an overlapping portion (shown by a thick dashed line in FIG. 5) between the clock position at which read data D0 with propagation delay time TMin can be acquired and the clock position at which read data D0 with propagation delay time TMax can be acquired. This allows the data receiving circuit 10 to acquire the read data at the specified timing regardless of whether the propagation delay time is TMax or TMin. On the other hand, as shown in FIG. 6, when the difference in propagation delay time TMax-TMin is large, there is no overlap between the clock position at which TMin data can be acquired and the clock position at which TMax data can be acquired. This results in a failure to acquire the read data, and the intended display data cannot be displayed on the display unit 2. As such, in the conventional data receiving circuit 10, the timing at which read data is acquired is constant. Therefore, when the difference in propagation delay time TMax-TMin is large, the circuit is unable to absorb the fluctuation, resulting in a failure to acquire the read data.

[0026] In contrast, in this embodiment, the data capture timing is changed according to the propagation delay time T, thereby enabling reliable data capture regardless of fluctuations in the propagation delay time T, thereby improving operational stability and reliability. Specifically, as shown in FIG. 7, when the propagation delay time is TMin, data is captured at the position indicated by the dashed line on the left side of the rising edge of the operating clock. On the other hand, when the propagation delay time is TMax, data is captured at the position indicated by the dashed line on the right side. In this way, by varying the data capture timing according to the propagation delay time rather than fixing it, read data can be stably read without being affected by factors such as differences in environmental temperature, thereby improving reliability. This will be described in detail below. (Data receiving circuit 10)

[0027] The details of the data receiving circuit 10 of FIG. 2 are shown in the block diagram of FIG. 8. The data receiving circuit 10 shown in this diagram comprises a recording unit 12, a storage unit 14, a comparison unit 16, and a control unit 18. As shown in this diagram, the master-side data receiving circuit 10 captures read data output from the slave-side data transmission circuit 20 using the recording unit 12. The storage unit 14 also stores predetermined data in advance. The comparison unit 16 compares the predetermined data in the storage unit 14 with the captured data captured in the recording unit 12. Meanwhile, the control unit 18 changes the edge of the capture clock for the read data based on the comparison result between the predetermined data and the captured data. (Capture clock)

[0028] Here, the capture clock refers to the operational clock generated by the clock source 30 that is the timing for capturing read data from the data transmission circuit 20 into the recording unit 12. The control unit 18 can avoid missing read data by selecting an appropriate capture clock from multiple operational clocks according to capture data that varies depending on propagation delay time while maintaining the phase of the operational clock. In addition, the time required to determine the appropriate timing for capturing read data can be shortened, thereby achieving faster dynamic scanning. (clock source 30)

[0029] The clock source 30 is a component for generating an operating clock. The data receiving circuit 10 determines the operating timing of the comparison unit 16, recording unit 12, and control unit 18 in accordance with the operating clock from the clock source 30. Such a clock source 30 can be configured as an oscillator. In addition to directly generating the operating clock using an oscillator, the clock of the oscillator (e.g., 20 MHz) may be converted into a different clock (e.g., 90 MHz) using a PLL circuit or the like to use as the operating clock. The PLL circuit may be incorporated into the oscillator or the data receiving circuit 10. A data receiving system 200 according to a modified example shown in FIG. 9 shows an example in which a clock source 30′ is incorporated into a data receiving circuit 10′.

[0030] The operating clock can be the output clock itself of an oscillator such as a crystal oscillator or a MEMS oscillator, or the output clock of an oscillator whose frequency has been converted by a PLL or DLL. In this disclosure, the output clock of an oscillator is used as the operating clock. (Recording Section 12)

[0031] The recording unit 12 is a member for taking in or writing read data output from the data transmission circuit 20 to the data reception circuit 10. For such a recording unit 12, for example, a shift register or a RAM can be used. (Capture enable)

[0032] A capture enable is used to capture (write) the read data output from the data transmission circuit 20. The capture enable defines the timing for reading data. While the capture enable is at H level, the read data is captured at the edge of the capture clock. There are two types of capture enables: a temporary capture enable used in dummy communication (described later) and a real capture enable used in normal communication. The operating clock has a rising edge and a falling edge, as shown in FIG. 3. Either the rising edge or the falling edge, or both, can be used to capture read data. In this disclosure, an example of capturing at the rising edge will be described. (Preservation part 14)

[0033] Predetermined data is stored in the storage unit 14. Examples of the predetermined data include fixed data such as an ID or password, and data that is used while changing, such as display data displayed on the display unit 2. Such storage unit 14 can use, for example, volatile memory such as a shift register or RAM, or non-volatile memory such as a ROM. If data written to the data transmission circuit 20 can be read, the predetermined data can be the data written to the data transmission circuit 20. In this case, it is desirable to use a rewritable shift register or RAM for the storage unit 14. On the other hand, if data is only read from the data transmission circuit 20, predetermined data is used as the predetermined data. In this case, it is desirable to use a ROM for the storage unit 14. (Comparison section 16)

[0034] The comparison unit 16 is a component for comparing the data captured in the recording unit 12 with predetermined data stored in the storage unit 14. Such a comparison unit 16 can be implemented by a combinational circuit such as an XNOR or XOR. (Control unit 18)

[0035] The control unit 18 is a member for generating a control clock to be sent to the data sending circuit 20 as shown in FIG. 8, and controlling the taking in and writing of read data in the recording unit 12.

[0036] The control unit 18 controls the capture enable to select the edge position of the capture clock for the read data from among multiple operating clocks, based on the result of the comparison between the captured data in the recording unit 12 and the predetermined data in the storage unit 14 in the comparison unit 16. In other words, the capture clock is changed to an appropriate one depending on the read data that changes depending on the propagation delay time T. The period when this capture enable is at H level is the optimal data capture timing for capturing the read data into the recording unit 12.

[0037] Such a control unit 18 can be, for example, an FPGA, a microcomputer, or a combination of these. The entire data receiving circuit 10 may be configured using an FPGA. The data transmission circuit 20 may also be made up of a ROM, RAM, or shift register. Furthermore, serial or parallel methods can be used for input and output data. In this embodiment, for the sake of simplicity, a serial ROM is used for the data transmission circuit 20. [Data reception method]

[0038] Here, we will explain a data reception method in which the data receiving circuit 10 acquires read data transmitted from the data transmitting circuit 20 based on the operating clock generated by the clock source 30. First, the control unit 18 of the data receiving circuit 10 generates an acquisition enable signal. Next, based on the acquisition enable signal generated by the control unit 18, the data receiving circuit 10 acquires read data from the data transmitting circuit 20 and records the acquired data in the recording unit 12. The comparator 16 of the data receiving circuit 10 then compares predetermined data previously stored in the storage unit 14 with the acquired data recorded in the recording unit 12. Based on the comparison result, the control unit 18 selects an acquisition clock from the operating clocks that corresponds to the timing for acquiring the read data. In this way, an appropriate acquisition clock can be selected from multiple operating clocks, preventing missed read data acquisition. Furthermore, the time required to determine the appropriate timing for acquiring read data is shortened, thereby achieving faster dynamic scanning. (Dummy communication)

[0039] Alternatively, the data reception method may involve performing dummy communication prior to normal communication to determine the appropriate data acquisition timing. Specifically, as shown in the flowchart of FIG. 10, first, dummy communication is performed in step S101. Then, in step S102, the appropriate data acquisition timing is selected, corrected, or updated. Then, in step S103, normal communication is performed. Then, as appropriate, the process returns to step S101, where dummy communication is performed, and the process of correcting and updating to the appropriate data acquisition timing in step S102 is repeated.

[0040] In one example of a data reception method in this case, the control unit 18 of the data receiving circuit 10 first generates a first temporary capture enable. Next, based on the first temporary capture enable generated by the control unit 18, the data receiving circuit 10 provisionally captures read data from the data transmission circuit 20 and records the captured temporary capture data in the recording unit 12. The comparator 16 of the data receiving circuit 10 then compares predetermined data previously stored in the storage unit 14 with the temporary capture data recorded in the recording unit 12, and based on the comparison result, the control unit 18 selects an capture clock from the operating clocks that corresponds to the timing for capturing the read data. Furthermore, based on the capture clock selected by the control unit 18, the control unit 18 generates a final capture enable. Furthermore, based on the final capture enable generated by the control unit 18, the data receiving circuit 10 captures read data from the data transmission circuit 20 and records the captured final capture data in the recording unit 12. In this way, an appropriate capture clock can be selected from multiple operating clocks, preventing read data from being missed. In addition, the time required to determine the appropriate timing for capturing read data is shortened, thereby realizing faster dynamic scanning. In particular, by performing dummy communication using the first temporary capture enable prior to normal communication using this capture enable, even if the signal propagation delay changes over time, it can be handled by updating the selected position of the capture clock accordingly.

[0041] Furthermore, the method may include a step in which the control unit 18 generates a second temporary capture enable signal following the step of recording the actual capture data in the recording unit 12. In this case, based on the second temporary capture enable signal generated by the control unit 18, the data receiving circuit 10 temporarily captures read data from the data transmission circuit 20 and records the captured second temporary capture data in the recording unit 12. The comparison unit 16 then compares the predetermined data with the second temporary capture data recorded in the recording unit 12, and based on the comparison result, the control unit 18 reselects the capture clock from the operating clocks. In this way, by further capturing the temporary capture data and reselecting the capture clock, even if the propagation delay time fluctuates over time, a capture clock with appropriate timing that corresponds to the fluctuation can be selected, thereby preventing data from being missed.

[0042] Furthermore, the acquisition clock may be updated based on the acquired data. That is, as shown in Fig. 11, first, in step S111, dummy communication is performed, and then in step S112, appropriate data acquisition timing is selected, corrected, or updated. Then, in step S113, normal communication is performed. Up to this point, the process is the same as in Fig. 10 described above, but in step S114, the data acquisition timing is corrected to be appropriate during normal communication.

[0043] For example, following the step of recording the actual captured data in the recording unit 12, the control unit 18 generates a second actual captured enable. Furthermore, based on the second actual captured enable generated by the control unit 18, the data receiving circuit 10 captures read data from the data transmission circuit 20 and records the captured second actual captured data in the recording unit 12. The comparison unit 16 then compares the actual captured data with the second actual captured data recorded in the recording unit 12, and based on the comparison result, the control unit 18 reselects the capture clock from among the operating clocks. In this way, by reselecting the capture clock based on the actual captured data, temporary captured data becomes unnecessary, and the timing is changed to an appropriate timing that efficiently corresponds to temporal fluctuations in propagation delay time, thereby preventing data from being missed.

[0044] The details of dummy communication are explained below. Prior to normal communication, the data receiving circuit 10 performs dummy communication using dummy data that differs from normal communication, thereby determining the appropriate data acquisition timing. Unlike normal data, the dummy data does not indicate display data for the display unit 2 and does not affect the display content of the display unit 2. Here, the procedure for performing dummy communication in the data receiving circuit 10 according to the first embodiment will be explained based on the timing chart of FIG. 12. In the timing charts below, the rising edge of the operating clock is indicated by a dashed line. FIG. 12 explains the procedure for determining the optimal data acquisition timing by reading 3-bit data "0, 1, 0" written at a predetermined address from the data transmission circuit 20 by the data receiving circuit 10 and comparing this with the predetermined data "1" stored in the storage unit 14 by the comparison unit 16.

[0045] First, in dummy communication, 3-bit data "0, 1, 0" written at a specified address is read. Here, the control unit 18 generates a control clock by dividing the operating clock by 8 (master output). Then, at the timing of the control clock, read data is read from the data transmission circuit 20 to the recording unit 12 (master input). Here, a propagation delay time T occurs between the master output and the master input, that is, between the output of the control clock and the input of the read data. In other words, the read data output by the data transmission circuit 20 returns to the data reception circuit 10 after the propagation delay time T has elapsed since the data reception circuit 10 generated the control clock. (Temporary import enable)

[0046] In dummy communication, the timing for reading data is determined by the temporary capture enable. As shown in FIG. 12, the period during which the temporary capture enable is at the H level is the range in which it is confirmed whether or not the read data can be captured. Here, the recording unit 12 captures read data within the estimated range of propagation delay time T after the control clock is generated, i.e., the period during which the temporary capture enable is at the H level. The range in which it is confirmed whether or not the read data can be captured is estimated from the minimum and maximum of the propagation delay time T, and is the period during which the temporary capture enable is at the H level, and is defined as (1) to (15). If the read data is captured into the recording unit 12 at the rising edge of the operating clock during this period, (1) to (3) will be "0", (4) to (11) will be "1", and (12) to (15) will be "0".

[0047] Then, the comparison unit 16 compares the data "000111111110000" captured in the recording unit 12 with the predetermined data "1" stored in the storage unit 14. As a result, (1) to (3) are mismatched and marked with "X", (4) to (11) are matched and marked with "O", and (12) to (15) are mismatched and marked with "X".

[0048] Based on the comparison result, the control unit 18 determines the optimal data capture timing. Preferably, the control unit 18 selects, as the capture clock, an operating clock located in the middle of the interval in which the capture data and the predetermined data continuously match. In this way, the capture clock can be set at a timing that allows stable reading of the read data, taking into account a time margin. As a result, it is possible to provide a margin for variations in setup time, hold time, and propagation delay time T. In the example of FIG. 12, in the range (4) to (11) where the comparison results match, (7) or (8) is the optimal data capture timing to capture data near the center. By capturing read data at the data capture edge of such optimal data capture timing, it is possible to accommodate variations in the propagation delay time T, resulting in stable operation and improved reliability.

[0049] Such dummy communication is performed prior to normal communication. The timing for performing dummy communication may be immediately before normal communication, or may be a predetermined timing, such as when the power supply to the data transmission circuit 20 is turned on, or at a fixed interval. (Normal communication)

[0050] In this way, normal communication is performed at the optimal data acquisition timing determined by the dummy communication. How the data receiving circuit 10 performs normal communication will be described with reference to the timing chart in Figure 13. Here, the description will be given assuming that (7) is selected as the optimal data acquisition timing. (Enable main capture)

[0051] In normal communication, the control unit 18 controls the period of the main capture enable, which is the capture enable for capturing in normal communication, so that read data can be captured at the optimal data capture timing. In the example of Fig. 13, the main capture enable is controlled to be at H level at (7) so that read data is captured at data capture timing (7) during normal communication. Here, the period when the main capture enable is at H level is one cycle of the operating clock.

[0052] The recording unit 12 captures data at count (7) of the operating clock after the control clock is generated. During each period when the main capture enable is at H level, the data captured by the recording unit 12 at the rising edge of the operating clock is "1, 0, 1." As shown in Figure 13, it can be seen that the main capture enable is able to capture data near the center of each read data of "1, 0, 1."

[0053] As described above, the data receiving circuit 10 according to the first embodiment can determine whether or not read data can be acquired within approximately the maximum propagation delay time T, thereby shortening the time required to determine the optimal data acquisition timing. In other words, the dummy communication period can be shortened. Furthermore, because the communication time is short, the decrease in the scan rate of the display unit 2 can be reduced, thereby suppressing degradation of display quality. As shown in FIG. 14A, an operating clock is selected for each read data, so a single read data communication is sufficient. In this example, one of six operating clocks that overlap with the read data is selected. If the phase of the operating clock itself were to be changed, as shown in FIG. 14B, the phase of the operating clock would need to be changed and checked at six points, which would take six times longer to determine the optimal data acquisition timing. Therefore, this embodiment can be said to have the advantage of shortening the time required to determine the optimal data acquisition timing.

[0054] The data transmission circuit 20 is not limited to ROM, and may be RAM or a shift register. When RAM is used, the specified data is data written in advance at a specified address. When a shift register is used, the specified data is data written in advance at a specified shift bit position. When a shift register is used in the data transmission circuit 20, an effective application is achieved by returning the register contents set or preset on the data transmission circuit 20 side to the data receiving circuit 10 side. This function is installed in constant current driver ICs used in some display devices 100, and is used to exchange alarm information such as open or short circuits in the display elements and abnormal heat generation in the IC. [Embodiment 2]

[0055] In the first embodiment described above, one bit is used as the predetermined data, but the present disclosure is not limited to this configuration and the predetermined data may be composed of multiple bits. Such an example will be described as a data receiving circuit 10 according to a second embodiment with reference to the timing chart of dummy communication in FIG. 15. In the data receiving circuit 10 according to the second embodiment, the predetermined data is two bits, but this is not limited to this and may be three or more bits. FIG. 15 describes a procedure for reading out four-bit data "0, 1, 0, 1" written at a predetermined address from the data transmission circuit 20 and comparing it with the predetermined data "1, 0" to determine the optimal data capture timing. (Dummy communication in embodiment 2)

[0056] First, in the dummy communication of the second embodiment, 4-bit data "0, 1, 0, 1" written at a predetermined address is read. Here, a control clock is generated by dividing the operating clock by 4, and read data is read from the data transmission circuit 20. After the data reception circuit 10 generates the control clock, the read data output by the data transmission circuit 20 is returned to the data reception circuit 10 with propagation delay times T1 and T2.

[0057] Although the first embodiment uses one temporary capture enable, the present disclosure is not limited to this, and multiple temporary capture enables may be used. For example, a second temporary capture enable may be used following a first temporary capture enable. In the data receiving circuit 10 according to the second embodiment, first to seventh temporary capture enables are used, which are referred to as temporary capture enables 1 to 7 for convenience. In this way, in the second embodiment, the confirmation range for whether or not read data can be captured is estimated and confirmed using seven temporary capture enables 1 to 7. The H-level period of each temporary capture enable is one cycle of the operating clock. When read data is captured into the recording unit 12 using the operating clock during each period, temporary capture enables 1 and 7 are "0, 1," temporary capture enable 2 is "1, 1," and temporary capture enables 3 to 6 are "1, 0."

[0058] When the comparison unit 16 compares the data "0, 1", "1, 1", and "1, 0" captured in the recording unit 12 with the specified data "1, 0" stored in the storage unit 14, temporary capture enables 1, 2, and 7 do not match and are marked "X", while temporary capture enables 3 to 6 (shown in bold frames in Figure 15) match and are marked "O".

[0059] Based on the above comparison results, the optimal data capture timing is determined. Here, as in the first embodiment, it is desirable to capture data near the center of the range where the comparison results match, in order to allow for some leeway for fluctuations in the setup time, hold time, and propagation delay time T. Furthermore, it can be assumed that the provisional capture enable 2, which captured the same data "1, 1," is near the lower limit of the setup time or hold time, or is a part that is affected by fluctuations in the propagation delay time T.

[0060] Therefore, within the range of matching temporary fetch enables 3 to 6, the optimal data fetch timing is temporary fetch enable 4. In other words, among the operating clocks (1) to (9) numbered from the rising edge of the control clock, the timing is (6), which is the same as temporary fetch enable 4. (Normal communication in embodiment 2)

[0061] Next, normal communication in the data receiving circuit 10 according to the second embodiment will be described with reference to the timing chart of Fig. 16. Here, the description will be made assuming that the operating clock (6) is selected as the optimal data acquisition timing as a result of the above dummy communication.

[0062] In normal communication, the control unit 18 controls the main capture enable to be at H level at (6) so that read data is captured at the optimal data capture timing. The period during which the main capture enable is at H level is also one cycle of the operating clock, as in the first embodiment.

[0063] When this capture enable is at H level, the data captured into the recording unit 12 at the rising edge of the operating clock is "0, 1, 0, 1."

[0064] As described above, the data receiving circuit 10 according to the second embodiment can achieve both resistance to fluctuations in propagation delay time and a reduction in the time required to determine the optimal data acquisition timing.

[0065] 8, the predetermined data stored in the storage unit 14 may use data written in advance in the data transmission circuit 20 or a part of that data. For example, "0, 1, 0, 1" may be written in advance in the data transmission circuit 20, and "0, 1, 0, 1" or "1, 0" may be stored in the storage unit 14 and used as the predetermined data. [Embodiment 3]

[0066] In the above example, dummy communication is performed prior to normal communication to select the optimal data acquisition timing, i.e., the data acquisition edge. However, the optimal data acquisition timing may fluctuate during normal communication. Therefore, as described above, the data acquisition timing can be updated by appropriately performing dummy communication. On the other hand, updating the data acquisition timing is not limited to dummy communication, but may also be performed during normal communication. In this case, one or more temporary acquisition enables can be used in normal communication. Here, the acquisition enable that acquires read data as display data in normal communication is referred to as a real acquisition enable to distinguish it from a temporary acquisition enable. Furthermore, one or more real acquisition enables are referred to in order as a first real acquisition enable, a second real acquisition enable, ..., and similarly, one or more temporary acquisition enables are referred to in order as a first temporary acquisition enable, a second temporary acquisition enable, .... As an example, an example in which a real acquisition enable, a first temporary acquisition enable, and a second temporary acquisition enable are used in normal communication will be described using a data receiving circuit 10 according to the third embodiment with reference to the timing charts of FIGS. 17 to 20.

[0067] 17 shows a timing chart of dummy communication of the data receiving circuit 10 according to the third embodiment. Here, the procedure for reading 3-bit data "0, 1, 0" written at a predetermined address from the data sending circuit 20 and comparing it with the predetermined data "1" to determine the optimal data acquisition timing will be described. (Dummy communication in embodiment 3)

[0068] First, in dummy communication, the 3-bit data "0, 1, 0" written at a specified address is read. Here, a control clock is generated by dividing the operating clock by 8, and read data is read from the data transmission circuit 20. After the data reception circuit 10 generates the control clock, the read data output by the data transmission circuit 20 is returned to the data reception circuit 10 with a propagation delay time T1.

[0069] The range for checking whether or not the read data can be imported is estimated from the minimum and maximum of the propagation delay time T, and the period during which the temporary import enable is at H level is set to (1) to (13) as shown in Figure 17. If the read data is imported into the recording unit 12 using the operating clock during this period, (1) and (2) will be "0", (3) to (10) will be "1", and (11) to (13) will be "0".

[0070] When the comparator 16 compares the data "0011111111000" captured in the recorder 12 with the predetermined data "1" stored in the storage unit 14, they match in (3) to (10).

[0071] Based on the comparison results, the optimal data acquisition timing is determined. In this case, as in the above embodiments, it is desirable to acquire data near the center of the range where the comparison results match in order to allow for some margin for fluctuations in the setup time, hold time, and propagation delay time T. Therefore, within the matched range (3) to (10), the optimal data acquisition timing is (6) or (7). (Normal communication in embodiment 3)

[0072] Next, normal communication of the data receiving circuit 10 according to the third embodiment will be described with reference to the timing chart of Fig. 18. Here, the description will be made assuming that (6) is selected as the optimal data acquisition timing determined by the dummy communication.

[0073] Although not shown in Fig. 8, the predetermined data stored in the storage unit 14 may use data captured in the recording unit 12 or a portion of that data. For example, data captured in the recording unit 12 during dummy communication or normal communication can be stored in the storage unit 14 in advance and used as the predetermined data. In Fig. 18, the predetermined data is changed from "1" to "0011111111000" at the stage of transitioning from dummy communication to normal communication.

[0074] In normal communication, the control unit 18 controls the main capture enable to be at H level so that read data is captured at the optimal data capture timing. The period during which the main capture enable is at H level is one cycle of the operating clock.

[0075] In parallel with this, it is confirmed whether the optimum data fetch timing is being maintained. The control unit 18 controls the range for checking whether or not read data can be fetched so that the tentative fetch enables 1 and 2 are at H level.

[0076] During the first read data capture period, temporary capture enable 2 is at H level and "1100000000001" is captured into the recording unit 12. When this is compared with the data "0" captured at the optimal data capture timing (6), the result is "xxxxxxxxxxxxxxxxxxxx", as boxed in Figure 18.

[0077] Similarly, when the predetermined data "0011111111000" stored in the storage unit 14 is compared with the data "1" acquired at the optimal data acquisition timing (6), the result is "xxxxxxxxxxxxxxxxxx." When the data acquired in the recording unit 12 and the predetermined data stored in the storage unit 14 are corrected to have data sequences of "O" and "X," respectively, and compared, (11) and (12) change from "X" to "O." In other words, it can be seen that the propagation delay time of the read data has increased during the acquisition period of the next read data.

[0078] On the other hand, the main capture enable at the optimum data capture timing (6) is at H level, and "0" is captured into the recording unit 12.

[0079] Accordingly, during the second read data import period, the optimal data import timing will change to (7) or (8), which is in the center of "xxxxxxxxxxxxxxxxxxxx." Here, we will explain the case where (7) is selected as the optimal data import timing.

[0080] During this period, temporary capture enable 1 is at H level and "0000111111110" is captured in the recording unit 12. When this is compared with the data "1" captured at the optimal data capture timing (7), it becomes "xxxxxxxxxxxxxxxxxx", as boxed in Figure 19.

[0081] Here, the specified data is changed from "0011111111000" to "1100000000001" when the first to second read data capture period is shifted. When this is compared with the data "0" captured at the optimal data capture timing (7), it becomes "xxxxxxxxxxxxxxxxxxxx".

[0082] When the data captured in the recording unit 12 and the predetermined data stored in the storage unit 14 are corrected to have data arrangements of "o" and "x", respectively, and compared, (3) and (4) change from "o" to "x". In other words, it can be seen that the propagation delay time of the read data during the period in which the next read data is captured remains unchanged.

[0083] On the other hand, the main capture enable at the optimum data capture timing (7) is at H level, and "1" is captured in the recording unit 12.

[0084] Accordingly, during the third read data import period, the optimal data import timing will change to either (8) or (9), which is in the middle of "xxxxxxxxxxxxxxxxxx". Here, we will explain the case where (8) is selected as the optimal data import timing.

[0085] During this period, temporary capture enable 2 is at H level and "1111000000001" is captured in the recording unit 12. When this is compared with the data "0" captured at the optimal data capture timing (8), it becomes "xxxxxxxxxxxxxxxxxx".

[0086] Here, the specified data is changed from "1100000000001" to "0000111111110" when the second to third read data capture period is reached. Comparing this with the data "1" captured at the optimal data capture timing (8), the result is "xxxxxxxxxxxxxxxxxxxxx", as boxed in Figure 20.

[0087] When the data captured in the recording unit 12 and the predetermined data stored in the storage unit 14 are compared after being corrected to have data arrangements of "◯" and "X", respectively, they are found to be exactly the same. In other words, it can be seen that the propagation delay time of the read data during the period in which the next read data is captured has not changed.

[0088] On the other hand, the main capture enable at the optimum data capture timing (8) is at H level, and "0" is captured into the recording unit 12.

[0089] In this way, once the optimum data acquisition timing is determined by dummy communication, deviations in the data acquisition timing can be corrected in normal communication.

[0090] As described above, the data receiving circuit 10 according to the third embodiment can correct and update the data acquisition timing to the optimum timing in normal communication. Therefore, by reducing the frequency of dummy communication, the time required to determine the optimum data acquisition timing can be shortened.

[0091] Since the data captured in the recording unit 12 may not meet the setup time or hold time, the switching between 0 and 1 may be ignored. For example, the specified data "0011111111000" can be used as "00*111111*000" (* can be either 0 or 1).

[0092] Although the above-mentioned first to third embodiments have been described as the data receiving circuit 10, it goes without saying that the present invention is not limited to this and can be used as a data receiving method. [Example]

[0093] Next, the data receiving circuit 10 according to the first embodiment will be described.

[0094] The data receiving circuit 10 according to the first embodiment was designed using an FPGA for the data receiving circuit 10. A ROM was used for the data sending circuit 20, and a 100 MHz crystal oscillator was used for the oscillator.

[0095] The operating clock is a 100MHz oscillator clock, the control clock is 25MHz, which is the operating clock divided by 4, and the propagation delay time of the read data is set to 5ns, 30ns, and 55ns so that it changes three times each time the optimal data capture timing is calculated.

[0096] The recording unit 12 has a 10-bit register controlled by the temporary capture enable and an 8-bit register controlled by the main capture enable. The specified data "1" is stored in the register of the storage unit 14, and the 3-bit data "0, 1, 0" written at a specified address is read from the data transmission circuit 20 and compared by the comparison unit 16, so as to correct for the optimal data capture timing.

[0097] In this way, it was confirmed whether data written to an arbitrary address could be successfully read from the data transmission circuit 20. Here, the data was set to "01001011".

[0098] When the data receiving circuit 10 was confirmed by RTL simulation, it was found that data could be successfully received even when the propagation delay time changed. Therefore, the data receiving circuit 10 according to the first embodiment can be evaluated as a high-quality data receiving circuit 10.

[0099] Next, a data receiving circuit according to a first comparative example will be considered.

[0100] The data receiving circuit according to Comparative Example 1 has basically the same configuration as the data receiving circuit according to Example 1, but the data fetch timing is fixed and not corrected to the optimum data fetch timing.

[0101] When such a data receiving circuit was checked by RTL simulation, it was found that data reception failed when the propagation delay time changed. Therefore, the data receiving circuit according to Comparative Example 1 can be evaluated as a data receiving circuit of poor quality.

[0102] Although the embodiments and examples have been described above, these descriptions are merely examples and do not limit the configurations described in the claims. Furthermore, for the sake of convenience and simplification, some details have been omitted.

[0103] The present invention can also be implemented in the following manner.

[0104] [Section 1] a clock source that generates an operating clock; a data transmission circuit for transmitting read data; a recording unit for recording the read data sent from the data sending circuit; a storage unit for storing predetermined data in advance; a comparison unit for comparing the predetermined data stored in the storage unit with the captured data recorded in the recording unit; a control unit that selects, based on a comparison result between the predetermined data and the captured data by the comparison unit, an capture clock that is a timing for capturing the read data from the data transmission circuit from among the operation clocks generated by the clock source while maintaining the phase of the operation clock; a data receiving circuit comprising: A data receiving system comprising: The above configuration allows the selection of an appropriate capture clock from multiple operating clocks, preventing read data from being missed. It also reduces the time required to determine the appropriate timing for capturing read data, enabling faster dynamic scanning.

[0105] [Section 2] Item 1, the data receiving system, The data receiving system is configured such that the control unit selects, as the acquisition clock, an operation clock located in the middle of a section in which the acquisition data and the predetermined data continuously match. With the above configuration, the capture clock can be set at a timing that allows stable reading of read data, taking into consideration a time margin.

[0106] [Section 3] Item 1 or 2, the data receiving system; a display unit configured with a plurality of light-emitting elements; A display device comprising: the data receiving circuit uses the predetermined data stored in the storage unit as display data to be displayed on the display unit, The display device is configured such that the brightness of the plurality of light-emitting elements is controlled by the data transmission circuit. With the above configuration, when performing dynamic scanning on a display device that displays display data stored in the data receiving circuit, it is possible to avoid missing data and increase the display speed.

[0107] [Section 4] A data receiving circuit for receiving read data sent from a data sending circuit based on an operation clock generated by a clock source, a recording unit for recording the captured read data; a storage unit for storing predetermined data in advance; a comparison unit for comparing the predetermined data stored in the storage unit with the captured data recorded in the recording unit; a control unit that selects, from among the operation clocks, an acquisition clock that is a timing for acquiring the read data, based on a comparison result between the predetermined data and the acquisition data by the comparison unit, while maintaining the phase of the operation clock; A data receiving circuit comprising: The above configuration allows the selection of an appropriate capture clock from multiple operating clocks, preventing read data from being missed. It also shortens the time required to determine the appropriate timing for capturing read data, thereby achieving faster dynamic scanning.

[0108] [Section 5] Item 4. The data receiving circuit according to item 4, The control unit is configured to select, as the capture clock, an operation clock located in the middle of a section in which the captured data and the specified data continuously match, from the operation clocks in the section in which the captured data and the specified data continuously match.

[0109] [Section 6] Item 4 or 5, the data receiving circuit according to item 4 or 5, The data receiving circuit is configured such that the control unit selects the capture clock from among the operating clocks based on the result of dummy communication using dummy data that is different from normal communication. With the above configuration, by performing dummy communication prior to normal communication, it is possible to select an appropriate position of the capture clock from among a plurality of operation clocks.

[0110] [Section 7] Item 6. The data receiving circuit according to item 6, The control unit In the dummy communication, a provisional acquisition enable for acquiring the read data is set to The data receiving circuit is configured such that a period is set longer than a main capture enable period for capturing the read data in the normal communication.

[0111] [Section 8] A data receiving method in which read data sent from a data sending circuit is taken in by a data receiving circuit based on an operation clock generated by a clock source, comprising: a control unit of the data receiving circuit generating a capture enable; a step in which the data receiving circuit receives the read data from the data sending circuit based on the capture enable generated by the control unit, and records the received capture data in a recording unit; a step of comparing predetermined data stored in advance in a storage unit with the captured data recorded in the recording unit by a comparison unit of the data receiving circuit, and selecting, based on the comparison result, a capture clock from among the operating clocks that is the timing for capturing the read data by the control unit; A data receiving method including: This allows the appropriate clock to be selected from multiple operating clocks, preventing read data from being missed. It also shortens the time required to determine the appropriate timing to capture read data, thereby achieving faster dynamic scanning.

[0112] [Section 9] A data receiving method in which read data sent from a data sending circuit is taken in by a data receiving circuit based on an operation clock generated by a clock source, comprising: a control unit of the data receiving circuit generating a first tentative capture enable; a step in which the data receiving circuit provisionally acquires the read data from the data sending circuit based on the first provisional acquisition enable generated by the control unit, and records the acquired provisional acquisition data in a recording unit; a step of comparing predetermined data stored in advance in a storage unit with the provisionally acquired data recorded in the recording unit by a comparison unit of the data receiving circuit, and selecting, based on the comparison result, an acquisition clock from among the operation clocks that is the timing for acquiring the read data by the control unit; generating a main capture enable signal by the control unit based on a capture clock selected by the control unit; a step in which the data receiving circuit receives the read data from the data sending circuit based on the actual capture enable generated by the control unit, and records the received actual capture data in the recording unit; A data receiving method including: This allows the selection of an appropriate capture clock from multiple operating clocks, preventing read data from being missed. It also shortens the time required to determine the appropriate timing for capturing read data, thereby achieving faster dynamic scanning. In particular, by performing dummy communication using the first temporary capture enable before normal communication using this capture enable, even if the signal propagation delay changes over time, the selected capture clock position can be updated accordingly.

[0113] [Section 10] Item 9. The data receiving method according to item 9, further comprising: a step of generating a second temporary capture enable signal by the control unit following the step of recording the actual capture data in the recording unit; a step in which the data receiving circuit provisionally acquires the read data from the data sending circuit based on the second provisional acquisition enable generated by the control unit, and records the acquired second provisional acquisition data in a recording unit; a step of comparing the actual captured data with the second provisional captured data recorded in the recording unit by the comparison unit, and reselecting the capture clock from among the operation clocks by the control unit based on the comparison result; A data receiving method including: This allows further fetching of provisional fetch data and reselection of the fetch clock, so that even if the propagation delay time fluctuates over time, the fetch clock with the appropriate timing corresponding to the fluctuation can be reselected, thereby preventing data from being missed.

[0114] [Section 11] Item 10. The data receiving method according to item 10, further comprising: a step of generating the second actual capture enable signal by the control unit following the step of recording the actual capture data in the recording unit; a step in which the data receiving circuit acquires the read data from the data sending circuit based on the second acquisition enable generated by the control unit, and records the acquired second acquisition data in a recording unit; a step of comparing the actual captured data with the second actual captured data recorded in the recording unit by the comparison unit, and reselecting the capture clock from among the operation clocks by the control unit based on the comparison result; A data receiving method including: This makes it possible to reselect the capture clock based on the actual capture data, eliminating the need for temporary capture data, and efficiently changing to an appropriate timing that corresponds to temporal fluctuations in propagation delay time, thereby avoiding data loss.

[0115] [Section 12] The data receiving method according to any one of items 9 to 11, a step in which the control unit selects the capture clock based on a comparison between the specified data and the captured data by the comparison unit, the step being performed by selecting, as the capture clock, an operating clock located midway between the operating clocks in a section in which the captured data and the specified data continuously match. This allows for a time margin to be taken into consideration and allows for the acquisition clock to be set at a timing at which read data can be read stably. [Industrial Applicability]

[0116] The data receiving system, display device, data receiving circuit, and data receiving method according to the present disclosure can be incorporated into a display device composed of pixels, and can be applied to data reception in, for example, traffic information boards and displays used in train stations, airports, bus stops, etc., and large televisions. [Explanation of symbols]

[0117] 1000...display device 100, 200...Data receiving system 1...Light emitting element 2...Display section 10...Data receiving circuit 12...Recording section 14...Storage section 16...Comparison section 18...Control unit 20...Data transmission circuit 30...Clock source

Claims

1. a clock source that generates an operating clock; a data transmission circuit for transmitting read data; a recording unit for recording the read data sent from the data sending circuit; a storage unit for storing predetermined data in advance; a comparison unit for comparing the predetermined data stored in the storage unit with the captured data recorded in the recording unit; a control unit that selects, based on a comparison result between the predetermined data and the captured data by the comparison unit, an capture clock that is a timing for capturing the read data from the data transmission circuit from among the operation clocks generated by the clock source while maintaining the phase of the operation clock; a data receiving circuit comprising: A data receiving system comprising:

2. 2. The data receiving system according to claim 1, The data receiving system is configured such that the control unit selects, as the acquisition clock, an operation clock located in the middle of a section in which the acquisition data and the predetermined data continuously match.

3. A data receiving system according to claim 1 or 2; a display unit configured with a plurality of light-emitting elements; A display device comprising: the data receiving circuit uses the predetermined data stored in the storage unit as display data to be displayed on the display unit, The display device is configured such that the brightness of the plurality of light-emitting elements is controlled by the data transmission circuit.

4. A data receiving circuit for receiving read data sent from a data sending circuit based on an operation clock generated by a clock source, a recording unit for recording the captured read data; a storage unit for storing predetermined data in advance; a comparison unit for comparing the predetermined data stored in the storage unit with the captured data recorded in the recording unit; a control unit that selects, from among the operation clocks, an acquisition clock that is a timing for acquiring the read data, based on a comparison result between the predetermined data and the acquisition data by the comparison unit, while maintaining the phase of the operation clock; A data receiving circuit comprising:

5. 5. The data receiving circuit according to claim 4, The control unit is configured to select, as the capture clock, an operation clock located in the middle of a section in which the captured data and the specified data continuously match, from the operation clocks in the section in which the captured data and the specified data continuously match.

6. 6. The data receiving circuit according to claim 4, The data receiving circuit is configured such that the control unit selects the capture clock from among the operating clocks based on the result of dummy communication using dummy data different from normal communication.

7. 7. The data receiving circuit according to claim 6, The control unit In the dummy communication, a provisional acquisition enable for acquiring the read data is set to The data receiving circuit is configured such that a period is set longer than a main capture enable period for capturing the read data in the normal communication.

8. A data receiving method in which read data sent from a data sending circuit is taken in by a data receiving circuit based on an operation clock generated by a clock source, comprising: a control unit of the data receiving circuit generating a capture enable; a step in which the data receiving circuit receives the read data from the data sending circuit based on the capture enable generated by the control unit, and records the received capture data in a recording unit; a step of comparing predetermined data stored in advance in a storage unit with the captured data recorded in the recording unit by a comparison unit of the data receiving circuit, and selecting, based on the comparison result, a capture clock from among the operation clocks that is a timing for capturing the read data by the control unit; A data receiving method including:

9. A data receiving method in which read data sent from a data sending circuit is taken in by a data receiving circuit based on an operation clock generated by a clock source, comprising: a control unit of the data receiving circuit generating a first tentative capture enable; the data receiving circuit provisionally acquiring the read data from the data sending circuit based on the first provisional acquisition enable signal generated by the control unit, and recording the acquired provisional acquisition data in a recording unit; a step of comparing predetermined data stored in advance in a storage unit with the provisionally acquired data recorded in the recording unit by a comparison unit of the data receiving circuit, and selecting, based on the comparison result, an acquisition clock from among the operation clocks that is the timing for acquiring the read data by the control unit; generating a main capture enable signal by the control unit based on a capture clock selected by the control unit; a step in which the data receiving circuit receives the read data from the data sending circuit based on the actual capture enable generated by the control unit, and records the received actual capture data in the recording unit; A data receiving method including:

10. 10. The data receiving method according to claim 9, further comprising: a step of generating a second temporary capture enable signal by the control unit following the step of recording the actual capture data in the recording unit; a step in which the data receiving circuit provisionally acquires the read data from the data sending circuit based on the second provisional acquisition enable generated by the control unit, and records the acquired second provisional acquisition data in a recording unit; a step of comparing the actual captured data with the second provisional captured data recorded in the recording unit by the comparison unit, and reselecting the capture clock from among the operation clocks by the control unit based on the comparison result; A data receiving method including:

11. The data receiving method according to claim 10, further comprising: a step of generating the second actual capture enable signal by the control unit following the step of recording the actual capture data in the recording unit; a step in which the data receiving circuit acquires the read data from the data sending circuit based on the second acquisition enable generated by the control unit, and records the acquired second acquisition data in a recording unit; a step of comparing the actual captured data with the second actual captured data recorded in the recording unit by the comparison unit, and reselecting the capture clock from among the operation clocks by the control unit based on the comparison result; A data receiving method including:

12. The data receiving method according to any one of claims 9 to 11, a step in which the control unit selects the capture clock based on a comparison between the specified data and the captured data by the comparison unit, the step being performed by selecting, as the capture clock, an operating clock located midway between the operating clocks in a section in which the captured data and the specified data continuously match.

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