Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

To provide a nitride semiconductor device capable of achieving a MOSFET having high channel mobility and low on-resistance, and to provide a method of manufacturing the nitride semiconductor device.SOLUTION: A nitride semiconductor device includes a nitride semiconductor layer of a first conductivity type, a well region of a second conductivity type provided in the nitride semiconductor layer, and a gate insulating film provided on a first surface side of the nitride semiconductor layer and covering the well region. The well region includes a first region to which Al is not added and a second region provided on the first region and to which Al is added. The second region has an Al concentration distribution in which an Al concentration is highest at a first surface in contact with the gate insulating film and the Al concentration decreases continuously or stepwise from the first surface toward the first region.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

Background Art

[0002] In a high electron mobility transistor having a hetero-structure composed of AlxGal-xN / GaN (where 0 < X ≦ 1) formed on a substrate, the thickness of the AlxGal-xN barrier layer formed on the substrate surface side is set to a range where lattice relaxation does not occur, and the Al composition in the direction perpendicular to the substrate of the barrier layer is set to a region where the Al composition is modulated continuously or stepwise in part or all of the barrier layer (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a nitride semiconductor device, it is desired to realize a MOSFET having a high channel mobility and a low on-resistance.

[0005] An object of the present disclosure is to provide a nitride semiconductor device and a method for manufacturing a nitride semiconductor device capable of realizing a MOSFET having a high channel mobility and a low on-resistance.

Means for Solving the Problems

[0006] In order to solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure includes a first conductivity type nitride semiconductor layer, a second conductivity type well region provided in the nitride semiconductor layer, and a gate insulating film provided on a first surface side of the nitride semiconductor layer and covering the well region. The well region has a first region not doped with Al and a second region provided on the first region and doped with Al. The second region has an Al concentration distribution in which the Al concentration is highest at the first surface in contact with the gate insulating film and the Al concentration decreases continuously or stepwise from the first surface toward the first region.

[0007] A method for manufacturing a nitride semiconductor device according to one aspect of the present disclosure includes forming a well region of a second conductivity type on a first surface side of a nitride semiconductor layer of a first conductivity type, and forming a gate insulating film on the first surface side of the nitride semiconductor layer to cover the well region. The forming of the well region includes forming a first region to which Al is not added, and forming a second region to which Al is added on the first region. In the forming of the second region, an Al concentration distribution is formed in the second region in which the Al concentration is highest on the first surface in contact with the gate insulating film and the Al concentration decreases continuously or stepwise from the first surface toward the first region. [Effects of the Invention]

[0008] According to one aspect of the present disclosure, it is possible to provide a nitride semiconductor device that can realize a MOSFET having high channel mobility and low on-resistance, and a method for manufacturing the nitride semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 shows a cross section taken along line AA' in the plan view of FIG. [Figure 3] FIG. 3 is an enlarged view of the cross-sectional view of FIG. 2, showing an example of the configuration of one vertical MOSFET (unit structure). [Figure 4] FIG. 4 is an example (example) of an embodiment of the present disclosure, and is a schematic diagram illustrating the Al concentration distribution in the depth direction from the surface of the well region and the electron concentration distribution in the depth direction when the channel is formed. [Figure 5A] FIG. 5A is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in the order of steps. [Figure 5B] 5B is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in the order of steps. [Figure 5C] 5A to 5C are cross-sectional views illustrating a method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in the order of steps. [Figure 5D] 5A to 5D are cross-sectional views illustrating a method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in order of steps. [Figure 5E] 5A to 5E are cross-sectional views illustrating a method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in the order of steps. [Figure 5F] 5F is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in the order of steps. [Figure 5G] 5A to 5G are cross-sectional views illustrating a method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in the order of steps. [Figure 6A] FIG. 6A is a cross-sectional view showing a second method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in order of steps. [Figure 6B] 6B is a cross-sectional view showing a second method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in order of steps. [Figure 6C] 6A to 6C are cross-sectional views illustrating a second method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in order of steps. [Figure 7A] FIG. 7A is a cross-sectional view showing a manufacturing method 3 of a vertical MOSFET according to the first embodiment of the present disclosure in the order of steps. [Figure 7B] 7B is a cross-sectional view showing a third method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in order of steps. [Figure 7C]7A to 7C are cross-sectional views illustrating a third method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in order of steps. [Figure 7D] 7A to 7D are cross-sectional views illustrating a third method for manufacturing a vertical MOSFET according to the first embodiment of the present disclosure in order of steps. [Figure 8] FIG. 8 is a schematic diagram showing Comparative Example 1 of the present disclosure, illustrating the Al concentration distribution in the depth direction from the surface of the well region and the electron concentration distribution in the depth direction when the channel is formed. [Figure 9] FIG. 9 is a graph showing the results of an experiment conducted by the present inventors, comparing the field mobility of Example and Comparative Example 2. [Figure 10] FIG. 10 is a graph schematically showing the lattice constant difference between AlGaN and GaN in a well region according to an example of the present disclosure. [Figure 11] FIG. 11 is a graph schematically showing the difference in lattice constant between AlGaN and GaN in the well region according to Comparative Example 1 of the present disclosure. [Figure 12] FIG. 12 is a cross-sectional view showing a configuration example of a vertical MOSFET (unit structure) according to the second embodiment of the present disclosure. [Figure 13] FIG. 13 is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the second embodiment of the present disclosure. [Figure 14] FIG. 14 is a cross-sectional view showing a configuration example of a vertical MOSFET (unit structure) according to the third embodiment of the present disclosure. [Figure 15A] FIG. 15A is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the third embodiment of the present disclosure. [Figure 15B] FIG. 15B is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the third embodiment of the present disclosure. [Figure 15C] FIG. 15C is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the third embodiment of the present disclosure. [Figure 15D] FIG. 15D is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the third embodiment of the present disclosure. [Figure 15E] FIG. 15E is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the third embodiment of the present disclosure. [Figure 15F] FIG. 15F is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the third embodiment of the present disclosure. [Figure 15G] FIG. 15G is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the third embodiment of the present disclosure. [Figure 16] FIG. 16 is a cross-sectional view showing a configuration example of a vertical MOSFET (unit structure) according to the fourth embodiment of the present disclosure. [Figure 17] FIG. 17 is a cross-sectional view illustrating a method for manufacturing a vertical MOSFET according to the fourth embodiment of the present disclosure. [Figure 18] FIG. 18 is a cross-sectional view showing a configuration example of a vertical MOSFET (unit structure) according to the fifth embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram schematically illustrating a vertical MOSFET (Configuration Example 1) according to the sixth embodiment of the present disclosure. [Figure 20] FIG. 20 is a diagram schematically illustrating a vertical MOSFET (Configuration Example 2) according to the sixth embodiment of the present disclosure. [Figure 21] FIG. 21 is a diagram schematically illustrating a vertical MOSFET (Configuration Example 3) according to the sixth embodiment of the present disclosure. [Figure 22A] FIG. 22A is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to a sixth embodiment of the present disclosure in the order of steps. [Figure 22B] FIG. 22B is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 22C] FIG. 22C is a cross-sectional view showing a manufacturing method 1 of a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 22D] FIG. 22D is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 22E] FIG. 22E is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 22F] FIG. 22F is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 22G] FIG. 22G is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 22H] FIG. 22H is a cross-sectional view showing a manufacturing method 1 of a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 23A] FIG. 23A is a cross-sectional view showing a manufacturing method 3 of a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 23B] FIG. 23B is a cross-sectional view showing a manufacturing method 3 of a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 23C] FIG. 23C is a cross-sectional view showing a manufacturing method 3 of a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 23D] FIG. 23D is a cross-sectional view showing a third method for manufacturing a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 23E] FIG. 23E is a cross-sectional view showing a third method for manufacturing a vertical MOSFET according to the sixth embodiment of the present disclosure in the order of steps. [Figure 24] FIG. 24 is a cross-sectional view showing a configuration example (modification) of the vertical MOSFET 1 according to the sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] An embodiment of the present disclosure will be described below. In the following description of the drawings, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device or component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0011] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10, which will be described later. The X-axis and Y-axis directions are also referred to as horizontal directions. The Z-axis direction is a direction perpendicular to the surface 10a of the GaN substrate 10. The X-axis, Y-axis, and Z-axis directions are orthogonal to one another.

[0012] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down." "Up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship of regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present disclosure. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up."

[0013] In the following description, + or - attached to p or n indicating the conductivity type means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same p and p (or n and n) are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0014] <Embodiment 1> (Configuration example) FIG. 1 is a plan view illustrating a configuration example of a gallium nitride (GaN) semiconductor device 100 (an example of a "nitride semiconductor device" of the present disclosure) according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view illustrating a configuration example of the GaN semiconductor device 100 according to the first embodiment of the present disclosure. FIG. 2 shows a cross section taken along line AA' in the plan view of FIG. 1. FIG. 3 is an enlarged view of the cross-sectional view of FIG. 2, illustrating a configuration example of one vertical MOSFET 1 (unit structure).

[0015] 1 and 2 is a power device. As shown in FIGS. 1 and 2, the GaN semiconductor device 100 includes a GaN substrate 10 having a front surface 10a and a back surface 10b, and a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 provided on the GaN substrate 10. For example, the plurality of vertical MOSFETs 1 are repeatedly provided in one direction (e.g., the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and this unit structure is arranged side by side in one direction.

[0016] As shown in FIGS. 1 to 3 , GaN substrate 10 includes an n+ type GaN single crystal substrate 11 (an example of a "nitride semiconductor substrate" in the present disclosure) and an n- type GaN layer 12 (an example of a "nitride semiconductor layer" in the present disclosure) provided on GaN single crystal substrate 11. GaN single crystal substrate 11 is, for example, an n+ type c-plane GaN single crystal substrate. The n-type impurity contained in GaN single crystal substrate 11 is, for example, one or more of silicon (Si), oxygen (O), and germanium (Ge). As an example, GaN single crystal substrate 11 contains Si as an n-type impurity, and the impurity concentration of Si in GaN single crystal substrate 11 is 5×10 17 cm -3 That's all.

[0017] The GaN single crystal substrate 11 has a dislocation density of 1×10 7 cm -2 The GaN single crystal substrate 11 may be a low-dislocation freestanding substrate having a dislocation density of less than 1000 nm. When the GaN single crystal substrate 11 is a low-dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN single crystal substrate 11 is also low. Furthermore, by using a low-dislocation freestanding substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This allows the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, ion-implanted impurities can be prevented from diffusing deeply along dislocations during heat treatment.

[0018] The GaN layer 12 is a single crystal GaN layer epitaxially grown on one surface of the GaN single crystal substrate 11. The GaN layer 12 is formed by doping with n-type impurities during the epitaxial growth process. The n-type impurities are, for example, Si. The GaN layer 12 is formed by doping with, for example, 1×10 Si as the n-type impurity. 15 cm -3 5x10 or more 16 cm -3 Contains the following concentrations:

[0019] The vertical MOSFET 1 has a p-type well region 13 and a p+ type contact region 15 provided on the side of the front surface 10a of the GaN substrate 10 (i.e., the front surface of the GaN layer 12; an example of the "first surface" in the present disclosure). In the GaN layer 12, the n-type region excluding the well region 13 and the contact region 15 constitutes a drift region 121. The drift region 121 is located between the front surface 10a of the GaN substrate 10 (i.e., the front surface of the GaN layer 12) and the back surface 12b of the GaN layer 12 (an example of the "second surface" in the present disclosure). The drift region 121 is in contact with an n+ type GaN single crystal substrate 11 provided on the back surface 12b of the GaN layer 12. The vertical MOSFET 1 also includes a gate insulating film 21 provided on the front surface 10a side of the GaN substrate 10, a gate electrode 22 provided on the gate insulating film 21, a source electrode 25 provided on the front surface 10a side of the GaN substrate 10 and in contact with the n+ type source region 23 and the p+ type contact region 15, and a drain electrode 26 provided on the back surface 10b side of the GaN substrate 10 and in contact with the n+ type GaN single crystal substrate 11.

[0020] The well region 13 is a p-type layer formed by ion-implanting a p-type impurity such as Mg into the surface 10a of the GaN substrate 10 and activating the p-type impurity by heat treatment. The well region 13 is formed by ion-implanting a p-type impurity such as Mg at a concentration of 1×10 17 cm -3 3x10 or more 18 cm -3 The well region 13 faces the surface 10a of the GaN substrate 10 and is in contact with the gate insulating film 21. The first region 131 and the second region 132 will be described later with reference to FIG.

[0021] The source region 23 is an n+ type layer formed by ion-implanting n-type impurities such as Si or O into the surface 10a of the GaN substrate 10 and activating the n-type impurities by heat treatment. For example, Si is implanted into the source region 23 at a concentration of 1×10 19 cm -3 5x10 or more 20 cm -3 The source regions 23 are provided in the well region 13 below both sides of the gate electrode 22, and face the surface 10a of the GaN substrate 10. The source regions 23 are located inside the well region 13 and are in contact with the well region 13.

[0022] The contact region 15 is a p+ type layer formed by ion-implanting p-type impurities such as Mg into the surface 10a of the GaN substrate 10 and activating the p-type impurities by heat treatment. The contact region 15 is formed by ion-implanting Mg as a p-type impurity at a concentration of 3×10 18 cm -3 More than 1×10 21 cm -3 It is contained at a concentration of 1×10 or less, more preferably 1×10 19 cm -3 Over 2×10 20 cm -3 Contains the following concentrations:

[0023] The contact region 15 faces the surface 10a of the GaN substrate 10. The contact region 15 is located inside the well region 13 and is in contact with the well region 13. The contact region 15 also contacts the source region 23.

[0024] The well region 13 is connected to the source electrode 25 via the contact region 15. As a result, the potential of the well region 13 is fixed to the potential of the source electrode 25 (for example, a reference potential such as ground potential (GND)).

[0025] The gate insulating film 21 is, for example, an SiO2 film, and has a thickness of 100 nm. The gate electrode 22 is adjacent to a region where a channel is formed (hereinafter referred to as a channel region) via the gate insulating film 21. The gate electrode 22 is made of a metal such as Al, titanium (Ti), nickel (Ni), or tungsten (W), or polysilicon doped with impurities. The gate electrode 22 may also be made of a silicide such as WSi or NiSi.

[0026] Source electrode 25 is in ohmic contact with source region 23, which is an n+ type layer, and contact region 15, which is a p+ type layer. Drain electrode 26 is in ohmic contact with the other surface of n+ type GaN single crystal substrate 11 (i.e., the surface opposite to the surface in contact with GaN layer 12).

[0027] The source electrode 25 and the drain electrode 26 are made of Al or an Al-Si alloy, Ni, a Ni alloy, a Ti-Al alloy, a Ni-gold (Au) alloy, or the like. The source electrode 25 may have a barrier metal layer between it and the source region 23. The drain electrode 26 may have a barrier metal layer between it and the n+ type GaN single crystal substrate 11. The barrier metal layer may be made of Ti (titanium).

[0028] That is, the source electrode 25 and the drain electrode 26 may be a laminate of a Ti layer and an Al layer, or a laminate of a Ti layer and an Al-Si alloy layer. The source electrode 25 and the drain electrode 26 may be made of different materials or may have different laminate structures. The source electrode 25 may also serve as a source pad (not shown), or may be an electrode provided separately from the source pad. The drain electrode 26 may also serve as a drain pad (not shown), or may be an electrode provided separately from the drain pad.

[0029] 4 is an example (embodiment) of the present disclosure, and is a schematic diagram illustrating the Al concentration distribution in the depth direction from the surface of the well region 13 and the electron concentration distribution in the depth direction during channel formation. As shown in FIG. 4, no Al is added to the first region 131 of the well region 13. The Al concentration in the first region 131 is zero (0) or almost zero. On the other hand, Al is added to the second region 132 of the well region 13. The second region 132 has an Al concentration distribution in which the Al concentration is highest at the surface in contact with the gate insulating film 21 and the Al concentration continuously decreases from this surface in the depth direction (i.e., toward the first region 131).

[0030] That is, the second region 1132 is AlGaN having a gradient in which the Al composition ratio decreases in the depth direction. While FIG. 4 shows a case in which this gradient is linear, this gradient is not limited to a linear shape and may be curved or stepped. The thickness of the second region 132 (i.e., the depth from the surface of the well region 13 to the first region 131) is, for example, 50 nm or less, and more preferably 5 nm or less. The Al added to the second region 132 exists mainly as nitride.

[0031] The well region 13 is a p-type region doped with, for example, magnesium (Mg). This p-type region (i.e., Mg-doped region) contains a thin AlGaN (i.e., second region 132) with a gradient distribution of Al composition and a thickness of 50 nm or less. That is, the first region 131 and the second region 132 each contain Mg as a p-type impurity. During channel formation, electrons are widely distributed even deep within the second region 132, as shown in FIG. 4. That is, a buried channel distributed three-dimensionally is formed in the second region 132.

[0032] The surface 10a of the GaN substrate 10 is, for example, a polar plane. A first region 131 and a second region 132 are stacked on this polar plane. A polar plane is a plane in which, when a GaN crystal is cut along a certain plane, the atomic arrangement in the axial direction (the direction perpendicular to the plane) is not symmetrical.

[0033] (Manufacturing method) Next, manufacturing methods 1 to 3 will be described as methods for manufacturing the vertical MOSFET 1 described with reference to FIGS. 1 to 4. In manufacturing method 1, the second region 132 is formed by diffusing Al from an Al-containing nitride film into the surface 10a and its vicinity 10c of the GaN substrate 10. In manufacturing method 2, the second region 132 is formed by ion-implanting Al into the surface 10a and its vicinity 10c of the GaN substrate 10. In manufacturing method 3, the second region 132 is formed by epitaxial growth. Specific examples will be described in (1) to (3) below. The vertical MOSFET 1 is manufactured using various types of equipment, such as a film-forming apparatus, an exposure apparatus, an ion-implantation apparatus, a heat treatment apparatus, and an etching apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing apparatuses.

[0034] (1) Manufacturing method 1 5A to 5G are cross-sectional views sequentially illustrating a manufacturing method 1 of a vertical MOSFET 1 according to the first embodiment of the present disclosure. As shown in FIG. 5A, a manufacturing apparatus ion-implants Mg as a p-type impurity into a region 13′ of a GaN substrate 10 where a well region 13 (see FIG. 3) is to be formed (hereinafter referred to as a well formation region). For example, the manufacturing apparatus forms a mask M1 on a surface 10a of the GaN substrate 10. The mask M1 is an SiO film or photoresist that can be selectively removed from the GaN substrate 10. The mask M1 has a shape that opens above the well formation region 13′ and covers the other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M1 has been formed. After the ion implantation, the manufacturing apparatus removes the mask M1 from the GaN substrate 10.

[0035] In the Mg ion implantation step shown in FIG. 5A, the Mg ion implantation is performed so that the Mg concentration in the well formation region 13′ is 1×10 17 cm -3 The Mg implantation energy (acceleration voltage) and dose are set so that: The Mg ion implantation step shown in Fig. 5A may be performed as a single-stage ion implantation in which the acceleration energy is one condition, or as a multi-stage ion implantation in which the acceleration energy is multiple conditions.

[0036] Next, as shown in FIG. 5B, the manufacturing equipment ions-implants Si as an n-type impurity into a region 23′ in the GaN substrate 10 where a source region is to be formed (hereinafter referred to as a source formation region). For example, the manufacturing equipment forms a mask M2 on the GaN substrate 10. The mask M2 is an SiO2 film or a photoresist. The mask M2 has a shape that opens above the source formation region 23′ and covers above other regions. The manufacturing equipment ions-implants Si into the GaN substrate 10 on which the mask M2 has been formed. After the ion implantation, the manufacturing equipment removes the mask M2 from the GaN substrate 10.

[0037] In the Si ion implantation step shown in FIG. 5B, the Si ion implantation is performed so that the Si concentration in the source formation region 23′ is 1×10 19 cm -3 The Si implantation energy (acceleration voltage) and dose are set so that:

[0038] Next, as shown in FIG. 5C, the manufacturing equipment ion-implants Mg as a p-type impurity into a region 15′ of the GaN substrate 10 where the contact region 15 (see FIG. 3) is to be formed (hereinafter referred to as the contact formation region). For example, the manufacturing equipment forms a mask M3 on the surface 10a of the GaN substrate 10. The mask M3 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M3 has a shape that opens above the contact formation region 15′ and covers the above of other regions. The manufacturing equipment ion-implants Mg into the GaN substrate 10 on which the mask M3 has been formed. After the ion implantation, the manufacturing equipment removes the mask M3 from the GaN substrate 10.

[0039] In the Si ion implantation step shown in FIG. 5C, the Mg ion implantation is performed so that the Mg concentration in the contact formation region 15′ is 1×10 19 cm -3 The Mg implantation energy (acceleration voltage) and dose are set so that:

[0040] 5D, the manufacturing equipment then deposits an Al-containing nitride film, such as an aluminum nitride (AlN) film 31, on the surface 10a of the GaN substrate 10. The thickness of the AlN film 31 is, for example, 100 nm to 500 nm. The method for depositing the AlN film 31 is not particularly limited, but examples thereof include MOCVD (Metal Organic Chemical Vapor Deposition), sputtering, ALD (Atomic Layer Deposition), and PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0041] Next, as shown in FIG. 5E, the manufacturing equipment performs a heat treatment on the AlN film 31 and the GaN substrate 10 covered with the AlN film 31. This heat treatment is, for example, a rapid thermal treatment. The maximum temperature of this heat treatment is, for example, 1000°C or higher and 1500°C or lower, the heat treatment time at the maximum temperature is, for example, 1 minute or higher and 60 minutes or lower, and the heat treatment atmosphere is, for example, N2. As a result of this heat treatment, as shown in FIG. 5F, the Mg and Si introduced into the GaN substrate 10 are activated, forming the well region 13, the n+ type source region 23, and the p+ type contact region 15, and also defining the drift region 121.

[0042] This heat treatment also allows defects in the GaN substrate 10 caused by ion implantation to be repaired to some extent. Furthermore, the AlN film 31 has the function of suppressing the release of nitrogen atoms from the GaN substrate 10 during the heat treatment. Nitrogen vacancies are formed at positions where nitrogen atoms are released from the GaN substrate 10. Nitrogen vacancies can function as donor defects, which may inhibit the development of p-type characteristics. Since the GaN substrate 10 is heat-treated while covered with the AlN film 31, the release of nitrogen atoms can be suppressed, and the development of p-type characteristics can be prevented from being inhibited.

[0043] Furthermore, this heat treatment diffuses Al contained in the AlN film 31 from the AlN film 31 into the surface 10a of the GaN substrate 10 and its vicinity 10c (for example, within a range of 50 nm from the surface 10a in the depth direction, more preferably within a range of 5 nm from the surface 10a in the depth direction). As a result, a first region 131 to which Al is not added and a second region 132 to which Al is added are formed in the well region 13. The second region 132 is GaN to which Al has been added, i.e., AlGaN.

[0044] The Al concentration distribution in the second region 132 (AlGaN) has, for example, the form shown in Fig. 4. The Al concentration is highest at the surface of the second region 132 (i.e., the surface 10a of the GaN substrate 10), and decreases continuously or stepwise from the surface 10a toward the first region 131. The Al concentration at the surface of the second region 132 is, for example, 10 atomic % (at %) or more and 30 atomic % or less.

[0045] During this heat treatment, Al diffuses from the AlN film 31 into regions other than the well region 13, such as the source region 23 and the contact region 15. As a result, Al is added to the surface and its vicinity of the source region 23 and the surface and its vicinity of the contact region 15. After the heat treatment, the manufacturing equipment removes the AlN film 31 from the GaN substrate 10.

[0046] 5G, the manufacturing equipment forms a gate insulating film 21 on the surface 10a of the GaN substrate 10. As the gate insulating film 21, for example, an SiO2 film is formed to a thickness of 100 nm.

[0047] Next, the manufacturing equipment forms gate electrode 22 (see FIG. 3) and source electrode 25 (see FIG. 3). For example, a Ti film and an Al film are sequentially formed on front surface 10a of GaN substrate 10 on which gate insulating film 21 is formed, and then patterned to form gate electrode 22 and source electrode 25. The manufacturing equipment also forms drain electrode 26 (see FIG. 3) on rear surface 10b of GaN substrate 10. For example, a Ti film and an Al film are sequentially formed on rear surface 10b of GaN substrate 10, and then patterned to form drain electrode 26. Through the above steps, the vertical MOSFET 1 shown in FIG. 3 is completed.

[0048] (2) Manufacturing method 2 6A to 6C are cross-sectional views sequentially illustrating a manufacturing method 2 of a vertical MOSFET 1 according to the first embodiment of the present disclosure. In FIG. 6A, the manufacturing steps up to the step of ion-implanting Mg into the contact formation region 15' are the same as those described in FIG. 5C of manufacturing method 1. As shown in FIG. 5C, the manufacturing equipment ion-implants Mg into the GaN substrate 10 using the mask M3, and then removes the mask M3 from above the GaN substrate 10.

[0049] 6A, the manufacturing equipment implants Al ions into the surface 10a and its vicinity 10c of the GaN substrate 10. The dose of Al ions in this ion implantation is, for example, 1×10 21 cm -2 More than 1×10 22 cm -2 As a result, a first region 131' to which Al is not added and a second region 132' to which Al is added are formed in the well formation region 13'. The second region 132' is GaN to which Al is added, that is, AlGaN.

[0050] In this Al ion implantation, the implantation energy of the Al ions is adjusted so that the Al concentration is highest at the surface of the second region 132' (i.e., the surface 10a of the GaN substrate 10) and decreases continuously or stepwise from the surface 10a toward the first region 131. In addition, the implantation energy of the Al ions is adjusted so that the Al concentration at the surface of the second region 132' is, for example, 10 atomic % to 30 atomic %.

[0051] In this step, Al ions are also implanted into regions other than the well formation region 13′, such as the source formation region 23′ and the contact formation region 15′. Therefore, Al is also added to the surface of the source formation region 23′ and its vicinity, and the surface of the contact formation region 15′ and its vicinity. Note that in FIG. 6A, Al ions may be implanted into the well formation region 13′ while the source formation region 23′ and the contact formation region 15′ are covered with a mask (not shown). This may prevent Al ions from being implanted into the source formation region 23′ and the contact formation region 15′.

[0052] Next, as shown in FIG. 6B, the manufacturing equipment deposits an Al-containing nitride film, such as an AlN film 31, on the surface 10a of the GaN substrate 10. The thickness of the AlN film 31 is, for example, 100 nm to 500 nm. As with manufacturing method 1, the method for depositing the AlN film 31 is not particularly limited, but examples include MOCVD, sputtering, ALD, and PECVD. Alternatively, in manufacturing method 2, since Al has already been introduced into the surface 10a and its vicinity 10c of the GaN substrate 10, a protective film other than an AlN film may be deposited in the step of FIG. 6B. The protective film may be, for example, a SiO2 film or a SiN film, or a stacked film including at least one of an AlN film, a SiO2 film, and a SiN film.

[0053] Next, as shown in Fig. 6C, the GaN substrate 10 covered with the AlN film 31 (or protective film) is subjected to a heat treatment. The conditions for this heat treatment are, for example, the same as those for manufacturing method 1. This heat treatment activates the Mg and Si introduced into the GaN substrate 10, and as shown in Fig. 5F, a p-type well region 13, an n+ type source region 23, and a p+ type contact region 15 are formed, and a drift region 121 is also defined.

[0054] The subsequent steps are the same as in manufacturing method 1. After the heat treatment, the manufacturing equipment removes the AlN film 31 from the GaN substrate 10. Next, the manufacturing equipment forms a gate insulating film 21 (see FIG. 5G) on the front surface 10a of the GaN substrate 10. Next, the manufacturing equipment forms a gate electrode 22 (see FIG. 3) and a source electrode 25 (see FIG. 3). The manufacturing equipment also forms a drain electrode 26 (see FIG. 3) on the back surface 10b side of the GaN substrate 10. Through the above steps, the vertical MOSFET 1 shown in FIG. 3 is completed.

[0055] (3) Manufacturing method 3 7A to 7D are cross-sectional views sequentially illustrating a manufacturing method 3 of a vertical MOSFET 1 according to the first embodiment of the present disclosure. In FIG. 6A, a manufacturing apparatus epitaxially grows an n-type GaN layer 12 on an n+ type GaN single crystal substrate 11 to form a GaN substrate 10. In this epitaxial growth step, Al is added to the surface of GaN layer 12 and its vicinity (i.e., surface 10a and its vicinity 10c of GaN substrate 10), but not to other regions. That is, an AlGaN layer 12A is continuously grown epitaxially following an Al-free GaN layer 12NA.

[0056] In this epitaxial growth process, the Al composition is graded so that the Al concentration is highest at the surface of the AlGaN and decreases continuously or stepwise from the surface toward the depth, as shown in Figure 4. The thickness of the AlGaN formed by this epitaxial growth method is, for example, 50 nm or less, and more preferably, 5 nm or less. The Al concentration at the surface of the AlGaN is, for example, 10 atomic % (at %) or more and 30 atomic % or less.

[0057] 7B, the manufacturing equipment forms a mask M1 on the GaN substrate 10, the mask M1 having an opening above the well formation region 13' and a shape that covers the tops of other regions. Then, the manufacturing equipment uses the mask M1 to ion-implant Mg as a p-type impurity into the well formation region 13' of the GaN substrate 10. After the ion implantation, the manufacturing equipment removes the mask M1 from the GaN substrate 10.

[0058] 7C, the manufacturing equipment forms a mask M2 on the GaN substrate 10, the mask M2 having an opening above the source formation region 23′ and a shape that covers the tops of other regions. Then, the manufacturing equipment uses the mask M2 to ion-implant Si as an n-type impurity into the source formation region 23′ of the GaN substrate 10. After the ion implantation, the manufacturing equipment removes the mask M2 from the GaN substrate 10.

[0059] 7D, the manufacturing equipment forms a mask M3 on the GaN substrate 10, which has an opening above the contact formation region 15' and a shape that covers the upper portions of other regions. Then, the manufacturing equipment uses the mask M3 to ion-implant Mg as a p-type impurity into the contact formation region 15' of the GaN substrate 10. After the ion implantation, the manufacturing equipment removes the mask M3 from the GaN substrate 10.

[0060] 6B and thereafter in manufacturing method 2. The manufacturing equipment forms an Al-containing nitride film, such as an AlN film 31, on the surface 10a of the GaN substrate 10. Alternatively, since Al has already been introduced into the surface 10a of the GaN substrate 10 and its vicinity 10c, a protective film other than the AlN film 31 may be formed, as in manufacturing method 2.

[0061] Next, the manufacturing equipment applies heat treatment to the GaN substrate 10 covered with the AlN film 31 (or protective film). The conditions for this heat treatment are, for example, the same as those for manufacturing method 1. This heat treatment activates the Mg and Si introduced into the GaN substrate 10, and as shown in FIG. 5F, n+ type source region 23 and p+ type contact region 15 are formed, and drift region 121 is also defined.

[0062] After the heat treatment, the manufacturing equipment removes the AlN film 31 (or protective film) from the GaN substrate 10. Next, the manufacturing equipment forms a gate insulating film 21 (see FIG. 5G) on the front surface 10a of the GaN substrate 10. Next, the manufacturing equipment forms a gate electrode 22 (see FIG. 3) and a source electrode 25 (see FIG. 3). The manufacturing equipment also forms a drain electrode 26 (see FIG. 3) on the back surface 10b side of the GaN substrate 10. Through the above steps, the vertical MOSFET 1 shown in FIG. 3 is completed.

[0063] (Comparison with Comparative Examples 1 and 2) FIG. 8 is a schematic diagram illustrating Comparative Example 1 of the present disclosure, showing the Al concentration distribution in the depth direction from the surface of the well region 113 and the electron concentration distribution in the depth direction during channel formation. As shown in FIG. 8, in Comparative Example 1, Al is not added to the first region 1131 of the well region 113. The Al concentration in the first region 1131 is zero (0) or almost zero. On the other hand, Al is added to the second region 1132 of the well region 113. In Comparative Example 1, the Al concentration is constant in the depth direction from the surface in contact with the gate insulating film 21 (i.e., toward the first region 1131). That is, the second region 1132 is AlGaN, whose Al composition ratio is constant in the depth direction. The well region 113 is a p-type region doped with Mg. During channel formation, electrons are narrowly distributed at and near the interface between the first region 131 and the second region 132, as shown in FIG. 8. That is, a two-dimensional electron gas (2DEG) is formed at the interface.

[0064] Comparative Example 2 of the present disclosure is a vertical MOSFET in which the second region (AlGaN) is not present in the well region, and the channel is formed on the first region (GaN). Comparative Example 2 has a structure in which the second region 1132 (AlGaN) is removed from between the first region 1131 and the gate insulating film 21 (SiO2) in Figure 8. In Comparative Example 2, the channel is formed at the GaN / SiO2 interface.

[0065] FIG. 9 is a graph showing the results of an experiment conducted by the present inventors, comparing the field-effect mobility of Example and Comparative Example 2. In the data shown in FIG. 9, Example is a vertical MOSFET in which p-type well region 13 is configured with a first region 131 to which Al is not added and a second region 132 to which Al is added and whose composition ratio is graded in the depth direction, as shown in FIG. 4. As shown in FIG. 9, it was confirmed that Example had a higher field-effect mobility than Comparative Example 2, which did not have the second region (AlGaN). If the field-effect mobility of Comparative Example 2 was set to 1, the field-effect mobility of Example was 8 or more.

[0066] Unlike a channel formed at the GaN / SiO2 interface, which is subject to scattering and trapping due to interface defects and the like (when no composition-graded AlGaN is formed), the embodiments of the present disclosure can form a three-dimensional channel inside the crystal of the second region 132 (AlGaN) of the well region 13, so that the channel mobility approaches the bulk mobility and minority carriers (e.g., electrons) are less likely to be trapped.

[0067] Furthermore, in the examples of the present disclosure, the second region 132 (AlGaN) has a graded composition, which reduces polarization charge generated in the AlGaN and facilitates threshold voltage control. This point will be described in more detail with reference to FIGS. 10 and 11. FIG. 10 is a graph schematically showing the lattice constant difference between AlGaN and GaN in the well region 13 according to the examples of the present disclosure. FIG. 11 is a graph schematically showing the lattice constant difference between AlGaN and GaN in the well region 113 according to Comparative Example 1 of the present disclosure. As can be seen from comparing FIGS. 10 and 11, the Al composition ratio in the AlGaN in the examples is graded, and this graded distribution results in a gradual difference in the lattice constant with GaN. This gradual difference in lattice constant results in a small piezoelectric polarization charge. In contrast, in Comparative Example 1, the Al composition ratio in the AlGaN is constant, and the difference in lattice constant with GaN is large. This large difference in lattice constant results in a large piezoelectric polarization charge. Therefore, the examples of the present disclosure provide easier control of the threshold voltage than Comparative Example 1.

[0068] (Effects of the First Embodiment) As described above, GaN semiconductor device 100 according to embodiment 1 of the present disclosure includes n-type GaN substrate 10, p-type well region 13 provided in GaN substrate 10, and gate insulating film 21 provided on the surface 10a side of GaN substrate 10 and covering well region 13. Well region 13 has first region 131 to which Al is not added, and second region 132 provided on first region 131 to which Al is added. Second region 132 has an Al concentration distribution in which the Al concentration is highest at surface 10a in contact with gate insulating film 21 and decreases continuously or stepwise from surface 10a toward first region 131.

[0069] According to this, the Al compound layer formed inside the crystal of the GaN substrate 10 forms a three-dimensional channel, which reduces scattering effects and traps present at the interface with the gate insulating film 21, and brings the channel mobility closer to bulk mobility. This improves channel mobility and reduces channel resistance. In a vertical MOSFET 1 formed on the GaN substrate 10, the channel resistance accounts for a large proportion of the on-resistance, so reducing the channel resistance can reduce the on-resistance. From the above, a vertical MOSFET 1 with high channel mobility and low on-resistance can be realized. Below, the effects of this embodiment, including issues with vertical MOSFETs, will be described in more detail.

[0070] Reducing the on-resistance of a MOSFET can reduce power loss during operation. The on-resistance of a MOSFET is the total resistance between the drain and source. Since the thickness of the drift layer (which generates drift resistance) varies depending on the target value of the vertical MOSFET's withstand voltage, the dominant resistance factor for the on-resistance of the vertical MOSFET changes.

[0071] In vertical MOSFETs formed on GaN substrates, when the target breakdown voltage is in the 1 kV range, channel resistance becomes a large component, accounting for several tens of percent of the on-resistance. One possible way to reduce channel resistance is to improve channel mobility. Channel mobility indicates the ease of transport of minority carriers in the inversion layer (i.e., the channel) formed on the surface of the GaN substrate. For example, if minority carriers are scattered by charged defects in the gate insulating film or by unevenness on the surface of the GaN substrate, channel mobility decreases and channel resistance increases.

[0072] In the first embodiment, a region in which Al is present in a diffusion-shaped distribution is formed in the GaN crystal by thermal diffusion. An Al compound layer is formed having a gradient composition determined by the thermal diffusion of Al in the GaN substrate, such that the Al composition ratio gradually decreases from the surface of the GaN substrate toward the depth direction. The thickness of the Al compound layer is determined by the diffusion constant of Al in the GaN substrate, and therefore variation is expected to be small. Furthermore, compared to Comparative Example 1 (constant Al concentration) shown in FIG. 11, the Al compound layer having a gradient Al composition ratio as in the first embodiment has a lattice constant closer to that of GaN, and therefore the amount of polarization charge is expected to be suppressed, and mass production stability (applicability for mass production) is expected to be high.

[0073] Furthermore, by forming a compositionally graded Al compound layer inside the GaN crystal by thermal diffusion, the channel mobility becomes approximately 50% of the bulk mobility, achieving a dramatic improvement in mobility. This is thought to be because the Al compound layer formed inside the GaN crystal forms a three-dimensional channel, which becomes a buried channel, reducing the scattering effect present at the interface with the gate insulating film. As a result, a vertical MOSFET with high channel mobility and low on-resistance can be realized, while also being suitable for mass production.

[0074] (Variation) In the manufacturing methods 1 to 3 of the first embodiment described above, the impurities contained in the well formation region 13′, the source formation region 23′, and the contact formation region 15′ are activated by the heat treatment shown in FIG. 5E to simultaneously form the p-type well region 13, the n+ type source region 23, and the p+ type contact region 15′. However, in this embodiment, the well region 13, the source region 23, and the contact region 15 may be formed separately by heat treatment at different times, rather than simultaneously. For example, the p-type well region 13 may be formed by ion-implanting Mg into the well formation region 13′, forming a protective film, and performing a first heat treatment. Then, Si may be ion-implanted into the source formation region 23′, Mg ion-implanted into the contact formation region 15′, forming a protective film, and performing a second heat treatment to form the n+ type source region 23 and the p+ type contact region 15. Performing the first and second heat treatments separately allows for a wider range of options and facilitates individual control of the characteristics of the well region 13 and the source region 23, for example. This modification may be applied not only to the first embodiment but also to each of the embodiments described below.

[0075] <Embodiment 2> 12 is a cross-sectional view showing a configuration example of a vertical MOSFET 1A (unit structure) according to embodiment 2 of the present disclosure. As shown in Fig. 12, the vertical MOSFET 1A includes an n-type JFET region 41 (an example of a "high-concentration region" in the present disclosure) provided in a GaN layer 12 and having a higher n-type impurity concentration than an n-type drift layer. The JFET region 41 is located between one well region 13 and the other well region 13 adjacent to each other in the horizontal direction (e.g., the X-axis direction).

[0076] Like the well region 13, the JFET region 41 also has Al added to its surface and its vicinity. The Al concentration distribution in the JFET region 41 has a tendency to be highest at the surface and decrease continuously or stepwise from the surface toward the depth (for example, toward the drift region 121). The inclusion of the JFET region reduces the on-resistance of the vertical MOSFET 1A. The rest of the configuration is the same as that of the vertical MOSFET 1 described in the first embodiment.

[0077] 13 is a cross-sectional view showing a manufacturing method of a vertical MOSFET 1A according to the second embodiment of the present disclosure. In FIG. 13, the manufacturing process up to the step of implanting Mg ions into the contact formation region 15' is the same as the manufacturing process described in FIG. 5C of Manufacturing Method 1 of the first embodiment. As shown in FIG. 5C, the manufacturing equipment implants Mg ions into the GaN substrate 10 using the mask M3, and then removes the mask M3 from above the GaN substrate 10.

[0078] Next, as shown in FIG. 13, the manufacturing equipment ion-implants Si as an n-type impurity into a region (hereinafter, JFET formation region) 41′ where a JFET region 41 (see FIG. 12) is to be formed. For example, the manufacturing equipment forms a mask M4 on the surface 10a of the GaN substrate 10. The mask M4 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M4 has a shape that opens above the JFET formation region 41′ and covers above other regions. The manufacturing equipment ion-implants Si into the GaN substrate 10 on which the mask M4 has been formed. After the ion implantation, the manufacturing equipment removes the mask M4 from the GaN substrate 10. The subsequent steps are the same as the steps from FIG. 5D onward in Manufacturing Method 1 of Embodiment 1. Through the above steps, the vertical MOSFET 1A shown in FIG. 12 is completed.

[0079] In the vertical MOSFET 1A according to the second embodiment, as in the vertical MOSFET 1 according to the first embodiment, the second region 132 has an Al concentration distribution in which the Al concentration is highest at the surface 10a in contact with the gate insulating film 21 and decreases continuously or stepwise from the surface 10a toward the first region 131. This allows a three-dimensional channel to be formed in the second region 132, thereby realizing a vertical MOSFET with high channel mobility and low on-resistance. Furthermore, the vertical MOSFET 1A includes the JFET region 41, which enables the on-resistance to be reduced.

[0080] <Embodiment 3> In the above-described first and second embodiments, the vertical MOSFETs 1 and 1A are of the planar type. However, in the embodiments of the present disclosure, the vertical MOSFET is not limited to the planar type and may be of the trench gate type.

[0081] 14 is a cross-sectional view showing a configuration example of a vertical MOSFET 1B (unit structure) according to Embodiment 3 of the present disclosure. As shown in FIG. 14, the vertical MOSFET 1B according to Embodiment 3 has a trench H provided in a GaN substrate 10. The trench H opens to the surface 10a side of the GaN substrate 10. The trench H is formed deeper than the p-type well region 13, and the bottom of the trench H reaches the n-type GaN layer 12 (drift region 121).

[0082] A gate insulating film 21 and a gate electrode 22 are disposed inside the trench H. The inner side and bottom surfaces of the trench H are covered with the gate insulating film 21. The gate electrode 22 is buried in the trench H via the gate insulating film 21. In the trench-gate vertical MOSFET 1B, a region of the well region 13 that faces the gate electrode 22 via the gate insulating film 21 provided on the side surface of the trench H serves as a channel region.

[0083] In the vertical MOSFET 1B according to the third embodiment, the well region 13 also includes a first region 131 to which Al is not added, and a second region 132 provided on the first region and to which Al is added. The second region 132 faces the side surface of the trench H and is in contact with the gate insulating film 21 at the side surface of the trench H. The second region 132 and the first region 131 are arranged in this order in the horizontal direction (e.g., the X-axis direction) from the side surface of the trench H. The second region 132 has an Al concentration distribution in which the Al concentration is highest at a surface in contact with the gate insulating film 21 (an example of the "first surface" in the present disclosure) and decreases continuously or stepwise from the surface in contact with the gate insulating film 21 toward the first region 131.

[0084] In the GaN substrate 10, the side surface of the trench H is, for example, a nonpolar surface. The nonpolar surface may also be referred to as a nonpolar plane. The first region 131 and the second region 132 are stacked on this nonpolar surface. A nonpolar surface is a surface in which, when a GaN crystal is cut along a certain plane, the atomic arrangement is symmetrical in the axial direction (the direction perpendicular to the plane).

[0085] Next, a manufacturing method will be described. Figures 15A to 15G are cross-sectional views showing a manufacturing method of a vertical MOSFET 1B according to embodiment 3 of the present disclosure. In Figure 15A, a manufacturing apparatus epitaxially grows, for example, an n-type GaN layer 12 containing Si as an n-type impurity and a p-type GaN layer containing Mg as a p-type impurity (i.e., p-type well region 13) sequentially on a GaN single crystal substrate 11.

[0086] Next, the manufacturing equipment forms a mask M2 on the GaN substrate 10, which has an opening above the source formation region 23' and a shape that covers the tops of other regions. Then, the manufacturing equipment uses the mask M2 to ion-implant Si as an n-type impurity into the source formation region 23' of the GaN substrate 10. After the ion implantation, the manufacturing equipment removes the mask M2 from the GaN substrate 10.

[0087] 15B, the manufacturing equipment forms a mask M3 on the GaN substrate 10, which has an opening above the contact formation region 15' and a shape that covers the upper portions of other regions. Then, the manufacturing equipment uses the mask M3 to ion-implant Mg as a p-type impurity into the contact formation region 15' of the GaN substrate 10. After the ion implantation, the manufacturing equipment removes the mask M3 from the GaN substrate 10.

[0088] 15C, the manufacturing equipment forms a mask M5 on the GaN substrate 10. The mask M5 has an opening above a region where trench H is to be formed and a shape that covers the other regions. The manufacturing equipment then dry-etches the GaN substrate 10 using the mask M5 to form trench H. After trench H is formed, the manufacturing equipment removes mask M5 from the GaN substrate 10.

[0089] 15D, the manufacturing equipment deposits an Al-containing nitride film, such as an aluminum nitride (AlN) film 31, on the surface 10a of the GaN substrate 10. In the third embodiment, the AlN film 31 is deposited not only on the surface 10a of the GaN substrate 10 but also on the side and bottom surfaces of the trenches H. The thickness of the AlN film 31 is, for example, 100 nm or more and 500 nm or less. The method for depositing the AlN film 31 is not particularly limited, but examples thereof include MOCVD, sputtering, ALD, and PECVD.

[0090] Next, as shown in Fig. 15E, the manufacturing equipment performs a heat treatment on the AlN film 31 and the GaN substrate 10 covered with the AlN film 31. The conditions for this heat treatment are the same as those in manufacturing method 1 of embodiment 1. By this heat treatment, as shown in Fig. 5F, the Mg and Si introduced into the GaN substrate 10 are activated, and an n+ type source region 23 and a p+ type contact region 15 are formed.

[0091] Furthermore, this heat treatment causes Al contained in the AlN film 31 to diffuse from the AlN film 31 to the surface 10a and its vicinity 10c of the GaN substrate 10. In the third embodiment, Al also diffuses horizontally from the AlN film 31 covering the side surfaces of the trenches H. The diffusion of Al from the AlN film 31 to the GaN substrate 10 is within a range of up to 50 nm from the surface 10a of the GaN substrate 10 in the depth direction (or horizontally from the side surfaces of the trenches H), more preferably within a range of up to 5 nm from the surface 10a in the depth direction (or horizontally from the side surfaces of the trenches H). As a result, as shown in FIG. 15F , a first region 131 to which Al is not added and a second region 132 to which Al is added are formed in the well region 13. The second region 132 is GaN to which Al is added, i.e., AlGaN. The second region 132 (AlGaN) is formed on the side surfaces of the trenches H and in their vicinity. After the heat treatment, the manufacturing equipment removes the AlN film 31 from the GaN substrate 10.

[0092] 15G, the manufacturing equipment forms a gate insulating film 21 on the surface 10a side of the GaN substrate 10. As the gate insulating film 21, for example, a SiO film is formed to a thickness of 100 nm. The gate insulating film 21 is formed not only on the surface 10a of the GaN substrate 10 but also on the side surfaces and bottom surfaces of the trench H.

[0093] Next, the manufacturing equipment forms a gate electrode 22 (see FIG. 14) and a source electrode 25 (see FIG. 14) on the front surface 10a of the GaN substrate 10 on which the gate insulating film 21 has been formed. The gate electrode 22 is formed so as to be embedded in the trench H via the gate insulating film 21. Next, the manufacturing equipment forms a drain electrode 26 (see FIG. 14) on the back surface 10b of the GaN substrate 10. Through the above steps, the vertical MOSFET 1B shown in FIG. 14 is completed.

[0094] In the vertical MOSFET 1B according to the third embodiment, as in the vertical MOSFET 1 according to the first embodiment, the second region 132 has an Al concentration distribution in which the Al concentration is highest at a surface in contact with the gate insulating film 21 (for example, a side surface of the trench H) and decreases continuously or stepwise from the surface 10a toward the first region 131. This allows a three-dimensional channel to be formed in the second region 132, thereby realizing a vertical MOSFET with high channel mobility and low on-resistance. Furthermore, because the vertical MOSFET 1B is a trench-gate type, the cell pitch can be made shorter than that of a planar vertical MOSFET, thereby enabling further reduction in on-resistance.

[0095] <Embodiment 4> FIG. 16 is a cross-sectional view showing a configuration example of a vertical MOSFET 1C (unit structure) according to Embodiment 4 of the present disclosure. As shown in FIG. 16, in the vertical MOSFET 1C according to Embodiment 3, the drift region 121 has a superjunction structure (i.e., an SJ structure). For example, the drift region 121 has an n-type pillar 121n and a p-type pillar 121p (an example of a "second conductivity type pillar" in the present disclosure). The n-type pillar 121n and the p-type pillar 121p are adjacent to each other in the horizontal direction (e.g., the X-axis direction). The p-type pillar 121p is provided from the bottom of the well region 13 toward the back surface 12b of the GaN layer 12 and is in contact with the well region 13 and the GaN single crystal substrate 11. The n-type pillar 121n is located between one pillar 121p and the other pillar 121p adjacent to each other in the horizontal direction.

[0096] The pillar 121p has the same or almost the same p-type impurity concentration as the well region 13. The pillar 121n has a lower n-type impurity concentration than the source region 23. The pillar 121n functions as a current path between the GaN single crystal substrate 11 and the well region 13. The rest of the configuration is the same as that of the vertical MOSFET 1 described in the first embodiment.

[0097] 17 is a cross-sectional view showing a manufacturing method of a vertical MOSFET 1C according to the fourth embodiment of the present disclosure. In FIG. 17, the manufacturing process up to the step of implanting Mg ions into the well formation region 13′ is the same as the manufacturing process described in FIG. 5A of Manufacturing Method 1 of the first embodiment. As shown in FIG. 5A, the manufacturing equipment implants Mg ions into the GaN substrate 10 using a mask M1, and then removes the mask M1 from above the GaN substrate 10.

[0098] Next, as shown in FIG. 17, the manufacturing equipment ion-implants Mg as a p-type impurity into a region 121p' (hereinafter referred to as a pillar formation region) where a pillar 121p (see FIG. 17) is to be formed. For example, the manufacturing equipment forms a mask M6 on the surface 10a of the GaN substrate 10. The mask M6 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M6 has a shape that opens above the pillar formation region 121p' and covers above other regions. The manufacturing equipment ion-implants Mg deeply into the GaN substrate 10 on which the mask M6 has been formed. After the ion implantation, the manufacturing equipment removes the mask M6 from the GaN substrate 10. For example, in the n-type GaN layer 12, a region other than the well formation region 13' and the pillar formation region 121p' becomes an n-type pillar 121n. The subsequent steps are the same as the steps from FIG. 5B onward in Manufacturing Method 1 of Embodiment 1. 5E activates Mg and Si introduced into the GaN substrate 10, forming the well region 13, the pillar 121p, the n+ type source region 23, and the p+ type contact region 15, and also defining the pillar 121n. Through the above steps, the vertical MOSFET 1C shown in FIG. 16 is completed.

[0099] In the vertical MOSFET 1C according to the fourth embodiment, similarly to the vertical MOSFET 1 according to the first embodiment, the second region 132 has an Al concentration distribution in which the Al concentration is highest at the surface 10a in contact with the gate insulating film 21 and decreases continuously or stepwise from the surface 10a toward the first region 131. This allows a three-dimensional channel to be formed in the second region 132, thereby realizing a vertical MOSFET with high channel mobility and low on-resistance.

[0100] Furthermore, since the vertical MOSFET 1C includes the drift region 121 with an SJ structure, the impurity concentration of the n-type pillars 121n can be increased while suppressing a decrease in breakdown voltage, thereby reducing the drift resistance. This makes it possible to further reduce the on-resistance of the vertical MOSFET. By further reducing the on-resistance, the contribution of the channel resistance to the on-resistance becomes even greater. The presence of the second region 132 (composition-graded Al layer) further enhances the effect of reducing the channel resistance.

[0101] (Variation) In the above-described fourth embodiment, the p-type pillars 121p are formed by deep ion implantation of Mg into the GaN substrate 10 on which the mask M6 is formed. However, the method of forming the p-type pillars 121p in the fourth embodiment is not limited to this. The p-type pillars 121p may be formed by a multi-stage epitaxial growth method. For example, the p-type pillars 121p may be formed by repeating multiple times the steps of forming a GaN layer by epitaxial growth and implanting Mg ions into the GaN layer formed by epitaxial growth using the mask M6, and then performing the heat treatment shown in FIG. 5E. The vertical MOSFET 1C shown in FIG. 16 may be manufactured by this method.

[0102] <Embodiment 5> In the above-described first to fourth embodiments, the gate insulating film 21 is an SiO2 film, but this embodiment is not limited to this. In the above-described first to fourth embodiments, the gate insulating film 21 may be an insulating film other than an SiO2 film (for example, an aluminum oxide film (Al2O3 film)), or may be an insulating film with a stacked structure including at least one of an SiO2 film and an Al2O3 film.

[0103] 18 is a cross-sectional view showing a configuration example of a vertical MOSFET 1D (unit structure) according to Embodiment 5 of the present disclosure. As shown in Fig. 18, the gate insulating film 21 has a silicon oxynitride film (SiON film 211; an example of a "Si oxynitride film" in the present disclosure) and a silicon oxide film (SiO2 film 212; an example of a "Si oxide" in the present disclosure) provided on the SiON film 211. The SiON film 211 and the SiO2 film 212 are stacked in this order on the GaN layer 12.

[0104] The thickness of the SiON film 211 is thinner than the thickness of the SiO2 film 212. For example, the thickness of the SiON film 211 is 0.5 nm or more and 5 nm or less, and the thickness of the SiO2 film 212 is 30 nm or more and 200 nm or less.

[0105] As a modification, the gate insulating film 21 may have an aluminum oxide film (Al2O3 film; an example of "Al oxide" in the present disclosure) instead of the SiO2 film 212. Alternatively, the gate insulating film 21 may be an insulating film in which a SiON film, a SiO2 film, and an Al2O3 film are stacked in this order from the surface 10a of the GaN substrate 10. The rest of the configuration is the same as that of the vertical MOSFET 1 described in the first embodiment.

[0106] The vertical MOSFET 1D according to the fifth embodiment, like the vertical MOSFET 1 according to the first embodiment, can form a three-dimensional channel in the second region 132, thereby realizing a vertical MOSFET with high channel mobility and low on-resistance. Furthermore, since the vertical MOSFET 1D has a SiON film below the SiO2 film 212 (or Al2O3 film), surface oxidation of the GaN layer 12 can be suppressed during deposition of the SiO2 film 212 (or Al2O3 film), and thus generation of positive fixed charges can be suppressed. This enables an increase in threshold voltage.

[0107] <Embodiment 6> In the embodiment of the present disclosure, there may be a difference in not only the Al concentration but also the Mg concentration between the first region 131 and the second region 132 of the well region 13. (1) Configuration example 1 FIG. 19 is a diagram schematically illustrating a vertical MOSFET 1E (Configuration Example 1) according to Embodiment 6 of the present disclosure. Specifically, the diagram on the right side of FIG. 19 is a cross-sectional view illustrating the configuration example of the vertical MOSFET 1E (unit structure), the diagram on the left side of FIG. 19 is a graph illustrating the Al concentration distribution (hereinafter also referred to as Al distribution) and the Mg concentration distribution (hereinafter also referred to as Mg distribution) (1) in the first region 131 and the second region 132, and the diagram in the center of FIG. 19 is a cross-sectional view illustrating an enlarged view of the first region 131 and the second region 132. The vertical axis of the graph on the left side of FIG. 19 indicates the depth from the surface 10a of the GaN substrate 10 (for example, the surface where the second region 132 and the gate insulating film 21 contact each other), and the horizontal axis indicates the impurity concentration. The horizontal axis of FIG. 19 indicates the impurity concentration. x (x is an integer) is 1×10xcm -3 means.

[0108] Similar to the vertical MOSFETs described in the above embodiments, the vertical MOSFET 1E shown in FIG. 19 also has a well region 13 including a first region 131 to which no Al is added (i.e., the Al concentration is zero (0) or approximately zero) and a second region 132 provided on the first region 131 and to which Al is added. The second region 132 has an Al concentration distribution in which the Al concentration is highest at a surface 10a in contact with the gate insulating film 21 and decreases continuously or stepwise from the surface 10a toward the first region 131. FIG. 19 shows, as an example, an aspect in which the Al concentration decreases continuously from the surface 10a toward the first region 131.

[0109] In the vertical MOSFET 1E, the second region 132 contains Mg at a higher concentration than the first region 131. The second region 132 is p-type, and the first region 131 is p-type. The maximum value (i.e., peak value) of the Mg concentration in the second region 132 is higher than the maximum value of the Mg concentration in the first region 131. For example, in the second region 132, the Mg concentration is highest at the surface 10a in contact with the gate insulating film 21 and in the vicinity thereof. In the following description, the Mg concentration at the surface 10a in contact with the gate insulating film 21 and in the vicinity thereof will also be referred to as the surface Mg concentration. The surface Mg concentration of the second region 132 is, for example, 5×10 18 cm -3 5x10 or more 19cm -3 For example, it is about 1 × 10 19 cm -3 The boundary between the first region 131 and the second region 132 is, for example, in the range of 0.5 nm to 3 nm in the depth direction from the surface 10a.

[0110] 19, the second region 132 has a Mg concentration distribution in which the Mg concentration continuously increases from the first region 131 side toward the surface 10a in contact with the gate insulating film 21. That is, the second region 132 has a compositionally graded profile in which the Mg concentration gradually increases from the first region 131 side toward the surface 10a in contact with the gate insulating film 21. For example, the Mg concentration at the boundary between the first region 131 and the second region 132 is 5×10 16 cm -3 5x10 or more 17 cm -3 For example, 1×10 17 cm -3 The second region 132 has a Mg concentration distribution in which the Mg concentration increases continuously from the boundary with the first region 131 toward the surface 10a.

[0111] The Mg concentration in the first region 131 is highest at the boundary between the first region 131 and the second region 132. The Mg concentration in the first region 131 is constant in the depth direction, for example, and is, for example, 1×10 17 cm -3 The first region 131 does not have a composition gradient.

[0112] In the vertical MOSFET 1E (Configuration Example 1) according to Embodiment 6, similarly to the vertical MOSFET 1 according to Embodiment 1, the second region 132 has an Al concentration distribution in which the Al concentration is highest at the surface 10a in contact with the gate insulating film 21 and decreases continuously or stepwise from the surface 10a toward the first region 131. This allows a three-dimensional channel to be formed in the second region 132, thereby realizing a vertical MOSFET with high channel mobility and low on-resistance.

[0113] By using compositionally graded AlGaN for the second region 132, a channel is formed in a region away from the surface 10a of the second region 132. Therefore, even if the surface Mg concentration of the second region 132 is increased as a countermeasure against hole traps, it is possible to prevent the threshold voltage from becoming too high or the channel mobility from becoming too low. It is possible to achieve both low hole traps and high mobility.

[0114] (2) Configuration example 2 In the above-described Configuration Example 1, it has been described that the Mg concentration in the second region 132 increases continuously from the first region 131 side toward the surface 10a in contact with the gate insulating film 21. However, the increase in the Mg concentration may be stepwise rather than continuously. FIG. 20 is a diagram schematically illustrating a vertical MOSFET 1F (Configuration Example 2) according to Embodiment 6 of the present disclosure. As in FIG. 19, in FIG. 20 as well, the diagram on the right is a cross-sectional view illustrating a configuration example of a unit structure, the diagram on the left is a graph showing Al distribution and Mg distribution (2), and the diagram in the center is an enlarged view of the first region 131 and the second region 132. The vertical and horizontal axes of the graph in FIG. 20 are also described in the same manner as in FIG. 19.

[0115] 20 differs from Configuration Example 1 in the Mg concentration distribution in the second region 132. The second region 132 of MOSFET 1F has a Mg concentration distribution in which the Mg concentration increases stepwise from the first region 131 side toward the surface 10a in contact with the gate insulating film 21. For example, the second region 132 has a high concentration only at and near the surface 10a, and below that, has the same Mg concentration distribution as the first region 131. If the surface 10a and its vicinity of the second region 132 and the area below that are referred to as an upper region 1322 and a lower region 1321, respectively, the upper region 1322 is p-type and the lower region 1321 is p-type.

[0116] For example, the Mg concentration in the upper region 1322 is 5×10 16 cm -3 5x10 or more 17 cm -3 For example, 1×10 17 cm -3The Mg concentration in the lower region 1321 and the p-type first region 131 is constant in the depth direction, for example, and is 1×10 17 cm -3 The rest of the configuration is the same as in Configuration Example 1.

[0117] The vertical MOSFET 1F (Configuration Example 2) has an Al concentration distribution similar to that of the vertical MOSFET 1E (Configuration Example 1), and therefore a three-dimensional channel can be formed in the second region 132. This allows for a vertical MOSFET with high channel mobility and low on-resistance to be realized. Also in Configuration Example 2, as in Configuration Example 1, the channel is formed in a region away from the surface 10a of the second region 132. Therefore, even if the surface Mg concentration of the second region 132 is increased as a countermeasure against hole traps, it is possible to prevent the threshold voltage from becoming too high or the channel mobility from becoming too low. Low hole traps and high mobility can both be achieved.

[0118] (3) Configuration example 3 In the above-described Configuration Example 1, the Mg concentration in the first region 131 is constant in the depth direction. However, the Mg concentration in the first region 131 may not be constant in the depth direction but may decrease in the depth direction. In other words, the Mg concentration in the first region 131 may increase toward the second region 132. FIG. 21 is a diagram schematically illustrating a vertical MOSFET 1G (Configuration Example 3) according to Embodiment 6 of the present disclosure. As in FIG. 19, in FIG. 21, the diagram on the right is a cross-sectional view illustrating a configuration example of a unit structure, the diagram on the left is a graph showing Al distribution and Mg distribution (3), and the diagram in the center is an enlarged view of the first region 131 and the second region 132. The vertical and horizontal axes of the graph in FIG. 21 are also described in the same manner as in FIG. 19.

[0119] 21 differs from Configuration Example 1 in the Mg concentration distribution in first region 131. First region 131 of MOSFET 1G has an Mg concentration distribution in which the Mg concentration increases continuously or stepwise from the n-type GaN layer 12 side toward the boundary with second region 132. That is, first region 131 has a compositionally graded profile in which the Mg concentration gradually increases from the n-type GaN layer 12 side toward the boundary with second region 132. If the side of first region 131 closer to the boundary with second region 132 is defined as upper region 1312 and the side farther from the boundary with second region 132 is defined as lower region 1311, upper region 1312 is a p-type with a graded composition, and lower region 1311 is a p-type without a graded composition.

[0120] For example, the Mg concentration at the boundary between the upper region 1312 and the lower region 1311 is 1×10 17 cm -3 The Mg concentration in the lower region 1311 is constant in the depth direction, whereas the Mg concentration in the upper region 1312 increases continuously toward the boundary with the second region 132. The Mg concentration in the first region 131 is highest at the boundary between the upper region 1312 and the second region 132. The Mg concentration at this boundary is 5×10 17 cm -3 is.

[0121] Although both are p-type, the second region 132 has a higher Mg concentration than the upper region 1312 of the first region 131. Furthermore, the proportion of the composition gradient is greater in the second region 132 than in the upper region 1312. In other words, the concentration gradient (slope) of Mg in the depth direction is greater in the second region 132 than in the first region 131. The Mg concentration increases more steeply in the second region 132 than in the first region 131. Other configurations are the same as in Configuration Example 1.

[0122] The vertical MOSFET 1G (Configuration Example 3) has an Al concentration distribution similar to that of the vertical MOSFET 1E (Configuration Example 1), and therefore a three-dimensional channel can be formed in the second region 132. This allows for a vertical MOSFET with high channel mobility and low on-resistance to be realized. Also in Configuration Example 3, as in Configuration Example 1, the channel is formed in a region away from the surface 10a of the second region 132. Therefore, even if the surface Mg concentration of the second region 132 is increased as a countermeasure against hole traps, it is possible to prevent the threshold voltage from becoming too high or the channel mobility from becoming too low. Low hole traps and high mobility can both be achieved.

[0123] (4) Manufacturing method 1 Next, a method for manufacturing a vertical MOSFET according to an embodiment of the present disclosure will be described. (1) Manufacturing method 1 22A to 22H are cross-sectional views illustrating a manufacturing method 1 of a vertical MOSFET according to a sixth embodiment of the present disclosure in the order of steps. In FIG. 22A, a manufacturing apparatus forms a through film 51 on the surface 10a of a GaN substrate 10. The through film 51 is, for example, a SiO2 film. Here, the through film 51 is formed to a predetermined thickness so that the Mg implantation peak is at or near the surface 10a of the GaN substrate 10 in the high-concentration Mg ion implantation step shown in FIG. 22B, which will be described later. That is, the through film 51 is formed to a predetermined thickness so that the Mg concentration in the second region 132 is highest at or near the surface 10a.

[0124] For example, the relationship between the film thickness of the through film 51, the Mg implantation energy (acceleration voltage), and the Mg concentration distribution (profile) in the depth direction of the GaN substrate 10 is investigated in advance by experiment or simulation. Then, based on the above relationship, the film thickness of the through film 51 when the Mg implantation peak occurs at or near the surface 10a of the GaN substrate 10 when Mg ions are implanted through the through film 51 with a preset implantation energy is determined. In FIG. 22A, the through film 51 is formed to have this film thickness. The method for forming the through film 51 is not particularly limited, and may be, for example, a CVD method.

[0125] Before performing the high-concentration ion implantation of Mg, the manufacturing equipment ion-implants Mg as a p-type impurity at a low concentration into the well formation region 13' of the GaN substrate 10, as shown in Fig. 22A. For example, the manufacturing equipment forms a mask M1 on the through film 51, and ion-implants Mg at a low concentration into the GaN substrate 10 on which the mask M1 has been formed, via the through film 51. In the low-concentration ion implantation step of Mg shown in Fig. 22A, the Mg ion-implanted Mg concentration in the well formation region 13' is set to 1×10 17 cm -3 The Mg implantation energy (acceleration voltage) and dose are set so that: This low concentration ion implantation step may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0126] Next, as shown in FIG. 22B, the manufacturing equipment uses the mask M1 as it is to ion-implant Mg as a p-type impurity at a high concentration into the surface 10a of the well formation region 13′ and its vicinity, thereby forming an Mg high-concentration layer 150 on the surface 10a and its vicinity.

[0127] For example, as shown in the Mg distribution (2) in the graph of Fig. 20, Mg ions are implanted into at least the second region 132 so that the maximum value of the Mg concentration in the second region 132 is greater than the maximum value of the Mg concentration in the first region 131, the Mg concentration increases stepwise from the first region 131 side toward the surface 10a in contact with the gate insulating film 21, and the Mg concentration is highest at the surface 10a. Preferably, the Mg concentration at the surface 10a is 5 x 10 18 cm -3 5x10 or more 19 cm -3 Mg ions are implanted into at least the second region 132 so that the following is true.

[0128] For example, the Mg concentration in the surface 10a of the second region 132 and its vicinity (upper region 1322) is 1×10 19 cm -3 The Mg concentration in the region below this (the lower region 1321 and the first region 131) is 1×10 17 cm-3 The implantation energy and dose of Mg are set so that:

[0129] This high-concentration ion implantation process may be performed as a single-stage ion implantation or a multi-stage ion implantation. Either the single-stage ion implantation or the multi-stage ion implantation may be used depending on the thickness of the Mg high-concentration layer 130. After the high-concentration Mg ion implantation, the manufacturing equipment sequentially removes the mask M1 and the through film 51.

[0130] Next, as shown in FIG. 22C, the manufacturing equipment ions-implants Si as an n-type impurity into the source formation region 23' of the GaN substrate 10. For example, the manufacturing equipment forms a mask M2 on the GaN substrate 10, and ions-implants Si into the GaN substrate 10 on which the mask M2 has been formed. After the ion implantation, the manufacturing equipment removes the mask M2 from the GaN substrate 10. In the Si ion implantation step shown in FIG. 22C, the Si ions are implanted so that the Si concentration in the source formation region 23' is 3×10 19 cm -3 The implantation energy and dose of Si are set so that:

[0131] Next, as shown in FIG. 22D, the manufacturing equipment ions-implants Mg as a p-type impurity into the contact formation region 15' of the GaN substrate 10. For example, the manufacturing equipment forms a mask M3 on the surface 10a of the GaN substrate 10, and ions-implants Mg into the GaN substrate 10 on which the mask M3 has been formed. After the ion implantation, the manufacturing equipment removes the mask M3 from the GaN substrate 10. In the Si ion implantation step shown in FIG. 22C, the Mg ions are implanted so that the Mg concentration in the contact formation region 15' is 1×10 19 cm -3 The implantation energy and dose of Mg are set so that:

[0132] 22E, the manufacturing equipment then deposits an Al-containing nitride film, such as an AlN film 31, on the surface 10a of the GaN substrate 10. The thickness of the AlN film 31 is, for example, not less than 100 nm and not more than 500 nm.

[0133] Next, as shown in FIG. 22F, the manufacturing equipment performs a heat treatment on the AlN film 31 and the GaN substrate 10 covered with the AlN film 31. This heat treatment is, for example, a rapid thermal treatment. The maximum temperature of this heat treatment is, for example, 1000°C or higher and 1500°C or lower, the heat treatment time at the maximum temperature is, for example, 1 minute or higher and 60 minutes or lower, and the heat treatment atmosphere is, for example, N2. By this heat treatment, as shown in FIG. 22G, the Mg and Si introduced into the GaN substrate 10 are activated to form the well region 13, the n+ type source region 23, and the p+ type contact region 15, and also define the drift region 121.

[0134] Furthermore, this heat treatment diffuses Al contained in the AlN film 31 from the AlN film 31 into the surface 10a of the GaN substrate 10 and its vicinity 10c (for example, within a range of 50 nm from the surface 10a in the depth direction, more preferably within a range of 5 nm from the surface 10a in the depth direction). As a result, a first region 131 to which Al is not added and a second region 132 to which Al is added are formed in the well region 13. The second region 132 is GaN to which Al has been added, i.e., AlGaN.

[0135] The Al concentration distribution in the second region 132 has the form shown in Fig. 4, for example. The Al concentration is highest at the surface 10a of the second region 132, and decreases continuously or stepwise from the surface 10a toward the first region 131. The Al concentration at the surface of the second region 132 is, for example, 10 atomic % (at %) or more and 30 atomic % or less.

[0136] Furthermore, this heat treatment also activates the Mg contained in the Mg high-concentration layer 130. As a result, the region of the second region 132 that overlaps with the Mg high-concentration layer 130 becomes p-type. The Mg concentration distribution in the second region 132 becomes, for example, the form of Configuration Example 2 shown in FIG. 20. After the heat treatment, the manufacturing equipment removes the AlN film 31 from the GaN substrate 10.

[0137] Next, as shown in FIG. 22H, the manufacturing equipment forms a gate insulating film 21 on the front surface 10a of the GaN substrate 10. For example, a SiO2 film is deposited to a thickness of 100 nm as the gate insulating film 21. Next, the manufacturing equipment forms a gate electrode 22 (see FIG. 20) and a source electrode 25 (see FIG. 20). The manufacturing equipment also forms a drain electrode 26 (see FIG. 20) on the rear surface 10b side of the GaN substrate 10. Through the above steps, for example, a vertical MOSFET 1F (Configuration Example 2) shown in FIG. 20 is completed.

[0138] (5) Manufacturing method 2 22B, Mg ions may be implanted so that the Mg concentration continuously increases from below the well formation region 13' toward the surface 10a (i.e., so that the Mg concentration gradually decreases from the surface 10a in the depth direction). For example, as shown in Mg distribution (1) in the graph of FIG. 19, Mg ions may be implanted into the second region 132 so that the Mg concentration continuously increases from the boundary between the first region 131 and the second region 132 toward the surface 10a. This makes it possible to form, for example, the vertical MOSFET 1E (Configuration Example 1) shown in FIG. 19.

[0139] Alternatively, as shown in Mg distribution (3) in the graph of Fig. 21, Mg ions may be implanted into the second region 132 and the first region 131 so that the Mg concentration increases continuously from the first region 131 toward the surface 10a. Mg ions may be implanted into the second region 132 and the first region 131 so that the Mg concentration increases more steeply in the second region 132 than in the first region 131. In this way, for example, the vertical MOSFET 1G (Configuration Example 3) shown in Fig. 21 can be formed.

[0140] (6) Manufacturing method 3 22A, Mg ions may be implanted into the GaN substrate 10 without using the mask M1. That is, Mg ions may be implanted at a high concentration into the JFET region located between one well region 13 and the other well region 13 adjacent to each other in the horizontal direction (for example, the X-axis direction). A method for manufacturing a vertical MOSFET in which Mg is introduced at a high concentration into the JFET region as well will be described below.

[0141] 23A to 23E are cross-sectional views sequentially illustrating a manufacturing method 3 of a vertical MOSFET according to embodiment 6 of the present disclosure. In Fig. 23A, the manufacturing method 3 is the same as manufacturing method 1 up to the step of forming a through film 51 on the surface 10a of a GaN substrate 10 and ion-implanting low-concentration Mg into the well formation region 13' through the through film 51. In manufacturing method 3, after the low-concentration Mg ion-implantation, the mask M1 is removed.

[0142] In this manufacturing method 3, after removing the mask M1, Mg ions are implanted at a high concentration into the surface 10a of the GaN substrate 10 and its vicinity to form a high-concentration Mg layer 150 at the surface 10a and its vicinity. The high-concentration Mg ions are implanted into the JFET region as well. For example, the high-concentration Mg ions are implanted into the JFET region as well to achieve the Mg distribution (2) in the graph of FIG. 20.

[0143] 23B, the manufacturing equipment ion-implants Si as an n-type impurity into source formation region 23' of GaN substrate 10. Next, the manufacturing equipment ion-implants Mg as a p-type impurity into contact formation region 15' of GaN substrate 10.

[0144] 23C, the manufacturing equipment forms an Al-containing nitride film, such as an AlN film 31, on the surface 10a of the GaN substrate 10. Next, the manufacturing equipment performs a heat treatment on the AlN film 31 and the GaN substrate 10 covered with the AlN film 31. This heat treatment activates the Mg and Si introduced into the GaN substrate 10, forming the well region 13, the n+ type source region 23, and the p+ type contact region 15, and also defining the drift region 121, as shown in FIG.

[0145] Furthermore, this heat treatment causes Al contained in the AlN film 31 to diffuse from the AlN film 31 to the surface 10a of the GaN substrate 10 and its vicinity 10c, forming a first region 131 to which Al is not added and a second region 132 to which Al is added.

[0146] Furthermore, this heat treatment also activates the Mg contained in the Mg high-concentration layer 130. As a result, the region of the second region 132 that overlaps with the Mg high-concentration layer 130 becomes p-type. The Mg concentration distribution in the second region 132 becomes, for example, the form of Configuration Example 2 shown in FIG. 20. After the heat treatment, the manufacturing equipment removes the AlN film 31 from the GaN substrate 10.

[0147] Next, as shown in FIG. 23E, the manufacturing equipment forms a gate insulating film 21 on the front surface 10a of the GaN substrate 10. Next, the manufacturing equipment forms a gate electrode 22 and a source electrode 25. The manufacturing equipment also forms a drain electrode 26 on the back surface 10b side of the GaN substrate 10. Through the above steps, a vertical MOSFET 1H is completed in which a p-type second region 132 is also formed in the JFET region. This vertical MOSFETH can reduce hole traps in the JFET region and suppress fluctuations in the threshold voltage.

[0148] (7) Variations (7.1) Variation 1 24 is a cross-sectional view showing a configuration example (modification) of a vertical MOSFET 1I according to the sixth embodiment of the present disclosure. As shown in FIG. 24, in the above-described manufacturing method 3, n-type impurities (e.g., Si) may be ion-implanted into the JFET region before the heat treatment shown in FIG. 23C (e.g., before forming the AlN film 31). This allows an n-type layer (e.g., an n-type JFET region 41) to be formed in the JFET region below a region (e.g., a p-type second region 132) into which Mg is highly doped, as shown in FIG. 24. The vertical MOSFET 1I can reduce its on-resistance by including the n-type JFET region 41.

[0149] In the manufacturing process of the vertical MOSFET 1I according to this modification, n-type impurities are ion-implanted into the JFET region. The surface 10a of the p-type second region 132 and the region below the surface 10a are counter-doped to n-type by this ion implantation. Therefore, the Mg concentration distribution in the JFET region is not limited to the Mg distribution (2) shown in FIG. 20, but may be the Mg distribution (1) shown in FIG. 19 or the Mg distribution (3) shown in FIG. 20. Even when Mg is introduced from the surface 10a of the JFET region to a relatively deep position, as in the Mg distributions (2) and (3), a low-resistance current path can be ensured by the counter-doping.

[0150] (7.2) Variation 2 In the above-described manufacturing methods 1 to 3, the Mg concentration in the second region 132 is adjusted to be highest at the surface in contact with the gate insulating film 21 (i.e., the surface 10a) by implanting Mg ions at a high concentration through the through film 51. However, the method for adjusting the surface concentration is not limited to this. For example, after implanting Mg ions at a high concentration, the surface 10a of the GaN substrate 10 may be ground by etch-back or CMP or the like so that the Mg implantation peak is at the surface 10a. Alternatively, the high-concentration Mg ion implantation through the through film 51 may be combined with the etch-back or grinding. Even with this method, it is possible to achieve the Mg distributions (1) to (3) shown in, for example, FIGS. 19 to 21 .

[0151] <Other embodiments> As described above, the present disclosure has been described with reference to embodiments 1 to 6 and modifications. However, the descriptions and drawings that form part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments and modifications will be apparent to those skilled in the art from this disclosure. For example, in the above embodiments 1 to 5, the electrode in contact with the contact region 15 is the source electrode 25, but the embodiments of the present disclosure are not limited thereto. The contact region 15 may also be in contact with an electrode other than the source electrode. Thus, the present technology naturally includes various embodiments not described herein. Various omissions, substitutions, and / or modifications of components may be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described herein are merely exemplary and not limiting, and other effects may also be present.

[0152] The present disclosure can also be configured as follows. (1) a first conductivity type nitride semiconductor layer; a second conductivity type well region provided in the nitride semiconductor layer; a gate insulating film provided on the first surface side of the nitride semiconductor layer and covering the well region, The well region is a first region to which Al is not added; a second region provided on the first region and doped with Al; The second region is The nitride semiconductor device has an Al concentration distribution in which the Al concentration is highest on a first surface in contact with the gate insulating film and the Al concentration decreases continuously or stepwise from the first surface toward the first region. (2) the first conductivity type is n-type and the second conductivity type is p-type; The nitride semiconductor device according to (1), wherein the first region and the second region each contain Mg as a p-type impurity. (3) The nitride semiconductor device according to (2), wherein the maximum value of the Mg concentration in the second region is greater than the maximum value of the Mg concentration in the first region. (4) The nitride semiconductor device according to (3), wherein the second region has a Mg concentration distribution in which the Mg concentration increases continuously or stepwise from the first region side toward the first surface in contact with the gate insulating film. (5) The nitride semiconductor device according to (3) or (4), wherein the Mg concentration in the second region is highest in the first surface in contact with the gate insulating film. (6) In the second region, the Mg concentration of the first surface in contact with the gate insulating film is 5×10 18 cm -3 5x10 or more 19 cm -3 The nitride semiconductor device according to (3) or (4), wherein: (7) The nitride semiconductor device according to any one of (1) to (6), wherein the first region and the second region are stacked on a non-polar plane of the nitride semiconductor layer. (8) The nitride semiconductor device according to any one of (1) to (6), wherein the first region and the second region are stacked on a polar surface of the nitride semiconductor layer. (9) The nitride semiconductor device according to any one of (1) to (8), wherein the second region has a thickness of 50 nm or less. (10) The nitride semiconductor device according to any one of (1) to (8), wherein the second region has a thickness of 5 nm or less. (11) a drift region of the first conductivity type provided in the nitride semiconductor layer and positioned between a second surface of the nitride semiconductor layer opposite to the first surface and the well region; The nitride semiconductor device according to any one of (1) to (10), further comprising: a nitride semiconductor substrate of the first conductivity type provided on the second surface side of the nitride semiconductor layer and in contact with the drift region. (12) a plurality of the well regions; the first conductivity type high concentration region being provided in the nitride semiconductor layer and positioned between adjacent well regions of the plurality of well regions, The nitride semiconductor device according to (11), wherein the high concentration region has a higher concentration of the first conductivity type impurity than the drift region. (13) a gate electrode provided on the first surface side of the nitride semiconductor layer and facing the well region via the gate insulating film; a source region of the first conductivity type provided in the nitride semiconductor layer and in contact with the well region; a source electrode provided on the first surface side of the nitride semiconductor layer and connected to the source region; The nitride semiconductor device according to (11) or (12), further comprising: a drain electrode provided on the opposite side of the nitride semiconductor layer with the nitride semiconductor substrate interposed therebetween, the drain electrode being connected to the drift region via the nitride semiconductor substrate. (14) a trench provided in the nitride semiconductor layer; The nitride semiconductor device according to (13), wherein the gate electrode is provided in the trench via the gate insulating film. (15) The drift region is The nitride semiconductor device according to any one of (11) to (14), further comprising a pillar of the second conductivity type provided from a bottom of the well region toward the second surface. (16) The nitride semiconductor device according to any one of (1) to (15) above, wherein Al added to the second region exists mainly as a nitride. (17) The nitride semiconductor device according to any one of (1) to (16), wherein the gate insulating film contains at least one of a silicon oxide and an aluminum oxide. (18) The nitride semiconductor device according to any one of (1) to (16), wherein the gate insulating film is composed of a Si oxynitride film and at least one of a Si oxide and an Al oxide, and is stacked in this order from the first surface side of the nitride semiconductor layer: the Si oxynitride film, and at least one of a Si oxide and an Al oxide. (19) The nitride semiconductor device according to any one of (1) to (18), wherein a channel of a MOSFET is formed in the second region. (20) forming a well region of a second conductivity type on the first surface side of the nitride semiconductor layer of the first conductivity type; forming a gate insulating film on the first surface side of the nitride semiconductor layer to cover the well region; The step of forming the well region includes: forming a first region to which Al is not added; forming a second region on the first region to which Al is added; In the step of forming the second region, a first surface in contact with the gate insulating film, and an Al concentration distribution is formed in the second region such that the Al concentration is highest at the first surface that is in contact with the gate insulating film, and the Al concentration decreases continuously or stepwise from the first surface toward the first region. (twenty one) the first conductivity type is n-type and the second conductivity type is p-type; In the step of forming the well region, The method for manufacturing a nitride semiconductor device according to (20), wherein Mg is introduced into the first region and the second region by ion-implanting Mg as a p-type impurity into the first surface side of the nitride semiconductor layer or by epitaxially growing a nitride semiconductor containing Mg as the p-type impurity. (twenty two) In the step of forming the well region, The method for manufacturing a nitride semiconductor device according to (21), wherein Mg ions are implanted into at least the second region so that the maximum value of the Mg concentration in the second region is greater than the maximum value of the Mg concentration in the first region. (twenty three) In the step of forming the well region, The method for manufacturing a nitride semiconductor device according to (22), wherein Mg ions are implanted into at least the second region so that the Mg concentration increases continuously or stepwise from the first region side toward the first surface in contact with the gate insulating film. (twenty four) In the step of forming the well region, The method for manufacturing a nitride semiconductor device according to (22) or (23), wherein Mg ions are implanted into at least the second region so that the Mg concentration in the second region is highest on the first surface in contact with the gate insulating film. (twenty five) In the step of forming the well region, In the second region, the Mg concentration of the first surface in contact with the gate insulating film is 5×10 18 cm -3 5x10 or more 19 cm -3 The method for manufacturing a nitride semiconductor device according to (22) or (23), wherein Mg ions are implanted into at least the second region so that: (26) In the step of forming the second region, The method for manufacturing a nitride semiconductor device according to any one of (20) to (25), further comprising forming a nitride film containing Al on the first surface of the nitride semiconductor layer, and performing a heat treatment on the nitride film and the nitride semiconductor layer covered with the nitride film, thereby forming the Al concentration distribution in the second region. (27) In the step of forming the second region, The method for manufacturing a nitride semiconductor device according to any one of (20) to (25), further comprising: implanting Al ions into the first surface side of the nitride semiconductor layer; and performing a heat treatment on the nitride semiconductor layer into which Al ions have been implanted, thereby forming the Al concentration distribution in the second region. (28) In the step of forming the second region, The method for manufacturing a nitride semiconductor device according to any one of (20) to (25), wherein the second region having the Al concentration distribution is epitaxially grown on the first region. [Explanation of symbols]

[0153] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I Vertical MOSFET 10a surface 10b back side Near 10c 11 GaN single crystal substrate 12 GaN layers 12A AlGaN layer 12b Back 12NA GaN layer 13 well area 13´ Well formation area 15 Contact Area 15´ Contact formation area 21 Gate insulating film 22 gate electrode 23 Source Region 23´ Source formation region 25 Source electrode 26 Drain electrode 31 AlN film 41 JFET area 41´ JFET formation area 51 Through membrane 100 GaN semiconductor devices 121 Drift Region 121n n-type pillar 121n´ n-type pillar formation region 121p p-type pillar 121p´ p-type pillar formation region 131, 131´ 1st area 132, 132´ 2nd area 150 Mg high concentration layer 211 SiON membrane 212 SiO2 film 1311, 1321 lower area 1312, 1322 upper area H Trench M1, M2, M3, M4, M5, M6 Masks

Claims

1. a first conductivity type nitride semiconductor layer; a second conductivity type well region provided in the nitride semiconductor layer; a gate insulating film provided on the first surface side of the nitride semiconductor layer and covering the well region, The well region is a first region to which Al is not added; a second region provided on the first region and doped with Al; The second region is a nitride semiconductor device having an Al concentration distribution in which the Al concentration is highest at a first surface in contact with the gate insulating film and the Al concentration decreases continuously or stepwise from the first surface toward the first region.

2. the first conductivity type is n-type and the second conductivity type is p-type; The nitride semiconductor device according to claim 1 , wherein said first region and said second region each contain Mg as a p-type impurity.

3. The nitride semiconductor device according to claim 2 , wherein the maximum value of the Mg concentration in said second region is greater than the maximum value of the Mg concentration in said first region.

4. 4. The nitride semiconductor device according to claim 3, wherein said second region has a Mg concentration distribution in which the Mg concentration increases continuously or stepwise from said first region side toward said first surface in contact with said gate insulating film.

5. 5. The nitride semiconductor device according to claim 3, wherein the Mg concentration in said second region is highest in said first surface in contact with said gate insulating film.

6. In the second region, the Mg concentration of the first surface in contact with the gate insulating film is 5×10 １８ cm －３ 5x10 or more １９ cm －３ 5. The nitride semiconductor device according to claim 3, wherein:

7. The nitride semiconductor device according to claim 1 , wherein the first region and the second region are stacked on a nonpolar plane of the nitride semiconductor layer.

8. The nitride semiconductor device according to claim 1 , wherein the first region and the second region are stacked on a polar surface of the nitride semiconductor layer.

9. 3. The nitride semiconductor device according to claim 1, wherein said second region has a thickness of 50 nm or less.

10. The nitride semiconductor device according to claim 1 , wherein the second region has a thickness of 5 nm or less.

11. a drift region of the first conductivity type provided in the nitride semiconductor layer and positioned between a second surface of the nitride semiconductor layer opposite to the first surface and the well region; The nitride semiconductor device according to claim 1 , further comprising: a nitride semiconductor substrate of the first conductivity type provided on the second surface side of the nitride semiconductor layer and in contact with the drift region.

12. a plurality of the well regions; the first conductivity type high concentration region being provided in the nitride semiconductor layer and positioned between adjacent well regions of the plurality of well regions, The nitride semiconductor device according to claim 11 , wherein said high concentration region has a higher concentration of said first conductivity type impurities than said drift region.

13. a gate electrode provided on the first surface side of the nitride semiconductor layer and facing the well region via the gate insulating film; a source region of the first conductivity type provided in the nitride semiconductor layer and in contact with the well region; a source electrode provided on the first surface side of the nitride semiconductor layer and connected to the source region; The nitride semiconductor device according to claim 11 , further comprising: a drain electrode provided on the opposite side of the nitride semiconductor layer with the nitride semiconductor substrate interposed therebetween, the drain electrode being connected to the drift region via the nitride semiconductor substrate.

14. a trench provided in the nitride semiconductor layer; The nitride semiconductor device according to claim 13 , wherein said gate electrode is provided in said trench via said gate insulating film.

15. The drift region is The nitride semiconductor device according to claim 11 , further comprising a pillar of the second conductivity type provided from a bottom of the well region toward the second surface.

16. 3. The nitride semiconductor device according to claim 1, wherein the Al added to said second region exists mainly as a nitride.

17. 3. The nitride semiconductor device according to claim 1, wherein said gate insulating film contains at least one of a silicon oxide and an aluminum oxide.

18. 3. The nitride semiconductor device according to claim 1, wherein the gate insulating film is composed of a Si oxynitride film and at least one of a Si oxide and an Al oxide, and the Si oxynitride film and at least one of a Si oxide and an Al oxide are stacked in this order from the first surface side of the nitride semiconductor layer.

19. The nitride semiconductor device according to claim 1 , wherein a channel of a MOSFET is formed in said second region.

20. forming a well region of a second conductivity type on the first surface side of the nitride semiconductor layer of the first conductivity type; forming a gate insulating film on the first surface side of the nitride semiconductor layer to cover the well region; The step of forming the well region includes: forming a first region to which Al is not added; forming a second region on the first region to which Al is added; In the step of forming the second region, a first surface in contact with the gate insulating film, and an Al concentration distribution is formed in the second region such that the Al concentration is highest at the first surface that is in contact with the gate insulating film, and the Al concentration decreases continuously or stepwise from the first surface toward the first region.

21. the first conductivity type is n-type and the second conductivity type is p-type; In the step of forming the well region, 21. The method for manufacturing a nitride semiconductor device according to claim 20, wherein Mg is introduced into the first region and the second region by ion-implanting Mg as a p-type impurity into the first surface side of the nitride semiconductor layer or by epitaxially growing a nitride semiconductor containing Mg as the p-type impurity.

22. In the step of forming the well region, 22. The method for manufacturing a nitride semiconductor device according to claim 21, wherein Mg ions are implanted into at least said second region so that a maximum value of the Mg concentration in said second region is greater than a maximum value of the Mg concentration in said first region.

23. In the step of forming the well region, 23. The method for manufacturing a nitride semiconductor device according to claim 22, wherein Mg ions are implanted into at least the second region so that the Mg concentration increases continuously or stepwise from the first region side toward the first surface in contact with the gate insulating film.

24. In the step of forming the well region, 24. The method for manufacturing a nitride semiconductor device according to claim 22, wherein Mg ions are implanted into at least said second region so that the Mg concentration in said second region is highest in said first surface in contact with said gate insulating film.

25. In the step of forming the well region, In the second region, the Mg concentration of the first surface in contact with the gate insulating film is 5×10 １８ cm －３ 5x10 or more １９ cm －３ 24. The method for manufacturing a nitride semiconductor device according to claim 22, wherein Mg ions are implanted into at least the second region so that:

26. In the step of forming the second region, 22. The method for manufacturing a nitride semiconductor device according to claim 20, further comprising: forming a nitride film containing Al on the first surface of the nitride semiconductor layer; and performing a heat treatment on the nitride film and the nitride semiconductor layer covered with the nitride film, thereby forming the Al concentration distribution in the second region.

27. In the step of forming the second region, 22. The method for manufacturing a nitride semiconductor device according to claim 20, wherein the Al concentration distribution is formed in the second region by ion-implanting Al into the first surface side of the nitride semiconductor layer and performing a heat treatment on the nitride semiconductor layer into which Al has been ion-implanted.

28. In the step of forming the second region, The method for manufacturing a nitride semiconductor device according to claim 20 or 21, wherein the second region having the Al concentration distribution is epitaxially grown on the first region.

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