Semiconductor device

Abstract

To provide a semiconductor device including a stacked multi-gate transistor.SOLUTION: A first active pattern including a first lower active pattern A11 and a first upper active pattern A12 extending in a first direction X, a second active pattern including a second lower active pattern A22 and a second upper active pattern LA extending in the first direction X, first gate structures extending in a second direction Y on the first active pattern, the semiconductor device may include the first gate structures, the second gate structures arranged in the second direction, the cut patterns C1 to C3 between the first active patterns and the second active patterns and extending in the first direction X to separate the first gate structures from the second gate structures, the front interconnection patterns 311 on the upper surfaces of the cut patterns, the first rear interconnection patterns 411 on the second surface, and the first through-via TV1 penetrating the substrate 101 and the cut patterns C2 to connect the front interconnection patterns 311 to the first rear interconnection patterns 411.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including stacked multi-gate transistors. [Background technology]

[0002] As one of the scaling technologies for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and a gate is formed on the surface of the silicon body.

[0003] Such multi-gate transistors are easy to scale because they use a three-dimensional channel. They also improve current control capability without increasing the gate length of the multi-gate transistor. Furthermore, they effectively suppress the short channel effect (SCE), which is the effect of drain voltage on the potential of the channel region. Summary of the Invention [Problem to be solved by the invention]

[0004] The technical problem to be solved by the present invention is to provide a semiconductor device with improved integration and performance.

[0005] The technical problems of the present invention are not limited to those described above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] In some embodiments, a semiconductor device for achieving the above technical object includes a substrate having a first surface and a second surface opposite to each other, a first active pattern sequentially stacked on the first surface and including a first lower active pattern and a first upper active pattern each extending in a first direction, a second active pattern sequentially stacked on the first surface and including a second lower active pattern and a second upper active pattern each extending in the first direction, a first gate structure on the first active pattern extending in a second direction intersecting the first direction, a second gate structure on the second active pattern extending in the second direction and aligned with the first gate structure along the second direction, a cutting structure extending in the first direction between the first active pattern and the second active pattern to separate the first gate structure from the second gate structure, a front wiring pattern on an upper surface of the cutting structure extending in the first direction, a first back wiring pattern on the second surface extending in the first direction, and a first through via penetrating the substrate and the cutting structure to connect the front wiring pattern and the first back wiring pattern.

[0007] A semiconductor device according to some embodiments for achieving the above technical object includes a substrate having a first surface and a second surface opposite to each other, a lower active pattern extending in a first direction on the first surface, an upper active pattern spaced apart from the first surface by the lower active pattern and extending in the first direction, a gate structure extending in a second direction intersecting the first direction on the lower active pattern and the upper active pattern, a first cutting structure spaced apart from the lower active pattern and the upper active pattern in the second direction and extending in the first direction to cut the gate structure, a first front wiring pattern extending in the first direction on an upper surface of the first cutting structure, and a gate structure. The gate structure includes a first upper connection contact on the side surface connected to the upper source / drain region of the upper active pattern, a first back surface wiring pattern extending in a first direction on the second surface, a first lower connection contact on the side surface of the gate structure connected to the lower source / drain region of the lower active pattern, a first through via that penetrates the substrate and the first cutting structure to connect the first front surface wiring pattern and the first back surface wiring pattern, and a second through via that penetrates the substrate and the first cutting structure to connect the first upper connection contact and the first lower connection contact, and the first through via and the second through via are arranged along the first direction.

[0008] According to some embodiments, the semiconductor device includes a first cell region, a second cell region arranged with the first cell region along a first direction, and a third cell region arranged with the first cell region along a second direction intersecting the first direction, the semiconductor device including a substrate having a first surface and a second surface opposite to each other, a front wiring pattern extending in the first direction on the first surface, a first back wiring pattern extending in the first direction on the second surface, a first through via penetrating the substrate between the first cell region and the third cell region, connecting the front wiring pattern and the first back wiring pattern, and a second through via arranged with the first through via along the first direction, the first to third cell regions being sequentially stacked on the first surface, each including a lower active pattern and an upper active pattern extending in the first direction, and a gate structure extending in the second direction on the lower active pattern and the upper active pattern, the second through via electrically connecting the lower active pattern of the second cell region and the upper active pattern of the second cell region. [Brief explanation of the drawings]

[0009] Specific details of other embodiments are included in the detailed description and drawings.

[0010] [Figure 1] 1 is a schematic layout diagram illustrating a semiconductor device according to some embodiments. [Figure 2] FIG. 2 is an exemplary layout diagram for explaining the R region in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line AA in FIG. 2. [Figure 4] FIG. 3 is a cross-sectional view taken along line BB in FIG. 2. [Figure 5] FIG. 3 is a cross-sectional view taken along CC in FIG. 2. [Figure 6] FIG. 3 is a cross-sectional view taken along the line DD in FIG. 2. [Figure 7] FIG. 3 is a cross-sectional view taken along the line EE in FIG. 2. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments. [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments. [Figure 10] 1 is an exemplary layout diagram illustrating a semiconductor device according to some embodiments. [Figure 11] FIG. 11 is a cross-sectional view taken along the line FF in FIG. [Figure 12] 1 is an exemplary layout diagram illustrating a semiconductor device according to some embodiments. [Figure 13] FIG. 13 is a cross-sectional view taken along line GG in FIG. [Figure 14] 1 is an exemplary layout diagram illustrating a semiconductor device according to some embodiments. [Figure 15] FIG. 15 is a cross-sectional view taken along line HH in FIG. [Figure 16] 1A-1D are various schematic layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 17] 1A-1D are various schematic layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 18] 1A-1D are various schematic layout diagrams illustrating semiconductor devices according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] In this specification, terms such as "first" and "second" are used to describe various elements or components, but it goes without saying that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it goes without saying that a first element or first component referred to below may be a second element or second component within the technical concept of the present invention.

[0012] Semiconductor devices according to exemplary embodiments will be described below with reference to FIGS.

[0013] FIG. 1 is a schematic layout diagram for explaining a semiconductor device according to some embodiments.

[0014] Referring to FIG. 1, a semiconductor device according to some embodiments includes a plurality of unit cell regions UC, a first power supply wiring PR1, a second power supply wiring PR2, and a first through via TV1.

[0015] The plurality of unit cell regions UC may be arranged two-dimensionally. For example, the plurality of unit cell regions UC may be arranged in a matrix along a first direction X and a second direction Y that intersect with each other. Each unit cell region UC may provide various logic elements such as, but not limited to, an inverter, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate, and / or a static random access memory (SRAM).

[0016] The first power supply wiring PR1 and the second power supply wiring PR2 may each extend long in a first direction X. The first power supply wiring PR1 and the second power supply wiring PR2 may be arranged alternately along a second direction Y. Different power supply voltages may be applied to the first power supply wiring PR1 and the second power supply wiring PR2. For example, a first power supply voltage (e.g., V SS ) may be applied to the second power supply wiring PR2, and a second power supply voltage (for example, V DD ) may be applied. The first power supply wiring PR1 may provide the first power supply voltage to each unit cell region UC. The second power supply wiring PR2 may provide the second power supply voltage to each unit cell region UC.

[0017] The first through via TV1 may be interposed between two unit cell regions UC adjacent to each other in the second direction Y. The first through via TV1 may be connected to the first power wiring PR1. For example, the first through via TV1 may overlap with the first power wiring PR1 in a third direction Z intersecting the first direction X and the second direction Y.

[0018] One first power wiring PR1 may be commonly connected to a plurality of first through vias TV1 arranged along the first direction X. The plurality of first through vias TV1 arranged along the first direction X may be spaced apart from each other at predetermined intervals. For example, a plurality of unit cell regions UC arranged along the first direction X may be disposed in a region between two first through vias TV1 adjacent to each other in the first direction X.

[0019] In some embodiments, the first through vias TV1 may be spaced apart in the first direction X by about 3 gate pitches or more. For example, the first through vias TV1 may be spaced apart in the first direction X by about 3 gate pitches to about 100 gate pitches. Alternatively, the first through vias TV1 may be spaced apart in the first direction X by about 5 gate pitches to about 60 gate pitches. The first through vias TV1 will be described in more detail below with reference to FIGS. 2 to 7.

[0020] Fig. 2 is an exemplary layout diagram for explaining region R in Fig. 1. Fig. 3 is a cross-sectional view taken along line AA in Fig. 2. Fig. 4 is a cross-sectional view taken along line BB in Fig. 2. Fig. 5 is a cross-sectional view taken along line CC in Fig. 2. Fig. 6 is a cross-sectional view taken along line DD in Fig. 2. Fig. 7 is a cross-sectional view taken along line EE in Fig. 2.

[0021] 1 to 7, in a semiconductor device according to some embodiments, a plurality of unit cell regions UC include first to fourth cell regions UC1 to UC4 adjacent to each other.

[0022] The first cell region UC1 and the second cell region UC2 may be adjacent to each other in the first direction X. The first cell region UC1 and the third cell region UC3 may be adjacent to each other in the second direction Y. The fourth cell region UC4 may be adjacent to the second cell region UC2 in the second direction Y and adjacent to the third cell region UC3 in the first direction X. That is, the fourth cell region UC4 may be adjacent to the first cell region UC1 in the diagonal direction between the first direction X and the second direction Y.

[0023] In the semiconductor device according to some embodiments, each of the first to fourth cell regions UC1 to UC4 may include a first region I and a second region II.

[0024] The first region I and the second region II may be sequentially stacked along the third direction Z. Transistors of the same conductivity type or different conductivity types may be formed in the first region I and the second region II. In the following description, a case where the first region I is a PFET region and the second region II is an NFET region will be exemplified. However, this is merely an example, and a person skilled in the art will understand that the first region I may be an NFET region and the second region II may be a PFET region, or both the first region I and the second region II may be NFET regions, or both the first region I and the second region II may be PFET regions.

[0025] A semiconductor device according to some embodiments may include a substrate 101, first active patterns A11, A12, second active patterns A21, A22, first to fourth gate structures G1 to G4, first to sixth isolation structures B1 to B6, first to third cutting patterns C1 to C3, a lower source / drain region 160, an upper source / drain region 260, a lower source / drain contact 170, an upper source / drain contact 270, first to eighth upper connection contacts FC1 to FC8, first to fifth lower connection contacts BC1 to BC5, a backside wiring structure BW, a frontside wiring structure FW, a first through via TV1 and a second through via TV2.

[0026] The substrate 101 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 101 may be a silicon substrate or may include other materials such as silicon germanium, silicon germanium on insulator (SOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 101 may be a base substrate on which an epitaxial layer is formed.

[0027] In some embodiments, the substrate 101 may be an insulating substrate including an insulating material. For example, but not limited to, the substrate 101 may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof. As an example, the substrate 101 may include a silicon oxide film.

[0028] The substrate 101 may include a first side 101a and a second side 101b that are opposite to each other. In this specification, the first side 101a is also referred to as the front side of the substrate 101, and the second side 101b is also referred to as the back side of the substrate 101.

[0029] The first active patterns A11 and A12 and the second active patterns A21 and A22 are formed on the first surface 101a. The first active patterns A11 and A12 and the second active patterns A21 and A22 may be spaced apart from each other in the second direction Y and may each extend longitudinally in the first direction X. The first active patterns A11 and A12 may extend in the first direction X across the first cell region UC1 and the second cell region UC2. The second active patterns A21 and A22 may extend in the first direction X across the third cell region UC3 and the fourth cell region UC4.

[0030] The first active patterns A11 and A12 may include a first lower active pattern A11 and a first upper active pattern A12 sequentially stacked on the first surface 101a. The first lower active pattern A11 and the first upper active pattern A12 may be spaced apart from each other in the third direction Z and may each extend longitudinally in the first direction X. The first lower active pattern A11 may be disposed in a first region I, and the first upper active pattern A12 may be disposed in a second region II.

[0031] The second active patterns A21 and A22 may include a second lower active pattern A21 and a second upper active pattern A22 sequentially stacked on the first surface 101a. The second lower active pattern A21 and the second upper active pattern A22 may be spaced apart from each other in the third direction Z and each extend longitudinally in the first direction X. The second lower active pattern A21 may be disposed in the first region I, and the second upper active pattern A22 may be disposed in the second region II.

[0032] In some embodiments, each of the first lower active pattern A11 and the second lower active pattern A21 may include a plurality of lower bridge patterns 111, 112 stacked sequentially on the substrate 101 and spaced apart from each other. In some embodiments, each of the first upper active pattern A12 and the second upper active pattern A22 may include a plurality of upper bridge patterns 211, 212 stacked sequentially on the substrate 101 and spaced apart from each other. The lower bridge patterns 111, 112 and the upper bridge patterns 211, 212 are used as channel regions of an MBCFET (registered trademark) including a multi-bridge channel. The numbers of the lower bridge patterns 111, 112 and the upper bridge patterns 211, 212 are merely examples and are not limited to those shown in the figures.

[0033] The first lower active pattern A11, the first upper active pattern A12, the second lower active pattern A21, and the second upper active pattern A22 may each include an elemental semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the first lower active pattern A11, the first upper active pattern A12, the second lower active pattern A21, and the second upper active pattern A22 may each include a compound semiconductor, such as a IV-IV compound semiconductor or a III-V compound semiconductor. The IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a IV element. The III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of group III elements aluminum (Al), gallium (Ga), and indium (In) with at least one of group V elements phosphorus (P), arsenic (As), and antimony (Sb).

[0034] In some embodiments, a base insulating pattern 102 is formed between the substrate 101 and the lower active patterns A11 and A21. The base insulating pattern 102 may extend elongately in the first direction X. The base insulating pattern 102 may electrically isolate the substrate 101 from the lower active patterns A11 and A21. The base insulating pattern 102 may include, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof. As an example, the base insulating pattern 102 may include a silicon nitride film.

[0035] In some embodiments, an intermediate insulating pattern 202 is formed between the lower active patterns A11, A21 and the upper active patterns A12, A22. The intermediate insulating pattern 202 may extend elongately in the first direction X. The intermediate insulating pattern 202 may electrically isolate the lower active patterns A11, A21 from the upper active patterns A12, A22. The intermediate insulating pattern 202 may include, for example, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof. As an example, the intermediate insulating pattern 202 may include a silicon nitride film.

[0036] The first to fourth gate structures G1 to G4 are formed on the first active patterns A11 and A12 and the second active patterns A21 and A22. The first to fourth gate structures G1 to G4 may extend longitudinally in the second direction Y, respectively.

[0037] The first gate structure G1 and the second gate structure G2 may intersect with the first active patterns A11 and A12, respectively. The first gate structure G1 and the second gate structure G2 may be spaced apart from each other in a first direction X and extend in a second direction Y. The first gate structure G1 may be disposed in a first cell region UC1, and the second gate structure G2 may be disposed in a second cell region UC2.

[0038] In some embodiments, the first gate structure G1 and the second gate structure G2 may surround the periphery of the first active patterns A11 and A12. For example, the bridge patterns 111, 112, 211, and 212 of the first active patterns A11 and A12 may extend in the first direction X and penetrate the first gate structure G1 and the second gate structure G2.

[0039] The third gate structure G3 and the fourth gate structure G4 may intersect with the second active patterns A21 and A22, respectively. The third gate structure G3 and the fourth gate structure G4 may be spaced apart from each other in the first direction X and extend in the second direction Y, respectively. The third gate structure G3 may be disposed in the third cell region UC3, and the fourth gate structure G4 may be disposed in the fourth cell region UC4. The third gate structure G3 may be arranged in the second direction Y with the first gate structure G1. The fourth gate structure G4 may be arranged in the second direction Y with the second gate structure G2.

[0040] In some embodiments, the third gate structure G3 and the fourth gate structure G4 may surround the second active patterns A21 and A22. For example, the bridge patterns 111, 112, 211, and 212 of the second active patterns A21 and A22 may extend in the first direction X and penetrate the third gate structure G3 and the fourth gate structure G4.

[0041] Although FIG. 2 shows that only one gate structure is arranged in each of the first to fourth cell regions UC1 to UC4, this is just an example, and it goes without saying that multiple gate structures can be arranged in each of the first to fourth cell regions UC1 to UC4.

[0042] Each of the first to fourth gate structures G1 to G4 may include a gate dielectric layer 120, a lower gate electrode 130, an upper gate electrode 230, a gate spacer 135, and a gate capping layer 137.

[0043] The gate dielectric layer 120 may be interposed between the lower active patterns A11, A21 and the lower gate electrode 130, and between the upper active patterns A12, A22 and the upper gate electrode 230. The gate dielectric layer 120 may include at least one of a dielectric material, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, but is not limited to, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0044] In some embodiments, the gate dielectric film 120 may include an interface film 122 and a high-k film 124 sequentially stacked on the respective bridge patterns 111, 112, 211, and 212.

[0045] The interfacial film 122 may surround the periphery of each of the bridge patterns 111, 112, 211, and 212. For example, the interfacial film 122 may conformally extend along the periphery of each of the bridge patterns 111, 112, 211, and 212. In some embodiments, the interfacial film 122 may include an oxide film formed by oxidizing the surface of each of the bridge patterns 111, 112, 211, and 212. As an example, if each of the bridge patterns 111, 112, 211, and 212 includes silicon (Si), the interfacial film 122 may include a silicon oxide film.

[0046] The high-k dielectric film 124 may surround the periphery of the interface film 122. Also, a portion of the high-k dielectric film 124 may be interposed between the upper gate electrode 230 and the gate spacer 135. For example, the high-k dielectric film 124 may conformally extend along the periphery of the interface film 122 and the profile of the inner surface of the gate spacer 135. The high-k dielectric film 124 may also extend further along the substrate 101, the base insulating pattern 102, and the intermediate insulating pattern 202.

[0047] In some embodiments, the high-k dielectric film 124 may include a high-k material having a dielectric constant greater than that of silicon oxide, such as hafnium oxide (HfO), zirconium oxide (ZrO), lanthanum oxide (LaO), aluminum oxide (AlO), titanium oxide (TiO), strontium titanium oxide (SrTiO), lanthanum aluminum oxide (LaAlO), yttrium oxide (YO), hafnium oxynitride (HfO), or the like. x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (LaO x N y ), aluminum oxynitride (AlO x N y ), titanium oxynitride (TiO x N y ), strontium titanium oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (YO x N y ) and combinations thereof, but are not limited thereto.

[0048] The bottom gate electrode 130 may be disposed in the first region I. The bottom gate electrode 130 may cross the lower active patterns A11 and A21. For example, each of the lower bridge patterns 111 and 112 may extend in the first direction X and penetrate the bottom gate electrode 130.

[0049] The upper gate electrode 230 is disposed in the second region II. The upper gate electrode 230 may cross the upper active patterns A12 and A22. For example, each of the upper bridge patterns 211 and 212 may extend in the first direction X and penetrate the upper gate electrode 230.

[0050] The lower gate electrode 130 and the upper gate electrode 230 may each include, but are not limited to, at least one of a conductive material such as TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, and combinations thereof. The lower gate electrode 130 and the upper gate electrode 230 are each formed by, but are not limited to, a replacement process.

[0051] Although the bottom gate electrode 130 and the top gate electrode 230 are each shown as a single film, this is merely an example, and it goes without saying that each may be formed by stacking multiple conductive films. For example, the bottom gate electrode 130 and the top gate electrode 230 may each include a work function adjustment film that adjusts the work function and a filling conductive film that fills the space formed by the work function adjustment film. The work function adjustment film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al.

[0052] In some embodiments, the bottom gate electrode 130 and the top gate electrode 230 may include different conductive materials. For example, the bottom gate electrode 130 and the top gate electrode 230 may include work function tuning films of different conductivity types. As an example, the bottom gate electrode 130 may include a p-type work function tuning film, and the top gate electrode 230 may include an n-type work function tuning film.

[0053] The gate spacer 135 may extend along a side surface of the lower gate electrode 130 and a side surface of the upper gate electrode 230. Each of the bridge patterns 111, 112, 211, and 212 may extend in the first direction X and penetrate the gate spacer 135. The gate spacer 135 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof.

[0054] The gate capping film 137 may extend along the upper surface of the upper gate electrode 230. The gate capping film 137 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof.

[0055] The first to sixth separating structures B1 to B6 may each extend elongately in the second direction Y. The first to sixth separating structures B1 to B6 may cut the first active patterns A11 and A12 and the second active patterns A21 and A22.

[0056] The first, second, and third isolation structures B1-B3 may cut the first active patterns A11 and A12, respectively. The first, second, and third isolation structures B1-B3 may be spaced apart from each other in the first direction X and extend in the second direction. The first, second, and third isolation structures B1-B3 may be spaced apart from the first gate structure G1 and the second gate structure G2 in the first direction X.

[0057] The first gate structure G1 may be interposed between the first isolation structure B1 and the second isolation structure B2. The first isolation structure B1 and the second isolation structure B2 may define a first cell region UC1 in the first direction X.

[0058] The second gate structure G2 may be interposed between the second isolation structure B2 and the third isolation structure B3. The second isolation structure B2 and the third isolation structure B3 may define a second cell region UC2 in the first direction X.

[0059] The fourth through sixth isolation structures B4 through B6 may cut the second active patterns A21 and A22, respectively. The fourth through sixth isolation structures B4 through B6 may be spaced apart from one another in the first direction X and extend in the second direction. The fourth through sixth isolation structures B4 through B6 may be spaced apart from the third gate structure G3 and the fourth gate structure G4 in the first direction X.

[0060] The third gate structure G3 may be interposed between the fourth isolation structure B4 and the fifth isolation structure B5. The fourth isolation structure B4 and the fifth isolation structure B5 may define a third cell region UC3 in the first direction X.

[0061] The fourth gate structure G4 may be interposed between the fifth isolation structure B5 and the sixth isolation structure B6. The fifth isolation structure B5 and the sixth isolation structure B6 may define a fourth cell region UC4 in the first direction X.

[0062] The first through sixth isolation structures B1-B6 may each include, but are not limited to, an insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof. For example, the first through sixth isolation structures B1-B6 may each include a silicon oxide film.

[0063] In this specification, adjacent gate structures and / or isolation structures are said to be spaced apart by one gate pitch. One gate pitch can be defined as the sum of the distance between two adjacent gate structures (or the distance between adjacent gate structures and isolation structures) and the width of one gate structure (or the width of one isolation structure). Alternatively, one gate pitch can be defined as the distance between the centerline of one gate structure and the centerline of another adjacent gate structure (or the centerline of an adjacent isolation structure). As an example, the first isolation structure B1 and the first gate structure G1 may be spaced apart by one gate pitch.

[0064] The first to third cutting patterns C1 to C3 may be spaced apart from each other in the second direction Y and may each extend longitudinally in the first direction X. The first to third cutting patterns C1 to C3 may be spaced apart from the first active patterns A11 and A12 and the second active patterns A21 and A22 in the second direction Y. The first to third cutting patterns C1 to C3 may cut the first to fourth gate structures G1 to G4.

[0065] The first active patterns A11 and A12 may be interposed between the first cutting pattern C1 and the second cutting pattern C2. The first cutting pattern C1 and the second cutting pattern C2 may define a first cell region UC1 and a second cell region UC2 in the second direction Y. The first gate structure G1, the second gate structure G2, and the first to third isolation structures B1 to B3 may be cut by the first cutting pattern C1 and the second cutting pattern C2. The first gate structure G1, the second gate structure G2, and the first to third isolation structures B1 to B3 may extend in the second direction Y between the first cutting pattern C1 and the second cutting pattern C2, respectively.

[0066] The second active patterns A21 and A22 may be interposed between the second cutting pattern C2 and the third cutting pattern C3. The second cutting pattern C2 and the third cutting pattern C3 may define a third cell region UC3 and a fourth cell region UC4 in the second direction Y. The third gate structure G3, the fourth gate structure G4, and the fourth to sixth isolation structures B4 to B6 may be cut by the second cutting pattern C2 and the third cutting pattern C3. The third gate structure G3, the fourth gate structure G4, and the fourth to sixth isolation structures B4 to B6 may extend in the second direction Y between the second cutting pattern C2 and the third cutting pattern C3, respectively.

[0067] The first to third cutting patterns C1 to C3 may each include, but are not limited to, at least one of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof. For example, the first to third cutting patterns C1 to C3 may each include a silicon nitride film.

[0068] The lower source / drain regions 160 are formed in the lower active patterns A11 and A21 on side surfaces of the first through fourth gate structures G1 to G4 and the first through sixth isolation structures B1 to B6. The lower bridge patterns 111 and 112 may be connected to the lower source / drain regions 160 through the lower gate electrode 130 and the gate spacer 135. The lower source / drain regions 160 may be separated from the lower gate electrode 130 by the gate spacer 135 and / or the gate dielectric layer 120. In this specification, the lower source / drain regions 160 may be described as a component included in the lower active patterns A11 and A21, or as a separate component distinct from the lower active patterns A11 and A21.

[0069] In some embodiments, the lower source / drain regions 160 may include an epitaxial layer doped with impurities. For example, the lower source / drain regions 160 may include epitaxial patterns grown by epitaxial growth from the lower active patterns A11 and A21. When the lower active patterns A11 and A21 are channel regions of PFETs, the lower source / drain regions 160 may include P-type impurities (e.g., B, In, Ga, or Al) and / or impurities for preventing diffusion of the P-type impurities.

[0070] The upper source / drain regions 260 are formed in the upper active patterns A12 and A22 on side surfaces of the first through fourth gate structures G1 to G4 and side surfaces of the first through sixth isolation structures B1 to B6. The upper bridge patterns 211 and 212 may be connected to the upper source / drain regions 260 through the upper gate electrode 230 and the gate spacer 135. The upper source / drain regions 260 may be separated from the upper gate electrode 230 by the gate spacer 135 and / or the gate dielectric film 120. In this specification, the upper source / drain regions 260 may be described as a component included in the upper active patterns A12 and A22, or as a separate component separate from the upper active patterns A12 and A22.

[0071] In some embodiments, the upper source / drain regions 260 may include an epitaxial layer doped with impurities. For example, the upper source / drain regions 260 may include epitaxial patterns grown by epitaxial growth from the upper active patterns A12 and A22. When the upper active patterns A12 and A22 are channel regions of an NFET, the upper source / drain regions 260 may include N-type impurities (e.g., P, Sb, or As) and / or impurities to prevent diffusion of the N-type impurities.

[0072] In some embodiments, an intermediate insulating layer 182 is formed between the lower source / drain region 160 and the upper source / drain region 260. The intermediate insulating layer 182 may cover the lower source / drain region 160, and the upper source / drain region 260 may be formed on the intermediate insulating layer 182. The intermediate insulating layer 182 may electrically isolate the lower source / drain region 160 from the upper source / drain region 260. The intermediate insulating layer 182 may include, for example, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof.

[0073] In some embodiments, an intermediate spacer 184 may be formed between the intermediate insulating pattern 202 and the intermediate insulating layer 182. The intermediate spacer 184 may extend along a side of the intermediate insulating pattern 202. The intermediate spacer 184 may be interposed between the lower source / drain region 160 and the upper source / drain region 260. The intermediate spacer 184 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof.

[0074] The first interlayer insulating film 280 may fill spaces on the outer surfaces of the gate spacers 135. The first interlayer insulating film 280 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbonitride, silicon oxycarbonitride, and a low-k material having a dielectric constant smaller than that of silicon oxide.

[0075] The lower source / drain contacts 170 may be connected to the lower source / drain regions 160. For example, the lower source / drain contacts 170 may extend in the third direction Z to penetrate the substrate 101 and contact the lower source / drain regions 160. Thus, the lower source / drain contacts 170 may be electrically connected to the lower source / drain regions 160 of the lower active patterns A11 and A21.

[0076] The upper source / drain contacts 270 may be connected to the upper source / drain regions 260. For example, the upper source / drain contacts 270 may extend in the third direction Z to penetrate the first interlayer insulating film 280 and contact the upper source / drain regions 260. Thus, the upper source / drain contacts 270 may be electrically connected to the upper source / drain regions 260 of the upper active patterns A12 and A22.

[0077] The first to fifth lower connection contacts BC1 to BC5 may be connected to the lower source / drain contacts 170. For example, a lower interlayer insulating film 295 covering the substrate 101 and the lower source / drain contacts 170 may be formed on the second surface 101b of the substrate 101. The first to fifth lower connection contacts BC1 to BC5 may penetrate the lower interlayer insulating film 295 and contact the lower source / drain contacts 170, respectively. The first to fifth lower connection contacts BC1 to BC5 may be electrically connected to the lower source / drain regions 160 of the lower active patterns A11 and A21 through the lower source / drain contacts 170. In the following description, the number, shape, and arrangement of the first to fifth lower connection contacts BC1 to BC5 are merely examples and are not limited to those illustrated. Unlike the illustrations, some of the first to fifth lower connection contacts BC1 to BC5 may be omitted.

[0078] The first bottom connection contact BC1 may be connected to the bottom source / drain contact 170 between the first gate structure G1 and the second isolation structure B2. The second bottom connection contact BC2 may be connected to the bottom source / drain contact 170 between the second isolation structure B2 and the second gate structure G2. The third bottom connection contact BC3 may be connected to the bottom source / drain contact 170 between the second gate structure G2 and the third isolation structure B3. The fourth bottom connection contact BC4 may be connected to the bottom source / drain contact 170 between the fourth isolation structure B4 and the third gate structure G3. The fifth bottom connection contact BC5 may be connected to the bottom source / drain contact 170 between the fifth isolation structure B5 and the fourth gate structure G4.

[0079] The first to eighth upper connection contacts FC1 to FC8 may be connected to the upper source / drain contacts 270. For example, a second interlayer insulating film 290 may be formed on the upper surface of the first interlayer insulating film 280 to cover the first to fourth gate structures G1 to G4, the first interlayer insulating film 280, and the upper source / drain contacts 270. The first to eighth upper connection contacts FC1 to FC8 may each penetrate the second interlayer insulating film 290 and contact the upper source / drain contacts 270. The first to eighth upper connection contacts FC1 to FC8 may be electrically connected to the upper source / drain regions 260 of the upper active patterns A12 and A22 through the upper source / drain contacts 270. In the following description, the number, shape, and arrangement of the first to eighth upper connection contacts FC1 to FC8 are merely examples and are not limited to those illustrated. Unlike the illustrations, some of the first to eighth upper connection contacts FC1 to FC8 may be omitted.

[0080] The first upper connection contact FC1 may be connected to the upper source / drain contact 270 between the first isolation structure B1 and the first gate structure G1. The second upper connection contact FC2 may be connected to the upper source / drain contact 270 between the first gate structure G1 and the second isolation structure B2. The third upper connection contact FC3 may be connected to the upper source / drain contact 270 between the second isolation structure B2 and the second gate structure G2. The fourth upper connection contact FC4 may be connected to the upper source / drain contact 270 between the second gate structure G2 and the third isolation structure B3. The fifth upper connection contact FC5 may be connected to the upper source / drain contact 270 between the fourth isolation structure B4 and the third gate structure G3. The sixth upper connection contact FC6 may be connected to the upper source / drain contact 270 between the third gate structure G3 and the fifth isolation structure B5. The seventh upper connection contact FC7 may be connected to the upper source / drain contact 270 between the fifth isolation structure B5 and the fourth gate structure G4. The eighth upper connecting contact FC8 may be connected to the upper source / drain contact 270 between the fourth gate structure G4 and the sixth isolation structure B6.

[0081] The back surface wiring structure BW is formed on the second surface 101b of the substrate 101. For example, the back surface wiring structure BW may include a back surface inter-wiring insulating film 400 covering the lower interlayer insulating film 295 and back surface wiring patterns 411 to 413 in the back surface inter-wiring insulating film 400. The back surface wiring patterns 411 to 413 may be insulated from each other by the back surface inter-wiring insulating film 400. The number, shape, arrangement, etc. of the back surface wiring patterns 411 to 413 are merely examples and are not limited to those shown in the drawings.

[0082] In some embodiments, the back surface wiring patterns 411 to 413 may include a first back surface wiring pattern 411, a second back surface wiring pattern 412, and a third back surface wiring pattern 413. The first back surface wiring pattern 411, the second back surface wiring pattern 412, and the third back surface wiring pattern 413 may be spaced apart from each other in the second direction Y and may each extend long in the first direction X.

[0083] The first back surface wiring pattern 411 and the third back surface wiring pattern 413 may be alternately arranged in the second direction Y. The second back surface wiring pattern 412 may be interposed between the first back surface wiring pattern 411 and the third back surface wiring pattern 413 in the second direction Y. In some embodiments, one first back surface wiring pattern 411 may overlap the second cut pattern C2 in the third direction Z. In some embodiments, one third back surface wiring pattern 413 may overlap the first cut pattern C1 in the third direction Z, and the other third back surface wiring pattern 413 may overlap the third cut pattern C3 in the third direction Z.

[0084] In some embodiments, the first back surface wiring pattern 411 and the third back surface wiring pattern 413 are power supply lines (for example, V SS or V DD 1. For example, the first back surface wiring pattern 411 is provided as the first power supply wiring PR1 in FIG. 1, and the third back surface wiring pattern 413 is provided as the second power supply wiring PR2 in FIG. 1. The first back surface wiring pattern 411 supplies the first power supply voltage (for example, V SS) to the first to fourth cell regions UC1 to UC4, and the third back surface wiring pattern 413 applies the second power supply voltage (for example, V DD ) may be applied.

[0085] In some embodiments, the first cell region UC1 and the second cell region UC2 may share one third back surface wiring pattern 413. For example, a portion of the first bottom connection contact BC1 and a portion of the third bottom connection contact BC3 may overlap with the one third back surface wiring pattern 413 in the third direction Z. The first bottom connection contact BC1 and the third bottom connection contact BC3 may be electrically connected to the one third back surface wiring pattern 413 via back surface via patterns 403 extending in the third direction Z.

[0086] In some embodiments, the third cell region UC3 and the fourth cell region UC4 may share another third back surface wiring pattern 413. For example, a portion of the fourth bottom connection contact BC4 and a portion of the fifth bottom connection contact BC5 may overlap with the other third back surface wiring pattern 413 in the third direction Z. The fourth bottom connection contact BC4 and the fifth bottom connection contact BC5 may be electrically connected to the other third back surface wiring pattern 413 via back surface via patterns 403 extending in the third direction Z.

[0087] The front wiring structure FW is formed on the first surface 101a of the substrate 101. For example, the front wiring structure FW may include a front inter-wire insulating film 300 covering the second interlayer insulating film 290 and front wiring patterns 311-314 in the front inter-wire insulating film 300. The front wiring patterns 311-314 may be insulated from each other by the front inter-wire insulating film 300. The number, shape, arrangement, etc. of the front wiring patterns 311-314 are merely examples and are not limited to those shown in the drawings.

[0088] In some embodiments, the front surface wiring patterns 311 to 314 may include a first front surface wiring pattern 311, a second front surface wiring pattern 312, a third front surface wiring pattern 313, and a fourth front surface wiring pattern 314. The first front surface wiring pattern 311, the second front surface wiring pattern 312, the third front surface wiring pattern 313, and the fourth front surface wiring pattern 314 may be spaced apart from each other in the second direction Y and may each extend long in the first direction X.

[0089] The first front wiring pattern 311 and the fourth front wiring pattern 314 may be arranged alternately in the second direction Y. The second front wiring pattern 312 and the third front wiring pattern 313 may be interposed between the first front wiring pattern 311 and the fourth front wiring pattern 314 in the second direction Y. In some embodiments, one first front wiring pattern 311 may overlap the second cut pattern C2 in the third direction Z. In some embodiments, one fourth front wiring pattern 314 may overlap the first cut pattern C1 in the third direction Z, and the other fourth front wiring pattern 314 may overlap the third cut pattern C3 in the third direction Z.

[0090] In some embodiments, the first to fourth cell regions UC1 to UC4 may share one first front wiring pattern 311. For example, a portion of the first upper connection contact FC1, a portion of the fourth upper connection contact FC4, a portion of the fifth upper connection contact FC5, and a portion of the eighth upper connection contact FC8 may overlap with the one first front wiring pattern 311 in the third direction Z. The first upper connection contact FC1, the fourth upper connection contact FC4, the fifth upper connection contact FC5, and the eighth upper connection contact FC8 may be electrically connected to the one first front wiring pattern 311 through a first front via pattern 301 extending in the third direction Z.

[0091] In some embodiments, the second front wiring pattern 312 may be electrically connected to the upper source / drain regions 260 of the upper active patterns A12 and A22. For example, a portion of the second upper connection contact FC2, a portion of the third upper connection contact FC3, a portion of the sixth upper connection contact FC6, and a portion of the seventh upper connection contact FC7 may each overlap with the second front wiring pattern 312 in the third direction Z. The second upper connection contact FC2, the third upper connection contact FC3, the sixth upper connection contact FC6, and the seventh upper connection contact FC7 may each be electrically connected to the second front wiring pattern 312 through the second front via pattern 302 extending in the third direction Z.

[0092] In some embodiments, the third front wiring pattern 313 may be electrically connected to the first through fourth gate structures G1-G4. For example, the upper gate electrodes 230 of each of the first through fourth gate structures G1-G4 may overlap with the third front wiring pattern 313 in the third direction Z. The upper gate electrodes 230 of each of the first through fourth gate structures G1-G4 may be electrically connected to the third front wiring pattern 313 through third front via patterns 303 extending in the third direction Z.

[0093] In some embodiments, the width of the first front surface wiring pattern 311 may be greater than the width of each of the second to fourth front surface wiring patterns 312 to 314. Here, the width refers to the width in the second direction Y.

[0094] The first through via TV1 may be interposed between the first cell region UC1 and the third cell region UC3. The first through via TV1 may extend in the third direction Z and penetrate the substrate 101 and the second cutting pattern C2. The first through via TV1 may electrically connect the first back surface wiring pattern 411 and the first front surface wiring pattern 311. The first through via TV1 may include a conductive material, for example, but is not limited to, tungsten (W) or aluminum (Al).

[0095] The first front wiring pattern 311 can also be provided as the first power supply wiring PR1 in FIG. 1 by being electrically connected to the first back wiring pattern 411 by the first through via TV1. For example, the first front wiring pattern 311 can supply the first power supply voltage (for example, V SS ) can be applied.

[0096] In some embodiments, the width of the first through via TV1 may be smaller than the width of the second cutting pattern C2, where width means the width in the second direction Y.

[0097] In some embodiments, the first through via TV1 may not be aligned with the first to fourth gate structures G1 to G4 and / or the first to sixth isolation structures B1 to B6 along the second direction Y. For example, as shown, the first through via TV1 may be aligned with the second top connection contact FC2 and the sixth top connection contact FC6 along the second direction Y.

[0098] In some embodiments, the width of the first through via TV1 may decrease from the second region II toward the first region I. This is due to, but is not limited to, the fact that the etching process for forming the first through via TV1 is performed in the direction from the second region II toward the first region I.

[0099] The second through via TV2 may be arranged along the first direction X with the first through via TV1. The second through via TV2 may extend in the third direction Z to penetrate the substrate 101 and the second cutting pattern C2. The second through via TV2 may electrically connect the lower source / drain region 160 and the upper source / drain region 260. For example, a portion of the second lower connection contact BC2 and a portion of the third upper connection contact FC3 may overlap the second cutting pattern C2 in the third direction Z. The second through via TV2 may extend in the third direction Z to connect the second lower connection contact BC2 and the third upper connection contact FC3.

[0100] In some embodiments, the width of the second through via TV2 may be smaller than the width of the second cutting pattern C2, where width means the width in the second direction Y.

[0101] In some embodiments, the width of the second through via TV2 may decrease from the second region II toward the first region I. This is due to, but is not limited to, the fact that the etching process for forming the second through via TV2 is performed in the direction from the second region II toward the first region I.

[0102] As semiconductor devices become increasingly highly integrated, individual circuit patterns are becoming finer to accommodate more elements in the same area. To this end, semiconductor devices using stacked multi-gate transistors, in which a multi-gate transistor in an upper region (e.g., a second region II) is stacked on a multi-gate transistor in a lower region (e.g., a first region I), are being researched.

[0103] In addition, in order to reduce a voltage drop (e.g., IR drop) of a power delivery network (PDN) provided to the stacked multi-gate transistor, a so-called back side power delivery network (BSPDN) can be provided, in which a power supply voltage is provided from the back side of the substrate 101. However, the connection between the back side power delivery network and the upper region causes various problems due to its complexity.

[0104] For example, a tall via extending from the lower region to the upper region may be provided within the unit cell region to connect the backside power supply network to the upper region. However, since the area adjacent to the gate structure of such a tall via is larger than that of a via extending only in the lower region or a via extending only in the upper region, the parasitic capacitance with the gate structure increases, which causes a decrease in the performance of the semiconductor device. Therefore, a tap cell is separately provided outside the unit cell region to electrically connect the backside power supply network to the frontside wiring pattern. However, since such a tap cell requires an additional area, the integration density of the semiconductor device decreases.

[0105] Alternatively, semiconductor devices according to some embodiments may provide improved integration and performance by utilizing the first through vias TV1. Specifically, as described above, the first through vias TV1 are disposed between unit cell regions adjacent in the second direction Y (e.g., between the first cell region UC1 and the third cell region UC3). In addition, the first through vias TV1 connect the first back surface wiring pattern 411 to the first front surface wiring pattern 311, thereby applying the first power supply voltage (e.g., V SS ) can be provided. Such first through vias TV1 can provide improved integration because an additional region for connecting the backside wiring structure BW and the second region II is not required. Also, as described above, the first through vias TV1 can be arranged at predetermined intervals in the first direction X and can be arranged to avoid other through vias (e.g., the second through vias TV2) in the first direction X. This can reduce the complexity of connections between the backside power supply network and the upper region, thereby providing a semiconductor device with improved integration and performance.

[0106] 8 is a cross-sectional view illustrating a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with the contents explained with reference to FIGS. 1 to 7 will be briefly explained or omitted. For reference, FIG. 8 is another cross-sectional view taken along line AA in FIG. 2.

[0107] 2 and 8, in devices according to some embodiments, each of the first through fourth gate structures G1-G4 further includes an inner spacer 136.

[0108] Inner spacers 136 are formed in the second region II. The inner spacers 136 are formed on the side surfaces of the upper gate electrode 230 between the upper bridge patterns 211 and 212. The inner spacers 136 may be formed on the side surfaces of the upper gate electrode 230 between the intermediate insulating pattern 202 and the upper active patterns A12 and A22. The upper source / drain regions 260 may be separated from the upper gate electrode 230 by the gate spacers 135, the inner spacers 136, and / or the gate dielectric film 120.

[0109] Although the inner spacers 136 are shown only as not being formed in the first region I, this is merely an example. Contrary to what is shown, the inner spacers 136 may be formed in both the first region I and the second region II. Alternatively, contrary to what is shown, the inner spacers 136 may be formed only in the first region I and not in the second region II.

[0110] 9 is a cross-sectional view illustrating a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with the contents explained with reference to FIGS. 1 to 7 will be briefly explained or omitted. For reference, FIG. 9 is another cross-sectional view taken along line DD in FIG. 2.

[0111] 2 and 9, in the semiconductor device according to some embodiments, the width of the first through via TV1 decreases from the first region I toward the second region II.

[0112] This is because the etching process for forming the first through via TV1 is performed in the direction from the first region I to the second region II, but is not limited to this.

[0113] Figure 10 is an exemplary layout diagram illustrating a semiconductor device according to some embodiments. Figure 11 is a cross-sectional view taken along line FF in Figure 10. For convenience of explanation, parts that overlap with those described with reference to Figures 1 to 7 will be briefly explained or omitted.

[0114] Referring to Figures 10 and 11, in semiconductor devices according to some embodiments, the first through via TV1 is not aligned with the first to eighth upper connection contacts FC1 to FC8 and / or the first to fifth lower connection contacts BC1 to BC5 along the second direction Y.

[0115] For example, as shown, the first through via TV1 may be aligned along the second direction Y with the first gate structure G1 and the third gate structure G3.

[0116] Figure 12 is an exemplary layout diagram illustrating a semiconductor device according to some embodiments. Figure 13 is a cross-sectional view taken along line GG in Figure 12. For convenience of explanation, parts that overlap with those described with reference to Figures 1 to 7 will be briefly explained or omitted.

[0117] 12 and 13, in the semiconductor device according to some embodiments, the first through via TV1 is aligned with the first front-side via pattern 301 along the second direction Y.

[0118] For example, a portion of the sixth upper connection contact FC6 may overlap with the first front wiring pattern 311 in the third direction Z. The sixth upper connection contact FC6 may be electrically connected to the first front wiring pattern 311 through the first front via pattern 301 extending in the third direction Z. The first through via TV1 may be arranged along the second direction Y with the sixth upper connection contact FC6.

[0119] Figure 14 is an exemplary layout diagram illustrating a semiconductor device according to some embodiments. Figure 15 is a cross-sectional view taken along line HH in Figure 14. For convenience of explanation, parts that overlap with those described with reference to Figures 1 to 7 will be briefly described or omitted.

[0120] 14 and 15, the semiconductor device according to some embodiments further includes a third through via TV3.

[0121] The third through via TV3 is arranged with the first through via TV1 along the first direction X. The third through via TV3 may extend in the third direction Z to penetrate the substrate 101 and the second cutting pattern C2. The third through via TV3 may electrically connect the lower source / drain region 160 and the upper source / drain region 260. For example, a portion of the sixth lower connection contact BC6 and a portion of the first upper connection contact FC1 may overlap the second cutting pattern C2 in the third direction Z. The third through via TV3 may extend in the third direction Z to connect the sixth lower connection contact BC6 and the first upper connection contact FC1.

[0122] Although the third through via TV3 is shown only connecting the lower source / drain region 160 and the upper source / drain region 260 in the first cell region UC1, this is merely an example. It goes without saying that the third through via TV3 can also connect the lower source / drain region 160 and the upper source / drain region 260 in the third cell region UC3 and / or the fourth cell region UC4.

[0123] In some embodiments, the width of the third through via TV3 may be smaller than the width of the second cutting pattern C2, where width refers to the width in the second direction Y.

[0124] In some embodiments, the width of the third through via TV3 may decrease from the second region II toward the first region I. This is due to, but is not limited to, the fact that the etching process for forming the third through via TV3 is performed in the direction from the second region II toward the first region I.

[0125] 16 to 18 are various schematic layout diagrams illustrating semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with the contents described with reference to FIGS. 1 to 15 will be briefly described or omitted.

[0126] 16, in semiconductor devices according to some embodiments, at least some of the plurality of first through vias TV1 may be arranged in a zigzag pattern in the second direction Y.

[0127] For example, the first power wiring PR1 may include a first power line PR1a and a second power line PR1b. The first power line PR1a and the second power line PR1b may be spaced apart from each other in the second direction Y and may each extend long in the first direction X.

[0128] The first through via TV1 may include a plurality of first sub-through vias TV1a and a plurality of second sub-through vias TV1b. The plurality of first sub-through vias TV1a may be arranged along the first direction X at predetermined intervals. The first power supply line PR1a may be commonly connected to the plurality of first sub-through vias TV1a. The plurality of second sub-through vias TV1b may be arranged along the first direction X at predetermined intervals. The second power supply line PR1b may be commonly connected to the plurality of second sub-through vias TV1b. The first sub-through vias TV1a and the second sub-through vias TV1b do not have to be arranged along the second direction Y.

[0129] Referring to FIG. 17, in semiconductor devices according to some embodiments, at least some of the first through vias TV1 arranged along the first direction X are spaced apart at different intervals.

[0130] For example, the first through via TV1 may include a third sub-through via TV1c, a fourth sub-through via TV1d, and a fifth sub-through via TV1e arranged sequentially along the first direction X. One first power wiring PR1 may be commonly connected to the third sub-through via TV1c, the fourth sub-through via TV1d, and the fifth sub-through via TV1e. The third sub-through via TV1c and the fourth sub-through via TV1d may be spaced apart by a first distance D11 in the first direction X. The fourth sub-through via TV1d and the fifth sub-through via TV1e may be spaced apart by a second distance D12 different from the first distance D11 in the first direction X.

[0131] Referring to FIG. 18, in semiconductor devices according to some embodiments, at least some of the plurality of first through vias TV1 may be spaced apart at different intervals.

[0132] For example, the first power wiring PR1 may include a first power line PR1a and a second power line PR1b. The first power line PR1a and the second power line PR1b may be spaced apart from each other in the second direction Y and may each extend long in the first direction X.

[0133] The first through via TV1 may include a plurality of sixth sub-through vias TV1f and a plurality of seventh sub-through vias TV1g. The sixth sub-through vias TV1f may be arranged along the first direction X at a third distance D21. The first power line PR1a may be commonly connected to the sixth sub-through vias TV1f. The seventh sub-through vias TV1g may be arranged along the first direction X at a fourth distance D22 different from the third distance D21. The second power line PR1b may be commonly connected to the seventh sub-through vias TV1g.

[0134] Although the present invention has been described above with reference to the accompanying drawings, it should be understood that the present invention is not limited to the above-described embodiments and can be manufactured in various different forms, and that those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. [Explanation of symbols]

[0135] 101 Substrate 102 Base insulation pattern 111,112 Lower Bridge Pattern 120 Gate dielectric film 130 first gate electrode 135 Gate spacer 137 Gate capping film 160 Lower source / drain region 170 bottom source / drain contact 202 Intermediate insulation pattern 211,212 Upper Bridge Pattern 260 upper source / drain region 270 Top Source / Drain Contact 300 Front inter-wiring insulating film 311~314 Front wiring pattern 400 Backside inter-wiring insulating film 411~413 Back wiring pattern A11, A12 First active pattern A21, A22 Second active pattern B1~B6 Separation structure BC1~BC6 Lower connection contacts C1~C3 cutting patterns FC1~FC8 Upper connection contacts G1~G4 gate structure TV1~TV3 through vias UC1~UC4 cell area

Claims

1. a substrate including opposed first and second surfaces; a first active pattern including a first lower active pattern and a first upper active pattern sequentially stacked on the first surface and extending in a first direction; a second active pattern including a second lower active pattern and a second upper active pattern sequentially stacked on the first surface and extending in the first direction; a first gate structure extending in a second direction intersecting the first direction on the first active pattern; a second gate structure extending in the second direction on the second active pattern and arranged in the second direction with respect to the first gate structure; a cutting structure extending in the first direction between the first active pattern and the second active pattern and separating the first gate structure and the second gate structure; a front wiring pattern extending in the first direction on an upper surface of the cutting structure; a first back surface wiring pattern extending in the first direction on the second surface; a first through via penetrating the substrate and the cutting structure and connecting the front wiring pattern and the first back wiring pattern;

2. The semiconductor device of claim 1 , wherein a width of the first through via in the second direction is smaller than a width of the cutting structure.

3. an upper connection contact on a side surface of the first gate structure, the upper connection contact being connected to an upper source / drain region of the first upper active pattern; The semiconductor device according to claim 1 , wherein the first through via is aligned with the upper connection contact along the second direction.

4. 2. The semiconductor device according to claim 1, further comprising a first upper connection contact on a side surface of the first gate structure, the first upper source / drain region of the first upper active pattern connecting the front wiring pattern.

5. The semiconductor device according to claim 4 , wherein the first through via does not overlap the first upper connection contact in the second direction.

6. 5. The semiconductor device of claim 4, further comprising a second upper connection contact on a side surface of the second gate structure, the second upper source / drain region of the second upper active pattern connecting the front wiring pattern.

7. a second rear surface wiring pattern extending in the first direction on the second surface and arranged along the second direction with respect to the first rear surface wiring pattern; 2. The semiconductor device according to claim 1, wherein different power supply voltages are applied to said first back surface wiring pattern and said second back surface wiring pattern.

8. 8. The semiconductor device according to claim 7, further comprising a lower connection contact on a side surface of said first gate structure, said lower connection contact connecting a lower source / drain region of said first lower active pattern to said second backside wiring pattern.

9. a substrate including opposed first and second surfaces; a lower active pattern extending in a first direction on the first surface; an upper active pattern that is spaced apart from the first surface relative to the lower active pattern and extends in the first direction; a gate structure extending in a second direction intersecting the first direction on the lower active pattern and the upper active pattern; a first cutting structure spaced apart from the lower active pattern and the upper active pattern in the second direction and extending in the first direction to cut the gate structure; a first front surface wiring pattern extending in the first direction on an upper surface of the first cutting structure; a first upper connection contact on a side surface of the gate structure, the first connection contact being connected to an upper source / drain region of the upper active pattern; a first back surface wiring pattern extending in the first direction on the second surface; a first lower connection contact on a side surface of the gate structure, the first lower connection contact being connected to a lower source / drain region of the lower active pattern; a first through via that penetrates the substrate and the first cutting structure and connects the first front surface wiring pattern and the first back surface wiring pattern; a second through via passing through the substrate and the first disconnecting structure and connecting the first upper connection contact and the first lower connection contact; The semiconductor device, wherein the first through vias and the second through vias are arranged along the first direction.

10. A semiconductor device including a first cell region, a second cell region arranged with the first cell region along a first direction, and a third cell region arranged with the first cell region along a second direction intersecting the first direction, a substrate including opposed first and second surfaces; a front wiring pattern extending in the first direction on the first surface; a first back surface wiring pattern extending in the first direction on the second surface; a first through via that penetrates the substrate between the first cell region and the third cell region and connects the front wiring pattern and the first back wiring pattern; The first through via and the second through via arranged along the first direction, each of the first to third cell regions includes a lower active pattern and an upper active pattern that are sequentially stacked on the first surface and extend in the first direction, and a gate structure that extends in the second direction on the lower active pattern and the upper active pattern; The second through via electrically connects the lower active pattern in the second cell region and the upper active pattern in the second cell region.

Images