Pattern determination method, semiconductor device manufacturing method, and exposure apparatus

Abstract

To improve throughput in forming a wiring pattern of FO-WLP.SOLUTION: A pattern determination method includes acquiring misalignment information of a first semiconductor chip, and selecting a pattern from a plurality of patterns based on the misalignment information, wherein the pattern is a pattern of a first wiring region formed on the first semiconductor chip, and a first end portion of the first wiring region overlaps a pad of the first semiconductor chip.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to a pattern determination method, a semiconductor device manufacturing method, and an exposure apparatus. [Background technology]

[0002] In recent years, semiconductor device packages called Fan Out Wafer Level Packages (FO-WLPs) and Fan Out Plate Level Packages (FO-PLPs) have become known.

[0003] For example, in the manufacture of FO-WLP, multiple semiconductor chips are arranged on a wafer-shaped support substrate and solidified with a molding material such as resin to form a pseudo-wafer, and an exposure device is used to form a rewiring layer that connects the pads of the semiconductor chips.

[0004] There is a demand for an improvement in throughput in forming the rewiring layer of FO-WLP and FO-PLP (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-081281 Summary of the Invention

[0006] According to an aspect of the disclosure, there is provided an exposure apparatus including: a spatial light modulator; a calculation unit that calculates positions of the first connection portion and the second connection portion based on a first position measurement result that is a position measurement result of a predetermined measurement point on a first semiconductor chip arranged on a substrate; a second position measurement result that is a position measurement result of a predetermined measurement point on a second semiconductor chip arranged on the substrate; and design information of the first connection portion of the first semiconductor chip and the second connection portion of the second semiconductor chip; and an exposure processing unit that controls the spatial light modulator based on the calculation result of the calculation unit to expose a wiring pattern that connects the first connection portion and the second connection portion.

[0007] The configurations of the embodiments described below may be modified as appropriate, and at least a portion of the configuration may be replaced with other components. Furthermore, components that are not particularly limited in terms of their placement may be placed in any position that allows them to achieve their function, not limited to the placement disclosed in the embodiments. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a top view showing an outline of a FO-WLP wiring pattern forming system including an exposure apparatus according to the first embodiment. [Figure 2] FIG. 2 is a perspective view that schematically shows the configuration of the exposure apparatus according to the first embodiment. [Figure 3] 3A and 3B are diagrams for explaining the wiring pattern formed by the wiring pattern forming system. [Figure 4] FIG. 4 is a diagram for explaining the module arranged on the optical surface plate. [Figure 5] FIG. 5 is a block diagram showing a control system of the exposure apparatus according to the first embodiment. [Figure 6] FIG. 6(A) is a schematic diagram showing a wafer WF in which all chips are arranged in their designed positions, and FIG. 6(B) is a schematic diagram showing a wafer WF in which chips are arranged shifted from their designed positions. [Figure 7]Figure 7(A) is a diagram showing the optical system of the illumination and projection module, Figure 7(B) is a diagram showing the DMD in outline, Figure 7(C) is a diagram showing the DMD when the power is OFF, Figure 7(D) is a diagram explaining the mirror in the ON state, and Figure 7(E) is a diagram explaining the mirror in the OFF state. [Figure 8] Figure 8 is an enlarged view of the illumination and projection module and its surroundings. [Figure 9] 9(A) to 9(C) are diagrams for explaining predetermined measurement points on a chip. [Figure 10] Figure 10(A) shows a chip fixed to a wafer in a state shifted from its design position, Figure 10(B) is an enlarged view of a partial wiring section, and Figure 10(C) shows chips placed in positions shifted from their design positions connected together by a wiring pattern. [Figure 11] Figure 11(A) shows a wiring pattern that connects pads of chips placed in the design position, Figures 11(B) and 11(C) are figures for explaining an example of a wiring pattern that connects pads of chips that are shifted from the design position, and Figures 11(D) to 11(F) are figures for explaining a method of creating a wiring pattern. [Figure 12] Figure 12(A) shows a wiring pattern that connects pads of chips placed at the design position, and Figures 12(B) and 12(C) are figures for explaining other examples of wiring patterns that connect pads of chips that are shifted from the design position. [Figure 13] FIG. 13 is a conceptual diagram showing the procedure for forming a wiring pattern on a FO-WLP in an exposure apparatus. [Figure 14] Figure 14(A) is a diagram showing a wiring pattern that connects pads of chips placed in the designed position, and Figures 14(B) to 14(G) are diagrams for explaining an example of a method for forming wiring patterns that connect pads of chips that are shifted from the designed position. [Figure 15]FIG. 15(A) is a diagram showing the configuration of an illumination and projection module according to the second embodiment, and FIGS. 15(B) to 15(D) are diagrams for explaining the correction of a wiring pattern using a set of prisms. [Figure 16] Figure 16(A) is a diagram showing a wiring pattern that connects pads of chips placed in the design position, and Figures 16(B) to 16(F) are diagrams for explaining another example of a method for forming a wiring pattern that connects pads of chips that are shifted from the design position. [Figure 17] FIG. 17 is a top view showing an overview of a wiring pattern forming system according to the third embodiment. [Figure 18] FIG. 18 is a top view showing an overview of a wiring pattern forming system according to the fourth embodiment. [Figure 19] 19(A) and 19(B) are diagrams for explaining another example 1 of predetermined measurement points on a chip. [Figure 20] 20(A) and 20(B) are diagrams for explaining another example 2 of predetermined measurement points on a chip. DETAILED DESCRIPTION OF THE INVENTION

[0009] First Embodiment An exposure apparatus according to a first embodiment will be described with reference to FIGS. 1 to 13. In the following description, when simply referred to as a substrate P, a rectangular substrate is referred to, and a wafer-shaped substrate is referred to as a wafer WF. The normal direction of the substrate P or wafer WF placed on a substrate stage 30 (described later) is referred to as the Z-axis direction, the direction in which the substrate P or wafer WF is scanned relative to a spatial light modulator (SLM) in a plane perpendicular to the Z-axis direction is referred to as the X-axis direction, the direction perpendicular to the Z-axis and the X-axis is referred to as the Y-axis direction, and the directions of rotation (tilt) around the X-axis, Y-axis, and Z-axis are referred to as the θx, θy, and θz directions, respectively. Examples of spatial light modulators include liquid crystal elements, digital micromirror devices (DMDs), and magneto-optic spatial light modulators (MOSLMs). The exposure apparatus EX according to the first embodiment includes a DMD 204 as a spatial light modulator, but may also include other spatial light modulators.

[0010] Fig. 1 is a top view showing an overview of a wiring pattern forming system 500 for FO-WLP and FO-PLP, including an exposure apparatus EX according to one embodiment. Fig. 2 is a perspective view showing a schematic configuration of the exposure apparatus EX. Figs. 3(A) and 3(B) are diagrams for explaining the wiring pattern formed by the wiring pattern forming system.

[0011] The wiring pattern forming system 500 is a system for forming wiring patterns that connect between semiconductor chips (hereinafter referred to as chips) arranged on a wafer WF, as shown in Figure 3(A), or between chips arranged on a substrate P, as shown in Figure 3(B).

[0012] In this embodiment, a wiring pattern is formed that connects between chips C1 and C2 included in each set (indicated by two-dot chain lines) of chips arranged on wafer WF or substrate P. Although Figures 3(A) and 3(B) illustrate a case where each set includes two chips, the number of chips included in each set may be three or more.

[0013] The following describes the case where a wiring pattern for connecting chips arranged on a wafer WF is formed.

[0014] As shown in FIG. 1, the wiring pattern forming system 500 includes a coater developer apparatus CD and an exposure apparatus EX.

[0015] The coater developer device CD applies a photosensitive resist to the wafer WF. The wafer WF coated with the resist is then carried into a buffer unit PB, which can store multiple wafers WF. The buffer unit PB also serves as a transfer port for the wafer WF.

[0016] More specifically, the buffer unit PB is composed of an inlet and an outlet. Wafers WF coated with resist are loaded one by one into the inlet from the coater-developer device CD. The resist-coated wafers WF are loaded one by one from the coater-developer device CD into the inlet at predetermined intervals, but since multiple wafers are loaded together on a tray TR (described later), the inlet functions as a buffer for storing the wafers WF.

[0017] The unloading section also functions as a buffer when unloading the exposed wafers WF to the coater-developer device CD. The coater-developer device CD can only unload exposed wafers WF one at a time. Therefore, a tray TR carrying multiple exposed wafers WF is placed in the unloading section. This allows the coater-developer device CD to unload the exposed wafers WF one at a time from the tray TR.

[0018] The exposure apparatus EX includes a main body 1 and a substrate exchange unit 2. As shown in Fig. 1, a robot RB is installed in the substrate exchange unit 2. The robot RB arranges multiple wafers WF placed in a buffer unit PB on a single tray TR.

[0019] 1 and 2, in the first embodiment, wafers WF can be placed in three rows of four on the substrate stages 30R and 30L, which will be described later. The tray TR according to the first embodiment is a lattice-shaped tray that can sequentially place wafers WF in one row of four on the substrate stages 30R and 30L. The tray TR may also be a tray that can simultaneously place wafers WF over the entire surface of the substrate stages 30R and 30L (i.e., a tray that can accommodate wafers WF in three rows of four).

[0020] 2, the substrate exchange unit 2 includes exchange arms 20R and 20L. The exchange arm 20R loads and unloads wafers WF (more specifically, a tray TR on which a plurality of wafers WF are placed) onto and from the substrate holder PH of the substrate stage 30R, and the exchange arm 20L loads and unloads wafers WF onto and from the substrate holder PH of the substrate stage 30L. In the following description, when there is no need to particularly distinguish between the exchange arms 20R and 20L, they will be referred to as exchange arm 20. In addition, the substrate holder PH is not shown in any drawings other than FIG. 2.

[0021] Generally, the exchange arms 20R, 20L are each provided with two arms: a load arm for loading the tray TR and a load arm for unloading the tray TR. This allows for high-speed exchange of the tray TR. When loading the wafer WF, the lattice-shaped tray TR is supported by substrate exchange pins 10. When the substrate exchange pins 10 are lowered, the tray TR sinks into grooves (not shown) formed in the substrate stage 30, and the wafer WF is attracted and held by the substrate holder PH on the substrate stage 30. When a row of substrates is placed on the tray TR as shown in FIG. 2, the positions of the substrate stages 30R, 30L or the positions of the exchange arms 20R, 20L are changed to match the positions on the substrate stages 30R, 30L where each tray TR is to be placed.

[0022] When the wafer WF is attracted to the substrate holder PH, the position of a predetermined measurement point on a chip placed on the wafer WF is measured by the alignment system ALG_R or ALG_L mounted on the optical surface plate 110. Figure 4 is a diagram for explaining the modules placed on the optical surface plate 110.

[0023] As shown in Fig. 4, alignment system ALG_R or ALG_L is mounted on an optical table 110 that is kinematically supported on a column 100 (see Fig. 2). Also, as shown in Fig. 4, in addition to alignment system ALG_R or ALG_L, a plurality of illumination and projection modules 200, an autofocus system AF, and alignment system ALG_C are arranged on optical table 110.

[0024] Alignment systems ALG_R and ALG_L are equipped with multiple measurement microscopes, and measure the positions of predetermined measurement points on chips arranged on each wafer WF placed on the substrate holder of the substrate stage 30, using as reference a reference mark 60a (see FIG. 8) of the alignment device 60. The measurement results are output to a data creation device 300 provided in a control system 600 of the exposure apparatus EX.

[0025] 5 is a block diagram showing a control system 600 of the exposure apparatus EX according to this embodiment. As shown in FIG. 5, the control system 600 includes a data creating device 300, a first storage device 310R, a second storage device 310L, and an exposure control device 400.

[0026] The data creation device 300 calculates the positions of all pads of each chip based on the position measurement results received from alignment systems ALG_R and ALG_L of predetermined measurement points on the chip provided on the wafer WF placed on the substrate holder of the substrate stage 30. The data creation device 300 determines a wiring pattern connecting the pads based on the calculation results of the pad positions of each chip, and creates control data to be used for controlling the DMD 204 (details of which will be described later) when generating the determined wiring pattern.

[0027] Here, the reason why the data generating device 300 determines the wiring pattern for connecting the pads based on the calculation results of the pad positions of each chip will be explained.

[0028] FIG. 6A is a schematic diagram showing a wafer WF with all chips arranged in their designed positions (hereinafter referred to as the "design positions"). As shown in FIG. 6A, a wiring pattern WL connecting chip C1 and chip C2 is exposed (formed) using an exposure tool EX. In the FO-WLP system, the chips are solidified on the wafer WF with a molding material such as resin, and as shown in FIG. 6B, the positions of individual chips may be shifted from their designed positions. In this case, if the DMD 204 is controlled to expose the wiring pattern using data indicating the wiring pattern connecting chips located in their designed positions (hereinafter referred to as the "design value data"), the wiring pattern may be shifted from the pad positions, resulting in poor connection or short circuits.

[0029] Therefore, in this embodiment, the positions of predetermined measurement points on each chip included in each set of multiple chips arranged on wafer WF are measured by alignment system ALG_R or ALG_L. Data creation device 300 calculates the positions of all pads on the chip based on the position measurement results obtained from alignment system ALG_R or ALG_L, and creates wiring pattern data in which part of the design value data is corrected based on the calculation results.

[0030] The created wiring pattern data is stored in the first storage device 310R or the second storage device 310L. The first storage device 310R and the second storage device 310L are, for example, SSDs (Solid State Drives).

[0031] The first storage device 310R stores wiring pattern data used to control the DMD 204 when exposing the wafer WF placed on the substrate stage 30R. The second storage device 310L stores wiring pattern data used to control the DMD 204 when exposing the wafer WF placed on the substrate stage 30L. The wiring pattern data stored in the first storage device 310R or the second storage device 310L is transferred to the exposure control device 400.

[0032] The exposure control device 400 controls the illumination and projection modules 200 based on the wiring pattern data to expose the wiring pattern onto the wafer WF. As shown in Fig. 2, in this embodiment, multiple rows (four rows in Fig. 2) each including a plurality of illumination and projection modules 200 are arranged. Note that, for simplification, Fig. 1 shows only one row including a plurality of illumination and projection modules 200. Also, for simplification, Fig. 2 omits the illustration of the alignment systems ALG_R and ALG_L.

[0033] A plurality of illumination and projection modules 200 are provided so that wiring patterns in different sets can be exposed at the same time. In FIG. 2, four rows of illumination and projection modules 200 are provided, but the number of rows of illumination and projection modules 200 may be one to three, or five or more. The number of illumination and projection modules 200 included in each row may be two or more. Furthermore, when multiple wafers WF are placed on the substrate holder, the different sets exposed at the same time by the illumination and projection modules 200 may be different sets within the same wafer WF, or may be sets within different wafers WF.

[0034] 7A is a diagram showing the optical system of the illumination and projection module 200. The illumination and projection module 200 includes a collimator lens 201, a fly-eye lens 202, a main condenser lens 203, a DMD 204, and the like.

[0035] Laser light emitted from a light source LS (see FIG. 2) is taken in by a delivery fiber FB into an illumination / projection module 200. The laser light passes through a collimator lens 201, a fly-eye lens 202, and a main condenser lens 203, and illuminates a DMD 204 almost uniformly.

[0036] Fig. 7(B) is a diagram showing a schematic view of the DMD 204, and Fig. 7(C) shows the DMD 204 when the power is OFF. Note that in Fig. 7(B) to Fig. 7(E), mirrors that are in the ON state are indicated by hatching.

[0037] The DMD 204 has multiple micromirrors 204a whose reflection angles can be controlled. Each micromirror 204a is turned on by tilting around the Y axis. FIG. 7D shows a case where only the central micromirror 204a is turned on, while the other micromirrors 204a are in a neutral state (neither on nor off). Each micromirror 204a is turned off by tilting around the X axis. FIG. 7E shows a case where only the central micromirror 204a is turned off, while the other micromirrors 204a are in a neutral state. The DMD 204 generates an exposure pattern of wiring (hereinafter referred to as wiring pattern) that connects chips by switching the on and off states of each micromirror 204a.

[0038] Illumination light reflected by a mirror in the OFF state is absorbed by an OFF light absorbing plate 205, as shown in Figure 7(A). The illumination / projection module 200 has a magnification for projecting one pixel of the DMD 204 at a predetermined size, and the magnification can be slightly corrected by focusing by driving the lens along the Z axis and by driving some of the lenses. In addition, the DMD 204 itself can be driven in the X, Y, and θz directions by controlling the X, Y, and θ stage (not shown) on which the DMD 204 is mounted, and deviations from a target value of the substrate stage 30, for example, are corrected.

[0039] Although the DMD 204 has been described as an example of a spatial light modulator and is therefore a reflective type that reflects laser light, the spatial light modulator may be a transmissive type that transmits laser light or a diffractive type that diffracts laser light. The spatial light modulator can modulate laser light spatially and temporally.

[0040] 4, the autofocus system AF is arranged to sandwich the illumination and projection module 200. This allows measurements to be performed by the autofocus system AF before the exposure operation that forms the wiring pattern that connects the chips arranged on the wafer WF, regardless of the scanning direction of the wafer WF.

[0041] Before exposure begins, alignment system ALG_C measures the position of wafer WF placed on substrate holder PH of substrate stage 30, using fiducial mark 60a (see FIG. 8) of alignment device 60 as a reference. Typically, the position of each wafer WF is measured by determining the number and arrangement of measurement points so that six parameters of wafer WF placed on substrate holder PH can be calculated: X-direction shift (X), Y-direction shift (Y), rotation (Rot), X-direction magnification (X_Mag), Y-direction magnification (Y_Mag), and orthogonality (Oth). Based on the measurement results of alignment system ALG_C, the positional deviation of wafer WF relative to substrate stage 30 is detected, and the exposure start position, etc. are changed.

[0042] 8 is an enlarged view of the vicinity of the illumination and projection module 200. As shown in FIG.

[0043] 8, the substrate stage 30 is provided with an alignment device 60. The alignment device 60 includes a reference mark 60a and a two-dimensional image sensor 60e. The alignment device 60 is used to measure and calibrate the positions of various modules, and is also used to calibrate the alignment systems ALG_R, ALG_L, and ALG_C arranged on the optical surface plate 110.

[0044] The position of each module is measured and calibrated by projecting a calibration DMD pattern onto the reference mark 60a of the alignment device 60 using the illumination and projection module 200, and measuring the relative position of the reference mark 60a and the DMD pattern.

[0045] Furthermore, alignment systems ALG_R, ALG_L, and ALG_C can be calibrated by measuring reference mark 60a of alignment device 60 with alignment systems ALG_R, ALG_L, and ALG_C. That is, by measuring reference mark 60a of alignment device 60 with alignment systems ALG_R, ALG_L, and ALG_C, the positions of alignment systems ALG_R, ALG_L, and ALG_C can be determined. Furthermore, using reference mark 60a, it is possible to determine the relative position with respect to the position of the module.

[0046] Before exposure begins, alignment system ALG_C measures the position of wafer WF placed on substrate holder PH of substrate stage 30 using fiducial mark 60a (see FIG. 8) of alignment device 60 as a reference. However, if the positional relationship between substrate stage 30 and wafer WF remains unchanged, measurement by alignment system ALG_C may be omitted. Furthermore, if slight deviations occur in the X, Y, θ, and magnification of each wafer WF placed on substrate holder PH, alignment system ALG_C measures the current state of wafer WF, and the difference between this and the state of wafer WF measured by alignment systems ALG_R and ALG_L (the state of wafer WF used to create the wiring pattern data) can be corrected by changing the state of the X, Y, and θ stage on which DMD 204 is mounted and the lens magnification. This eliminates the need to rewrite the wiring pattern data, allowing for a smooth transition to exposure.

[0047] The substrate stage 30 is also provided with a moving mirror MR, a DM monitor 70, and the like, which are used to measure the position of the substrate stage 30.

[0048] (predetermined measurement points) Next, the predetermined measurement points on the chip that are measured by alignment systems ALG_R and ALG_L will be described. Figures 9(A) to 9(C) are diagrams that explain the predetermined measurement points on the chip. Figure 9(A) shows a case where each chip in the design position is connected to each other by a wiring pattern WL.

[0049] 9A, a case will be described in which the chip C11 is connected to each of the chips C21 to C23. More specifically, the pad P11a of the chip C11 is connected to the pad P21 of the chip C21, the pad P11b of the chip C11 is connected to the pad P22 of the chip C22, and the pad P11c of the chip C11 is connected to the pad P23 of the chip C23. In this case, the data creation device 300 creates wiring pattern data for a partial wiring section WP1 connecting the pad P11a of the chip C11 to the pad P21 of the chip C21, a partial wiring section WP2 connecting the pad P11b of the chip C11 to the pad P22 of the chip C22, and a partial wiring section WP3 connecting the pad P11c of the chip C11 to the pad P23 of the chip C23.

[0050] 9(B) is a diagram showing an example of chips C11 and C21-C23 fixed to wafer WF while being shifted from their design positions. As shown in FIG. 9(B), consider a case where chips C21-C23 are fixed to wafer WF while being shifted from their design positions indicated by dotted lines. In this case, alignment systems ALG_R and ALG_L measure the positions of two pads located at both ends in the pad arrangement direction for each of two chips included in partial wiring portions WP1, WP2, and WP3.

[0051] The partial wiring section WP1 will be described as an example. Fig. 9C is a diagram showing a pad P11a of the chip C11 and a pad P21 of the chip C21 included in the partial wiring section WP1.

[0052] In the partial wiring unit WP1, alignment systems ALG_R and ALG_L measure the positions of two pads P11a located at both ends in the arrangement direction of the pads P11a (Y direction in FIG. 9C) among the pads P11a of the chip C11 (shown by black circles in FIG. 9C). That is, the predetermined measurement points on the chip C11 are the two pads P11a located at both ends in the arrangement direction of the pads P11a. Furthermore, alignment systems ALG_R and ALG_L measure the positions of two pads P21 located at both ends in the arrangement direction of the pads P21 among the pads P21 of the chip C21 (shown by black circles in FIG. 9C). That is, the predetermined measurement points on the chip C21 are the two pads P21 located at both ends in the arrangement direction of the pads P21. The positions of the pads P11a located at both ends and the pads P21 located at both ends may be calculated from the amount of movement due to the movement of the substrate stage 30, or may be measured by imaging the pads P11a located at both ends and the pads P21 located at both ends at once by using a large field of view for the alignment systems ALG_R and ALG_L.

[0053] (How to calculate the pad position) The data generating device 300 calculates the positions of all pads, including the pad P11a of the chip C11 and the pad P21 of the chip C21, from the positions of the four pads measured as described above.

[0054] Fig. 10(A) is a diagram showing a chip C11 and chips C21 to C23 fixed to a wafer WF in a state displaced from their designed positions, and Fig. 10(B) is an enlarged view of a partial wiring portion WP1. In the example of Fig. 10(A), chip C11 is in its designed position, but chips C21 to C23 are fixed in positions displaced from their designed positions. Therefore, as shown in Fig. 10(B), pad P21 is in a position displaced from its designed position, as indicated by the dotted line.

[0055] 10(B), the straight lines connecting pad P11a at the measurement point in the design position and pad P21 form a rectangle. Data creation device 300 calculates the positions of all pads P11a and pad P21 present in partial wiring portion WP1 from the relationship between the coordinates of the four corners of the rectangle formed by connecting pad P11a at the measurement point in the design position and pad P21 with the straight lines and the coordinates of pads P11a and P21 at the measurement points in partial wiring portion WP1 measured by alignment system ALG_R or ALG_L.

[0056] The data creating device 300 creates wiring pattern data for the partial wiring section WP1 based on the calculated positions of the pads P11a and P21. Similar processing is then performed for the other partial wiring sections WP2 and WP3. As a result, as shown in FIG. 10(C), the chip C11 and the chips C21 to C23 are connected by the wiring patterns WL, respectively.

[0057] (How to create wiring pattern data) Next, a description will be given of a method for creating wiring pattern data executed by the data creation device 300. Fig. 11(A) shows design value data for a wiring pattern WL that connects the pads of chips C11 and C21 arranged at their design positions. Note that in Fig. 11(B) and Fig. 11(C), the design positions of chips C11 and C21 are indicated by dotted lines.

[0058] 11B shows an example of chips C11 and C21 fixed on the wafer WF while being shifted from their designed positions. In the case of FIG. 11B, chip C21 is shifted in the +X direction and the −Y direction from its designed position, and chip C21 is rotated around the Z axis from its designed position.

[0059] Here, if data for a wiring pattern connecting chips C11 and C21 that are shifted from their design positions were to be created from scratch, it would take an enormous amount of time. Therefore, in this embodiment, as shown in Figure 11(A), the design value data is divided into a correction area and a non-correction area, and data for the wiring pattern in the correction area is created as wiring pattern data.

[0060] For example, in the case of Figure 11(B), the data creation device 300 creates, as wiring pattern data, data for a wiring pattern (shown by cross-hatching) that connects pad P11a of chip C11 to wiring in the unmodified area, and data for a wiring pattern (shown by cross-hatching) that connects pad P21 of chip C21 to wiring in the unmodified area.

[0061] 11(C) shows a case where the chip C11 is shifted in the +X direction and the -Y direction from the design position and rotated around the Z axis, and the chip C21 is shifted in the +X direction from the design position and rotated around the Z axis. In this case, the data creation device 300 creates, as wiring pattern data, data of a wiring pattern (shown by cross-hatching) that connects the pads P11a and P21 of the chips C11 and C21 to the wiring in the unmodified area, as shown in FIG.

[0062] By doing so, the time required to create the wiring pattern data can be shortened and the volume of the wiring pattern data can be reduced, thereby shortening the time required to transfer the wiring pattern data to the first storage device 310R or the second storage device 310L that stores the wiring pattern data.

[0063] The wiring pattern data of the correction area may be created using predefined wiring pattern data according to the deviation patterns from the design positions of the chips C11 and C21, as shown in Figures 11(D) to 11(F).

[0064] For example, if chip C21 is shifted in the +X direction, a wiring pattern obtained by shifting the design wiring pattern indicated by the dotted line in the +X direction in the correction area on the chip C21 side is used, as shown in Figure 11(D). Also, if chip C21 is shifted in the -Y direction, a wiring pattern obtained by rotating the design wiring pattern indicated by the dotted line around the Z axis in the correction area on the chip C2 side is used, as shown in Figure 11(E). Also, if chip C21 is shifted in the +X direction and -Y direction and rotated around the Z axis, a wiring pattern obtained by shifting the design wiring pattern indicated by the dotted line in the correction area on the chip C2 side in the +X direction and rotating it around the Z axis, and expanding or contracting the length of each wire according to the rotation angle of chip C21, as shown in Figure 11(F). This further reduces the calculation time.

[0065] The exposure control device 400 controls the DMD 204 to expose the wiring pattern using data obtained by replacing the data in the correction area of ​​the design value data with the wiring pattern data created by the data creation device 300. This makes it possible to form a wiring pattern that connects chips together even if the actual chip positions on the wafer WF or substrate P are deviated from the design positions.

[0066] The method for creating wiring pattern data is not limited to the above-described method. Wiring pattern data may be created without dividing the design value data into correction and non-correction regions. For example, assume that design value data for the wiring pattern WL is set as shown in FIG. 12(A). If chips C11 and C21 are displaced from their design positions, wiring pattern data may be created such that the wires extending from the pads of chips C11 and C21 toward the center along the X direction are connected on an arbitrary Y axis, as shown in FIG. 12(B). Furthermore, if the wires overlap when connected using the method of FIG. 12(B), the connection positions may be changed as shown in FIG. 12(C). In this way, when the design value data for wiring parallel to the X axis, as shown in FIG. 12(A), the X-direction length of the wires extending from each pad toward the center along the X direction is changed based on the X coordinate of each pad whose position is measured. Next, the distance in the Y direction between the pads to be connected by wiring is calculated based on the Y coordinate of each pad, and the ends of the central portions of the wiring extending from each pad in the X direction are connected with wiring parallel to the Y axis and of a length equal to this distance. In this way, wiring pattern data can be easily created. Note that it is desirable that the method of creating and wiring wiring pattern data from scratch based on the measured pad positions as shown in Figure 10, the method of creating and wiring wiring pattern data from design value data by dividing the correction area and the non-correction area as shown in Figure 11, and the method of creating and wiring wiring pattern data in which the positional deviation of each pad in the X direction and the positional deviation in the Y direction are corrected by the wiring length in each direction as shown in Figure 12 be selectable by the exposure recipe (setting information).

[0067] Next, an example of the procedure for forming the wiring pattern of the FO-WLP in the exposure apparatus EX according to this embodiment will be described. Fig. 13 is a conceptual diagram of the procedure for forming the wiring pattern of the FO-WLP in the exposure apparatus EX.

[0068] 13, in this embodiment, for example, while the wafer WF on the substrate stage 30R is being exposed, the wafer WF is loaded onto the substrate stage 30L, and the alignment system ALG_L measures the positions of predetermined measurement points on the chip. Based on the position measurement results of the predetermined measurement points on the chip by the alignment system ALG_L, the data creation device 300 calculates the positions of pads on the chip and sequentially creates wiring pattern data based on the calculation results. The data creation device 300 then stores (transfers) the created wiring pattern data to the second storage device 310L. The wiring pattern data stored in the second storage device 310L is sequentially transferred to the exposure control device 400 in synchronization with the start of exposure of the wafer WF on the substrate stage 30L.

[0069] In addition, when wafers WF are arranged in a row of four on one tray TR as shown in FIG. 2, after all four wafers WF have been placed on one tray TR, the tray TR may be placed on the substrate stage 30L, and the alignment system ALG_L may begin measuring the positions of predetermined measurement points on the chips. In this case, the alignment system ALG_L may measure the positions of the predetermined measurement points and another wafer WF may be placed on the next tray TR in parallel. Then, in parallel with the process of placing the tray TR containing another wafer WF on the substrate stage 30L, the pad positions of the wafer WF whose positions have already been measured for the predetermined measurement points may be calculated based on the measurement results from the alignment system ALG_L, and wiring pattern data may be created and stored in the second storage device 310L. Such parallel processing is particularly effective when it takes a long time to create, transfer, and store wiring pattern data. In addition, if the time required to measure the position of the measurement point and to create and store the wiring pattern data is shorter than the exposure time, for example, four wafers WF in three rows may be placed on one tray TR, and then the wafers may be loaded onto the substrate stage 30L and measured using the alignment system ALG_L.

[0070] Meanwhile, when exposure of the wafer WF on the substrate stage 30L begins, the exposed wafer WF is removed from the substrate stage 30R, and a new wafer WF is then loaded onto the substrate stage 30R. Then, the alignment system ALG_R measures the positions of predetermined measurement points on the chip. The data creation device 300 calculates the positions of pads on the chip based on the measurement results of the positions of the predetermined measurement points on the chip, and sequentially creates wiring pattern data based on the calculation results. The data creation device 300 then transfers the created wiring pattern data to the first storage device 310R. The wiring pattern data stored in the first storage device 310R is sequentially transferred to the exposure control device 400 in synchronization with the start of exposure of the wafer WF on the substrate stage 30R.

[0071] In this manner, in this embodiment, while exposure processing is being performed using one of the two substrate stages 30R and 30L, the other substrate stage carries out the exposed wafer, carries in a new wafer, measures the positions of predetermined measurement points, calculates pad positions, and creates and transfers wiring pattern data.

[0072] As described above in detail, the exposure apparatus EX according to the first embodiment includes a DMD 204 that generates a wiring pattern connecting a plurality of pads P11a on a chip C11 arranged on the wafer WF and a plurality of pads P21 on a chip C22 arranged on the wafer WF. The exposure apparatus EX also includes a data creation device 300 that acquires position measurement results of predetermined measurement points on the chip C11 and a plurality of predetermined measurement points on the chip C21, calculates all positions of the plurality of pads P11a and P21 based on the acquired position measurement results and design information for the plurality of pads P11a and P21, determines a wiring pattern connecting the plurality of pads P11 and P21 based on the calculation results, and creates wiring pattern data used to control the DMD 204 when forming the determined wiring pattern. The exposure apparatus EX also includes an exposure control device 400 that controls the DMD 204 using the wiring pattern data to expose a wiring pattern connecting the plurality of pads P11 and P21. The data creation device 300 calculates the positions of all pads P11 and P21 based on the position measurement results of predetermined measurement points, thereby reducing the time required to identify the positions of all pads P11 and P21 compared to measuring the positions of all pads P11 and P21. This reduces the time required to form the wiring pattern. The time required to form the wiring pattern includes at least one of the following: the time required to load the wafer WF, the time required to measure the positions of the predetermined measurement points, the time required to calculate the pad positions, the time required to create and transfer the wiring pattern data, the time required for the exposure process, and the time required to load the exposed wafer WF.

[0073] In the first embodiment, the predetermined measurement points on the chip C11 are some of the pads P11a, and the predetermined measurement points on the chip C21 are some of the pads P21. Since the pads P11a and P21 provided on the chip C11 and the chip C21, respectively, are used as measurement points, there is no need to provide separate measurement points on the chips.

[0074] In the first embodiment, the pads P11a as measurement points are located at both ends in the arrangement direction of the pads P11a, and the pads P21 as measurement points are located at both ends in the arrangement direction of the pads P21. This improves the accuracy of calculating the pad positions compared to, for example, measuring the positions of adjacent pads P11a and adjacent pads P21 to calculate the pad positions.

[0075] In the first embodiment, the wiring pattern determined by the data creating device 300 is a wiring pattern obtained by changing a part of the wiring pattern connecting the pad P11a and the pad P21 at the design position. This reduces the time required to create the wiring pattern data and the volume of the wiring pattern data, thereby shortening the time required to transfer the wiring pattern data to the first storage device 310R or the second storage device 310L that stores the wiring pattern data.

[0076] In the first embodiment, while an exposure process is being performed using one of the two substrate stages 30R and 30L, the other substrate stage carries out the unloading of an exposed wafer, the loading of a new wafer, the measurement of the positions of predetermined measurement points on the chip, the calculation of pad positions, and the creation and transfer of wiring pattern data, but this is not limited to this. It is sufficient that while an exposure process is being performed using one of the two substrate stages 30R and 30L, at least one of the unloading of an exposed wafer, the loading of a new wafer, the measurement of the positions of predetermined measurement points on the chip, the calculation of pad positions, and the creation and transfer of wiring pattern data is performed on the other substrate stage.

[0077] In the first embodiment, the pads located at both ends in the pad arrangement direction among the multiple pads provided on each of the chips to be connected to each other are set as the predetermined measurement points, but this is not limited to this. At least two pads among the multiple pads may be set as the predetermined measurement points. Alternatively, all pads may be set as the predetermined measurement points. Even if the pads are not on a straight line, the actual positions may be calculated from the relationship between the design coordinates of each pad.

[0078] (Variation) The data creating device 300 may create drive data that defines the drive amount of the DMD 204 and the drive amount of the lens actuator, instead of the wiring pattern data. That is, the DMD 204 may generate a wiring pattern using design value data, and by changing the drive amount of the DMD 204 and the drive amount of the lens actuator, the position of the projection image of the wiring pattern projected onto the wafer WF may be changed, thereby changing the shape of the wiring pattern formed on the wafer WF.

[0079] FIG. 14A shows a wiring pattern WL that connects the pads of the chip C11 and the chip C21 that are placed at the design position.

[0080] 14(B) shows a case where the chips C11 and C21 are shifted in the +X direction from their designed positions. In this case, by shifting the position of the DMD 204 in the +X direction and then scanning and exposing the wafer in the X direction, it is possible to form the wiring pattern WL connecting the chips C11 and C21, as shown in FIG.

[0081] 14(C) shows a case where the chip C21 is shifted in the +Y direction from the design position indicated by the dotted line. In this case, by scanning and exposing the wafer in the X direction while shifting the position of the DMD 204 in the +Y direction, it is possible to form a diagonal wiring pattern WL connecting the chips C11 and C21, as shown in FIG.

[0082] 14(D) shows a case where the chip C11 is rotated from the design position and the chip C21 is shifted and rotated in the −X direction from the design position. In this case, the wiring pattern WL connecting the chip C11 and the chip C21 can be formed without changing the drive amount, so there is no need to change the drive data.

[0083] 14(E) shows a case where the position of chip C11 remains at the designed position, but chip C21 is shifted in the +X direction from the designed position. In this case, by scanning and exposing the wafer in the X direction while shifting the DMD 204 in the +X direction, it is possible to form a wiring pattern WL that is longer than the designed value, as shown in FIG.

[0084] 14(F) shows a case where the chips C11 and C21 are rotated from their designed positions. In this case, the DMD 204 is rotated around the Z axis, and then the DMD 204 is shifted in the -Y direction while scanning and exposing the wafer in the X direction, thereby forming a wiring pattern WL having the shape shown in FIG. 14(F).

[0085] 14(G) shows a case where the chip C11 is shifted and rotated in the +X direction from the design position, and the chip C21 is shifted and rotated in the -X direction from the design position. In this case, by scanning and exposing the wafer in the X direction while moving the DMD 204 in an arc, an arc-shaped wiring pattern WL as shown in FIG.

[0086] Second Embodiment The shape of the wiring pattern may be changed by optically correcting the image of the wiring pattern. Fig. 15(A) is a diagram showing the configuration of an illumination and projection module 200A according to the second embodiment.

[0087] 15(A), in an illumination / projection module 200A according to the second embodiment, a pair of wedge-shaped prisms 207a and 207b are disposed between a DMD 204 and a lens group 206. By controlling the position and attitude of the pair of prisms 207a and 207b, it is possible to optically deform the image of the wiring pattern generated by the DMD 204 based on design value data.

[0088] For example, as shown in FIG. 15(B), the position of the image can be shifted in the X direction by changing the distance in the Z direction between prism 207a and prism 207b. Furthermore, as shown in FIG. 15(C), the length of the image in the X direction can be changed by rotating prism 207a around the Y axis. Furthermore, by rotating prism 207a around the X axis and changing the distance in the Z direction between prism 207a and prism 207b in the Y direction (for example, the larger the Y coordinate, the larger the distance in the Z direction between prism 207a and prism 207b), the amount of shift of the image in the X direction can be increased as the Y coordinate increases, as shown in FIG. 15(D). In the following description, positioning prism 207a and prism 207b as shown in FIG. 15(D) is referred to as orthogonality correction.

[0089] In this case, the data generating device 300 generates control data (hereinafter referred to as correction optical system control data) for controlling the position and attitude of the pair of prisms 207a and 207b during exposure of the wiring pattern.

[0090] The deformation of the wiring pattern image using a pair of prisms 207a and 207b will be further described below. Fig. 16(A) shows a wiring pattern WL that connects the pads of chips C11 and C21 that are placed at the designed positions.

[0091] 16(B) shows a case where the chips C11 and C21 are shifted in the +X direction from the design positions indicated by the dotted lines. In this case, as shown in FIG. 15(B), by shifting the image in the +X direction, it is possible to form a wiring pattern WL that connects the chips C11 and C21.

[0092] 16(C) shows a case where the chip C21 is shifted in the +Y direction from the design position indicated by the dotted line. In this case, the orthogonality correction by the prisms 207a and 207b described in FIG. 15(D) allows the formation of a diagonal wiring pattern WL connecting the chips C11 and C21.

[0093] 16(D) shows a case where the chip C11 is rotated around the Z axis from the design position, and the chip C21 is shifted in the −X direction from the design position and also rotated around the Z axis. In this case, by correcting the X magnification while scanning the wafer in the Y direction, it is possible to form a wiring pattern WL that connects the chip C11 and the chip C21.

[0094] 16(E) shows a case where chip C21 is shifted in the +X direction from the designed position while chip C11 remains in the designed position. In this case, by correcting the X magnification using prisms 207a and 207b and shifting DMD 204 in the +X direction while scanning and exposing the wafer in the X direction, it is possible to form a wiring pattern WL that is longer than the designed value, as shown in FIG.

[0095] 16(F) shows a case where the chips C11 and C21 are rotated from their designed positions. In this case, the DMD 204 is rotated around the Z axis, and then orthogonality correction and rotation correction are performed using the prisms 207a and 207b, thereby forming the wiring pattern WL shown in FIG.

[0096] The other configurations are the same as those of the first embodiment, so detailed explanations will be omitted, but in the second embodiment as well, while the wafer WF on the substrate stage 30R is being exposed, the chip position on the substrate placed on the substrate stage 30L is measured, and correction optical system control data is created and transferred based on the measurement results.

[0097] According to the second embodiment, the exposure apparatus EX includes a pair of prisms 207a and 207b that optically corrects the wiring pattern generated by the DMD 204. The data generation device 300 acquires position measurement results of predetermined measurement points on the chip C11 and the chip C21, calculates all positions of the pads P11a and P21 based on the acquired position measurement results and design information for the pads P11a and P21, and generates correction optical system control data based on the calculation results. The correction optical system control data is used to control the prisms 207a and 207b to form a wiring pattern connecting the pads P11a and P21, respectively. The exposure control device 400 controls the DMD 204 based on design value data for generating a wiring pattern connecting the pads P11a and P21 at their design positions, and controls the prisms 207a and 207b using the correction optical system control data to expose the wiring pattern connecting the pads P11a and P21. When the exposure apparatus EX has the configuration of the second embodiment, it is possible to reduce the overall time required to form a wiring pattern, just as in the first embodiment.

[0098] Third Embodiment Since the process of attaching chips to the wafer WF is performed before the formation of the wiring pattern in the exposure apparatus EX, the data creation device 300 may create wiring pattern data, drive data, or correction optical system control data using measurement data of the pad positions measured in an inspection process that inspects the position of each chip relative to the wafer WF.

[0099] 17 is a top view showing an overview of a wiring pattern forming system 500A according to the third embodiment. The wiring pattern forming system 500A according to the third embodiment includes a chip measurement station CMS that measures the position of a chip on a wafer WF.

[0100] The chip measurement station CMS includes multiple measurement microscopes 61, which measure the positions of predetermined measurement points on chips in different sets. The positions of predetermined measurement points on chips in different sets measured by the multiple measurement microscopes 61 may be the positions of predetermined measurement points on chips in different sets on the same wafer WF, or the positions of predetermined measurement points on chips in each set on different wafers WF. In this embodiment, the multiple measurement microscopes 61 measure the positions of predetermined measurement points on chips in each set on different wafers WF. The number of measurement microscopes 61 and the number of wafers measured at one time in the chip measurement station CMS depend on the processing capacity of the chip measurement station CMS. For this reason, for example, if one processing device is provided to process the measurement results of multiple measurement microscopes 61 and the processing capacity of the processing device is insufficient, one processing device that processes the measurement results of the measurement microscope 61 may be provided for each measurement microscope 61, and multiple pairs of measurement microscopes 61 and processing devices may be provided.

[0101] The position measurement results of the predetermined measurement points are transmitted to the data generating device 300. The data generating device 300 calculates the positions of all pads based on the position measurement results of the predetermined measurement points received from the chip measurement station CMS, and generates wiring pattern data (which may be drive data or correction optical system control data) based on the calculation results. The generated wiring pattern data may be data of the wiring pattern in the correction area as described in the first embodiment, or data of the wiring pattern including the correction area and the non-correction area. The wiring pattern data generated by the data generating device 300 is stored in a storage device different from the storage device that stores the wiring pattern data used for exposure control of the currently exposed substrate. That is, if the wiring pattern data used for exposure control of the currently exposed wafer WF is stored in the first storage device 310R, the data generating device 300 stores (transfers) the generated wiring pattern data to the second storage device 310L. If it takes a long time to generate the wiring pattern data, the wiring pattern data can be generated and transferred while the coater developer device CD is applying resist. Therefore, having two storage devices as in this embodiment is effective. If necessary, the number of storage devices may be expanded to three or more.

[0102] In the exposure apparatus EX-A according to the third embodiment, the main body 1A is equipped with one substrate stage 30. In the third embodiment, the chip position is measured by the chip measurement station CMS, so alignment systems ALG_L and ALG_R can be omitted.

[0103] After measurement of the positions of predetermined measurement points on the chip is completed, the wafer WF is coated with a photosensitive resist by a coater developer device CD and then carried into the buffer unit PB. The wafers WF placed in the buffer unit PB are arranged on a single tray TR (four wafers x three rows in the third embodiment) by a robot RB installed in the substrate exchange unit 2A, carried into the main body unit 1A, and placed on the substrate holder of the substrate stage 30.

[0104] Alignment system ALG_C measures the position of each wafer WF relative to the substrate holder and corrects the exposure start position, etc. If the wafer WF rotates around the Z axis when placed on the substrate holder, causing the chip position to deviate from the position of the wiring pattern data created by data creation device 300, there is a risk that the chips will not be connected correctly when wiring is formed using that wiring pattern data.

[0105] In this case, the data generating device 300 generates drive data or correction optical system control data, as described in the first embodiment and its modifications, to correct the shape of the wiring pattern so that the chips are connected. For example, the data generating device 300 detects the positional deviation of each chip from the position of the wiring pattern data from the position of each wafer WF measured by the alignment system ALG_C based on the chip position relative to the position of each wafer WF measured by the chip measurement station CMS. The data generating device 300 generates drive data or correction optical system control data based on the deviation. This eliminates the need to rewrite the wiring pattern data, even if the wafer WF rotates around the Z axis when placed on the substrate holder, allowing for a smooth transition to exposure and the formation of wiring connecting the chips.

[0106] Incidentally, alignment system ALG_C may use an alignment mark on the chip to measure the position of wafer WF.

[0107] Fourth Embodiment The wafer WF may be attached to a base substrate B, and the position of each chip relative to the base substrate B may be measured in a chip measurement station CMS.

[0108] 18 is a top view showing an overview of a wiring pattern formation system 500B according to the fourth embodiment. The wiring pattern formation system 500B according to the fourth embodiment includes a wafer alignment apparatus WA that attaches multiple wafers WF, each having a chip arranged thereon, to a base substrate B, a chip measurement station CMS, and an exposure apparatus EX-B. The wafer alignment apparatus WA prevents the position of the wafer WF relative to the base substrate B from being changed.

[0109] The base substrate B, to which a plurality of wafers WF have been attached by the wafer placement device WA, is carried into the chip measurement station CMS.

[0110] The chip measurement station CMS is equipped with a plurality of measurement microscopes 61, and measures the position of a predetermined measurement point on each chip relative to the base substrate B. The plurality of measurement microscopes 61 measure the position of a predetermined measurement point on chips in different sets. The position measurement results of the predetermined measurement points are sent to the data creation device 300.

[0111] The data creation device 300 calculates the positions of all pads on the chip based on the position measurement results of predetermined measurement points received from the chip measurement station CMS, and creates wiring pattern data (which may be drive data or correction optical system control data) based on the calculation results. The created wiring pattern data may be data of the wiring pattern in the correction area as described in the first embodiment, or data of the wiring pattern including the correction area and the non-correction area. The wiring pattern data created by the data creation device 300 is stored in a storage device different from the storage device that stores the wiring pattern data used to control the exposure of the wafer WF on the base substrate B currently being exposed. In other words, if the wiring pattern data used to control the exposure of the wafer WF on the base substrate B currently being exposed is stored in the first storage device 310R, the data creation device 300 stores (transfers) the created wiring pattern data to the second storage device 310L.

[0112] After the measurement of the positions of the predetermined measurement points is completed, the wafer WF is carried into the coater-developer device CD together with the base substrate B, and after being coated with a photosensitive resist, is carried into the port PT of the substrate exchange unit 2B. Thereafter, the wafer WF together with the base substrate B is placed on the substrate holder of the substrate stage 30.

[0113] Subsequent processing is the same as in the third embodiment, and detailed description thereof will be omitted. In the fourth embodiment, exposure can be performed by managing everything using the position of the base substrate B on which the wafer WF is placed and fixed. For example, during alignment, alignment measurement and correction for the base substrate B can be performed. In other words, because the wafer WF is placed and fixed on the base substrate B, alignment for each wafer WF / each chip is not required when the base substrate B is placed on the substrate holder of the substrate stage 30, and alignment of only the base substrate B can be performed. Note that although the wafer placement device WA attaches the wafer WF to the base substrate B, the wafer WF may also be placed and fixed directly on the tray TR.

[0114] (Variation) In the fourth embodiment, the wafer placement device WA and the chip measurement station CMS are separate devices, but this configuration is not limited to this. The measuring microscope 61 may start measuring the position of a predetermined measurement point on a chip from the wafer WF attached to the base substrate B by the wafer placement device WA. In other words, the measuring microscope 61 performs the measurement operation in parallel with the attachment operation of multiple wafers WF to the base substrate B. The measuring microscope 61 may start the measurement operation after one wafer WF is attached to the base substrate B, or may start the measurement operation after multiple wafers WF are attached to the base substrate B. The measuring microscope 61 may temporarily suspend the measurement operation when the wafer WF is placed on the base substrate B. This is to prevent vibrations generated when the wafer WF is placed on the base substrate B from affecting the measurement results of the measuring microscope 61.

[0115] (Another example of a specified measurement point) In the above first to fourth embodiments, the case has been described in which the specified measurement points are two of the pads P11a of C11 and two of the pads P21 of C21 included in the partial wiring portion WP1, but this is not limited to this.

[0116] 19(A) and 19(B) are diagrams illustrating another example 1 of predetermined measurement points on a chip. Fig. 19(A) shows a case where chips at their designed positions are wired together, and Fig. 19(B) shows a chip C11 and chips C21 to C23 fixed on a wafer WF in a state shifted from their designed positions.

[0117] As shown in FIG. 19(A), the chip C11 is connected to three chips C21 to C23, and each of the chips C21 to C23 is connected to one chip C11.

[0118] In Modification Example 1, for a chip C11 connected to multiple chips C21 to C23, the position and orientation of the chip C11 relative to the design position are determined by measuring the positions of some of the pads P11a to P11c on the chip C11, and the positions of all of the pads P11a to P11c are calculated from the positions and orientations. Specifically, for the chip C11, at least two pads, preferably three pads, of the pads P11a to P11c included in the chip C11 are set as predetermined measurement points. For example, as shown in FIG. 19(B), pads selected from pads P11a, P11b, and P11c (indicated by black circles) are set as predetermined measurement points. This allows the position and orientation of the chip C11 relative to the design position to be determined, and the positions of all of the pads P11a to P11c can be calculated based on the design value data of the chip C11. It should be noted that which pads among the pads P11a to P11c are used as measurement points may be determined so that four parameters of the X-direction shift, Y-direction shift, rotation, and magnification of the chip C11 can be calculated.

[0119] On the other hand, for each of the chips C21 to C23 connected to one chip C11, the positions of the pads P21 to P23 at both ends in the arrangement direction of the pads are measured as predetermined measurement points in each of the partial wiring sections WP1 to WP3, and the positions of all the pads P21 to P23 are calculated based on the measurement results.

[0120] In the first modification, the number of measurement points can be reduced compared to the case where four pads in each partial wiring portion are measured as explained in the first embodiment, and therefore the time required for measurement can be shortened.

[0121] 20(A) and 20(B) are diagrams illustrating another example 2 of predetermined measurement points on a chip. Fig. 20(A) shows a case where chips at their designed positions are wired together, and Fig. 20(B) shows chip C11 and chips C21 to C23 fixed on wafer WF in a state shifted from their designed positions.

[0122] In Figures 20(A) and 20(B), predetermined marks M11, M21, M22, and M23 formed on the chip are set as predetermined measurement points. In this case, the coordinates of the pads can be calculated based on the measurement results of the mark positions from the design value data of the positional relationship between each mark and each pad. When measuring the position of the pads as predetermined measurement points, a measurement microscope with a resolution equivalent to that of the exposure tool is required. In Alternative Example 2, even if the resolution of the measurement microscope is not equivalent to that of the exposure tool (even if the resolution of the measurement microscope is lower than that of the exposure tool), the coordinates of the pads can be calculated, thereby reducing the component costs of the exposure tool or the chip measurement station CMS.

[0123] In the above first to fourth embodiments and their modifications, a case has been described in which a plurality of wafer-shaped substrates are placed on the substrate stage 30, but a plurality of rectangular substrates may also be placed on the substrate stage 30.

[0124] Moreover, the first to fourth embodiments and their modifications can also be applied to the formation of wiring patterns that connect chips on the substrate P shown in FIG. 3(B).

[0125] The above-described embodiment is a preferred example of the present invention, but the present invention is not limited to this and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0126] EX, EX-A, EX-B exposure equipment 204 DMD 204a Micromirror 207a, 207b Prism 300 Data Creation Device 400 Exposure control device C1, C2, C11, C21 to C23 semiconductor chips WF wafer P board P11a~P11c, P21~P23 Pads M11, M21~M23 marks WL wiring pattern

Claims

1. acquiring misalignment information of the first semiconductor chip; selecting a pattern from a plurality of patterns based on the misalignment information; Including, the pattern is a pattern of a first wiring region formed on the first semiconductor chip, and a first end of the first wiring region overlaps with a pad of the first semiconductor chip; How to determine the pattern.

2. the connection wiring includes the first wiring region and a second wiring region including a second end portion overlapping a pad of the second semiconductor chip, so that the connection wiring connects the first semiconductor chip and the second semiconductor chip; The pattern determination method according to claim 1 .

3. the connection wiring includes a third region located between the first wiring region and the second wiring region; the patterns include a pattern of the first wiring region selected based on the misalignment information, which is different from a pattern of the first wiring region of the connection wiring in design, and a pattern of the third region of the connection wiring in design; The pattern determination method according to claim 2 .

4. The positional deviation information is a displacement amount in a first direction along a surface of a substrate on which the first semiconductor chip is mounted; a deviation amount in a second direction along the surface and intersecting the first direction; a rotational deviation about an axis intersecting the surface; and Including, the plurality of patterns include patterns in which the positions in the first direction, the positions in the second direction, and the positions in the rotation direction are different from one another; The pattern determination method according to claim 1 .

5. the positional deviation information includes a positional deviation from a design position of the pad; The pattern determination method according to claim 1 .

6. preparing a plurality of patterns that differ from one another in a position in a first direction along a surface, a position in a second direction along the surface that intersects with the first direction, and a position in a rotational direction about an axis that intersects with the surface; selecting a pattern from the plurality of patterns; A pattern determination method comprising:

7. the pattern is a pattern of a first wiring region formed on a first semiconductor chip, and a first end of the first wiring region overlaps with a pad of the first semiconductor chip; The pattern determination method according to claim 6 .

8. the pattern is selected based on misalignment information of the first semiconductor chip; The pattern determination method according to claim 7 .

9. the connection wiring includes the first wiring region and a second wiring region including a second end portion overlapping a pad of the second semiconductor chip, so that the connection wiring connects the first semiconductor chip and the second semiconductor chip; The pattern determination method according to claim 8 .

10. the connection wiring includes a third region located between the first wiring region and the second wiring region; the patterns include a pattern of the first wiring region selected based on the misalignment information, which is different from a pattern of the first wiring region of the connection wiring in design, and a pattern of the third region of the connection wiring in design; The pattern determination method according to claim 9 .

11. The positional deviation information is a displacement amount in a first direction along a surface of a substrate on which the first semiconductor chip is mounted; a deviation amount in a second direction along the surface and intersecting the first direction; a rotational deviation about an axis intersecting the surface; and Including, the plurality of patterns include patterns in which the positions in the first direction, the positions in the second direction, and the positions in the rotation direction are different from one another; The pattern determination method according to claim 8 .

12. the positional deviation information is acquired by measuring the positions of non-adjacent pads among a plurality of pads arranged in a first direction on the first semiconductor chip; The pattern determination method according to any one of claims 1 to 5 and claims 7 to 11.

13. and controlling a plurality of light modulation elements included in a spatial light modulator, each of which can be controlled to a plurality of states, based on the pattern determined by the pattern determination method according to claim 12, thereby irradiating the light from the spatial light modulator onto a substrate on which the first semiconductor chip is mounted. A method for fabricating semiconductor devices.

14. a spatial light modulator including a plurality of light modulation elements each controllable to a plurality of states, the plurality of light modulation elements being controlled based on the pattern determined by the pattern determination method according to claim 12; a stage capable of holding a substrate on which the first semiconductor chip is mounted and on which light from the spatial light modulator is irradiated; An exposure apparatus comprising:

Images