Sic semiconductor device

Abstract

To provide an SiC semiconductor device capable of reducing an influence on an SiC semiconductor chip caused by a modified layer.SOLUTION: The SiC semiconductor device 1 includes the SiC semiconductor layer 2 (SiC semiconductor chip) having the first main surface 3, the second main surface 4, and the side surfaces 5A to 5D, and the modified lines 22A to 22D (modified layers) formed in portions made of the SiC semiconductor substrate 6 at intervals from the SiC epitaxial layer 7 in the side surfaces 5A to 5D. Each of the modified lines 22A to 22D has a plurality of modified portions 2829 each extending in the normal direction Z of the first main surface 3. The reformed portion 28,29 has a tapered shape that narrows toward the second main surface 4.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a SiC semiconductor device. [Background technology]

[0002] In recent years, a processing method for SiC semiconductor wafers known as the stealth dicing method has been attracting attention. In the stealth dicing method, a SiC semiconductor wafer is selectively irradiated with laser light, and then the SiC semiconductor wafer is cut along the irradiated portions. This method can cut SiC semiconductor wafers with relatively high hardness without using a cutting member such as a dicing blade, thereby shortening the manufacturing time.

[0003] Patent Document 1 discloses a method for manufacturing a SiC semiconductor device using a stealth dicing method. In the manufacturing method of Patent Document 1, multiple rows of modified regions (modified layers) are formed over the entire area of ​​each side surface of a SiC semiconductor chip (SiC semiconductor layer) cut from a SiC semiconductor wafer. The multiple rows of modified regions extend along the tangential direction of the main surface of the SiC semiconductor chip and are formed at intervals in the normal direction of the main surface of the SiC semiconductor chip. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-146878 Summary of the Invention [Problem to be solved by the invention]

[0005] The modified layer is formed by modifying the SiC single crystal to have other properties. Therefore, considering the influence of the modified layer on the SiC semiconductor chip (SiC semiconductor layer), it is not desirable to form multiple modified layers over the entire side surface of the SiC semiconductor chip. Examples of the influence of the modified layer on the SiC semiconductor chip include fluctuations in the electrical characteristics of the SiC semiconductor chip due to the modified layer and the occurrence of cracks in the SiC semiconductor chip originating from the modified layer.

[0006] One embodiment provides a SiC semiconductor device that can reduce the influence of a modified layer on a SiC semiconductor chip. [Means for solving the problem]

[0007] One embodiment provides a SiC semiconductor device including: a SiC semiconductor chip having a stacked structure including a SiC semiconductor substrate and a SiC epitaxial layer, the SiC semiconductor chip having an element formation surface formed by the SiC epitaxial layer and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer; and a single modified layer formed on the side surface in a portion of the SiC semiconductor substrate spaced apart from the SiC epitaxial layer, the modified layer having properties different from those of the SiC semiconductor substrate. This structure reduces the effects of the modified layer on the SiC semiconductor chip, particularly on the SiC epitaxial layer that forms the element formation surface.

[0008] One embodiment provides a SiC semiconductor device including: a SiC semiconductor chip having a first main surface as an element formation surface, a second main surface opposite the first main surface, and a side surface; a first impurity region of a first conductivity type formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a second impurity region of the first conductivity type formed in a region closer to the second main surface than the first impurity region so as to have a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the first impurity region, exposed from the second main surface and the side surface, and electrically connected to the first impurity region; and a single modified layer formed on the side surface at a location where the second impurity region is exposed and spaced from the first impurity region, the modified layer having properties different from those of the SiC semiconductor chip. This structure reduces the effects of the modified layer on the SiC semiconductor chip, particularly on the element formation surface where the first impurity region is exposed.

[0009] One embodiment provides a SiC semiconductor device including: a SiC chip having a first main surface on one side, a second main surface on the other side, and a side surface; a first conductivity type semiconductor substrate exposed from the side surface of the SiC chip; a first conductivity type semiconductor region stacked on the substrate main surface of the semiconductor substrate and formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a pn junction region formed in the surface layer portion of the first main surface at a peripheral portion of the first main surface; a second conductivity type impurity region formed in the surface layer portion of the semiconductor region at the peripheral portion of the first main surface and forming the semiconductor region and the pn junction region; and a single reforming line formed on the side surface at a distance from a depth position of the pn junction region toward the second main surface, the reforming line having properties different from SiC. The reforming line may be formed on the side surface at a distance from a depth position of the substrate main surface of the semiconductor substrate toward the second main surface. The reforming line may have multiple reforming portions each extending in a normal direction to the first main surface. The modified portion may have a tapered shape that narrows toward the second main surface.

[0010] One embodiment provides a SiC semiconductor device including: a SiC chip having a first main surface on one side, a second main surface on the other side, and a side surface; a first surface portion located in an inner portion of the first main surface; a second surface portion formed on the peripheral edge of the first main surface so as to be recessed from the first surface portion toward the second main surface; and a plateau defined on the first main surface by a connecting sidewall connecting the first surface portion and the second surface portion; a semiconductor substrate of a first conductivity type exposed from the side surface of the SiC chip; a semiconductor region of a first conductivity type stacked on the substrate main surface of the semiconductor substrate and formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a pn junction region formed in a surface layer portion of the second surface portion; an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region and forming the semiconductor region and the pn junction region; and a single modification line formed on the side surface at a distance from a depth position of the pn junction region toward the second main surface, the single modification line being modified to have properties different from SiC. The modification lines may be formed on the side surface at intervals from a depth position of the substrate main surface of the semiconductor substrate toward the second main surface. The modification lines may have a plurality of modification portions each extending in a normal direction of the first main surface. The modification portions may have a tapered shape narrowing toward the second main surface. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing a unit cell of a 4H—SiC single crystal applied to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the silicon surface of the unit cell of the 4H—SiC single crystal shown in FIG. [Figure 3] FIG. 3 is a perspective view of the SiC semiconductor device according to the first embodiment of the present disclosure viewed from one angle, showing a first example of a modification line. [Figure 4] FIG. 4 is a perspective view of the SiC semiconductor device shown in FIG. 3 as viewed from a different angle. [Figure 5] FIG. 5 is an enlarged view of region V shown in FIG. [Figure 6] FIG. 6 is an enlarged view of region VI shown in FIG. [Figure 7] FIG. 7 is a plan view of the SiC semiconductor device shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 9] FIG. 9 is a perspective view showing a SiC semiconductor wafer used in manufacturing the SiC semiconductor device shown in FIG. [Figure 10A] FIG. 10A is a cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 10B] FIG. 10B is a diagram showing a step subsequent to that of FIG. 10A. [Figure 10C] FIG. 10C is a diagram showing a step subsequent to FIG. 10B. [Figure 10D] FIG. 10D shows a step subsequent to FIG. 10C. [Figure 10E] FIG. 10E shows a step subsequent to FIG. 10D. [Figure 10F] FIG. 10F shows a step subsequent to FIG. 10E. [Figure 10G] FIG. 10G shows a step subsequent to FIG. 10F. [Figure 10H] FIG. 10H shows a step subsequent to FIG. 10G. [Figure 10I] FIG. 10I shows a step subsequent to FIG. 10H. [Figure 10J] FIG. 10J shows a step subsequent to FIG. 10I. [Figure 10K] FIG. 10K shows a step subsequent to FIG. 10J. [Figure 10L] FIG. 10L shows a step subsequent to FIG. 10K. [Figure 10M] FIG. 10M shows a step subsequent to FIG. 10L. [Figure 11] FIG. 11 is a perspective view showing a semiconductor package incorporating the SiC semiconductor device shown in FIG. 3, seen through a sealing resin. [Figure 12A] FIG. 12A is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a second embodiment of the reforming line. [Figure 12B]FIG. 12B is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a third embodiment of the reforming line. [Figure 12C] FIG. 12C is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a fourth embodiment of the reforming line. [Figure 12D] FIG. 12D is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a fifth embodiment of the reforming line. [Figure 12E] FIG. 12E is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a sixth embodiment of the reforming line. [Figure 13] FIG. 13 is a perspective view showing an SiC semiconductor device according to a second embodiment of the present disclosure, showing a structure to which the reforming line according to the first embodiment example is applied. [Figure 14] FIG. 14 is a perspective view of the SiC semiconductor device according to the third embodiment of the present disclosure, seen from one angle, showing a structure to which the reforming line according to the first embodiment example is applied. [Figure 15] FIG. 15 is a perspective view of the SiC semiconductor device shown in FIG. 14 as viewed from a different angle. [Figure 16] FIG. 16 is a plan view showing the SiC semiconductor device shown in FIG. [Figure 17] FIG. 17 is a plan view of FIG. 16 with the resin layer removed. [Figure 18] FIG. 18 is an enlarged view of region XVIII shown in FIG. 17, illustrating the structure of the first main surface of the SiC semiconductor layer. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21] FIG. 21 is an enlarged view of region XXI shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. [Figure 23] FIG. 23 is an enlarged view of region XXIII shown in FIG. [Figure 24] FIG. 24 is a graph illustrating the sheet resistance. [Figure 25] FIG. 25 is an enlarged view of a region corresponding to FIG. 18, showing the SiC semiconductor device according to the fourth embodiment of the present disclosure. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. [Figure 27] FIG. 27 is an enlarged view of a region corresponding to FIG. 21, showing the SiC semiconductor device according to the fifth embodiment of the present disclosure. [Figure 28] FIG. 28 is an enlarged view of a region corresponding to FIG. 18, showing the SiC semiconductor device according to the sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0013] In the embodiments of the present disclosure, a SiC (silicon carbide) single crystal having a hexagonal crystal structure is used. The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal, depending on the period of the atomic arrangement. In the embodiments of the present disclosure, an example in which a 4H-SiC single crystal is used will be described, but other polytypes are not excluded from the present disclosure.

[0014] The crystal structure of the 4H—SiC single crystal will be described below. Fig. 1 is a diagram showing a unit cell of a 4H—SiC single crystal (hereinafter simply referred to as a "unit cell") applied to an embodiment of the present disclosure. Fig. 2 is a plan view showing the silicon surface of the unit cell shown in Fig. 1.

[0015] 1 and 2, the unit cell includes a tetrahedral structure in which one Si atom and four C atoms are bonded in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which four periods of tetrahedral structures are stacked. The unit cell has a hexagonal prism structure with regular hexagonal silicon faces, regular hexagonal carbon faces, and six side faces connecting the silicon faces and the carbon faces.

[0016] The silicon surface is a surface terminated by Si atoms, with one Si atom located at each of the six vertices of a regular hexagon and one Si atom located at the center of the hexagon.

[0017] A carbon face is a terminal face terminated by C atoms, with one C atom located at each of the six vertices of a regular hexagon and one C atom located at the center of the hexagon.

[0018] The crystal planes of the unit cell are defined by four coordinate axes (a1, a2, a3, c), including the a1, a2, a3, and c axes. Of the four coordinate axes, the value of a3 is -(a1 + a2). Below, we will explain the crystal planes of 4H-SiC single crystals using the silicon plane as a reference, as an example of a hexagonal crystal termination plane.

[0019] The a1, a2, and a3 axes are set along the direction of the arrangement of the nearest Si atoms (hereinafter simply referred to as "nearest-neighbor atomic direction") with the Si atom located at the center as the reference in a plan view of the silicon surface seen from the c-axis. The a1, a2, and a3 axes are set at angles shifted by 120° from each other, following the arrangement of the Si atoms.

[0020] The c-axis is set in the normal direction to the silicon surface, with the Si atom at the center as the reference. The silicon surface is the (0001) surface. The carbon surface is the (000-1) surface.

[0021] The side surface of the hexagonal prism includes six crystal planes along the direction of nearest-neighbor atoms in a planar view of the silicon surface from the c-axis. More specifically, the side surface of the hexagonal prism includes six crystal planes each including two nearest-neighbor Si atoms in a planar view of the silicon surface from the c-axis.

[0022] In a plan view of the silicon surface viewed from the c-axis, the side surfaces of the hexagonal prism include, clockwise from the tip of the a1 axis, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes.

[0023] The diagonal planes along the diagonals of the hexagonal prism include six crystal planes along intersecting directions that intersect with the nearest-neighbor atom direction in a planar view of the silicon surface from the c-axis. More specifically, the diagonal planes of the hexagonal prism include six crystal planes each including two Si atoms that are not nearest neighbors in a planar view of the silicon surface from the c-axis. When viewed from the center of the Si atom as a reference, the intersecting direction of the nearest-neighbor atom direction is an orthogonal direction that is perpendicular to the nearest-neighbor atom direction.

[0024] The diagonal faces of the hexagonal prism include the (11-20), (1-210), (-2110), (-1-120), (-12-10), and (2-1-10) faces in a plan view of the silicon surface from the c-axis.

[0025] The crystal directions of the unit cell are defined by the normal directions of the crystal planes. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

[0026] The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

[0027] Hexagonal crystals have six-fold symmetry, and there are equivalent crystal planes and directions every 60°. For example, the (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10) planes form equivalent crystal planes.

[0028] The [1-100], [0-110], [-1010], [-1100], [01-10], and [10-10] directions are equivalent crystal directions, while the [11-20], [1-210], [-2110], [-1-120], [-12-10], and [2-1-10] directions are equivalent crystal directions.

[0029] The c-axis is in the

[0001] direction ([000-1] direction). The a1-axis is in the [2-1-10] direction ([-2110] direction). The a2-axis is in the [-12-10] direction ([1-210] direction). The a3-axis is in the [-1-120] direction ([11-20] direction).

[0030] The (0001) and (000-1) planes are collectively referred to as c-planes. The

[0001] and [000-1] directions are collectively referred to as the c-axis directions. The (11-20) and (-1-120) planes are collectively referred to as a-planes. The [11-20] and [-1-120] directions are collectively referred to as the a-axis directions. The (1-100) and (-1100) planes are collectively referred to as m-planes. The [1-100] and [-1100] directions are collectively referred to as the m-axis directions.

[0031] Fig. 3 is a perspective view of the SiC semiconductor device 1 according to the first embodiment of the present disclosure, seen from one angle, illustrating a first embodiment of the reforming lines 22A to 22D. Fig. 4 is a perspective view of the SiC semiconductor device 1 shown in Fig. 3, seen from another angle.

[0032] Fig. 5 is an enlarged view of region V shown in Fig. 3. Fig. 6 is an enlarged view of region VI shown in Fig. 3. Fig. 7 is a plan view of the SiC semiconductor device 1 shown in Fig. 3. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 7.

[0033] 3 to 8, SiC semiconductor device 1 includes a SiC semiconductor layer 2. SiC semiconductor layer 2 includes a 4H—SiC single crystal as an example of a SiC single crystal made of a hexagonal crystal. SiC semiconductor layer 2 (SiC semiconductor chip) is formed in the shape of a rectangular parallelepiped chip.

[0034] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (a square shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from the normal direction Z thereof.

[0035] The first main surface 3 is an element formation surface on which a semiconductor element is formed. The second main surface 4 of the SiC semiconductor layer 2 is a ground surface having grinding marks. The side surfaces 5A to 5D are each a smooth cleavage plane facing a crystal plane of the SiC single crystal. The side surfaces 5A to 5D do not have grinding marks.

[0036] The thickness TL of the SiC semiconductor layer 2 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

[0037] In this embodiment, the first and second principal surfaces 3 and 4 face the c-plane of the SiC single crystal. The first principal surface 3 faces the (0001) plane (silicon plane). The second principal surface 4 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0038] The first and second principal surfaces 3, 4 have an off-angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off-angle θ with respect to the c-axis (0001) direction of the SiC single crystal.

[0039] The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

[0040] The off angle θ may be set in the range of 3.0° to 4.5°, inclusive. In this case, the off angle θ is preferably set in the range of 3.0° to 3.5°, or 3.5° to 4.0°, inclusive.

[0041] The off angle θ may be set in the range of 1.5° to 3.0°, inclusive. In this case, the off angle θ is preferably set in the range of 1.5° to 2.0°, or 2.0° to 2.5°, inclusive.

[0042] The length of each of the side surfaces 5A to 5D may be 0.5 mm or more and 10 mm or less. In this embodiment, the surface areas of the side surfaces 5A to 5D are equal to one another. When the first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view, the surface areas of the side surfaces 5A and 5C may be less than or greater than the surface areas of the side surfaces 5B and 5D.

[0043] In this embodiment, side surface 5A and side surface 5C extend along a first direction X and face each other in a second direction Y that intersects with first direction X. In this embodiment, side surface 5B and side surface 5D extend along the second direction Y and face each other in first direction X. More specifically, second direction Y is a direction perpendicular to first direction X.

[0044] In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0045] Side surface 5A and side surface 5C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. Side surface 5A is formed by the (-1-120) plane of the SiC single crystal. Side surface 5C is formed by the (11-20) plane of the SiC single crystal.

[0046] Side surface 5B and side surface 5D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. Side surface 5B is formed by the (-1100) plane of the SiC single crystal. Side surface 5D is formed by the (1-100) plane of the SiC single crystal.

[0047] Side 5A and side 5C may form an inclined surface that is inclined toward the c-axis direction (0001 direction) of the SiC single crystal with respect to the normal to first main surface 3 of SiC semiconductor layer 2.

[0048] In this case, when the normal to the first main surface 3 of the SiC semiconductor layer 2 is defined as 0°, the side surface 5A and the side surface 5C may be inclined at an angle corresponding to the off angle θ with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2. The angle corresponding to the off angle θ may be equal to the off angle θ or may be an angle greater than 0° and less than the off angle θ.

[0049] On the other hand, side surface 5B and side surface 5D extend planarly along the normal to first main surface 3 of SiC semiconductor layer 2. More specifically, side surface 5B and side surface 5D are formed substantially perpendicular to first main surface 3 and second main surface 4.

[0050] In this embodiment, the SiC semiconductor layer 2 is + The SiC semiconductor layer 2 has a layered structure including an n-type SiC semiconductor substrate 6 (second impurity region) and an n-type SiC epitaxial layer 7 (first impurity region). The SiC semiconductor substrate 6 forms the second main surface 4 of the SiC semiconductor layer 2.

[0051] The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 7. The SiC semiconductor substrate 6 and the SiC epitaxial layer 7 form side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0052] The n-type impurity concentration of the SiC epitaxial layer 7 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 6. More specifically, the n-type impurity concentration of the SiC epitaxial layer 7 is lower than the n-type impurity concentration of the SiC semiconductor substrate 6. The n-type impurity concentration of the SiC semiconductor substrate 6 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 7 may be 1.0×10 or less. 15 cm -3 Over 1.0 x 10 18 cm -3 It may be the following:

[0053] The thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 6, the resistance value can be reduced by shortening the current path.

[0054] The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

[0055] The SiC semiconductor layer 2 has an active region 8 and an outer region 9. The active region 8 is a region in which a Schottky barrier diode D, which is an example of a semiconductor element, is formed. The outer region 9 is a region outside the active region 8.

[0056] In plan view, the active region 8 is set in the center of the SiC semiconductor layer 2 at a distance inward from the side surfaces 5A to 5D of the SiC semiconductor layer 2. In plan view, the active region 8 is set in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0057] The outer region 9 is set in a region between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the periphery of the active region 8. The outer region 9 is set in an endless shape (a square ring shape in this embodiment) surrounding the active region 8 in a plan view.

[0058] A main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 selectively covers the active region 8 and the outer region 9. The main surface insulating layer 10 may have a single-layer structure made of a silicon oxide (SiO2) layer or a silicon nitride (SiN) layer.

[0059] The main surface insulating layer 10 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on a silicon nitride layer. The silicon nitride layer may be formed on a silicon oxide layer. In this embodiment, the main surface insulating layer 10 has a single-layer structure consisting of a silicon oxide layer.

[0060] The main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C, and 11D exposed from the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are continuous with the side surfaces 5A to 5D of the SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are made of cleavage planes.

[0061] The thickness of the main surface insulating layer 10 may be 1 μm or more and 50 μm or less, 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0062] A first principal surface electrode layer 12 is formed on the principal surface insulating layer 10. The first principal surface electrode layer 12 is formed in the center of the SiC semiconductor layer 2 at an interval inward from the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0063] A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10. The passivation layer 13 may have a single layer structure made of a silicon oxide layer or a silicon nitride layer.

[0064] The passivation layer 13 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on a silicon nitride layer. The silicon nitride layer may be formed on a silicon oxide layer. In this form, the passivation layer 13 has a single-layer structure consisting of a silicon nitride layer.

[0065] In plan view, side surfaces 14A, 14B, 14C, and 14D of passivation layer 13 are formed at intervals inward from side surfaces 5A to 5D of SiC semiconductor layer 2. In plan view, passivation layer 13 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2. Passivation layer 13 exposes main surface insulating layer 10.

[0066] A subpad opening 15 that exposes a part of the first principal surface electrode layer 12 as a pad region is formed in the passivation layer 13. The subpad opening 15 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0067] The thickness of the passivation layer 13 may be 1 μm or more and 50 μm or less, 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0068] A resin layer 16 (insulating layer) is formed on the passivation layer 13. The passivation layer 13 and the resin layer 16 form a single insulating laminated structure (insulating layer). In Figure 7, the resin layer 16 is indicated by hatching.

[0069] The resin layer 16 may contain a negative or positive photosensitive resin. In this embodiment, the resin layer 16 contains polybenzoxazole as an example of a positive photosensitive resin. The resin layer 16 may also contain polyimide as an example of a negative photosensitive resin.

[0070] Resin side surfaces 17A, 17B, 17C, and 17D of resin layer 16 are formed at intervals inward from side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view. Resin layer 16 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2 in a plan view. Resin layer 16 exposes main surface insulating layer 10 as well as passivation layer 13. In this embodiment, resin side surfaces 17A to 17D of resin layer 16 are formed flush with side surfaces 14A to 14D of passivation layer 13.

[0071] Resin side surfaces 17A to 17D of resin layer 16 are portions that define dicing streets when cutting out SiC semiconductor devices 1 from a single SiC semiconductor wafer. In this embodiment, side surfaces 14A to 14D of passivation layer 13 are also portions that define dicing streets.

[0072] By exposing the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 from the resin layer 16 and the passivation layer 13, it is not necessary to physically cut the resin layer 16 and the passivation layer 13. This makes it possible to smoothly cut out the SiC semiconductor device 1 from one SiC semiconductor wafer. Also, the insulation distance from the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be increased.

[0073] The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or more and 15 μm or more and 20 μm or more and 25 μm or less. Of course, the side surfaces 14A to 14D of the passivation layer 13 may be formed flush with the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0074] A pad opening 18 that exposes a part of the first principal surface electrode layer 12 as a pad region is formed in the resin layer 16. The pad opening 18 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0075] The pad opening 18 communicates with the subpad opening 15. The inner wall of the pad opening 18 is formed flush with the inner wall of the subpad opening 15. The inner wall of the pad opening 18 may be located on the side of the side surfaces 5A to 5D of the SiC semiconductor layer 2 with respect to the inner wall of the subpad opening 15. The inner wall of the pad opening 18 may be located in an inner region of the SiC semiconductor layer 2 with respect to the inner wall of the subpad opening 15. The resin layer 16 may cover the inner wall of the subpad opening 15.

[0076] The thickness of the resin layer 16 may be 1 μm or more and 50 μm or less, 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0077] A second-main-surface electrode layer 19 is formed on the second main surface 4 of the SiC semiconductor layer 2. The second-main-surface electrode layer 19 forms ohmic contact with the second main surface 4 of the SiC semiconductor layer 2 (SiC semiconductor substrate 6).

[0078] A plurality of modified lines 22A to 22D (modified layers) are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2. More specifically, the modified lines 22A to 22D are formed one by one on the side surfaces 5A to 5D in a one-to-one correspondence.

[0079] The reforming lines 22A to 22D include one layer of reforming lines 22A formed on the side surface 5A, one layer of reforming lines 22B formed on the side surface 5B, one layer of reforming lines 22C formed on the side surface 5C, and one layer of reforming lines 22D formed on the side surface 5D. In this embodiment, the reforming lines 22A to 22D consist of a single layer.

[0080] The single layer of reforming lines 22A may include a form in which a plurality of reforming lines 22A are formed by overlapping each other, so that the reforming lines 22A made up of a plurality of layers can be considered to form a single layer of reforming lines 22A.

[0081] The single layer of reforming lines 22B may include a form in which a plurality of reforming lines 22B are formed by overlapping each other, so that the reforming lines 22B made up of a plurality of layers can be considered to form a single layer of reforming lines 22B.

[0082] The reforming line 22C in one layer may include a mode in which a plurality of reforming lines 22C are formed by overlapping each other, so that the reforming line 22C made up of a plurality of layers can be considered to form one layer of reforming line 22C.

[0083] The reforming line 22D of one layer may include a mode in which a plurality of reforming lines 22D are formed by overlapping each other, so that one layer of reforming line 22D can be considered to be formed by the reforming lines 22D made up of a plurality of layers.

[0084] However, in these cases, the reforming lines 22A to 22D must be formed in multiple layers on the corresponding side surfaces 5A to 5D, which is not preferable in terms of increasing the number of steps, delaying the manufacturing time, etc. Therefore, this embodiment shows an example in which the reforming lines 22A to 22D consisting of a single layer are formed on each of the side surfaces 5A to 5D.

[0085] The modified lines 22A to 22D include layered regions in which portions of the SiC single crystals forming the side surfaces 5A to 5D have been modified to have properties different from those of the SiC single crystals. The modified lines 22A to 22D include regions in which the density, refractive index, mechanical strength (crystal strength), or other physical properties have been modified to have properties different from those of the SiC single crystals.

[0086] The modification lines 22A to 22D may include at least one layer selected from the group consisting of a melt-rehardened layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The melt-rehardened layer is a layer formed by melting a portion of the SiC semiconductor layer 2 and then rehardening. The defect layer is a layer containing voids, cracks, etc. formed in the SiC semiconductor layer 2. The dielectric breakdown layer is a layer formed by dielectric breakdown in a portion of the SiC semiconductor layer 2. The refractive index change layer is a layer formed by changing a portion of the SiC semiconductor layer 2 to a refractive index different from that of the SiC single crystal.

[0087] The modification lines 22A to 22D extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. The tangential direction of the first main surface 3 is a direction perpendicular to the normal direction Z. The tangential direction includes a first direction X (the m-axis direction of the SiC single crystal) and a second direction Y (the a-axis direction of the SiC single crystal).

[0088] More specifically, the reforming line 22A is formed in a band shape that extends linearly along the m-axis direction on the side surface 5A. The reforming line 22B is formed in a band shape that extends linearly along the a-axis direction on the side surface 5B. The reforming line 22C is formed in a band shape that extends linearly along the m-axis direction on the side surface 5C. The reforming line 22D is formed in a band shape that extends linearly along the a-axis direction on the side surface 5D.

[0089] The reforming lines 22A to 22D are formed at intervals from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. The reforming lines 22A to 22D expose the surface portion of the first main surface 3 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D. In other words, the reforming lines 22A to 22D are not formed in the main surface insulating layer 10, the passivation layer 13, and the resin layer 16.

[0090] The modification lines 22A to 22D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. The modification lines 22A to 22D expose the surface portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.

[0091] As a result, the modification lines 22A to 22D divide each side surface 5A to 5D of the SiC semiconductor layer 2 into two regions, one on the first main surface 3 side and one on the second main surface 4 side, when viewed from the side normal to each side surface 5A to 5D of the SiC semiconductor layer 2.

[0092] The reforming lines 22A to 22D are formed on the SiC semiconductor substrate 6. The reforming lines 22A to 22D are formed from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4 at intervals.

[0093] As a result, the reforming lines 22A to 22D expose the SiC epitaxial layer 7 in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. In other words, the SiC epitaxial layer 7 is included in the region on the first main surface 3 side of the regions divided into two by the reforming lines 22A to 22D on each of the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0094] On each of the side surfaces 5A to 5D, a stripe pattern extending in the tangent direction of the first main surface 3 is formed by the reforming lines 22A to 22D, the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2, and the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2.

[0095] The reforming line 22A and the reforming line 22B are connected to each other at a corner portion connecting the side surface 5A and the side surface 5B of the SiC semiconductor layer 2. The reforming line 22B and the reforming line 22C are connected to each other at a corner portion connecting the side surface 5B and the side surface 5C of the SiC semiconductor layer 2.

[0096] The reforming line 22C and the reforming line 22D are connected to each other at a corner connecting the side surface 5C and the side surface 5D of the SiC semiconductor layer 2. The reforming line 22D and the reforming line 22A are connected to each other at a corner connecting the side surface 5D and the side surface 5A of the SiC semiconductor layer 2.

[0097] As a result, the reforming lines 22A to 22D are integrally formed so as to surround the SiC semiconductor layer 2. In other words, the reforming lines 22A to 22D form a single endless (annular) reforming line that surrounds the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0098] Preferably, the thickness TR of the modified lines 22A to 22D with respect to the normal direction Z is not more than the thickness TL of the SiC semiconductor layer 2 (TR≦TL). More preferably, the thickness TR of the modified lines 22A to 22D is less than the thickness TS of the SiC semiconductor substrate 6 (TR<TS).

[0099] The thickness TR of the modified lines 22A to 22D may be not less than the thickness TE of the SiC epitaxial layer 7 (TR≧TE). The thicknesses of the thickness TR of the modified line 22A, the thickness TR of the modified line 22B, the thickness TR of the modified line 22C, and the thickness TR of the modified line 22D may be equal to each other or different from each other.

[0100] Preferably, the ratio TR / TL of the thickness TR of the modified lines 22A to 22D to the thickness TL of the SiC semiconductor layer 2 is not less than 0.1 and less than 1.0. The ratio TR / TL may be not less than 0.1 and not more than 0.2, not less than 0.2 and not more than 0.4, not less than 0.4 and not more than 0.6, not less than 0.6 and not more than 0.8, or not less than 0.8 and less than 1.0.

[0101] The ratio TR / TL may be not less than 0.1 and not more than 0.2, not less than 0.2 and not more than 0.3, not less than 0.3 and not more than 0.4, not less than 0.4 and not more than 0.5, not less than 0.5 and not more than 0.6, not less than 0.6 and not more than 0.7, not less than 0.7 and not more than 0.8, not less than 0.8 and not more than 0.9, or not less than 0.9 and less than 1.0. Preferably, the ratio TR / TL is not less than 0.2 and not more than 0.5.

[0102] More preferably, the ratio TR / TS of the thickness TR of the modified lines 22A to 22D to the thickness TS of the SiC semiconductor substrate 6 is not less than 0.1 and less than 1.0. The ratio TR / TS may be not less than 0.1 and not more than 0.2, not less than 0.2 and not more than 0.4, not less than 0.4 and not more than 0.6, not less than 0.6 and not more than 0.8, or not less than 0.8 and less than 1.0.

[0103] The ratio TR / TS may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio TR / TS is preferably 0.2 or more and 0.5 or less.

[0104] 5, the modification line 22A includes a plurality of a-plane modified portions 28 (modified portions). In other words, the modification line 22A is formed by an assembly of a plurality of a-plane modified portions 28. The plurality of a-plane modified portions 28 are portions of the SiC single crystal exposed from the side surface 5A that have been modified to have properties different from those of the SiC single crystal. The area around each a-plane modified portion 28 on the side surface 5A may be modified to have properties different from those of the SiC single crystal.

[0105] Each of the multiple a-plane modified portions 28 includes one end portion 28a located on the first main surface 3 side, the other end portion 28b located on the second main surface 4 side, and a connecting portion 28c connecting the one end portion 28a and the other end portion 28b.

[0106] The multiple a-plane modified regions 28 are each formed in a line extending in the normal direction Z. As a result, the multiple a-plane modified regions 28 are formed in a striped pattern as a whole. The multiple a-plane modified regions 28 may include multiple a-plane modified regions 28 formed in a tapered shape in which the width in the m-axis direction narrows from one end 28a side to the other end 28b side.

[0107] The multiple a-plane modified regions 28 are formed at intervals in the m-axis direction so as to face each other in the m-axis direction. The multiple a-plane modified regions 28 may overlap each other in the m-axis direction. A band-shaped region extending in the m-axis direction is formed by a line connecting one end 28a of the multiple a-plane modified regions 28 and a line connecting the other end 28b of the multiple a-plane modified regions 28. The modification line 22A is formed by this band-shaped region.

[0108] Each of the multiple a-plane modified regions 28 may have a notch formed by cutting out the side surface 5A. Each of the multiple a-plane modified regions 28 may have a recess recessed from the side surface 5A toward the a-axis direction. The multiple a-plane modified regions 28 may be formed in a dot pattern according to their length in the normal direction Z and their width in the m-axis direction.

[0109] In the m-axis direction, the pitch PR between the central portions of adjacent a-plane modified portions 28 may be greater than 0 μm and less than or equal to 20 μm, or greater than 0 μm and less than or equal to 5 μm, greater than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, or greater than or equal to 15 μm and less than or equal to 20 μm.

[0110] In the m-axis direction, the width WR of each a-plane modified region 28 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, or greater than or equal to 15 μm and less than or equal to 20 μm.

[0111] The reforming line 22C has the same structure as the reforming line 22A, except that it is formed on the side surface 5C. The description of the reforming line 22A applies mutatis mutandis to the description of the reforming line 22C, with "side surface 5A" read as "side surface 5C."

[0112] 6, the modification line 22D includes a plurality of m-plane modified portions 29 (modified portions). In other words, the modification line 22D is formed by an aggregate of a plurality of m-plane modified portions 29. The plurality of m-plane modified portions 29 are portions of the SiC single crystal exposed from the side surface 5D that have been modified to have properties different from those of the SiC single crystal. The region around each m-plane modified portion 29 on the side surface 5D may be modified to have properties different from those of the SiC single crystal.

[0113] Each of the multiple m-plane modified portions 29 includes one end portion 29a located on the first main surface 3 side, the other end portion 29b located on the second main surface 4 side, and a connecting portion 29c connecting the one end portion 29a and the other end portion 29b.

[0114] The multiple m-plane modified regions 29 are each formed in a line extending in the normal direction Z. As a result, the multiple m-plane modified regions 29 are formed in a striped pattern as a whole. The multiple m-plane modified regions 29 may include multiple m-plane modified regions 29 formed in a tapered shape in which the width in the a-axis direction narrows from one end 29a to the other end 29b.

[0115] The multiple m-plane modified regions 29 are formed at intervals in the a-axis direction so as to face each other in the a-axis direction. The multiple m-plane modified regions 29 may overlap each other in the a-axis direction. A band-shaped region extending in the a-axis direction is formed by a line connecting one end 29a of the multiple m-plane modified regions 29 and a line connecting the other end 29b of the multiple m-plane modified regions 29. The modification line 22D is formed by this band-shaped region.

[0116] Each of the multiple m-plane modified regions 29 may form a notch by cutting out the side surface 5D. Each of the multiple m-plane modified regions 29 may form a recess that is recessed from the side surface 5D toward the m-axis direction. The multiple m-plane modified regions 29 may be formed in a dot pattern according to their length in the normal direction Z and their width in the a-axis direction.

[0117] In the a-axis direction, the pitch PR between the central portions of adjacent m-plane modified regions 29 may be 0 μm or more and 20 μm or less. The pitch PR may be 0 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

[0118] In the a-axis direction, the width WR of each m-plane modified region 29 may be greater than 0 μm and less than or equal to 20 μm. The width WR may be greater than 0 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, or greater than or equal to 15 μm and less than or equal to 20 μm.

[0119] The reforming line 22B has the same structure as the reforming line 22D, except that it is formed on the side surface 5B. The description of the reforming line 22D applies mutatis mutandis to the description of the reforming line 22B, with "side surface 5D" read as "side surface 5B."

[0120] 8, in active region 8, an n-type diode region 35 is formed in a surface layer portion of first main surface 3 of SiC semiconductor layer 2. In this embodiment, diode region 35 is formed in a central portion of first main surface 3 of SiC semiconductor layer 2. In this embodiment, diode region 35 is set in a quadrangular shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in plan view.

[0121] The n-type impurity concentration of the diode region 35 may be equal to or higher than the n-type impurity concentration of the SiC epitaxial layer 7. In this embodiment, the diode region 35 is formed by utilizing a part of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 35 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The diode region 35 may be formed by introducing n-type impurities into a surface portion of the SiC epitaxial layer 7.

[0122] In the outer region 9, the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 contains p + A mold guard region 36 is formed. The guard region 36 is formed in a strip shape extending along the diode region 35 in a plan view.

[0123] More specifically, the guard region 36 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners, or a circular ring) surrounding the diode region 35 in a plan view. As a result, the guard region 36 is formed as a guard ring region. In this embodiment, the diode region 35 is defined by the guard region 36. Furthermore, the active region 8 is defined by the guard region 36.

[0124] The p-type impurities in the guard region 36 may not be activated. In this case, the guard region 36 is formed as a non-semiconductor region. The p-type impurities in the guard region 36 may be activated. In this case, the guard region 36 is formed as a p-type semiconductor region.

[0125] The aforementioned main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. A diode opening 37 that exposes the diode region 35 is formed in the main surface insulating layer 10. The diode opening 37 exposes not only the diode region 35 but also the inner periphery of the guard region 36. The diode opening 37 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

[0126] The aforementioned first principal surface electrode layer 12 is formed on the principal surface insulating layer 10. The first principal surface electrode layer 12 extends from above the insulating layer into the diode opening 37. The first principal surface electrode layer 12 is electrically connected to the diode region 35 within the diode opening 37.

[0127] More specifically, the first principal surface electrode layer 12 forms a Schottky junction with the diode region 35. This forms a Schottky barrier diode D with the first principal surface electrode layer 12 as the anode and the diode region 35 as the cathode. The aforementioned passivation layer 13 and resin layer 16 are formed on the principal surface insulating layer 10.

[0128] FIG. 9 is a perspective view showing a SiC semiconductor wafer 41 used in manufacturing the SiC semiconductor device 1 shown in FIG.

[0129] The SiC semiconductor wafer 41 is a base member of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 includes a 4H—SiC single crystal, which is an example of a SiC single crystal made of a hexagonal crystal. In this form, the SiC semiconductor wafer 41 has an n-type impurity concentration corresponding to the n-type impurity concentration of the SiC semiconductor substrate 6.

[0130] The SiC semiconductor wafer 41 is formed in a plate or disk shape. The SiC semiconductor wafer 41 may be formed in a disk shape. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43.

[0131] The thickness TW of the SiC semiconductor wafer 41 exceeds the thickness TS of the SiC semiconductor substrate 6 (TS < TW). The thickness TW of the SiC semiconductor wafer 41 is adjusted to the thickness TS of the SiC semiconductor substrate 6 by grinding.

[0132] The thickness TW may be greater than 150 μm and less than or equal to 750 μm. The thickness TW may be greater than 150 μm and less than or equal to 300 μm, greater than or equal to 300 μm and less than or equal to 450 μm, greater than or equal to 450 μm and less than or equal to 600 μm, or greater than or equal to 600 μm and less than or equal to 750 μm. Considering the grinding time of the SiC semiconductor wafer 41, the thickness TW is preferably greater than 150 μm and less than or equal to 500 μm. The thickness TW is typically greater than or equal to 300 μm and less than or equal to 450 μm.

[0133] In this form, the first wafer main surface 42 and the second wafer main surface 43 face the c-plane of the SiC single crystal. The first wafer main surface 42 faces the (0001) plane (silicon plane). The second wafer main surface 43 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0134] The first wafer main surface 42 and the second wafer main surface 43 have an off-angle θ inclined at an angle of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 42 is inclined by the off-angle θ with respect to the c-axis (

[0001] direction) of the SiC single crystal.

[0135] The off-angle θ may be 0° or more and 5.0° or less. The off-angle θ may be set in the range of angles of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. It is preferable that the off-angle θ exceeds 0°. The off-angle θ may be less than 4.0°.

[0136] The off angle θ may be set in the range of 3.0° to 4.5°, inclusive. In this case, the off angle θ is preferably set in the range of 3.0° to 3.5°, or 3.5° to 4.0°, inclusive.

[0137] The off angle θ may be set in the range of 1.5° to 3.0°, inclusive. In this case, the off angle θ is preferably set in the range of 1.5° to 2.0°, or 2.0° to 2.5°, inclusive.

[0138] The SiC semiconductor wafer 41 includes a first wafer corner 45 connecting the first wafer main surface 42 and the wafer side surface 44, and a second wafer corner 46 connecting the second wafer main surface 43 and the wafer side surface 44. The first wafer corner 45 has a first chamfered portion 47 that slopes downward from the first wafer main surface 42 toward the wafer side surface 44. The second wafer corner 46 has a second chamfered portion 48 that slopes downward from the second wafer main surface 43 toward the wafer side surface 44.

[0139] The first chamfered portion 47 may be formed in a convex curved shape. The second chamfered portion 48 may be formed in a convex curved shape. The first chamfered portion 47 and the second chamfered portion 48 suppress cracks in the SiC semiconductor wafer 41.

[0140] An orientation flat 49 is formed on the wafer side surface 44 of the SiC semiconductor wafer 41 as an example of a mark indicating the crystal orientation of the SiC single crystal. The orientation flat 49 is a notch formed on the wafer side surface 44 of the SiC semiconductor wafer 41. In this form, the orientation flat 49 extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

[0141] A plurality of (e.g., two) orientation flats 49 indicating crystal orientation may be formed on the wafer side surface 44 of the SiC semiconductor wafer 41. The plurality of (e.g., two) orientation flats 49 may include a first orientation flat and a second orientation flat.

[0142] The first orientation flat may be a notch extending linearly along the a-axis direction ([11-20] direction) of the SiC single crystal, and the second orientation flat may be a notch extending linearly along the m-axis direction ([1-100] direction) of the SiC single crystal.

[0143] A plurality of device formation regions 51 corresponding to the SiC semiconductor devices 1 are set on the first wafer main surface 42 of the SiC semiconductor wafer 41. The device formation regions 51 are set in a matrix array at intervals in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).

[0144] Each device formation region 51 has four sides 52A, 52B, 52C, and 52D aligned along the crystal orientation of the SiC single crystal. The four sides 52A to 52D correspond to the four side surfaces 5A to 5D of the SiC semiconductor layer 2. The four sides 52A to 52D include two sides 52A and 52C aligned along the m-axis direction (the [1-100] direction) and two sides 52B and 52D aligned along the a-axis direction (the [11-20] direction).

[0145] The device formation regions 51 are each partitioned by lattice-shaped cutting lines 53 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The cutting lines 53 include a plurality of first cutting lines 54 and a plurality of second cutting lines 55.

[0146] The plurality of first cutting lines 54 extend along the m-axis direction (the [1-100] direction). The plurality of second cutting lines 55 extend along the a-axis direction (the [11-20] direction). After predetermined structures are formed in the plurality of device formation regions 51, the SiC semiconductor wafer 41 is cut along the cutting lines 53 to cut out a plurality of SiC semiconductor devices 1.

[0147] Figures 10A to 10M are cross-sectional views showing an example of a method for manufacturing the SiC semiconductor device 1 shown in Figure 3. For convenience of explanation, Figures 10A to 10M show only the regions where three SiC semiconductor devices 1 are formed, and omit illustration of other regions.

[0148] 10A, in manufacturing SiC semiconductor device 1, first, SiC semiconductor wafer 41 is prepared (also see FIG. 9). Next, n-type SiC epitaxial layer 7 is formed on first wafer main surface 42 of SiC semiconductor wafer 41.

[0149] In the step of forming the SiC epitaxial layer 7, SiC is epitaxially grown from the first wafer main surface 42 of the SiC semiconductor wafer 41. The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less.

[0150] This forms a SiC semiconductor wafer structure 61 including the SiC semiconductor wafer 41 and the SiC epitaxial layer 7. The SiC semiconductor wafer structure 61 includes a first main surface 62 and a second main surface 63.

[0151] The first and second main surfaces 62, 63 of the SiC semiconductor wafer structure 61 correspond to the first and second main surfaces 3, 4, respectively, of the SiC semiconductor layer 2. The thickness TWS of the SiC semiconductor wafer structure 61 may be greater than 150 μm and not greater than 800 μm. Preferably, the thickness TWS is greater than 150 μm and not greater than 550 μm.

[0152] Next, referring to FIG. 10B, a p + A p-type guard region 36 is formed in the SiC epitaxial layer 7. The step of forming the guard region 36 includes a step of selectively introducing p-type impurities into the surface layer portion of the first main surface 62 of the SiC semiconductor wafer structure 61 via an ion implantation mask (not shown). More specifically, the guard region 36 is formed in the surface layer portion of the SiC epitaxial layer 7.

[0153] The guard region 36 defines an active region 8 and an outer region 9 in the SiC semiconductor wafer structure 61. In the region surrounded by the guard region 36 (the active region 8), an n-type diode region 35 is defined.

[0154] The diode region 35 may be formed by selectively introducing n-type impurities into the surface layer portion of the first main surface 62 of the SiC semiconductor wafer structure 61 through an ion implantation mask (not shown).

[0155] 10C, a main surface insulating layer 10 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The main surface insulating layer 10 includes silicon oxide (SiO2). The main surface insulating layer 10 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (e.g., a thermal oxidation treatment method).

[0156] 10D, a mask 64 having a predetermined pattern is formed on the main surface insulating layer 10. The mask 64 has a plurality of openings 65. The plurality of openings 65 expose regions in the main surface insulating layer 10 where the diode openings 37 are to be formed.

[0157] Next, unnecessary portions of the main surface insulating layer 10 are removed by etching using the mask 64. This forms a diode opening 37 in the main surface insulating layer 10. After the diode opening 37 is formed, the mask 64 is removed.

[0158] 10E, a base electrode layer 66 that serves as a base for the first main surface electrode layer 12 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The base electrode layer 66 is formed over the entire first main surface 62 of the SiC semiconductor wafer structure 61, and covers the main surface insulating layer 10. The first main surface electrode layer 12 may be formed by vapor deposition, sputtering, or plating.

[0159] 10F, a mask 67 having a predetermined pattern is formed on the base electrode layer 66. The mask 67 has openings 68 that expose regions of the base electrode layer 66 other than the regions where the first principal surface electrode layer 12 is to be formed.

[0160] Next, unnecessary portions of the base electrode layer 66 are removed by etching using the mask 67. This divides the base electrode layer 66 into a plurality of first principal surface electrode layers 12. After the first principal surface electrode layers 12 are formed, the mask 67 is removed.

[0161] 10G, a passivation layer 13 is formed on the first main surface 62 of the SiC semiconductor wafer structure 61. The passivation layer 13 includes silicon nitride (SiN). The passivation layer 13 may be formed by a CVD method.

[0162] 10H, a resin layer 16 is applied on the passivation layer 13. The resin layer 16 collectively covers the active region 8 and the outer region 9. The resin layer 16 may contain polybenzoxazole, which is an example of a positive-type photosensitive resin.

[0163] 10I, the resin layer 16 is selectively exposed to light and then developed. As a result, pad openings 18 are formed in the resin layer 16. Also, dicing streets 69 are defined in the resin layer 16 along the cutting lines 53 (sides 52A to 52D of each device formation region 51).

[0164] Next, unnecessary portions of the passivation layer 13 are removed. The unnecessary portions of the passivation layer 13 may be removed by an etching method via the resin layer 16. As a result, subpad openings 15 are formed in the passivation layer 13. Also, dicing streets 69 are defined in the passivation layer 13 along the cutting lines 53.

[0165] In this embodiment, the process of removing unnecessary portions of the passivation layer 13 by using the resin layer 16 has been described. However, the resin layer 16 and the pad opening 18 may be formed after the subpad opening 15 is formed in the passivation layer 13.

[0166] In this case, prior to the step of forming the resin layer 16, unnecessary portions of the passivation layer 13 are removed by etching using a mask to form the subpad opening 15. This step allows the passivation layer 13 to be formed in any desired shape.

[0167] 10J, the second main surface 63 of the SiC semiconductor wafer structure 61 (the second wafer main surface 43 of the SiC semiconductor wafer 41) is ground. This thins the SiC semiconductor wafer structure 61 (the SiC semiconductor wafer 41). Grinding marks are also formed on the second main surface 63 of the SiC semiconductor wafer structure 61.

[0168] The SiC semiconductor wafer structure 61 is ground to a thickness TWS corresponding to the thickness TL of the SiC semiconductor layer 2. The SiC semiconductor wafer structure 61 may be ground to a thickness TWS of 40 μm or more and 200 μm or less.

[0169] That is, the SiC semiconductor wafer 41 is ground to a thickness TW corresponding to the thickness TS of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 may be ground to a thickness TW of 40 μm or more and 150 μm or less.

[0170] 10K, a plurality of modified lines 70 (modified layers) are formed as bases for the modified lines 22A to 22D. In the process of forming the modified lines 70, a pulsed laser beam is irradiated from a laser beam irradiation device 71 toward the SiC semiconductor wafer structure 61.

[0171] In this embodiment, the laser light is irradiated onto the SiC semiconductor wafer structure 61 from the first main surface 62 side of the SiC semiconductor wafer structure 61 through the main surface insulating layer 10. The laser light may also be irradiated directly onto the SiC semiconductor wafer structure 61 from the second main surface 63 side of the SiC semiconductor wafer structure 61.

[0172] The focusing point (focus) of the laser light is set at a midpoint in the thickness direction of the SiC semiconductor wafer structure 61. The irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the cutting lines 53 (the four sides 52A to 52D of each device formation region 51).

[0173] More specifically, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the first lines to cut 54. In addition, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the second lines to cut 55.

[0174] As a result, multiple modification lines 70 are formed in the middle of the thickness direction of the SiC semiconductor wafer structure 61, extending along the intended cutting lines 53 (the four sides 52A to 52D of each device formation region 51) and modifying the crystalline state of the SiC single crystal to properties different from those in other regions.

[0175] The two modified lines 70 along the sides 52A and 52C of the device formation region 51 each include an a-plane modified portion 28. The two modified lines 70 along the sides 52B and 52D of the device formation region 51 each include an m-plane modified portion 29.

[0176] The multiple modification lines 70 are formed one layer at a time in a one-to-one correspondence with the four sides 52A to 52D of each device formation region 51. The multiple modification lines 70 are also laser processing marks formed in the middle of the thickness direction of the SiC semiconductor wafer structure 61. More specifically, the a-plane modified portion 28 and the m-plane modified portion 29 included in the modification line 70 are laser processing marks.

[0177] The focused part (focus), laser energy, pulse duty ratio, irradiation speed, etc. of the laser light are determined to arbitrary values ​​depending on the position, size, shape, thickness, etc. of the modified lines 70 (modified lines 22A to 22D) to be formed.

[0178] 10L, a second main surface electrode layer 19 is formed on the second main surface 63 of the SiC semiconductor wafer structure 61. The second main surface electrode layer 19 may be formed by vapor deposition, sputtering, or plating.

[0179] Prior to the step of forming the second-main-surface electrode layer 19, an annealing treatment may be performed on the second main surface 63 (ground surface) of the SiC semiconductor wafer structure 61. The annealing treatment may be performed by a laser annealing method using laser light.

[0180] The laser annealing method modifies the SiC single crystal in the surface layer portion of the second main surface 63 of the SiC semiconductor wafer structure 61 to form an Si amorphous layer. In this case, the SiC semiconductor device 1 is manufactured, which has an Si amorphous layer in the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2. Grinding marks and an Si amorphous layer coexist on the second main surface 4 of the SiC semiconductor layer 2. The laser annealing method can improve the ohmic contact of the second main surface electrode layer 19 with the second main surface 4 of the SiC semiconductor layer 2.

[0181] 10M, a plurality of SiC semiconductor devices 1 are cut out from the SiC semiconductor wafer structure 61. In this step, a tape-shaped support member 73 is attached to the second main surface 63 side of the SiC semiconductor wafer structure 61.

[0182] Next, an external force is applied to the lines to cut 53 from the second main surface 63 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force to the lines to cut 53 may be applied by a pressing member such as a blade.

[0183] In another embodiment, a support member 73 may be attached to the first main surface 62 side of the SiC semiconductor wafer structure 61. In this case, an external force may be applied to the line to cut 53 from the first main surface 62 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force may be applied by a pressing member such as a blade.

[0184] In yet another embodiment, a stretchable support member 73 may be attached to the first main surface 62 or the second main surface 63 of the SiC semiconductor wafer structure 61. In this case, the SiC semiconductor wafer structure 61 may be cleaved by stretching the stretchable support member 73 in the m-axis direction and the a-axis direction.

[0185] When the SiC semiconductor wafer structure 61 is cleaved using the support member 73, it is preferable that the support member 73 be attached to the second main surface 63 side of the SiC semiconductor wafer structure 61 where there are fewer obstacles.

[0186] In this way, the SiC semiconductor wafer structure 61 is cleaved along the cutting lines 53 starting from the modification lines 70 (modification lines 22A to 22D), and a plurality of SiC semiconductor devices 1 are cut out from one SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

[0187] The portion of the modification line 70 that follows the side 52A of each device formation region 51 becomes the modification line 22A. The portion of the modification line 70 that follows the side 52B of each device formation region 51 becomes the modification line 22B. The portion of the modification line 70 that follows the side 52C of each device formation region 51 becomes the modification line 22C. The portion of the modification line 70 that follows the side 52D of each device formation region 51 becomes the modification line 22D. The SiC semiconductor device 1 is manufactured through processes including those described above.

[0188] In this embodiment, the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 is performed prior to the forming step (FIG. 10K) of the modification lines 70 (modification lines 22A to 22D). However, the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 can be performed at any timing after the preparing step (FIG. 10A) of the SiC semiconductor wafer 41 and before the forming step (FIG. 10L) of the second principal surface electrode layer 19.

[0189] For example, the grinding step of the SiC semiconductor wafer structure 61 (FIG. 10J) may be performed prior to the formation step of the SiC epitaxial layer 7 (FIG. 10A). Also, the grinding step of the SiC semiconductor wafer structure 61 (FIG. 10J) may be performed after the formation step of the modification line 70 (modification lines 22A to 22D) (FIG. 10K).

[0190] Furthermore, the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 may be performed in multiple steps at any timing after the preparation step (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation step (FIG. 10K) of the modification line 70 (modification lines 22A to 22D). Furthermore, the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61 may be performed in multiple steps at any timing after the preparation step (FIG. 10A) of the SiC semiconductor wafer 41 and before the formation step (FIG. 10L) of the second principal surface electrode layer 19.

[0191] FIG. 11 is a perspective view showing a semiconductor package 74 incorporating the SiC semiconductor device 1 shown in FIG. 3, with sealing resin 79 seen through.

[0192] 11, in this embodiment, semiconductor package 74 is a so-called TO-220 type. Semiconductor package 74 includes SiC semiconductor device 1, pad portion 75, heat sink 76, multiple (two in this embodiment) terminals 77, multiple (two in this embodiment) conductive wires 78, and sealing resin 79. Pad portion 75, heat sink 76, and multiple terminals 77 form a lead frame as an example of an object to be connected.

[0193] The pad portion 75 includes a metal plate. The pad portion 75 may include iron, gold, silver, copper, aluminum, etc. The pad portion 75 is formed in a quadrangular shape in a plan view. The pad portion 75 has a planar area equal to or greater than the planar area of ​​the SiC semiconductor device 1. The SiC semiconductor device 1 is disposed on the pad portion 75.

[0194] The second principal surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via a conductive bonding material 80. The conductive bonding material 80 is interposed in the region between the second principal surface electrode layer 19 and the pad portion 75.

[0195] The conductive bonding material 80 may be a metallic paste or solder. The metallic paste may be a conductive paste containing Au (gold), Ag (silver), or Cu (copper). The conductive bonding material 80 is preferably made of solder. The solder may be a lead-free solder. The solder may contain at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, or SnSbNi.

[0196] The heat sink 76 is connected to one side of the pad portion 75. In this embodiment, the pad portion 75 and the heat sink 76 are formed from a single metal plate. A through hole 76a is formed in the heat sink 76. The through hole 76a is formed in a circular shape.

[0197] The plurality of terminals 77 are arranged along the side of the pad portion 75 opposite to the heat sink 76. Each of the plurality of terminals 77 includes a metal plate. The terminals 77 may include iron, gold, silver, copper, aluminum, or the like.

[0198] The multiple terminals 77 include first terminals 77A and second terminals 77B. The first terminals 77A and second terminals 77B are arranged at intervals along the side of the pad portion 75 opposite to the heat sink 76. The first terminals 77A and second terminals 77B extend in a strip shape in a direction perpendicular to the direction in which they are arranged.

[0199] The plurality of conductors 78 may be bonding wires or the like. The plurality of conductors 78 include conductor 78A and conductor 78B. Conductor 78A is electrically connected to first terminal 77A and first main surface electrode layer 12 of SiC semiconductor device 1. As a result, first terminal 77A is electrically connected to first main surface electrode layer 12 of SiC semiconductor device 1 via conductor 78A.

[0200] Conductive wire 78B is electrically connected to second terminal 77B and pad portion 75. As a result, second terminal 77B is electrically connected to second main surface electrode layer 19 of SiC semiconductor device 1 via conductive wire 78B. Second terminal 77B may be formed integrally with pad portion 75.

[0201] Sealing resin 79 seals SiC semiconductor device 1, pad portion 75, and a plurality of conductive wires 78 so as to expose heat sink 76 and parts of a plurality of terminals 77. Sealing resin 79 is formed in a rectangular parallelepiped shape.

[0202] The form of the semiconductor package 74 is not limited to TO-220. The semiconductor package 74 may be a small outline package (SOP), a quad for non-lead package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), a small outline J-leaded package (SOJ), or any of a variety of other forms similar thereto.

[0203] As described above, the SiC semiconductor device 1 includes a plurality of reforming lines 22A-22D formed one layer on each of the side surfaces 5A-5D of the SiC semiconductor layer 2. According to the SiC semiconductor device 1, only one reforming line 22A-22D is formed on each of the side surfaces 5A-5D of the SiC semiconductor layer 2. This reduces the influence of the reforming lines 22A-22D on the SiC semiconductor layer 2.

[0204] Examples of the influence on the SiC semiconductor layer 2 caused by the reforming line include fluctuations in the electrical characteristics of the SiC semiconductor layer 2 caused by the reforming line, and the occurrence of cracks in the SiC semiconductor layer 2 originating from the reforming line.

[0205] The change in leakage current characteristics is exemplified as a change in the electrical characteristics of the SiC semiconductor layer 2 caused by the reforming lines. The SiC semiconductor device may be encapsulated with an encapsulating resin 79 as shown in FIG.

[0206] In this case, it is conceivable that mobile ions in the sealing resin 79 may enter the SiC semiconductor layer 2 through the modification lines. In a structure in which a plurality of modification lines are formed at intervals along the normal direction Z over the entire area of ​​each of the side surfaces 5A to 5D, the risk of current path formation due to such an external structure increases.

[0207] Furthermore, in a structure in which a plurality of reforming lines are formed along the normal direction Z over the entire area of ​​each of the side surfaces 5A to 5D of the SiC semiconductor layer 2, there is an increased risk of cracks occurring in the SiC semiconductor layer 2. Therefore, by limiting the areas in which the reforming lines 22A to 22D are formed, as in the SiC semiconductor device 1, it is possible to suppress fluctuations in the electrical characteristics of the SiC semiconductor layer 2 and the occurrence of cracks.

[0208] Furthermore, according to the SiC semiconductor device 1, since the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is thinned, the SiC semiconductor wafer structure 61 can be appropriately cleaved by one layer of modification lines 70 (modification lines 22A to 22D).

[0209] In other words, the thinned SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can be properly cleaved without forming multiple modification lines 70 (modification lines 22A to 22D) at intervals in the normal direction Z.

[0210] In this case, the second main surface 4 of the SiC semiconductor layer 2 is a ground surface. The SiC semiconductor device 1 preferably includes a SiC semiconductor layer 2 having a thickness TL of 40 μm or more and 200 μm or less. The SiC semiconductor layer 2 having such a thickness TL can be appropriately cut out from the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).

[0211] In the SiC semiconductor layer 2, the thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. In the SiC semiconductor layer 2, the thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. Thinning the SiC semiconductor layer 2 is also effective in reducing the resistance value.

[0212] Furthermore, according to the SiC semiconductor device 1, the reforming lines 22A to 22D are formed at intervals from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. Stress tends to concentrate at the corners connecting the first main surface 3 of the SiC semiconductor layer 2 and the side surfaces 5A to 5D.

[0213] Therefore, by forming the reforming lines 22A to 22D at intervals from the corners connecting the first main surface 3 and the side surfaces 5A to 5D of the SiC semiconductor layer 2, the occurrence of cracks at the corners of the SiC semiconductor layer 2 can be appropriately suppressed.

[0214] In particular, according to the SiC semiconductor device 1, the reforming lines 22A to 22D are formed on the SiC semiconductor substrate 6, avoiding the SiC epitaxial layer 7. In other words, the reforming lines 22A to 22D expose the SiC epitaxial layer 7 on which the main portion of the semiconductor element (in this embodiment, the Schottky barrier diode D) is formed. This makes it possible to appropriately reduce the influence of the reforming lines 22A to 22D on the semiconductor element.

[0215] Furthermore, according to the SiC semiconductor device 1, the reforming lines 22A to 22D are formed at intervals from the second main surface 4 to the first main surface 3 of the SiC semiconductor layer 2. Stress tends to concentrate at the corners connecting the second main surface 4 of the SiC semiconductor layer 2 and the side surfaces 5A to 5D.

[0216] Therefore, by forming the reforming lines 22A to 22D at intervals from the corners connecting the second main surface 4 and the side surfaces 5A to 5D of the SiC semiconductor layer 2, the occurrence of cracks at the corners of the SiC semiconductor layer 2 can be appropriately suppressed.

[0217] The SiC semiconductor device 1 also includes a main surface insulating layer 10 and a first main surface electrode layer 12 formed on the first main surface 3 of the SiC semiconductor layer 2. The main surface insulating layer 10 has insulating side surfaces 11A-11D continuous with the side surfaces 5A-5D of the SiC semiconductor layer 2.

[0218] In a structure in which the reforming lines 22A to 22D are formed, the main surface insulating layer 10 improves the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12. This makes it possible to improve the stability of the electrical characteristics of the SiC semiconductor layer 2 in a structure in which the reforming lines 22A to 22D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0219] Fig. 12A is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a second embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0220] The reforming lines 22A to 22D according to the first embodiment are connected to each other at corners connecting the side surfaces 5A to 5D of the SiC semiconductor layer 2. In contrast, the reforming lines 22A to 22D according to the second embodiment are formed spaced apart from each other at corners connecting the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0221] More specifically, the reforming line 22A and the reforming line 22B are formed at intervals from each other in the normal direction Z at a corner connecting the side surface 5A and the side surface 5B of the SiC semiconductor layer 2. The reforming line 22B and the reforming line 22C are formed at intervals from each other in the normal direction Z at a corner connecting the side surface 5B and the side surface 5C of the SiC semiconductor layer 2.

[0222] The reforming line 22C and the reforming line 22D are formed at intervals from each other in the normal direction Z at a corner connecting the side surface 5C and the side surface 5D of the SiC semiconductor layer 2. The reforming line 22D and the reforming line 22A are formed at intervals from each other in the normal direction Z at a corner connecting the side surface 5D and the side surface 5A of the SiC semiconductor layer 2.

[0223] Of course, at least one of the reforming lines 22A to 22D may be formed spaced apart from the other reforming lines 22A to 22D at a corner connecting any of the side surfaces 5A to 5D of the SiC semiconductor layer 2. Two or three of the reforming lines 22A to 22D may be connected to each other at a corner connecting any of the side surfaces 5A to 5D of the SiC semiconductor layer 2.

[0224] The reforming lines 22A to 22D according to the second embodiment are formed by adjusting the focusing point (focus) of the laser light in the process of forming the reforming lines 70 (the reforming lines 22A to 22D) (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the second embodiment are formed, the same effects as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

[0225] Fig. 12B is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a third embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0226] The reforming lines 22A to 22D according to the first embodiment are formed in strip shapes extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the reforming lines 22A to 22D according to the third embodiment are formed in strip shapes extending in a downwardly sloping manner from the first main surface 3 toward the second main surface 4 of the SiC semiconductor layer 2. More specifically, the reforming lines 22A to 22D according to the third embodiment each include a first end region 81, a second end region 82, and an inclined region 83.

[0227] The first end region 81 is located on the first main surface 3 side of the SiC semiconductor layer 2 near a corner of the SiC semiconductor layer 2. The second end region 82 is located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the first end region 81 near the corner of the SiC semiconductor layer 2. The inclined region 83 slopes downward from the first main surface 3 toward the second main surface 4 in the region between the first end region 81 and the second end region 82.

[0228] A first end region 81 of the reforming line 22A and a first end region 81 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. A second end region 82 of the reforming line 22A and a second end region 82 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2.

[0229] A first end region 81 of the reforming line 22A and a second end region 82 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. A second end region 82 of the reforming line 22A and a first end region 81 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2.

[0230] The reforming line 22A and the reforming line 22B may be connected to each other at a corner portion connecting the side surface 5A and the side surface 5B of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0231] A first end region 81 of the reforming line 22B and a first end region 81 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2. A second end region 82 of the reforming line 22B and a second end region 82 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

[0232] A first end region 81 of the reforming line 22B and a second end region 82 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2. A second end region 82 of the reforming line 22B and a first end region 81 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

[0233] The reforming line 22B and the reforming line 22C may be connected to each other at a corner portion connecting the side surface 5B and the side surface 5C of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0234] A first end region 81 of the reforming line 22C and a first end region 81 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. A second end region 82 of the reforming line 22C and a second end region 82 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2.

[0235] A first end region 81 of the reforming line 22C and a second end region 82 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. A second end region 82 of the reforming line 22C and a first end region 81 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2.

[0236] The reforming line 22C and the reforming line 22D may be connected to each other at a corner portion connecting the side surface 5C and the side surface 5D of the SiC semiconductor layer 2, or may be formed with a gap between them.

[0237] A first end region 81 of the reforming line 22D and a first end region 81 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2. A second end region 82 of the reforming line 22D and a second end region 82 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.

[0238] A first end region 81 of the reforming line 22D and a second end region 82 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2. A second end region 82 of the reforming line 22D and a first end region 81 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.

[0239] The reforming line 22D and the reforming line 22A may be connected to each other at a corner portion connecting the side surface 5D and the side surface 5A of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0240] The reforming lines 22A to 22D according to the third embodiment are formed by adjusting the focusing point (focus) of the laser light in the process of forming the reforming lines 70 (the reforming lines 22A to 22D) (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the third embodiment are formed, the same effects as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

[0241] In particular, according to the modification lines 22A to 22D of the third embodiment, cleavage origins can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be appropriately cleaved even when the modification lines 22A to 22D made of a single layer are formed.

[0242] Fig. 12C is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a fourth embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0243] The reforming lines 22A to 22D according to the first embodiment are formed in strip shapes extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the reforming lines 22A to 22D according to the fourth embodiment are formed in strip shapes extending in a curved (curved) manner and sloping downward from the first main surface 3 toward the second main surface 4 of the SiC semiconductor layer 2. More specifically, the reforming lines 22A to 22D according to the fourth embodiment each include a first end region 84, a second end region 85, and a curved region 86.

[0244] The first end region 84 is located on the first main surface 3 side of the SiC semiconductor layer 2 near a corner of the SiC semiconductor layer 2. The second end region 85 is located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the first end region 84 near the corner of the SiC semiconductor layer 2.

[0245] The curved region 86 slopes downward in a concave curve from the first main surface 3 toward the second main surface 4, and connects the first end region 84 and the second end region 85. The curved region 86 may also slope downward in a convex curve from the second main surface 4 toward the first main surface 3.

[0246] A first end region 84 of the reforming line 22A and a first end region 84 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. A second end region 85 of the reforming line 22A and a second end region 85 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2.

[0247] A first end region 84 of the reforming line 22A and a second end region 85 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. A second end region 85 of the reforming line 22A and a first end region 84 of the reforming line 22B may be located at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2.

[0248] The reforming line 22A and the reforming line 22B may be connected to each other at a corner portion connecting the side surface 5A and the side surface 5B of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0249] A first end region 84 of the reforming line 22B and a first end region 84 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2. A second end region 85 of the reforming line 22B and a second end region 85 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

[0250] A first end region 84 of the reforming line 22B and a second end region 85 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2. A second end region 85 of the reforming line 22B and a first end region 84 of the reforming line 22C may be located at a corner connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.

[0251] The reforming line 22B and the reforming line 22C may be connected to each other at a corner portion connecting the side surface 5B and the side surface 5C of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0252] A first end region 84 of the reforming line 22C and a first end region 84 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. A second end region 85 of the reforming line 22C and a second end region 85 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2.

[0253] A first end region 84 of the reforming line 22C and a second end region 85 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. A second end region 85 of the reforming line 22C and a first end region 84 of the reforming line 22D may be located at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2.

[0254] The reforming line 22C and the reforming line 22D may be connected to each other at a corner portion connecting the side surface 5C and the side surface 5D of the SiC semiconductor layer 2, or may be formed with a gap between them.

[0255] A first end region 84 of the reforming line 22D and a first end region 84 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2. A second end region 85 of the reforming line 22D and a second end region 85 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.

[0256] A first end region 84 of the reforming line 22D and a second end region 85 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2. A second end region 85 of the reforming line 22D and a first end region 84 of the reforming line 22A may be located at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.

[0257] The reforming line 22D and the reforming line 22A may be connected to each other at a corner portion connecting the side surface 5D and the side surface 5A of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0258] The reforming lines 22A to 22D according to the fourth embodiment are formed by adjusting the focusing point (focus) of the laser light in the process of forming the reforming lines 70 (the reforming lines 22A to 22D) (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the fourth embodiment are formed, the same effects as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

[0259] In particular, according to the modification lines 22A to 22D of the fourth embodiment, cleavage origins can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be appropriately cleaved even when the modification lines 22A to 22D made of a single layer are formed.

[0260] Fig. 12D is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a fifth embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0261] The reforming lines 22A to 22D according to the first embodiment are formed in strip shapes extending linearly along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. In contrast, the reforming lines 22A to 22D according to the fifth embodiment are formed in strip shapes extending in a meandering curved (curved) manner toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. More specifically, the reforming lines 22A to 22D according to the fifth embodiment each include a plurality of first regions 87, a plurality of second regions 88, and a plurality of connection regions 89.

[0262] The plurality of first regions 87 are located in a region on the first main surface 3 side of the SiC semiconductor layer 2. The plurality of second regions 88 are located in a region on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the plurality of first regions 87. The plurality of curved regions 86 connect the corresponding first regions 87 and second regions 88, respectively.

[0263] The reforming line 22A and the reforming line 22B may be connected to each other at a corner portion connecting the side surface 5A and the side surface 5B of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0264] The reforming line 22B and the reforming line 22C may be connected to each other at a corner portion connecting the side surface 5B and the side surface 5C of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0265] The reforming line 22C and the reforming line 22D may be connected to each other at a corner portion connecting the side surface 5C and the side surface 5D of the SiC semiconductor layer 2, or may be formed with a gap between them.

[0266] The reforming line 22D and the reforming line 22A may be connected to each other at a corner portion connecting the side surface 5D and the side surface 5A of the SiC semiconductor layer 2, or may be formed with an interval between them.

[0267] The meandering period of the reforming lines 22A to 22D is arbitrary. The reforming lines 22A to 22D may each be formed in a band shape extending in a concave curve from the first main surface 3 toward the second main surface 4. In this case, the reforming lines 22A to 22D may each include two first regions 87, one second region 88, and two connection regions 89.

[0268] Furthermore, the reforming lines 22A to 22D may each be formed in a strip shape extending in a convex curve from the second main surface 4 toward the first main surface 3. In this case, the reforming lines 22A to 22D may each include one first region 87, two second regions 88, and two connection regions 89.

[0269] The reforming lines 22A to 22D according to the fifth embodiment are formed by adjusting the focusing point (focus) of the laser light in the process of forming the reforming lines 70 (the reforming lines 22A to 22D) (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the fifth embodiment are formed, the same effects as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

[0270] In particular, according to the modification lines 22A to 22D of the fifth embodiment, cleavage origins can be formed in different regions in the thickness direction of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41). This allows the SiC semiconductor wafer structure 61 to be appropriately cleaved even when the modification lines 22A to 22D made of a single layer are formed.

[0271] Fig. 12E is a perspective view showing the SiC semiconductor device 1 shown in Fig. 3, and is a perspective view showing a sixth embodiment of the reforming lines 22A to 22D. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0272] The reforming lines 22A to 22D according to the first embodiment are formed in a shape equal to the side surfaces 5A to 5D of the SiC semiconductor layer 2. In contrast, the reforming lines 22A to 22D according to the sixth embodiment are formed with different exclusive ratios RA, RB, RC, and RD on the side surfaces 5A to 5D of the SiC semiconductor layer 2. The exclusive ratios RA to RD are the ratios that the reforming lines 22A to 22D occupy of the side surfaces 5A to 5D.

[0273] More specifically, the exclusive ratios RA to RD differ depending on the crystal plane of the SiC single crystal. The exclusive ratios RB and RD of the reforming lines 22B and 22D formed on the m-plane of the SiC single crystal are equal to or less than the exclusive ratios RA and RC of the reforming lines 22A and 22C formed on the a-plane of the SiC single crystal (RB, RD≦RA, RC). More specifically, the exclusive ratios RB and RD are less than the exclusive ratios RA and RC (RB, RD <RA,RC)である。

[0274] The exclusive ratios RA and RC of the reforming lines 22A and 22C may be equal to or different from each other, and the exclusive ratios RB and RD of the reforming lines 22B and 22D may be equal to or different from each other.

[0275] In this embodiment, the surface areas of the reforming lines 22B and 22D relative to the sides 5B and 5D are less than the surface areas of the reforming lines 22A and 22C relative to the sides 5A and 5C, respectively. In this embodiment, the thicknesses TR of the reforming lines 22B and 22D are less than the thicknesses TR of the reforming lines 22A and 22C, respectively.

[0276] The reforming lines 22A to 22D according to the sixth embodiment are formed by adjusting the focusing point (focus) of the laser light in the process of forming the reforming line 70 (see also FIG. 10K). Even when the reforming lines 22A to 22D according to the sixth embodiment are formed, the same effects as when the reforming lines 22A to 22D according to the first embodiment are formed can be achieved.

[0277] In particular, the reforming lines 22A to 22D according to the sixth embodiment are formed with different exclusive ratios RA to RD on the side surfaces 5A to 5D of the SiC semiconductor layer 2. More specifically, the reforming lines 22A to 22D have different exclusive ratios RA to RD depending on the crystal planes of the SiC single crystal.

[0278] The exclusive ratios RB, RD of the reforming lines 22B, 22D formed on the m-plane of the SiC single crystal are equal to or less than the exclusive ratios RA, RC of the reforming lines 22A, 22C formed on the a-plane of the SiC single crystal (RB, RD≦RA, RC).

[0279] SiC single crystals have the physical property that they easily crack along the nearest atomic direction (see also Figures 1 and 2) when viewed from the c-axis on the c-plane (silicon plane), but are difficult to crack along directions intersecting the nearest atomic direction. The nearest atomic direction is the a-axis direction and its equivalent direction. The directions intersecting the nearest atomic direction are the m-axis direction and its equivalent direction.

[0280] Therefore, in the process of forming the reforming lines 70, the crystal planes along the nearest neighbor atomic direction of the SiC single crystal have a relatively easy tendency to break, so the SiC single crystal can be appropriately cut (cleaved) without forming reforming lines 70 with a relatively large exclusive ratio (see also FIG. 10L). The crystal planes along the nearest neighbor atomic direction are the m-plane and its equivalent planes.

[0281] In other words, in the process of forming the modified lines 70, the occupancy ratio of the modified lines 70 along the second lines to cut 55 extending in the a-axis direction can be made smaller than the occupancy ratio of the modified lines 70 along the first lines to cut 54 extending in the m-axis direction.

[0282] On the other hand, a modification line 70 having a relatively large proportion of monopoly is formed on the crystal plane of the SiC single crystal along the direction intersecting the nearest neighbor atomic direction. This makes it possible to suppress inappropriate cutting (cleavage) of the SiC semiconductor wafer structure 61, thereby appropriately suppressing the occurrence of cracks due to the physical properties of the SiC single crystal. The crystal plane along the direction intersecting the nearest neighbor atomic direction is the a-plane and its equivalent planes.

[0283] As described above, according to the reforming lines 22A to 22D of the sixth embodiment, the physical properties of the SiC single crystal can be utilized to adjust and reduce the occupation ratios RA to RD of the reforming lines 22A to 22D relative to the side surfaces 5A to 5D. This can further reduce the influence of the reforming lines 22A to 22D on the SiC semiconductor layer 2. Furthermore, the time required for the process of forming the reforming lines 70 can be shortened.

[0284] The exclusive use ratios RA to RD may be adjusted by the surface area of ​​the reforming lines 22A to 22D relative to the side surfaces 5A to 5D. The exclusive use ratios RA to RD may be adjusted by the thickness TR of the reforming lines 22A to 22D. The exclusive use ratios RA to RD may be adjusted by the number of the reforming lines 22A to 22D.

[0285] A SiC semiconductor device 1 may be formed that simultaneously includes at least two of the modification lines 22A to 22D according to the first, second, third, fourth, fifth and sixth embodiment examples (hereinafter simply referred to as "first to sixth embodiment examples").

[0286] In addition, the features of the reforming lines 22A to 22D according to the first to sixth embodiments can be combined in any manner and in any form. That is, the reforming lines 22A to 22D may have a form in which at least two of the features of the reforming lines 22A to 22D according to the first to sixth embodiments are combined.

[0287] For example, the features of the reforming lines 22A to 22D according to the third embodiment may be combined with the features of the reforming lines 22A to 22D according to the fifth embodiment. In this case, the band-shaped reforming lines 22A to 22D are formed, sloping downward from the first main surface 3 toward the second main surface 4 of the SiC semiconductor layer 2 and extending in a meandering curved (bent) shape toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2.

[0288] 13 is a perspective view showing a SiC semiconductor device 91 according to the second embodiment of the present disclosure, and showing a structure to which the reforming lines 22A to 22D according to the first embodiment are applied. In the following, structures corresponding to those described with respect to the SiC semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0289] In this embodiment, the reforming lines 22A to 22D according to the first embodiment are applied. However, instead of or in addition to the reforming lines 22A to 22D according to the first embodiment, the reforming lines 22A to 22D according to the second, third, fourth, fifth, or sixth embodiment may be adopted. Furthermore, the reforming lines 22A to 22D may have a configuration in which at least two of the features of the reforming lines 22A to 22D according to the first to sixth embodiments are combined.

[0290] 13, in this embodiment, insulating side surfaces 11A-11D of main surface insulating layer 10 are formed inwardly from side surfaces 5A-5D of SiC semiconductor layer 2 in a plan view with a gap therebetween. Main surface insulating layer 10 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2 in a plan view.

[0291] Main surface insulating layer 10, together with resin layer 16 and passivation layer 13, exposes the peripheral edge of first main surface 3 of SiC semiconductor layer 2. In this embodiment, insulating side surfaces 11A-11D of main surface insulating layer 10 are formed flush with resin side surfaces 17A-17D of resin layer 16 and side surfaces 14A-14D of passivation layer 13. In this embodiment, insulating side surfaces 11A-11D of main surface insulating layer 10 also form parts that define dicing streets.

[0292] This main surface insulating layer 10 is formed by carrying out a step of removing the main surface insulating layer 10 by etching after the step of removing the passivation layer 13 in the step of FIG. 10I described above.

[0293] In this case, in the step of FIG. 10K, the inside of the SiC semiconductor wafer structure 61 may be directly irradiated with laser light from the first main surface 62 side of the SiC semiconductor wafer structure 61 without going through the main surface insulating layer 10.

[0294] As described above, the SiC semiconductor device 91 can also achieve the same effects as those described for the SiC semiconductor device 1. However, in terms of improving the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first principal surface electrode layer 12, the structure of the SiC semiconductor device 1 according to the first embodiment is preferable.

[0295] Fig. 14 is a perspective view of the SiC semiconductor device 101 according to the third embodiment of the present disclosure, seen from one angle, illustrating a structure to which the reforming lines 22A to 22D according to the first embodiment are applied. Fig. 15 is a perspective view of the SiC semiconductor device 101 shown in Fig. 14, seen from another angle. Fig. 16 is a plan view of the SiC semiconductor device 101 shown in Fig. 14. Fig. 17 is a plan view of Fig. 16 with the resin layer 129 removed.

[0296] In this embodiment, the reforming lines 22A to 22D according to the first embodiment are applied. That is, in the manufacturing process of the SiC semiconductor device 101, steps similar to those shown in the above-described Figures 10A to 10M are applied.

[0297] In the SiC semiconductor device 101, the reforming lines 22A to 22D according to the second, third, fourth, fifth, or sixth embodiment may be employed instead of or in addition to the reforming lines 22A to 22D according to the first embodiment. Also, the reforming lines 22A to 22D may have a configuration that combines at least two of the features of the reforming lines 22A to 22D according to the first to sixth embodiments.

[0298] 14 to 17, SiC semiconductor device 101 includes a SiC semiconductor layer 102. SiC semiconductor layer 102 includes a 4H—SiC single crystal as an example of a SiC single crystal made of a hexagonal system. SiC semiconductor layer 102 (SiC semiconductor chip) is formed in the shape of a rectangular parallelepiped chip.

[0299] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0300] The first main surface 103 is an element formation surface on which a semiconductor element is formed. The second main surface 104 of the SiC semiconductor layer 102 is a ground surface having grinding marks. The side surfaces 105A to 105D are each a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 105A to 105D do not have grinding marks.

[0301] The thickness TL of the SiC semiconductor layer 102 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

[0302] In this embodiment, the first main surface 103 and the second main surface 104 face the c-plane of the SiC single crystal. The first main surface 103 faces the (0001) plane (silicon plane). The second main surface 104 faces the (000-1) plane (carbon plane) of the SiC single crystal.

[0303] The first main surface 103 and the second main surface 104 have an off angle θ of 10° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off angle θ with respect to the c-axis (0001) direction of the SiC single crystal.

[0304] The off angle θ may be 0° or more and 5.0° or less. The off angle θ may be set in the range of 0° or more and 1.0° or less, 1.0° or more and 1.5° or less, 1.5° or more and 2.0° or less, 2.0° or more and 2.5° or less, 2.5° or more and 3.0° or less, 3.0° or more and 3.5° or less, 3.5° or more and 4.0° or less, 4.0° or more and 4.5° or less, or 4.5° or more and 5.0° or less. The off angle θ is preferably greater than 0°. The off angle θ may be less than 4.0°.

[0305] The off angle θ may be set in the range of 3.0° to 4.5°, inclusive. In this case, the off angle θ is preferably set in the range of 3.0° to 3.5°, or 3.5° to 4.0°, inclusive.

[0306] The off angle θ may be set in the range of 1.5° to 3.0°, inclusive. In this case, the off angle θ is preferably set in the range of 1.5° to 2.0°, or 2.0° to 2.5°, inclusive.

[0307] The length of each of the side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). In this embodiment, the surface area of ​​the side surfaces 105B and 105D exceeds the surface area of ​​the side surfaces 105A and 105C. The first main surface 103 and the second main surface 104 may be formed in a square shape in a plan view. In this case, the surface area of ​​the side surfaces 105B and 105D is equal to that of the side surfaces 105B and 105C.

[0308] In this embodiment, side surface 105A and side surface 105C extend along a first direction X and face each other in a second direction Y that intersects with first direction X. In this embodiment, side surface 105B and side surface 105D extend along the second direction Y and face each other in first direction X. More specifically, second direction Y is a direction perpendicular to first direction X.

[0309] In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is set to the a-axis direction ([11-20] direction) of the SiC single crystal.

[0310] Side surface 105A and side surface 105C form the short sides of SiC semiconductor layer 102 in plan view. Side surface 105A and side surface 105C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. Side surface 105A is formed by the (-1-120) plane of the SiC single crystal. Side surface 105C is formed by the (11-20) plane of the SiC single crystal.

[0311] Side surface 105B and side surface 105D form the long sides of SiC semiconductor layer 102 in plan view. Side surface 105B and side surface 105D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. Side surface 105B is formed by the (-1100) plane of the SiC single crystal. Side surface 105D is formed by the (1-100) plane of the SiC single crystal.

[0312] Side 105A and side 105C may form an inclined surface that is inclined toward the c-axis direction (0001 direction) of the SiC single crystal with respect to the normal to first main surface 103 of SiC semiconductor layer 102, when the normal is used as a reference.

[0313] In this case, when the normal to first main surface 103 of SiC semiconductor layer 102 is defined as 0°, side surface 105A and side surface 105C may be inclined at an angle corresponding to off angle θ with respect to the normal to first main surface 103 of SiC semiconductor layer 102. The angle corresponding to off angle θ may be equal to off angle θ or may be an angle greater than 0° and less than off angle θ.

[0314] In this embodiment, the SiC semiconductor layer 102 is + The SiC semiconductor layer 102 has a layered structure including an n-type SiC semiconductor substrate 106 (second impurity region) and an n-type SiC epitaxial layer 107 (first impurity region). The SiC semiconductor substrate 106 and the SiC epitaxial layer 107 correspond to the SiC semiconductor substrate 6 and the SiC epitaxial layer 7, respectively, according to the first embodiment. The SiC semiconductor substrate 106 forms the second main surface 104 of the SiC semiconductor layer 102.

[0315] The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 107. The SiC semiconductor substrate 106 and the SiC epitaxial layer 107 form side surfaces 105A to 105D of the SiC semiconductor layer 102.

[0316] The thickness TS of the SiC semiconductor substrate 106 may be 40 μm or more and 150 μm or less. The thickness TS may be 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. Thinning the SiC semiconductor substrate 106 can shorten the current path and reduce the resistance value.

[0317] The thickness TE of the SiC epitaxial layer 107 may be 1 μm or more and 50 μm or less. The thickness TE may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

[0318] The n-type impurity concentration of the SiC epitaxial layer 107 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 106. More specifically, the n-type impurity concentration of the SiC epitaxial layer 107 is lower than the n-type impurity concentration of the SiC semiconductor substrate 106. The n-type impurity concentration of the SiC semiconductor substrate 106 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 107 may be 1.0×10 or less. 15 cm -3 Over 1.0 x 10 18 cm -3 It may be the following:

[0319] In this embodiment, the SiC epitaxial layer 107 has a plurality of regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 107 includes a high-concentration region 108 having a relatively high n-type impurity concentration, and a low-concentration region 109 having a lower n-type impurity concentration than the high-concentration region 108.

[0320] The high concentration region 108 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102. The low concentration region 109 is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the high concentration region 108.

[0321] The n-type impurity concentration of the high concentration region 108 is 1×10 16 cm -3 More than 1×10 18 cm -3 The n-type impurity concentration of the low concentration region 109 may be 1×10 15 cm -3 More than 1×10 16 cm -3 It may be the following:

[0322] The thickness of the high concentration region 108 is equal to or less than the thickness of the low concentration region 109. More specifically, the thickness of the high concentration region 108 is less than the thickness of the low concentration region 109. The thickness of the high concentration region 108 is less than half the total thickness of the SiC epitaxial layer 107.

[0323] The SiC semiconductor layer 102 has an active region 111 and an outer region 112. The active region 111 is a region in which a vertical MISFET (Metal Insulator Field Effect Transistor) as an example of a semiconductor element is formed. The outer region 112 is a region outside the active region 111.

[0324] In plan view, the active region 111 is set in the center of the SiC semiconductor layer 102, spaced apart from the side surfaces 105A-105D of the SiC semiconductor layer 102. In plan view, the active region 111 is set in a quadrangular shape (rectangular in this embodiment) having four sides parallel to the side surfaces 105A-105D of the SiC semiconductor layer 102.

[0325] The outer region 112 is set in a region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 111. The outer region 112 is set in an endless shape (a quadrangular ring in this embodiment) surrounding the active region 111 in a plan view.

[0326] A main surface insulating layer 113 is formed on the first main surface 103 of the SiC semiconductor layer 102. The main surface insulating layer 113 selectively covers the active region 111 and the outer region 112. The main surface insulating layer 113 may contain silicon oxide (SiO2).

[0327] The main surface insulating layer 113 has insulating side surfaces 114A, 114B, 114C, and 114D exposed from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The insulating side surfaces 114A to 114D are continuous with the side surfaces 105A to 105D. The insulating side surfaces 114A to 114D are formed flush with the side surfaces 105A to 105D, respectively. The insulating side surfaces 114A to 114D are made of cleavage planes.

[0328] The thickness of the main surface insulating layer 113 may be 1 μm or more and 50 μm or less, 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0329] A main surface gate electrode layer 115, which serves as one of the first main surface electrode layers, is formed on the main surface insulating layer 113. The main surface gate electrode layer 115 penetrates the main surface insulating layer 113 and is electrically connected to an arbitrary region of the SiC semiconductor layer 102.

[0330] The main surface gate electrode layer 115 includes a gate pad 116 and gate fingers 117 and 118. The gate pad 116 and the gate fingers 117 and 118 are disposed in the active region 111.

[0331] The gate pad 116 is formed, in a plan view, along the side surface 105A of the SiC semiconductor layer 102. The gate pad 116 is formed, in a plan view, along the central region of the side surface 105A of the SiC semiconductor layer 102.

[0332] The gate pad 116 may be formed, in plan view, along a corner connecting any two of the side surfaces 105A to 105D of the SiC semiconductor layer 102. The gate pad 116 may be formed in a quadrangular shape in plan view.

[0333] The gate fingers 117, 118 include an outer gate finger 117 and an inner gate finger 118. The outer gate finger 117 is drawn out from the gate pad 116 and extends in a strip shape along the periphery of the active region 111.

[0334] In this embodiment, the outer gate fingers 117 are formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

[0335] The outer gate finger 117 has a pair of open ends 119, 120. The pair of open ends 119, 120 are formed in a region facing the gate pad 116 with an inner region of the active region 111 in between. In this embodiment, the pair of open ends 119, 120 are formed along the side surface 105C of the SiC semiconductor layer 102.

[0336] The inner gate finger 118 extends from the gate pad 116 to an inner region of the active region 111. The inner gate finger 118 extends in a strip shape in the inner region of the active region 111. The inner gate finger 118 extends from the gate pad 116 toward the side surface 105C.

[0337] A main surface source electrode layer 121, which serves as one of the first main surface electrode layers, is further formed on the main surface insulating layer 113. The main surface source electrode layer 121 penetrates the main surface insulating layer 113 and is electrically connected to an arbitrary region of the SiC semiconductor layer 102. In this embodiment, the main surface source electrode layer 121 includes a source pad 122, a source lead-out wiring 123, and a source connection portion 124.

[0338] The source pad 122 is formed in the active region 111 at a distance from the gate pad 116 and the gate fingers 117 and 118. The source pad 122 is formed in a C-shape (an inverted C-shape in FIGS. 16 and 17) in plan view so as to cover the C-shaped region (an inverted C-shape in FIGS. 16 and 17) defined by the gate pad 116 and the gate fingers 117 and 118.

[0339] The source lead-out wiring 123 is formed in the outer region 112. The source lead-out wiring 123 extends in a strip shape along the active region 111. In this embodiment, the source lead-out wiring 123 is formed in an endless shape (a quadrangular ring shape in this embodiment) surrounding the active region 111 in a plan view. The source lead-out wiring 123 is electrically connected to the SiC semiconductor layer 102 in the outer region 112.

[0340] The source connection portion 124 connects the source pad 122 and the source lead-out line 123. The source connection portion 124 is provided in a region between a pair of open ends 119, 120 of the outer gate finger 117. The source connection portion 124 extends from the source pad 122 across the boundary region between the active region 111 and the outer region 112, and is connected to the source lead-out line 123.

[0341] The MISFET formed in the active region 111 structurally includes an npn-type parasitic bipolar transistor. When an avalanche current generated in the outer region 112 flows into the active region 111, the parasitic bipolar transistor turns on. In this case, there is a possibility that the control of the MISFET becomes unstable due to, for example, latch-up.

[0342] Therefore, in the SiC semiconductor device 101, the structure of the main surface source electrode layer 121 is utilized to form an avalanche current absorption structure that absorbs the avalanche current generated in the outer region 112.

[0343] More specifically, the avalanche current generated in the outer region 112 is absorbed by the source routing wiring 123 and reaches the source pad 122 via the source connection part 124. If a conductor for external connection (e.g., a bonding wire) is connected to the source pad 122, the avalanche current is extracted by this conductor.

[0344] This makes it possible to prevent the parasitic bipolar transistor from turning on due to an undesired current generated in the outer region 112. This makes it possible to prevent latch-up, thereby improving the stability of control of the MISFET.

[0345] A gate voltage is applied to the main surface gate electrode layer 115. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the main surface source electrode layer 121. The source voltage may be a reference voltage (for example, a GND voltage).

[0346] A passivation layer 125 (insulating layer) is formed on the main surface insulating layer 113. The passivation layer 125 may have a single layer structure made of a silicon oxide layer or a silicon nitride layer.

[0347] The passivation layer 125 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this form, the passivation layer 125 has a single-layer structure consisting of a silicon nitride layer.

[0348] In a plan view, side surfaces 126A, 126B, 126C, and 126D of the passivation layer 125 are formed at intervals inward from the side surfaces 105A to 105D of the SiC semiconductor layer 102. In a plan view, the passivation layer 125 exposes the peripheral edge of the SiC semiconductor layer 102. The passivation layer 125 exposes the main surface insulating layer 113.

[0349] The passivation layer 125 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. A gate subpad opening 127 and a source subpad opening 128 are formed in the passivation layer 125. The gate subpad opening 127 exposes the gate pad 116. The source subpad opening 128 exposes the source pad 122.

[0350] The thickness of the passivation layer 125 may be 1 μm or more and 50 μm or less, 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0351] A resin layer 129 (insulating layer) is formed on the passivation layer 125. The passivation layer 125 and the resin layer 129 form a single insulating laminated structure (insulating layer). In Figure 16, the resin layer 129 is indicated by hatching.

[0352] The resin layer 129 may contain a negative or positive photosensitive resin. In this embodiment, the resin layer 129 contains polybenzoxazole, which is an example of a positive photosensitive resin. The resin layer 129 may also contain polyimide, which is an example of a negative photosensitive resin.

[0353] The resin layer 129 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. Resin side surfaces 130A, 130B, 130C, and 130D of the resin layer 129 are formed at intervals inward from the side surfaces 105A to 105D of the SiC semiconductor layer 102. The resin layer 129 exposes the main surface insulating layer 113 together with the passivation layer 125. In this embodiment, the resin side surfaces 130A to 130D of the resin layer 129 are formed flush with the side surfaces 126A to 126D of the passivation layer 125.

[0354] Resin side surfaces 130A-130D of resin layer 129 are portions that define dicing streets when cutting out SiC semiconductor devices 101 from a single SiC semiconductor wafer. In this embodiment, side surfaces 126A-126D of passivation layer 125 are also portions that define dicing streets.

[0355] By exposing the peripheral edge of the SiC semiconductor layer 102 from the resin layer 129 and the passivation layer 125, it is not necessary to physically cut the resin layer 129 and the passivation layer 125. This makes it possible to smoothly cut out the SiC semiconductor device 101 from one SiC semiconductor wafer. In addition, the insulation distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 can be increased.

[0356] The distance between the side surfaces 105A-105D and the resin side surfaces 130A-130D (side surfaces 126A-126D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 105A-105D and the resin side surfaces 130A-130D (side surfaces 126A-126D) may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less. Of course, the side surfaces 126A-126D of the passivation layer 125 may be formed flush with the side surfaces 105A-105D of the SiC semiconductor layer 102.

[0357] A gate pad opening 131 and a source pad opening 132 are formed in the resin layer 129. The gate pad opening 131 exposes the gate pad 116. The source pad opening 132 exposes the source pad 122.

[0358] The gate pad opening 131 in the resin layer 129 communicates with the gate subpad opening 127 in the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the gate subpad opening 127. The inner wall of the gate pad opening 131 may be located inside the inner wall of the gate subpad opening 127. The resin layer 129 may cover the inner wall of the gate subpad opening 127.

[0359] The source pad opening 132 in the resin layer 129 communicates with the source subpad opening 128 in the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the source subpad opening 128. The inner wall of the source pad opening 132 may be located inside the inner wall of the source subpad opening 128. The resin layer 129 may cover the inner wall of the source subpad opening 128.

[0360] The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less, 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.

[0361] A drain electrode layer 133 serving as a second principal surface electrode layer is connected to the second principal surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between the principal surface source electrode layer 121 and the drain electrode layer 133 in the off state may be 1000 V or more and 10000 V or less.

[0362] The drain electrode layer 133 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer, or may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer.

[0363] The drain electrode layer 133 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner, or may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in this order from the second main surface 104 of the SiC semiconductor layer 102.

[0364] The SiC semiconductor substrate 106 is formed as a drain region 134 (second impurity region) of the MISFET. The SiC epitaxial layer 107 is formed as a drift region 135 (first impurity region) of the MISFET.

[0365] A plurality of reforming lines 22A to 22D according to the first embodiment are formed on the side surfaces 105A to 105D of the SiC semiconductor layer 102. The structure of the reforming lines 22A to 22D according to the third embodiment is similar to the structure of the reforming lines 22A to 22D according to the first embodiment, except that they are formed on the SiC semiconductor layer 102 instead of the SiC semiconductor layer 2.

[0366] The description of the reforming lines 22A to 22D according to the first embodiment shall apply mutatis mutandis to the description of the reforming lines 22A to 22D according to the third embodiment, respectively, and a specific description of the reforming lines 22A to 22D according to the third embodiment will be omitted.

[0367] Fig. 18 is an enlarged view of region XVIII shown in Fig. 17 and is a diagram for explaining the structure of first main surface 103 of SiC semiconductor layer 102. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 18. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 18. Fig. 21 is an enlarged view of region XXI shown in Fig. 19. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 17. Fig. 23 is an enlarged view of region XXIII shown in Fig. 22.

[0368] 18 to 22, a p-type body region 141 is formed in a surface layer portion of first main surface 103 of SiC semiconductor layer 102 in active region 111. Body region 141 defines active region 111.

[0369] In this embodiment, the body region 141 is formed over the entire region in which the active region 111 is formed on the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the body region 141 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0370] In the active region 111, a plurality of gate trenches 142 are formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 142 are each formed in a strip shape extending along a first direction X (the m-axis direction of the SiC single crystal) in a plan view, and are formed at intervals along a second direction Y (the a-axis direction of the SiC single crystal).

[0371] In this embodiment, each gate trench 142 extends from the peripheral edge on one side (side surface 105B side) to the peripheral edge on the other side (side surface 105D side) in the active region 111. The plurality of gate trenches 142 are formed in a striped pattern as a whole in a plan view.

[0372] Each gate trench 142 crosses the middle portion between one peripheral edge and the other peripheral edge of the active region 111. One end of each gate trench 142 is located at one peripheral edge of the active region 111. The other end of each gate trench 142 is located at the other peripheral edge of the active region 111.

[0373] The length of each gate trench 142 may be 0.5 mm or more. The length of each gate trench 142 is the length from the end of the connection portion between each gate trench 142 and outer gate finger 117 to the opposite end in the cross section shown in FIG.

[0374] In this embodiment, the length of each gate trench 142 is 1 mm or more and 10 mm or less (e.g., 2 mm or more and 5 mm or less). The total extension of the one or more gate trenches 142 per unit area may be 0.5 μm / μm or more and 0.75 μm / μm or less.

[0375] Each gate trench 142 integrally includes an active trench portion 143 and a contact trench portion 144. The active trench portion 143 is a portion of the active region 111 that is along the channel of the MISFET.

[0376] The contact trench portion 144 is a portion of the gate trench 142 that is primarily intended to make contact with the outer gate finger 117. The contact trench portion 144 is drawn out from the active trench portion 143 to the periphery of the active region 111. The contact trench portion 144 is formed in a region directly below the outer gate finger 117. The amount of drawing of the contact trench portion 144 is optional.

[0377] Each gate trench 142 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each gate trench 142 includes a sidewall and a bottom wall. The sidewalls forming the long sides of each gate trench 142 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each gate trench 142 are formed by the m-plane of the SiC single crystal.

[0378] The sidewalls of each gate trench 142 may extend along the normal direction Z. The sidewalls of each gate trench 142 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

[0379] The angle formed by the sidewall of each gate trench 142 in the SiC semiconductor layer 102 with respect to the first main surface 103 of the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each gate trench 142 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

[0380] The bottom wall of each gate trench 142 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each gate trench 142 is located in the high concentration region 108 of the SiC epitaxial layer 107.

[0381] The bottom wall of each gate trench 142 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 142 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0382] The bottom wall of each gate trench 142 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each gate trench 142 may be formed in a convex curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

[0383] In the normal direction Z, the depth of each gate trench 142 may be 0.5 μm or more and 3.0 μm or less. The depth of each gate trench 142 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, or 2.5 μm or more and 3.0 μm or less.

[0384] The width of each gate trench 142 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 142 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0385] 21 , opening edge portion 146 of each gate trench 142 includes an inclined portion 147 that slopes downward from first main surface 103 of SiC semiconductor layer 102 toward the inside of each gate trench 142. Opening edge portion 146 of each gate trench 142 is a corner that connects first main surface 103 of SiC semiconductor layer 102 and the sidewall of each gate trench 142.

[0386] In this embodiment, the inclined portions 147 are formed in a concave curved shape directed inwardly of the SiC semiconductor layer 102. The inclined portions 147 may be formed in a convex curved shape directed inwardly of each gate trench 142. The inclined portions 147 reduce electric field concentration at the opening edge portions 146 of each gate trench 142.

[0387] A gate insulating layer 148 and a gate electrode layer 149 are formed in each gate trench 142. In Fig. 18, the gate insulating layer 148 and the gate electrode layer 149 are indicated by hatching.

[0388] The gate insulating layer 148 includes at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), and tantalum oxide (Ta 2 O 3 ).

[0389] The gate insulating layer 148 may have a layered structure including a SiN layer and a SiO layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a layered structure including a SiO layer and a SiN layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The gate insulating layer 148 may have a single-layer structure made of a SiO layer or a SiN layer. In this embodiment, the gate insulating layer 148 has a single-layer structure made of a SiO layer.

[0390] The gate insulating layer 148 is formed in the form of a film along the inner wall surface of the gate trench 142 so as to define a recessed space within the gate trench 142. The gate insulating layer 148 includes a first region 148a, a second region 148b, and a third region 148c.

[0391] The first region 148a is formed along the sidewall of the gate trench 142. The second region 148b is formed along the bottom wall of the gate trench 142. The third region 148c is formed along the first main surface 103 of the SiC semiconductor layer 102. The third region 148c of the gate insulating layer 148 forms part of the main surface insulating layer 113.

[0392] The thickness Ta of the first region 148a is smaller than the thickness Tb of the second region 148b and the thickness Tc of the third region 148c. The ratio Tb / Ta of the thickness Tb of the second region 148b to the thickness Ta of the first region 148a may be equal to or greater than 2 and equal to or less than 5. The ratio T3 / Ta of the thickness Tc of the third region 148c to the thickness Ta of the first region 148a may be equal to or greater than 2 and equal to or less than 5.

[0393] The thickness Ta of the first region 148a may be 0.01 μm or more and 0.2 μm or less. The thickness Tb of the second region 148b may be 0.05 μm or more and 0.5 μm or less. The thickness Tc of the third region 148c may be 0.05 μm or more and 0.5 μm or less.

[0394] By thinning the first region 148a of the gate insulating layer 148, it is possible to suppress an increase in carriers induced in the region near the sidewall of each gate trench 142 in the body region 141. This makes it possible to suppress an increase in channel resistance. By thickening the second region 148b of the gate insulating layer 148, it is possible to alleviate electric field concentration on the bottom wall of each gate trench 142.

[0395] By thickening the third region 148c of the gate insulating layer 148, it is possible to improve the breakdown voltage of the gate insulating layer 148 in the vicinity of the opening edge portion 146 of each gate trench 142. Furthermore, by thickening the third region 148c, it is possible to prevent the third region 148c from being lost by an etching method.

[0396] This can prevent the first region 148a from being removed by etching due to the disappearance of the third region 148c. As a result, the gate electrode layer 149 can be appropriately opposed to the SiC semiconductor layer 102 (body region 141) with the gate insulating layer 148 interposed therebetween.

[0397] The gate insulating layer 148 further includes a bulging portion 148d that bulges into each gate trench 142 at the opening edge portion 146 of each gate trench 142. The bulging portion 148d is formed at a corner portion that connects the first region 148a and the third region 148c of the gate insulating layer 148.

[0398] The bulging portions 148d protrude in a convex curved shape toward the inside of each gate trench 142. The bulging portions 148d narrow the openings of each gate trench 142 at opening edge portions 146 of each gate trench 142.

[0399] The bulging portion 148d improves the dielectric strength of the gate insulating layer 148 at the opening edge portion 146. Of course, the gate insulating layer 148 may be formed without the bulging portion 148d. Alternatively, the gate insulating layer 148 may be formed to have a uniform thickness.

[0400] The gate electrode layer 149 is embedded in each gate trench 142 with the gate insulating layer 148 sandwiched therebetween. More specifically, the gate electrode layer 149 is embedded in a concave space defined by the gate insulating layer 148 in each gate trench 142. The gate electrode layer 149 is controlled by a gate voltage.

[0401] The gate electrode layer 149 has an upper end portion located on the opening side of each gate trench 142. The upper end portion of the gate electrode layer 149 is formed in a concave curved shape recessed toward the bottom wall of each gate trench 142. The upper end portion of the gate electrode layer 149 has a constricted portion that is constricted along the bulging portion 148d of the gate insulating layer 148.

[0402] The cross-sectional area of ​​the gate electrode layer 149 (the cross-sectional area perpendicular to the direction in which each gate trench 142 extends) may be 0.05 μm or more and 0.5 μm or less. The cross-sectional area of ​​the gate electrode layer 149 is defined as the product of the depth of the gate electrode layer 149 and the width of the gate electrode layer 149.

[0403] The depth of the gate electrode layer 149 is the distance from the upper end to the lower end of the gate electrode layer 149. The width of the gate electrode layer 149 is the width of the gate trench 142 at the midpoint between the upper end and the lower end of the gate electrode layer 149. When the upper end is a curved surface (concavely curved in this embodiment), the position of the upper end of the gate electrode layer 149 is the midpoint in the depth direction on the upper surface of the gate electrode layer 149.

[0404] The gate electrode layer 149 includes p-type polysilicon doped with p-type impurities. The p-type impurities of the gate electrode layer 149 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0405] The p-type impurity concentration of the gate electrode layer 149 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the gate electrode layer 149 is higher than the p-type impurity concentration of the body region 141.

[0406] The p-type impurity concentration of the gate electrode layer 149 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the gate electrode layer 149 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0407] 18 and 20, a gate wiring layer 150 is formed in the active region 111. The gate wiring layer 150 is electrically connected to the gate pad 116 and the gate fingers 117 and 118. In FIG. 20, the gate wiring layer 150 is indicated by hatching.

[0408] The gate wiring layer 150 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 150 is formed on the third region 148c of the gate insulating layer 148.

[0409] In this embodiment, the gate wiring layer 150 is formed along the outer gate fingers 117. More specifically, the gate wiring layer 150 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions.

[0410] The gate wiring layer 150 is connected to the gate electrode layer 149 exposed from the contact trench portion 144 of each gate trench 142. In this embodiment, the gate wiring layer 150 is formed by an extended portion of the gate electrode layer 149 extended from each gate trench 142 onto the first main surface 103 of the SiC semiconductor layer 102. An upper end portion of the gate wiring layer 150 is connected to an upper end portion of the gate electrode layer 149.

[0411] 18, 19, and 21, a plurality of source trenches 155 are formed in first main surface 103 of SiC semiconductor layer 102 in active region 111. Each source trench 155 is formed in a region between two adjacent gate trenches 142.

[0412] The source trenches 155 are each formed in a strip shape extending along the first direction X (the m-axis direction of the SiC single crystal). The source trenches 155 are formed in a stripe shape as a whole in a plan view. The pitch between the centers of adjacent source trenches 155 in the second direction Y may be 1.5 μm or more and 3 μm or less.

[0413] Each source trench 155 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each source trench 155 includes a sidewall and a bottom wall. The sidewalls forming the long sides of each source trench 155 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each source trench 155 are formed by the m-plane of the SiC single crystal.

[0414] The sidewalls of each source trench 155 may extend along the normal direction Z. The sidewalls of each source trench 155 may be formed substantially perpendicular to the first main surface 103 of the SiC semiconductor layer 102.

[0415] The angle formed by the sidewall of each source trench 155 in the SiC semiconductor layer 102 with respect to the first main surface 103 of the SiC semiconductor layer 102 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). Each source trench 155 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.

[0416] The bottom wall of each source trench 155 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in a high concentration region 108 of the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in a region between the bottom wall of each gate trench 142 and the low concentration region 109.

[0417] The bottom wall of each source trench 155 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 155 has an off-angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0418] The bottom wall of each source trench 155 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102. Of course, the bottom wall of each source trench 155 may be formed in a convex curved shape toward the second main surface 104 of the SiC semiconductor layer 102.

[0419] In this embodiment, the depth of each source trench 155 is equal to or greater than the depth of each gate trench 142. More specifically, the depth of each source trench 155 is greater than the depth of each gate trench 142.

[0420] The bottom wall of each source trench 155 is located closer to the second main surface 104 of the SiC semiconductor layer 102 than the bottom wall of each gate trench 142. Of course, the depth of each source trench 155 may be equal to the depth of each gate trench 142.

[0421] The depth of each source trench 155 in the normal direction Z may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of each source trench 155 to the depth of each gate trench 142 may be 1.5 or more. The ratio of the depth of each source trench 155 to the depth of each gate trench 142 is preferably 2 or more.

[0422] The first direction width of each source trench 155 may be approximately equal to the first direction width of each gate trench 142. The first direction width of each source trench 155 may be equal to or greater than the first direction width of each gate trench 142. The first direction width of each source trench 155 may be equal to or greater than 0.1 μm and equal to or less than 2 μm (for example, approximately 0.5 μm).

[0423] A source insulating layer 156 and a source electrode layer 157 are formed in each source trench 155. In Fig. 18, the source insulating layer 156 and the source electrode layer 157 are indicated by hatching.

[0424] The source insulating layer 156 includes at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), and tantalum oxide (Ta 2 O 3 ).

[0425] The source insulating layer 156 may have a layered structure including a SiN layer and a SiO layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a layered structure including a SiO layer and a SiN layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102. The source insulating layer 156 may have a single-layer structure made of a SiO layer or a SiN layer. In this embodiment, the source insulating layer 156 has a single-layer structure made of a SiO layer.

[0426] The source insulating layer 156 is formed in the form of a film along the inner wall surface of each source trench 155 so as to define a recessed space within each source trench 155. The source insulating layer 156 includes a first region 156a and a second region 156b.

[0427] The first region 156a is formed along the sidewall of each source trench 155. The second region 156b is formed along the bottom wall of each source trench 155. The thickness Tsa of the first region 156a is smaller than the thickness Tsb of the second region 156b.

[0428] The ratio Tsb / Tsa of the thickness Tsb of the second region 156b to the thickness Tsa of the first region 156a may be equal to or greater than 2 and equal to or less than 5. The thickness Tsa of the first region 156a may be equal to or greater than 0.01 μm and equal to or less than 0.2 μm. The thickness Tsb of the second region 156b may be equal to or greater than 0.05 μm and equal to or less than 0.5 μm.

[0429] The thickness Tsa of the first region 156a may be approximately equal to the thickness Ta of the first region 156a of the gate insulating layer 148. The thickness Tsb of the second region 156b may be approximately equal to the thickness Tb of the second region 156b of the gate insulating layer 148. Of course, the source insulating layer 156 may be formed to have a uniform thickness.

[0430] The source electrode layer 157 is embedded in each source trench 155 with the source insulating layer 156 sandwiched therebetween. More specifically, the source electrode layer 157 is embedded in a concave space defined by the source insulating layer 156 in each source trench 155. The source electrode layer 157 is controlled by a source voltage.

[0431] The source electrode layer 157 has an upper end located on the opening side of each source trench 155. The upper end of the source electrode layer 157 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end of the source electrode layer 157 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0432] The upper end of the source electrode layer 157 is formed in a concave curved shape recessed toward the bottom wall of each source trench 155. The upper end of the source electrode layer 157 may be formed parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0433] The upper end of the source electrode layer 157 may protrude higher than the upper end of the source insulating layer 156. The upper end of the source electrode layer 157 may be located lower than the upper end of the source insulating layer 156. The thickness of the source electrode layer 157 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0434] The source electrode layer 157 preferably contains polysilicon, which has properties similar to those of SiC. This reduces stress generated in the SiC semiconductor layer 102. In this embodiment, the source electrode layer 157 contains p-type polysilicon doped with p-type impurities. In this case, the source electrode layer 157 can be formed simultaneously with the gate electrode layer 149.

[0435] The p-type impurity concentration of the source electrode layer 157 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the source electrode layer 157 is higher than the p-type impurity concentration of the body region 141. The p-type impurity of the source electrode layer 157 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0436] The p-type impurity concentration of the source electrode layer 157 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the source electrode layer 157 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0437] The p-type impurity concentration of the source electrode layer 157 may be approximately equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the source electrode layer 157 may be approximately equal to the sheet resistance of the gate electrode layer 149.

[0438] The source electrode layer 157 may contain n-type polysilicon instead of or in addition to p-type polysilicon, or may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

[0439] Thus, the SiC semiconductor device 101 has a plurality of trench gate structures 161 and a plurality of trench source structures 162. Each trench gate structure 161 includes a gate trench 142, a gate insulating layer 148, and a gate electrode layer 149. Each trench source structure 162 includes a source trench 155, a source insulating layer 156, and a source electrode layer 157.

[0440] In the surface layer portion of the body region 141, in the region along the sidewall of each gate trench 142, n +The n-type source region 163 is formed. The n-type impurity concentration of the source region 163 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity of the source region 163 may be phosphorus (P).

[0441] A plurality of source regions 163 are formed along one sidewall and the other sidewall of each gate trench 142. The plurality of source regions 163 are each formed in a strip shape extending along the first direction X.

[0442] The plurality of source regions 163 are formed in a striped pattern as a whole in a plan view. Each source region 163 is exposed from the sidewall of each gate trench 142 and the sidewall of each source trench 155.

[0443] In this way, in the surface portion of the first main surface 103 of the SiC semiconductor layer 102, in the region along the side wall of the gate trench 142, the source region 163, the body region 141, and the drift region 135 are formed in this order from the first main surface 103 toward the second main surface 104 of the SiC semiconductor layer 102.

[0444] A channel of the MISFET is formed in the body region 141 in a region along the sidewall of the gate trench 142. The channel is formed in the region along the sidewall of the gate trench 142 facing the a-plane of the SiC single crystal. The ON / OFF of the channel is controlled by the gate electrode layer 149.

[0445] In the active region 111, a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 is provided with a plurality of p + Each contact region 164 is formed in a region between two adjacent gate trenches 142 in plan view. Each contact region 164 is formed in a region on the opposite side of each source region 163 from the gate trench 142.

[0446] Each contact region 164 is formed along the inner wall of each source trench 155. In this embodiment, a plurality of contact regions 164 are formed at intervals along the inner wall of each source trench 155. Each contact region 164 is formed at an interval from each gate trench 142.

[0447] The p-type impurity concentration of each contact region 164 is higher than the p-type impurity concentration of the body region 141. The p-type impurity concentration of each contact region 164 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The p-type impurity in each contact region 164 may be aluminum (Al).

[0448] Each contact region 164 covers the sidewall and bottom wall of each source trench 155. The bottom of each contact region 164 may be formed parallel to the bottom wall of each source trench 155. More specifically, each contact region 164 integrally includes a first surface region 164a, a second surface region 164b, and an inner wall region 164c.

[0449] The first surface region 164a covers one sidewall of the source trench 155 in the surface portion of the body region 141. The first surface region 164a is electrically connected to the body region 141 and the source region 163.

[0450] The first surface region 164a is located in a region closer to the first main surface 103 of the SiC semiconductor layer 102 than the bottom of the source region 163. In this embodiment, the first surface region 164a has a bottom that extends parallel to the first main surface 103 of the SiC semiconductor layer 102.

[0451] In this embodiment, the bottom of first surface region 164a is located in a region between the bottom of body region 141 and the bottom of source region 163. The bottom of first surface region 164a may also be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141.

[0452] In this embodiment, the first surface region 164a extends from the source trench 155 toward the adjacent gate trench 142. The first surface region 164a may extend to an intermediate region between the gate trench 142 and the source trench 155. The first surface region 164a is formed at an interval from the gate trench 142 toward the source trench 155.

[0453] The second surface region 164b covers the other sidewall of the source trench 155 in the surface portion of the body region 141. The second surface region 164b is electrically connected to the body region 141 and the source region 163.

[0454] Second surface region 164b is located in a region closer to first main surface 103 of SiC semiconductor layer 102 than the bottom of source region 163. In this embodiment, second surface region 164b has a bottom that extends parallel to first main surface 103 of SiC semiconductor layer 102.

[0455] In this embodiment, the bottom of second surface region 164b is located in a region between the bottom of body region 141 and the bottom of source region 163. The bottom of second surface region 164b may also be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141.

[0456] In this embodiment, second surface region 164b extends from the other sidewall of source trench 155 toward the adjacent gate trench 142. Second surface region 164b may extend to an intermediate region between source trench 155 and gate trench 142. Second surface region 164b is formed at an interval from gate trench 142 toward source trench 155.

[0457] Inner wall region 164c is located in a region closer to second main surface 104 of SiC semiconductor layer 102 than first surface region 164a and second surface region 164b (bottom of source region 163). Inner wall region 164c is formed in a region of SiC semiconductor layer 102 along the inner wall of source trench 155. Inner wall region 164c covers the side wall of source trench 155.

[0458] The inner wall region 164c covers the corners connecting the side walls and bottom walls of the source trench 155. The inner wall region 164c covers the side walls of the source trench 155 through the corners and the bottom wall of the source trench 155. The bottom of the contact region 164 is formed by the inner wall region 164c.

[0459] A plurality of deep well regions 165 are formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. Each deep well region 165 is also referred to as a breakdown voltage adjusting region (breakdown voltage holding region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the active region 111.

[0460] Each deep well region 165 is formed in the SiC epitaxial layer 107. More specifically, each deep well region 165 is formed in a high concentration region 108 of the SiC epitaxial layer 107.

[0461] Each deep well region 165 is formed along the inner wall of each source trench 155 so as to cover each contact region 164. Each deep well region 165 is electrically connected to each contact region 164.

[0462] Each deep well region 165 is formed in a strip shape extending along each source trench 155 in a plan view. Each deep well region 165 covers the sidewall of each source trench 155.

[0463] Each deep well region 165 covers a corner connecting the sidewall and bottom wall of each source trench 155. Each deep well region 165 covers the sidewall of each source trench 155 through the corner and the bottom wall of each source trench 155. Each deep well region 165 is continuous with the body region 141 on the sidewall of each source trench 155.

[0464] Each deep well region 165 has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. The bottom of each deep well region 165 may be formed parallel to the bottom wall of each source trench 155.

[0465] The p-type impurity concentration of each deep well region 165 may be approximately equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of each deep well region 165 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of the body region 141.

[0466] The p-type impurity concentration of each deep well region 165 may be equal to or less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of each deep well region 165 may be 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0467] Each deep well region 165 forms a pn junction with the SiC semiconductor layer 102 (high concentration region 108 of the SiC epitaxial layer 107). A depletion layer extends from this pn junction toward a region between adjacent gate trenches 142. This depletion layer extends toward a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142.

[0468] The depletion layer extending from each deep well region 165 may overlap the bottom wall of each gate trench 142. The depletion layer extending from the bottom of each deep well region 165 may overlap the bottom wall of each gate trench 142.

[0469] 18 and 20 , a p-type peripheral deep well region 166 is formed in the peripheral portion of the active region 111. The peripheral deep well region 166 is formed in the SiC epitaxial layer 107. More specifically, the peripheral deep well region 166 is formed in the high concentration region 108 of the SiC epitaxial layer 107.

[0470] The peripheral deep well region 166 is electrically connected to each deep well region 165. The peripheral deep well region 166 has the same potential as each deep well region 165. In this embodiment, the peripheral deep well region 166 is formed integrally with each deep well region 165.

[0471] More specifically, the peripheral deep well region 166 is formed in a region along the inner wall of the contact trench portion 144 of each gate trench 142 at the periphery of the active region 111 .

[0472] The peripheral deep well region 166 covers the sidewalls of the contact trench portion 144 of each gate trench 142. The peripheral deep well region 166 covers the corners connecting the sidewalls and bottom wall of each contact trench portion 144.

[0473] The peripheral deep well region 166 covers the sidewalls and corners of each contact trench portion 144 and the bottom wall of each contact trench portion 144. Each deep well region 165 is continuous with the body region 141 at the sidewall of each contact trench portion 144. The bottom of the peripheral deep well region 166 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each contact trench portion 144.

[0474] In a plan view, the peripheral deep well region 166 overlaps the gate wiring layer 150. The peripheral deep well region 166 faces the gate wiring layer 150 with the gate insulating layer 148 (third region 148c) interposed therebetween.

[0475] The peripheral deep well region 166 includes a lead-out portion 166a that is led out from each contact trench portion 144 to each active trench portion 143. The lead-out portion 166a is formed in the high concentration region 108 of the SiC epitaxial layer 107. The lead-out portion 166a extends along the sidewall of each active trench portion 143, passes through the corners, and covers the bottom wall of the active trench portion 143.

[0476] The lead-out portion 166a covers the sidewalls of the active trench portion 143 of each gate trench 142. The lead-out portion 166a covers the corners connecting the sidewalls and bottom wall of each active trench portion 143.

[0477] The lead-out portion 166a covers the sidewalls and corners of each active trench 143 and the bottom wall of each active trench 143. The lead-out portion 166a is continuous with the body region 141 on the sidewall of each active trench 143. The bottom of the lead-out portion 166a is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each active trench 143.

[0478] The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the body region 141.

[0479] The p-type impurity concentration of the peripheral deep well region 166 may be approximately equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be greater than the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of each deep well region 165.

[0480] The p-type impurity concentration of the peripheral deep well region 166 may be equal to or less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0481] In a SiC semiconductor device having only a pn junction diode, the problem of electric field concentration in the SiC semiconductor layer 102 is reduced due to the structure not having a trench. Each deep well region 165 (peripheral deep well region 166) brings the trench gate type MISFET closer to the structure of a pn junction diode.

[0482] This allows the trench gate MISFET to reduce the electric field in the SiC semiconductor layer 102. Therefore, narrowing the pitch between the adjacent deep well regions 165 is effective in reducing the electric field concentration.

[0483] Furthermore, each deep well region 165 has a bottom on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142, and the depletion layer allows the electric field concentration on each gate trench 142 to be appropriately alleviated.

[0484] It is preferable that the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is approximately constant. This makes it possible to suppress variations in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0485] Therefore, the withstand voltage (for example, breakdown resistance) of the SiC semiconductor layer 102 can be prevented from being limited by the configuration of each deep well region 165, and the withstand voltage can be appropriately improved.

[0486] In this embodiment, a high concentration region 108 of the SiC epitaxial layer 107 is interposed in the region between the adjacent deep well regions 165. This makes it possible to reduce the JFET (Junction Field Effect Transistor) resistance in the region between the adjacent deep well regions 165.

[0487] Furthermore, in this embodiment, the bottom of each deep well region 165 is located within the high-concentration region 108 of the SiC epitaxial layer 107. This allows a current path to extend from the bottom of each deep well region 165 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. This reduces current spreading resistance. In this structure, the low-concentration region 109 of the SiC epitaxial layer 107 increases the breakdown voltage of the SiC semiconductor layer 102.

[0488] By forming the source trenches 155, p-type impurities can be introduced into the inner walls of the source trenches 155. This allows each deep well region 165 to be formed conformally to the source trenches 155, thereby appropriately suppressing variations in the depth of each deep well region 165. Furthermore, by using each source trench 155, each deep well region 165 can be appropriately formed in a relatively deep region of the SiC semiconductor layer 102.

[0489] 21, a low resistance electrode layer 167 is formed on the gate electrode layer 149. The low resistance electrode layer 167 covers the upper end of the gate electrode layer 149 in each gate trench 142.

[0490] The low resistance electrode layer 167 includes a conductive material having a sheet resistance lower than the sheet resistance of the gate electrode layer 149. The sheet resistance of the low resistance electrode layer 167 may be 0.01 Ω / □ or more and 10 Ω / □ or less.

[0491] The low-resistance electrode layer 167 is formed in a film shape. The low-resistance electrode layer 167 has a connection portion 167a that contacts the upper end of the gate electrode layer 149 and a non-connection portion 167b on the opposite side. The connection portion 167a and the non-connection portion 167b of the low-resistance electrode layer 167 may be formed in a concave curved shape following the upper end of the gate electrode layer 149. The connection portion 167a and the non-connection portion 167b of the low-resistance electrode layer 167 may take various forms.

[0492] The entire connecting portion 167a of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connecting portion 167a of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0493] The connection portion 167a of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 167a of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0494] For example, the central portion of the connection portion 167a of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the connection portion 167a of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0495] The entire non-connected portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire non-connected portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0496] The non-connected portion 167b of the low-resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connected portion 167b of the low-resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0497] For example, the central portion of the non-connected portion 167b of the low-resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the non-connected portion 167b of the low-resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0498] The low resistance electrode layer 167 has an edge 167c that contacts the gate insulating layer 148. The edge 167c of the low resistance electrode layer 167 contacts a corner of the gate insulating layer 148 that connects the first region 148a and the second region 148b.

[0499] An edge portion 167c of the low resistance electrode layer 167 is in contact with the third region 148c of the gate insulating layer 148. More specifically, the edge portion 167c of the low resistance electrode layer 167 is in contact with the bulging portion 148d of the gate insulating layer 148.

[0500] Edge portion 167c of low-resistance electrode layer 167 is formed in a region closer to first main surface 103 of SiC semiconductor layer 102 than the bottom of source region 163. Edge portion 167c of low-resistance electrode layer 167 is formed in a region closer to first main surface 103 of SiC semiconductor layer 102 than the boundary region between body region 141 and source region 163.

[0501] Therefore, the edge 167c of the low-resistance electrode layer 167 faces the source region 163 with the gate insulating layer 148 interposed therebetween. The edge 167c of the low-resistance electrode layer 167 does not face the body region 141 with the gate insulating layer 148 interposed therebetween.

[0502] Thereby, it is possible to suppress the formation of a current path in the region between the low-resistance electrode layer 167 and the body region 141 in the gate insulating layer 148. The current path can be formed by an undesired diffusion of the electrode material of the low-resistance electrode layer 167 with respect to the gate insulating layer 148.

[0503] In particular, the design of connecting the edge 167c of the low-resistance electrode layer 167 to the third region 148c (the corner of the gate insulating layer 148) of the relatively thick gate insulating layer 148 is effective in reducing the risk of forming a current path.

[0504] In the normal direction Z, the thickness Tr of the low-resistance electrode layer 167 is not more than the thickness TG of the gate electrode layer 149 (Tr ≦ TG). Preferably, the thickness Tr of the low-resistance electrode layer 167 is less than the thickness TG of the gate electrode layer 149 (Tr < TG). More specifically, preferably, the thickness Tr of the low-resistance electrode layer 167 is not more than half of the thickness TG of the gate electrode layer 149 (Tr ≦ TG / 2).

[0505] The ratio Tr / TG of the thickness Tr of the low-resistance electrode layer 167 to the thickness TG of the gate electrode layer 149 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 149 may be 0.5 μm or more and 3 μm or less. The thickness Tr of the low-resistance electrode layer 167 may be 0.01 μm or more and 3 μm or less.

[0506] The current supplied into each gate trench 142 flows through the low-resistance electrode layer 167 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 149. Thereby, since the entire gate electrode layer 149 (the entire active region 111) can be quickly shifted from the off state to the on state, the delay of the switching response can be suppressed.

[0507] In particular, in the case of gate trenches 142 having a length on the order of millimeters (length of 1 mm or more), it takes time for current to propagate, but delays in switching response can be appropriately suppressed by using the low-resistance electrode layer 167. In other words, the low-resistance electrode layer 167 is formed as a current diffusion electrode layer that diffuses current within each gate trench 142.

[0508] Furthermore, as the cell structure becomes finer, the width, depth, cross-sectional area, etc. of the gate electrode layer 149 become smaller, which raises concerns about delays in switching response due to increased electrical resistance in each gate trench 142.

[0509] However, the low resistance electrode layer 167 allows the entire gate electrode layer 149 to transition quickly from the OFF state to the ON state, so that delays in switching response due to miniaturization can be appropriately suppressed.

[0510] 20 , in this embodiment, the low-resistance electrode layer 167 also covers the upper end of the gate wiring layer 150. The portion of the low-resistance electrode layer 167 that covers the upper end of the gate wiring layer 150 is integrally formed with the portion of the low-resistance electrode layer 167 that covers the upper end of the gate electrode layer 149. As a result, the low-resistance electrode layer 167 covers the entire area of ​​the gate electrode layer 149 and the entire area of ​​the gate wiring layer 150.

[0511] Therefore, the current supplied from the gate pad 116 and the gate fingers 117, 118 to the gate wiring layer 150 is transmitted to the entire gate electrode layer 149 and gate wiring layer 150 via the low resistance electrode layer 167 having a relatively low sheet resistance.

[0512] This allows the entire gate electrode layer 149 (the entire active region 111) to be quickly transitioned from an OFF state to an ON state via the gate wiring layer 150, thereby suppressing delays in switching response.

[0513] In particular, in the case of the gate trench 142 having a length on the order of millimeters, the low resistance electrode layer 167 covering the upper end of the gate wiring layer 150 can appropriately suppress delay in switching response.

[0514] The low-resistance electrode layer 167 includes a polycide layer. The polycide layer is formed by silicidating the surface portion of the gate electrode layer 149 with a metal material. More specifically, the polycide layer is a p-type polycide layer containing p-type impurities added to the gate electrode layer 149 (p-type polysilicon). The polycide layer preferably has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0515] The sheet resistance in the gate trench 142 in which the gate electrode layer 149 and the low resistance electrode layer 167 are buried is equal to or less than the sheet resistance of the gate electrode layer 149 alone. The sheet resistance in the gate trench 142 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0516] The sheet resistance in the gate trench 142 is approximated to the sheet resistance of the low resistance electrode layer 167. That is, the sheet resistance in the gate trench 142 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 142 is preferably less than 10 Ω / □.

[0517] The low-resistance electrode layer 167 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Of these materials, NiSi, CoSi2, and TiSi2 are particularly suitable as a polycide layer for forming the low-resistance electrode layer 167 because of their relatively small resistivity and temperature dependency.

[0518] In the first main surface 103 of the SiC semiconductor layer 102, a source sub-trenches 168 communicating with each source trench 155 are formed in a region along the upper end of the source electrode layer 157. The source sub-trenches 168 form part of the sidewall of each source trench 155.

[0519] In this embodiment, the source sub-trench 168 is formed in an endless shape (in this embodiment, a square ring shape) in plan view so as to surround the upper end of the source electrode layer 157. The source sub-trench 168 borders the upper end of the source electrode layer 157.

[0520] The source sub-trench 168 is formed by digging down a part of the source insulating layer 156. More specifically, the source sub-trench 168 is formed by digging down from the first main surface 103 of the SiC semiconductor layer 102 to the upper end of the source insulating layer 156 and the upper end of the source electrode layer 157.

[0521] The upper end of the source electrode layer 157 has a shape that is narrowed inward relative to the lower end of the source electrode layer 157. The lower end of the source electrode layer 157 is a portion of the source electrode layer 157 that is located on the bottom wall side of each source trench 155. The width in the first direction of the upper end of the source electrode layer 157 may be smaller than the width in the first direction of the lower end of the source electrode layer 157.

[0522] The source sub-trench 168 is formed in a tapered shape in which the bottom area is smaller than the opening area in a cross-sectional view. The bottom wall of the source sub-trench 168 may be formed in a convex curved shape facing the second main surface 104 of the SiC semiconductor layer 102.

[0523] The source region 163, the contact region 164, the source insulating layer 156, and the source electrode layer 157 are exposed from the inner wall of the source sub-trench 168. The first surface region 164a and the second surface region 164b of the contact region 164 are exposed from the inner wall of the source sub-trench 168.

[0524] At least the first region 156a of the source insulating layer 156 is exposed from the bottom wall of the source sub-trench 168. The upper end of the first region 156a of the source insulating layer 156 is located lower than the first main surface 103 of the SiC semiconductor layer 102.

[0525] An opening edge 169 of each source trench 155 includes an inclined portion 170 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each source trench 155. The opening edge 169 of each source trench 155 is a corner that connects the first main surface 103 of the SiC semiconductor layer 102 and the sidewall of each source trench 155. The inclined portion 170 of each source trench 155 is formed by a source sub-trench 168.

[0526] In this embodiment, the inclined portions 170 are formed in a concave curved shape directed inwardly of the SiC semiconductor layer 102. The inclined portions 170 may be formed in a convex curved shape directed inwardly of the source sub-trench 168. The inclined portions 170 reduce electric field concentration at the opening edge portions 169 of each source trench 155.

[0527] 22 and 23, the active region 111 has an active main surface 171 that forms part of the first main surface 103 of the SiC semiconductor layer 102. The outer region 112 has an outer main surface 172 that forms part of the first main surface 103 of the SiC semiconductor layer 102. In this embodiment, the outer main surface 172 is connected to the side surfaces 105A to 105D of the SiC semiconductor layer 102.

[0528] The active principal surface 171 and the outer principal surface 172 each face the c-plane of the SiC single crystal, and each have an off-angle θ tilted in the [11-20] direction with respect to the c-plane of the SiC single crystal.

[0529] The outer principal surface 172 is located on the second principal surface 104 side of the SiC semiconductor layer 102 relative to the active principal surface 171. In this embodiment, the outer region 112 is formed by digging down the first principal surface 103 of the SiC semiconductor layer 102 toward the second principal surface 104. Therefore, the outer principal surface 172 is formed in a region recessed toward the second principal surface 104 side of the SiC semiconductor layer 102 relative to the active principal surface 171.

[0530] The outer principal surface 172 may be located closer to the second principal surface 104 of the SiC semiconductor layer 102 than the bottom walls of the gate trenches 142. The outer principal surface 172 may be formed at a depth substantially equal to the bottom walls of the source trenches 155. The outer principal surface 172 may be located on substantially the same plane as the bottom walls of the source trenches 155.

[0531] The distance between the outer major surface 172 and the second major surface 104 of the SiC semiconductor layer 102 may be approximately equal to the distance between the bottom wall of each source trench 155 and the second major surface 104 of the SiC semiconductor layer 102 .

[0532] Outer principal surface 172 may be located on the second principal surface 104 side of SiC semiconductor layer 102 relative to the bottom wall of each source trench 155. Outer principal surface 172 may be located on the second principal surface 104 side of SiC semiconductor layer 102 relative to the bottom wall of each source trench 155 within a range of 0 μm to 1 μm.

[0533] The SiC epitaxial layer 107 is exposed from the outer main surface 172. More specifically, the high concentration region 108 of the SiC epitaxial layer 107 is exposed from the outer main surface 172 of the outer region 112. The outer main surface 172 faces the low concentration region 109 of the SiC epitaxial layer 107, with the high concentration region 108 of the SiC epitaxial layer 107 sandwiched between them.

[0534] In this embodiment, the active region 111 is partitioned into a plateau shape by the outer region 112. The active region 111 is formed as an active plateau 173 that protrudes upward from the outer region 112.

[0535] The active plateau 173 includes an active sidewall 174 connecting the active main surface 171 and the outer main surface 172. The active sidewall 174 defines a boundary region between the active region 111 and the outer region 112. The first main surface 103 of the SiC semiconductor layer 102 is formed by the active main surface 171, the outer main surface 172, and the active sidewall 174.

[0536] In this embodiment, the active sidewall 174 extends along the normal direction Z of the active principal surface 171 (outer principal surface 172). The active sidewall 174 is formed by the m-plane and a-plane of a SiC single crystal.

[0537] The active sidewall 174 may have an inclined surface that slopes downward from the active main surface 171 toward the outer main surface 172. The inclination angle of the active sidewall 174 is the angle formed between the active sidewall 174 and the active main surface 171 within the SiC semiconductor layer 102.

[0538] In this case, the inclination angle of the active sidewall 174 may be greater than 90° and less than or equal to 135°. The inclination angle of the active sidewall 174 may be greater than 90° and less than or equal to 95°, greater than or equal to 95° and less than or equal to 100°, greater than or equal to 100° and less than or equal to 110°, greater than or equal to 110° and less than or equal to 120°, or greater than or equal to 120° and less than or equal to 135°. The inclination angle of the active sidewall 174 is preferably greater than 90° and less than or equal to 95°.

[0539] The SiC epitaxial layer 107 is exposed from the active sidewall 174. More specifically, the high concentration region 108 of the SiC epitaxial layer 107 is exposed from the active sidewall 174.

[0540] At least the body region 141 is exposed from the region of the active sidewall 174 on the active main surface 171 side. 22 and 23 show an example in which the body region 141 and the source region 163 are exposed from the active sidewall 174.

[0541] In the outer region 112, the surface layer portion of the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102 contains p + A p-type diode region 181 (impurity region), a p-type outer deep well region 182, and a p-type field limit structure 183 are formed.

[0542] The diode region 181 is formed in the outer region 112 in a region between the active sidewall 174 and the side surfaces 105A to 105D of the SiC semiconductor layer 102. The diode region 181 is formed at a distance from the active sidewall 174 and the side surfaces 105A to 105D.

[0543] In plan view, the diode region 181 extends in a strip shape along the active region 111. In this embodiment, the diode region 181 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 111 in plan view.

[0544] In a plan view, the diode region 181 overlaps with the source lead-out wiring 123. The diode region 181 is electrically connected to the source lead-out wiring 123. The diode region 181 forms a part of the avalanche current absorption structure.

[0545] The diode region 181 forms a pn junction with the SiC semiconductor layer 102. More specifically, the diode region 181 is located within the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the SiC epitaxial layer 107.

[0546] More specifically, the diode region 181 is located in the high concentration region 108 of the SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the high concentration region 108. This forms a pn junction diode Dpn in which the diode region 181 serves as the anode and the SiC semiconductor layer 102 serves as the cathode.

[0547] The entire diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of the diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.

[0548] The bottom of the diode region 181 may be formed at a depth position substantially equal to the bottom of the contact region 164. The bottom of the diode region 181 may be located on substantially the same plane as the bottom of the contact region 164.

[0549] The p-type impurity concentration of the diode region 181 is approximately equal to the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the diode region 181 is higher than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the diode region 181 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 It may be the following:

[0550] The outer deep well region 182 is formed in a region between the active sidewall 174 and the diode region 181 in a plan view. In this embodiment, the outer deep well region 182 is formed at an interval from the active sidewall 174 toward the diode region 181. The outer deep well region 182 is also referred to as a breakdown voltage adjusting region (breakdown voltage maintaining region) that adjusts the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112.

[0551] The outer deep well region 182 extends in a strip shape along the active region 111 in a plan view. In this embodiment, the outer deep well region 182 is formed in an endless shape (a square ring shape in this embodiment) surrounding the active region 111 in a plan view.

[0552] The outer deep well region 182 is electrically connected to the source lead-out wiring 123 via the diode region 181. The outer deep well region 182 may form part of a pn junction diode Dpn. The outer deep well region 182 may form part of an avalanche current absorption structure.

[0553] The entire outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each gate trench 142. The bottom of the outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of each source trench 155.

[0554] The bottom of outer deep well region 182 is located closer to second main surface 104 of SiC semiconductor layer 102 than the bottom of diode region 181. The bottom of outer deep well region 182 may be formed at a depth substantially equal to the bottom of each deep well region 165. The bottom of outer deep well region 182 may be located on substantially the same plane as the bottom of each deep well region 165.

[0555] The distance between the bottom of the outer deep well region 182 and the outer major surface 172 may be approximately equal to the distance between the bottom of each deep well region 165 and the bottom wall of each source trench 155 .

[0556] The distance between the bottom of the outer deep well region 182 and the second major surface 104 of the SiC semiconductor layer 102 may be approximately equal to the distance between the bottom of each deep well region 165 and the second major surface 104 of the SiC semiconductor layer 102 .

[0557] This prevents variations from occurring between the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0558] Therefore, the withstand voltage (for example, breakdown resistance) of the SiC semiconductor layer 102 can be prevented from being limited by the configuration of the outer deep well region 182 and the configuration of each deep well region 165, and the withstand voltage can be appropriately improved.

[0559] The bottom of the outer deep well region 182 may be located closer to the second main surface 104 of the SiC semiconductor layer 102 than the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located closer to the second main surface 104 of the SiC semiconductor layer 102 than the bottom of each deep well region 165, within a range of 0 μm to 1 μm.

[0560] The inner periphery of the outer deep well region 182 may extend close to the boundary region between the active region 111 and the outer region 112. The outer deep well region 182 may cross the boundary region between the active region 111 and the outer region 112.

[0561] The inner periphery of the outer deep well region 182 may cover the corner connecting the active sidewall 174 and the outer major surface 172. The inner periphery of the outer deep well region 182 may also extend along the active sidewall 174 and connect to the body region 141.

[0562] In this embodiment, the outer peripheral edge of the outer deep well region 182 covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The outer deep well region 182 may overlap with the source lead-out wiring 123 in a plan view. The outer peripheral edge of the outer deep well region 182 may be formed at a distance from the diode region 181 toward the active sidewall 174.

[0563] The p-type impurity concentration of the outer deep well region 182 may be equal to or less than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the diode region 181.

[0564] The p-type impurity concentration of the outer deep well region 182 may be approximately equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the outer deep well region 182 may be approximately equal to the p-type impurity concentration of the body region 141.

[0565] The p-type impurity concentration of the outer deep well region 182 may be greater than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the body region 141.

[0566] The p-type impurity concentration of the outer deep well region 182 may be equal to or less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the outer deep well region 182 may be 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0567] In plan view, the field limit structure 183 is formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102. In this embodiment, the field limit structure 183 is formed at an interval from the side surfaces 105A to 105D toward the diode region 181.

[0568] The field limit structure 183 includes one or more (for example, two or more and twenty or less) field limit regions 184. In this embodiment, the field limit structure 183 includes a field limit region group having a plurality (five) of field limit regions 184A, 184B, 184C, 184D, and 184E.

[0569] The field limit regions 184A to 184E are formed in this order at intervals along a direction away from the diode region 181. Each of the field limit regions 184A to 184E extends in a strip shape along the periphery of the active region 111 in a plan view.

[0570] More specifically, the field limit regions 184A to 184E are each formed in an endless shape (a quadrangular ring shape in this embodiment) in plan view surrounding the active region 111. The field limit regions 184A to 184E are also referred to as FLR (Field Limiting Ring) regions.

[0571] In this embodiment, the bottoms of the field limit regions 184A to 184E are located closer to the second main surface 104 of the SiC semiconductor layer 102 than the bottom of the diode region 181.

[0572] In this embodiment, the innermost field limit region 184A of the field limit regions 184A to 184E covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The field limit region 184A may overlap with the above-described source lead-out line 123 in plan view.

[0573] The field limit region 184A is electrically connected to the source lead-out wiring 123 via the diode region 181. The field limit region 184A may form a part of the pn junction diode Dpn. The field limit region 184A may form a part of the avalanche current absorption structure.

[0574] The entire field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of the respective gate trenches 142. The bottoms of the field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom walls of the respective source trenches 155.

[0575] The field limit regions 184A to 184E may be formed at a depth substantially equal to that of each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A to 184E may be located on substantially the same plane as the bottoms of each deep well region 165 (outer deep well region 182).

[0576] The bottoms of the field limit regions 184A-184E may be located closer to the outer main surface 172 than the bottoms of the deep well regions 165 (outer deep well regions 182). The bottoms of the field limit regions 184A-184E may be located closer to the second main surface 104 of the SiC semiconductor layer 102 than the bottoms of the deep well regions 165 (outer deep well regions 182).

[0577] The width between adjacent field limit regions 184A to 184E may be different from each other. The width between adjacent field limit regions 184A to 184E may increase in a direction away from the active region 111. The width between adjacent field limit regions 184A to 184E may decrease in a direction away from the active region 111.

[0578] The depths of the field limit regions 184A to 184E may be different from one another. The depths of the field limit regions 184A to 184E may decrease in a direction away from the active region 111. The depths of the field limit regions 184A to 184E may increase in a direction away from the active region 111.

[0579] The p-type impurity concentration of the field limit regions 184A to 184E may be equal to or lower than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the field limit regions 184A to 184E may be lower than the p-type impurity concentration of the diode region 181.

[0580] The p-type impurity concentration of the field limit regions 184A-184E may be equal to or lower than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A-184E may be lower than the p-type impurity concentration of the outer deep well region 182.

[0581] The p-type impurity concentration of the field limit regions 184A-184E may be equal to or higher than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of the field limit regions 184A-184E may be higher than the p-type impurity concentration of the outer deep well region 182.

[0582] The p-type impurity concentration of the field limit regions 184A to 184E is 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 It is preferable that the p-type impurity concentration of the diode region 181>the p-type impurity concentration of the outer deep well region 182>the p-type impurity concentration of the field limit regions 184A to 184E.

[0583] The field limit structure 183 relieves electric field concentration in the outer region 112. The number, width, depth, p-type impurity concentration, etc. of the field limit regions 184 can take various values ​​depending on the electric field to be relieved.

[0584] In this embodiment, an example has been described in which the field limit structure 183 includes one or more field limit regions 184 formed in the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view.

[0585] However, the field limit structure 183 may include one or more field limit regions 184 formed in the region between the active sidewall 174 and the diode region 181 in a planar view, instead of the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102.

[0586] The field limit structure 183 may also include one or more field limit regions 184 formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view, and one or more field limit regions 184 formed in a region between the active sidewall 174 and the diode region 181 in a planar view.

[0587] An outer insulating layer 191 is formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. The outer insulating layer 191 forms part of the main surface insulating layer 113. The outer insulating layer 191 forms part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113.

[0588] The outer insulating layer 191 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112. The outer insulating layer 191 is formed in the form of a film along the active sidewall 174 and the outer main surface 172. The outer insulating layer 191 is continuous with the gate insulating layer 148 on the active main surface 171. More specifically, the outer insulating layer 191 is continuous with the third region 148c of the gate insulating layer 148.

[0589] The outer insulating layer 191 may include silicon oxide or other insulating films such as silicon nitride. In this embodiment, the outer insulating layer 191 is formed of the same insulating material as the gate insulating layer 148.

[0590] The outer insulating layer 191 includes a first region 191a and a second region 191b. The first region 191a of the outer insulating layer 191 covers the active sidewall 174. The second region 191b of the outer insulating layer 191 covers the outer main surface 172.

[0591] The thickness of the second region 191b of the outer insulating layer 191 may be equal to or less than the thickness of the first region 191a of the outer insulating layer 191. The thickness of the second region 191b of the outer insulating layer 191 may be less than the thickness of the first region 191a of the outer insulating layer 191.

[0592] The thickness of the first region 191a of the outer insulating layer 191 may be approximately equal to the thickness of the first region 191a of the gate insulating layer 148. The thickness of the second region 191b of the outer insulating layer 191 may be approximately equal to the thickness of the third region 148c of the gate insulating layer 148. Of course, the outer insulating layer 191 may be formed to have a uniform thickness.

[0593] 22 and 23, SiC semiconductor device 101 further includes sidewalls 192 covering active sidewalls 174. Sidewalls 192 protect and reinforce active plateaus 173 from the outer region 112 side.

[0594] The sidewalls 192 also form a step reduction structure that reduces the step formed between the active principal surface 171 and the outer principal surface 172. When an upper layer structure (covering layer) is formed to cover the boundary region between the active region 111 and the outer region 112, the upper layer structure covers the sidewalls 192. The sidewalls 192 improve the flatness of the upper layer structure.

[0595] The sidewall 192 may have an inclined portion 193 that slopes downward from the active principal surface 171 toward the outer principal surface 172. The inclined portion 193 can appropriately reduce the step.

[0596] The inclined portion 193 of the sidewall 192 may be formed in a concave curve toward the SiC semiconductor layer 102. The inclined portion 193 of the sidewall 192 may be formed in a convex curve toward the opposite side from the SiC semiconductor layer 102.

[0597] The inclined portion 193 of the sidewall 192 may extend in a plane from the active principal surface 171 side toward the outer principal surface 172 side. The inclined portion 193 of the sidewall 192 may extend linearly from the active principal surface 171 side toward the outer principal surface 172 side.

[0598] The inclined portion 193 of the sidewall 192 may be formed in a descending staircase shape from the active principal surface 171 toward the outer principal surface 172. The inclined portion 193 of the sidewall 192 may have one or more steps recessed toward the outer principal surface 172. The multiple steps increase the surface area of ​​the inclined portion 193 of the sidewall 192 and improve adhesion to the upper layer structure.

[0599] The inclined portion 193 of the sidewall 192 may include a plurality of ridges that bulge outward from the sidewall 192. The plurality of ridges increases the surface area of ​​the inclined portion 193 of the sidewall 192, and improves adhesion to the upper layer structure.

[0600] The inclined portion 193 of the sidewall 192 may include a plurality of depressions recessed toward the inside of the sidewall 192. The plurality of depressions increases the surface area of ​​the inclined portion 193 of the sidewall 192, and improves adhesion to the upper layer structure.

[0601] The sidewalls 192 are formed in a self-aligned manner with respect to the active main surface 171. More specifically, the sidewalls 192 are formed along the active sidewalls 174. In this embodiment, the sidewalls 192 are formed in an endless shape (a quadrangular ring shape in this embodiment) surrounding the active region 111 in plan view.

[0602] The sidewalls 192 preferably contain p-type polysilicon doped with p-type impurities. In this case, the sidewalls 192 can be formed simultaneously with the gate electrode layer 149 and the source electrode layer 157.

[0603] The p-type impurity concentration of the sidewall 192 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the sidewall 192 is higher than the p-type impurity concentration of the body region 141. The p-type impurity of the sidewall 192 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0604] The p-type impurity concentration of the sidewall 192 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the sidewall 192 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment).

[0605] The p-type impurity concentration of the sidewall 192 may be approximately equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the sidewall 192 may be approximately equal to the sheet resistance of the gate electrode layer 149.

[0606] The sidewalls 192 may contain n-type polysilicon instead of or in addition to p-type polysilicon, or may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.

[0607] The sidewalls 192 may include an insulating material, in which case the sidewalls 192 can improve the insulation of the active region 111 from the outer region 112.

[0608] 19 to 23, an interlayer insulating layer 201 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 201 forms a part of the main surface insulating layer 113. The interlayer insulating layer 201 forms a part of the insulating side surfaces 114A to 114D of the main surface insulating layer 113. The main surface insulating layer 113 has a layered structure including the gate insulating layer 148 (outer insulating layer 191) and the interlayer insulating layer 201.

[0609] The interlayer insulating layer 201 selectively covers the active region 111 and the outer region 112. More specifically, the interlayer insulating layer 201 selectively covers the third region 148c of the gate insulating layer 148 and the outer insulating layer 191.

[0610] The interlayer insulating layer 201 is formed in a film shape along the active principal surface 171 and the outer principal surface 172. The interlayer insulating layer 201 selectively covers the trench gate structure 161, the gate wiring layer 150, and the trench source structure 162 in the active region 111. The interlayer insulating layer 201 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112.

[0611] The interlayer insulating layer 201 is formed along the outer surface (inclined portion 193) of the sidewall 192 in the boundary region between the active region 111 and the outer region 112. The interlayer insulating layer 201 forms part of an upper layer structure that covers the sidewall 192.

[0612] The interlayer insulating layer 201 may contain silicon oxide or silicon nitride. The interlayer insulating layer 201 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass), which are examples of silicon oxide.

[0613] Interlayer insulating layer 201 may have a layered structure including a PSG layer and a BPSG layer stacked in this order from the first main surface 103 side of SiC semiconductor layer 102. Interlayer insulating layer 201 may have a layered structure including a BPSG layer and a PSG layer stacked in this order from the first main surface 103 side of SiC semiconductor layer 102.

[0614] The interlayer insulating layer 201 is formed with a gate contact hole 202, a source contact hole 203, and a diode contact hole 204. The interlayer insulating layer 201 is also formed with an anchor hole 205.

[0615] The gate contact hole 202 exposes the gate wiring layer 150 in the active region 111. The gate contact hole 202 may be formed in a strip shape along the gate wiring layer 150. The opening edge portion of the gate contact hole 202 is formed in a convex curved shape facing inward of the gate contact hole 202.

[0616] The source contact hole 203 exposes the source region 163, the contact region 164, and the trench source structure 162 in the active region 111. The source contact hole 203 may be formed in a strip shape along the trench source structure 162, etc. The opening edge of the source contact hole 203 is formed in a convex curved shape facing inward of the source contact hole 203.

[0617] The diode contact hole 204 exposes the diode region 181 in the outer region 112. The diode contact hole 204 may be formed in a strip shape (more specifically, endless shape) extending along the diode region 181.

[0618] The diode contact hole 204 may expose the outer deep well region 182 and / or the field limit structure 183. The opening edge of the diode contact hole 204 is formed in a convex curve toward the inside of the diode contact hole 204.

[0619] The anchor holes 205 are formed in the outer region 112 by digging down the interlayer insulating layer 201. The anchor holes 205 are formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view. More specifically, the anchor holes 205 are formed in a region between the field limit structure 183 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a planar view.

[0620] Anchor hole 205 exposes first main surface 103 (outer main surface 172) of SiC semiconductor layer 102. An opening edge portion of anchor hole 205 is formed in a convex curved shape directed toward the inside of anchor hole 205.

[0621] 17, the anchor holes 205 extend in a strip shape along the active region 111 in a plan view. In this embodiment, the anchor holes 205 are formed in an endless shape (in this embodiment, a quadrangular ring shape) surrounding the active region 111 in a plan view.

[0622] In this embodiment, one anchor hole 205 is formed in the portion of the interlayer insulating layer 201 that covers the outer region 112. However, a plurality of anchor holes 205 may be formed in the portion of the interlayer insulating layer 201 that covers the outer region 112.

[0623] A main surface gate electrode layer 115 and a main surface source electrode layer 121 are formed on the interlayer insulating layer 201. The main surface gate electrode layer 115 and the main surface source electrode layer 121 each have a laminated structure including a barrier electrode layer 206 and a main electrode layer 207 laminated in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0624] The barrier electrode layer 206 may have a single-layer structure including a titanium layer or a titanium nitride layer, or may have a multilayer structure including a titanium layer and a titanium nitride layer stacked in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0625] The thickness of the main electrode layer 207 is greater than the thickness of the barrier electrode layer 206. The main electrode layer 207 includes a conductive material having a resistance value smaller than the resistance value of the barrier electrode layer 206. The main electrode layer 207 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

[0626] The main electrode layer 207 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. In this embodiment, the main electrode layer 207 includes an aluminum-silicon-copper alloy.

[0627] The outer gate fingers 117 of the main surface gate electrode layer 115 extend from above the interlayer insulating layer 201 into the gate contact holes 202. The outer gate fingers 117 are electrically connected to the gate wiring layer 150 within the gate contact holes 202. This allows an electrical signal from the gate pad 116 to be transmitted to the gate electrode layer 149 via the outer gate fingers 117.

[0628] The source pad 122 of the main surface source electrode layer 121 extends from above the interlayer insulating layer 201 into the source contact hole 203 and the source sub-trench 168. The source pad 122 is electrically connected to the source region 163, the contact region 164, and the source electrode layer 157 within the source contact hole 203 and the source sub-trench 168.

[0629] The source electrode layer 157 may be formed by utilizing a partial region of the source pad 122. The source electrode layer 157 may be formed by portions of the source pad 122 that extend into each source trench 155.

[0630] The source lead-out wiring 123 of the main surface source electrode layer 121 enters the diode contact hole 204 from above the interlayer insulating layer 201. The source lead-out wiring 123 is electrically connected to the diode region 181 in the diode contact hole 204.

[0631] The source connection portion 124 of the main surface source electrode layer 121 is led out from the active region 111 across the sidewall 192 to the outer region 112. The source connection portion 124 forms part of an upper layer structure that covers the sidewall 192.

[0632] The aforementioned passivation layer 125 is formed on the interlayer insulating layer 201. The passivation layer 125 is formed in the form of a film along the interlayer insulating layer 201. The passivation layer 125 selectively covers the active region 111 and the outer region 112 via the interlayer insulating layer 201.

[0633] The passivation layer 125 extends from the active region 111 across the sidewalls 192 to the outer region 112. The passivation layer 125 forms part of an upper structure that covers the sidewalls 192.

[0634] 22 , in the outer region 112, the passivation layer 125 extends from above the interlayer insulating layer 201 into the anchor hole 205. The passivation layer 125 is connected to the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102 within the anchor hole 205. In the outer surface of the passivation layer 125, in a region located above the anchor hole 205, a recess 211 is formed that is recessed in accordance with the shape of the anchor hole 205.

[0635] The aforementioned resin layer 129 is formed on the passivation layer 125. The resin layer 129 is formed in the form of a film along the passivation layer 125. The resin layer 129 selectively covers the active region 111 and the outer region 112, with the passivation layer 125 and the interlayer insulating layer 201 sandwiched between them.

[0636] The resin layer 129 extends from the active region 111 across the sidewalls 192 to the outer region 112. The resin layer 129 forms part of an upper layer structure that covers the sidewalls 192.

[0637] 22, resin layer 129 has anchor portions that enter recesses 211 of passivation layer 125 in outer region 112. In this manner, anchor structures for increasing the connection strength of resin layer 129 are formed in outer region 112.

[0638] The anchor structure includes an uneven structure formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112. More specifically, the uneven structure (anchor structure) includes unevenness formed by utilizing interlayer insulating layer 201 covering outer main surface 172. Even more specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in interlayer insulating layer 201.

[0639] The resin layer 129 is engaged with the anchor hole 205. In this embodiment, the resin layer 129 is engaged with the anchor hole 205 via the passivation layer 125. This increases the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102, thereby preventing the resin layer 129 from peeling off.

[0640] As described above, SiC semiconductor device 101 can also achieve the same effects as those described for SiC semiconductor device 1. Furthermore, according to SiC semiconductor device 101, the depletion layer can be expanded from the boundary region (pn junction) between SiC semiconductor layer 102 and deep well region 165 toward the region on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of gate trench 142.

[0641] This narrows the current path of the short-circuit current flowing between the main surface source electrode layer 121 and the drain electrode layer 133. Furthermore, the depletion layer extending from the boundary region between the SiC semiconductor layer 102 and the deep well region 165 reduces the reverse transfer capacitance Crss inversely proportionally. This makes it possible to provide a SiC semiconductor device 101 that can improve short-circuit resistance and reduce the reverse transfer capacitance Crss.

[0642] The depletion layer extending from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 may overlap the bottom wall of the gate trench 142. In this case, the depletion layer extending from the bottom of the deep well region 165 may overlap the bottom wall of the gate trench 142.

[0643] Furthermore, according to the SiC semiconductor device 101, it is possible to increase the area occupied by the depletion layer in the SiC semiconductor layer 102, thereby reducing the feedback capacitance Crss inversely proportionally. The feedback capacitance Crss is the electrostatic capacitance between the gate electrode layer 149 and the drain electrode layer 133.

[0644] Furthermore, in the SiC semiconductor device 101, the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is approximately constant. This makes it possible to suppress variations in the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0645] Therefore, the withstand voltage (for example, breakdown resistance) of the SiC semiconductor layer 102 can be prevented from being limited by the configuration of the deep well region 165, and the withstand voltage can be appropriately improved.

[0646] Moreover, according to the SiC semiconductor device 101, a diode region 181 is formed in the outer region 112. This diode region 181 is electrically connected to the main surface source electrode layer 121. This allows an avalanche current generated in the outer region 112 to flow into the main surface source electrode layer 121 via the diode region 181.

[0647] That is, the avalanche current generated in the outer region 112 can be absorbed by the diode region 181 and the main surface source electrode layer 121. As a result, the stability of the operation of the MISFET can be improved.

[0648] Furthermore, according to the SiC semiconductor device 101, the outer deep well region 182 is formed in the outer region 112. This allows the breakdown voltage of the SiC semiconductor layer 102 to be adjusted in the outer region 112.

[0649] In particular, in SiC semiconductor device 101, outer deep well region 182 is formed at a depth position substantially equal to that of deep well region 165. More specifically, the bottom of outer deep well region 182 is located on substantially the same plane as the bottom of deep well region 165.

[0650] The distance between the bottom of the outer deep well region 182 and the second major surface 104 of the SiC semiconductor layer 102 is approximately equal to the distance between the bottom of the deep well region 165 and the second major surface 104 of the SiC semiconductor layer 102 .

[0651] This prevents variations from occurring between the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of the deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102.

[0652] This prevents the breakdown voltage (for example, breakdown resistance) of the SiC semiconductor layer 102 from being limited by the configuration of the outer deep well region 182 and the configuration of the deep well region 165. As a result, the breakdown voltage can be appropriately improved.

[0653] In particular, in the SiC semiconductor device 101, the outer region 112 is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 relative to the active region 111. This allows the position of the bottom of the outer deep well region 182 to be appropriately brought close to the position of the bottom of the deep well region 165.

[0654] That is, when forming outer deep well region 182, it is no longer necessary to introduce p-type impurities into a relatively deep position in the surface layer portion of first main surface 103 of SiC semiconductor layer 102. Therefore, it is possible to appropriately prevent the position of the bottom of outer deep well region 182 from shifting significantly from the position of the bottom of deep well region 165.

[0655] Moreover, in SiC semiconductor device 101, outer main surface 172 of outer region 112 is located on approximately the same plane as the bottom wall of source trench 155. This allows deep well region 165 and outer deep well region 182 to be formed at approximately the same depth when p-type impurities are introduced into the bottom wall of source trench 155 and outer main surface 172 of outer region 112 with equal energy.

[0656] As a result, the position of the bottom of the outer deep well region 182 can be more appropriately prevented from shifting significantly from the position of the bottom of the deep well region 165.

[0657] Moreover, according to the SiC semiconductor device 101, the field limit structure 183 is formed in the outer region 112. This makes it possible to obtain an electric field relaxation effect by the field limit structure 183 in the outer region 112. Therefore, the breakdown resistance of the SiC semiconductor layer 102 can be appropriately improved.

[0658] Furthermore, according to the SiC semiconductor device 101, the active region 111 is formed as a plateau-shaped active plateau 173. The active plateau 173 includes an active sidewall 174 that connects the active main surface 171 of the active region 111 and the outer main surface 172 of the outer region 112.

[0659] A step reduction structure is formed in the region between the active principal surface 171 and the outer principal surface 172 to reduce the step between the active principal surface 171 and the outer principal surface 172. The step reduction structure includes a sidewall 192.

[0660] This makes it possible to appropriately reduce the step between the active main surface 171 and the outer main surface 172. This makes it possible to appropriately improve the flatness of the upper layer structure formed on the sidewall 192. In the SiC semiconductor device 101, as an example of the upper layer structure, an interlayer insulating layer 201, a main surface source electrode layer 121, a passivation layer 125, and a resin layer 129 are formed.

[0661] Moreover, according to SiC semiconductor device 101, an anchor structure is formed in outer region 112 to increase the connection strength of resin layer 129. The anchor structure includes an uneven structure formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112.

[0662] More specifically, the uneven structure (anchor structure) includes unevenness formed in outer region 112 by utilizing interlayer insulating layer 201 formed on first main surface 103 of SiC semiconductor layer 102. Even more specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in interlayer insulating layer 201.

[0663] The resin layer 129 is engaged with the anchor hole 205. In this embodiment, the resin layer 129 is engaged with the anchor hole 205 via the passivation layer 125. This increases the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102, thereby appropriately suppressing peeling of the resin layer 129.

[0664] Furthermore, according to the SiC semiconductor device 101, a trench gate structure 161 is formed in which a gate electrode layer 149 is embedded in a gate trench 142 with a gate insulating layer 148 sandwiched therebetween. In this trench gate structure 161, the gate electrode layer 149 is covered with a low-resistance electrode layer 167 in the limited space of the gate trench 142. Such a structure can achieve the effects described with reference to FIG. 24 .

[0665] Fig. 24 is a graph for explaining the sheet resistance in the gate trench 142. In Fig. 24, the vertical axis represents the sheet resistance [Ω / □], and the horizontal axis represents the item. Fig. 24 shows a first bar graph BL1, a second bar graph BL2, and a third bar graph BL3.

[0666] The first bar graph BL1 represents the sheet resistance in the gate trench 142 filled with n-type polysilicon, and the second bar graph BL2 represents the sheet resistance in the gate trench 142 filled with p-type polysilicon.

[0667] A third bar graph BL3 represents the sheet resistance in the gate trench 142 in which the gate electrode layer 149 (p-type polysilicon) and the low-resistance electrode layer 167 are embedded. Here, a case will be described in which the low-resistance electrode layer 167 is formed from TiSi2 (p-type titanium silicide) as an example of polycide (silicide).

[0668] Referring to the first bar graph BL1, the sheet resistance in the gate trench 142 filled with n-type polysilicon was 10 Ω / □. Referring to the second bar graph BL2, the sheet resistance in the gate trench 142 filled with p-type polysilicon was 200 Ω / □. Referring to the third bar graph BL3, the sheet resistance in the gate trench 142 filled with the gate electrode layer 149 (p-type polysilicon) and the low resistance electrode layer 167 was 2 Ω / □.

[0669] P-type polysilicon has a work function different from that of n-type polysilicon. With a structure in which p-type polysilicon is buried in the gate trench 142, the gate threshold voltage Vth can be increased by about 1V.

[0670] However, p-type polysilicon has a sheet resistance several tens of times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for gate electrode layer 149, the energy loss increases significantly as the parasitic resistance in gate trench 142 (hereinafter simply referred to as "gate resistance") increases.

[0671] In contrast, with a structure having the low resistance electrode layer 167 on the gate electrode layer 149 (p-type polysilicon), the sheet resistance can be reduced to one hundredth or less compared to a case in which the low resistance electrode layer 167 is not formed. In other words, with a structure having the low resistance electrode layer 167, the sheet resistance can be reduced to one fifth or less compared to a gate electrode layer 149 including n-type polysilicon.

[0672] In this way, the structure having the low-resistance electrode layer 167 can reduce the sheet resistance in the gate trench 142 while increasing the gate threshold voltage Vth (for example, by about 1 V). This reduces the gate resistance, allowing current to be efficiently diffused along the trench gate structure 161. As a result, switching delay can be reduced.

[0673] Furthermore, the structure including the low-resistance electrode layer 167 eliminates the need to increase the p-type impurity concentration in the body region 141 and the p-type impurity concentration in the contact region 164. This makes it possible to appropriately increase the gate threshold voltage Vth while suppressing an increase in channel resistance.

[0674] The low-resistance electrode layer 167 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Of these materials, NiSi, CoSi2, and TiSi2 are particularly suitable as a polycide layer for forming the low-resistance electrode layer 167 because of their relatively small resistivity and temperature dependency.

[0675] Further testing by the inventors of the present application revealed that when TiSi2 was used as the material for the low-resistance electrode layer 167, an increase in the leakage current between the gate and source was observed when a low electric field was applied. In contrast, when CoSi2 was used, no increase in the leakage current between the gate and source was observed when a low electric field was applied. Taking this into consideration, CoSi2 is considered to be the most preferable polycide layer for forming the low-resistance electrode layer 167.

[0676] Furthermore, in the SiC semiconductor device 101, the gate wiring layer 150 is covered with the low-resistance electrode layer 167. This also makes it possible to reduce the gate resistance of the gate wiring layer 150.

[0677] In particular, in a structure in which the gate electrode layer 149 and the gate wiring layer 150 are covered with the low-resistance electrode layer 167, current can be efficiently diffused along the trench gate structure 161. Therefore, switching delay can be appropriately reduced.

[0678] Fig. 25 is an enlarged view of a region corresponding to Fig. 18, showing a SiC semiconductor device 221 according to a fourth embodiment of the present disclosure. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 25. In the following, structures corresponding to those described with respect to the SiC semiconductor device 101 are given the same reference numerals, and descriptions thereof will be omitted.

[0679] 25 and 26 , SiC semiconductor device 221 includes outer gate trench 222 formed in first main surface 103 of SiC semiconductor layer 102 in active region 111. Outer gate trench 222 extends in a strip shape along the periphery of active region 111.

[0680] The outer gate trench 222 is formed in a region directly below the outer gate finger 117 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 222 extends along the outer gate finger 117.

[0681] More specifically, the outer gate trench 222 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the inner region of the active region 111 from three directions. The outer gate trench 222 may be formed in an endless shape (for example, a rectangular ring shape) surrounding the inner region of the active region 111.

[0682] The outer gate trench 222 communicates with the contact trench portion 144 of each gate trench 142. As a result, the outer gate trench 222 and the gate trench 142 are formed by a single trench.

[0683] A gate wiring layer 150 is buried in the outer gate trench 222. The gate wiring layer 150 is connected to the gate electrode layer 149 at the communicating portion between the gate trench 142 and the outer gate trench 222.

[0684] A low-resistance electrode layer 167 covering the gate wiring layer 150 is formed in the outer gate trench 222. In this case, the low-resistance electrode layer 167 covering the gate electrode layer 149 and the low-resistance electrode layer 167 covering the gate wiring layer 150 are located within one trench.

[0685] As described above, the SiC semiconductor device 221 can also achieve the same effects as those described for the SiC semiconductor device 101. Furthermore, according to the SiC semiconductor device 221, it is not necessary to extend the gate wiring layer 150 onto the first main surface 103 of the SiC semiconductor layer 102.

[0686] This makes it possible to prevent the gate wiring layer 150 from facing the SiC semiconductor layer 102 across the gate insulating layer 148 at the opening edge 146 of the gate trench 142 (outer gate trench 222).As a result, it is possible to prevent electric field concentration at the opening edge 146 of the gate trench 142 (outer gate trench 222).

[0687] Fig. 27 is an enlarged view of a region corresponding to Fig. 21, showing a SiC semiconductor device 231 according to a fifth embodiment of the present disclosure. In the following, structures corresponding to those described with respect to the SiC semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0688] 27, in this embodiment, the SiC epitaxial layer 107 includes a high concentration region 108, a low concentration region 109, and a concentration gradient region 232 interposed between the high concentration region 108 and the low concentration region 109.

[0689] The concentration gradient region 232 is formed in the SiC epitaxial layer 107 not only in the active region 111 but also in the outer region 112. The concentration gradient region 232 is formed throughout the entire SiC epitaxial layer 107.

[0690] The concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high-concentration region 108 to the low-concentration region 109. In other words, the concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually increases from the low-concentration region 109 to the high-concentration region 108. The concentration gradient region 232 suppresses a sudden change in the n-type impurity concentration in the region between the high-concentration region 108 and the low-concentration region 109.

[0691] When SiC epitaxial layer 107 includes concentration gradient region 232, the n-type impurity concentration of high-concentration region 108 is preferably 1.5 to 5 times the n-type impurity concentration of low-concentration region 109. The n-type impurity concentration of high-concentration region 108 may be 3 to 5 times the n-type impurity concentration of low-concentration region 109.

[0692] The thickness of the concentration gradient region 232 may be 0.5 μm or more and 2.0 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2.0 μm or less.

[0693] Although a detailed description will be omitted, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc. are formed in the high concentration region .

[0694] That is, the aforementioned gate trench 142, source trench 155, deep well region 165, outer deep well region 182, etc. are formed in the region of the SiC semiconductor layer 102 on the first main surface 103 side relative to the boundary region between the high concentration region 108 and the concentration gradient region 232.

[0695] As described above, the SiC semiconductor device 231 can also achieve the same effects as those described for the SiC semiconductor device 101.

[0696] 28 is an enlarged view of a region corresponding to FIG. 18, showing a SiC semiconductor device 241 according to a sixth embodiment of the present disclosure. In the following, structures corresponding to those described with respect to the SiC semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0697] 28, in this embodiment, the gate trenches 142 are formed in a lattice shape in plan view. More specifically, the gate trenches 142 include a plurality of first gate trenches 242 and a plurality of second gate trenches 243. The plurality of first gate trenches 242 and the plurality of second gate trenches 243 form an active trench portion 143.

[0698] The multiple first gate trenches 242 are formed at intervals in the second direction Y, and are each formed in a strip shape extending along the first direction X. The multiple first gate trenches 242 are formed in a stripe shape as a whole in a plan view.

[0699] The sidewalls forming the long sides of each first gate trench 242 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of each first gate trench 242 are formed by the m-plane of the SiC single crystal.

[0700] The second gate trenches 243 are formed at intervals in the first direction X, and are each formed in a strip shape extending along the second direction Y. The second gate trenches 243 are formed in a stripe shape as a whole in a plan view.

[0701] The sidewalls forming the long sides of each second gate trench 243 are formed by the m-plane of the SiC single crystal. The sidewalls forming the short sides of each second gate trench 243 are formed by the a-plane of the SiC single crystal.

[0702] The first gate trenches 242 and the second gate trenches 243 intersect with each other, thereby forming a single lattice-shaped gate trench 142 in plan view. A plurality of cell regions 244 are defined in the area surrounded by the gate trench 142.

[0703] The multiple cell regions 244 are arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view. The multiple cell regions 244 are formed in a quadrangular shape in a plan view. In each cell region 244, the body region 141 is exposed from the sidewall of the gate trench 142. The body region 141 is exposed from the sidewall of the gate trench 142 formed by the m-plane and a-plane of the SiC single crystal.

[0704] Of course, the gate trench 142 may be formed in a honeycomb shape, which is one aspect of a lattice shape, in a plan view. In this case, the multiple cell regions 244 may be arranged in a staggered pattern at intervals in the first direction X and the second direction Y. In this case, the multiple cell regions 244 may also be formed in a hexagonal shape in a plan view.

[0705] Each source trench 155 is formed in the center of each cell region 244 in plan view. Each source trench 155 is formed in a pattern that appears alone on a cut surface that appears when each cell region 244 is cut along the first direction X. Also, each source trench 155 is formed in a pattern that appears alone on a cut surface that appears when each cell region 244 is cut along the second direction Y.

[0706] More specifically, each source trench 155 is formed in a quadrangular shape in plan view. The four side walls of each source trench 155 are formed by the m-plane and a-plane of the SiC single crystal.

[0707] The planar shape of each source trench 155 is arbitrary. Each source trench 155 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, or a hexagonal shape, or in a circular or elliptical shape in plan view.

[0708] The cross-sectional view taken along line XIX-XIX in Fig. 28 corresponds to the cross-sectional view shown in Fig. 19. The cross-sectional view taken along line XX-XX in Fig. 28 corresponds to the cross-sectional view shown in Fig. 20.

[0709] As described above, the SiC semiconductor device 241 can also achieve the same effects as those described for the SiC semiconductor device 101.

[0710] Although the embodiments of the present disclosure have been described, the embodiments of the present disclosure may be embodied in other forms.

[0711] In the above-described embodiments, the side surfaces 5A, 105A and 5C, 105C of the SiC semiconductor layers 2, 102 face the a-plane of the SiC single crystal, and the side surfaces 5B, 105B and 5D, 105D face the m-plane of the SiC single crystal. However, a configuration may also be employed in which the side surfaces 5A, 105A and 5C, 105C face the m-plane of the SiC single crystal, and the side surfaces 5B, 105B and 5D, 105D face the a-plane of the SiC single crystal.

[0712] In each of the above-described embodiments, examples have been described in which the reforming lines 22A-22D are formed in the shape of a continuously extending band. However, in each of the above-described embodiments, the reforming lines 22A-22D may be formed in the shape of a broken band (dashed line). That is, the reforming lines 22A-22D may be formed in the shape of a band that extends intermittently. In this case, one, two, or three of the reforming lines 22A-22D may be formed in the shape of a broken band, and the rest may be formed in the shape of a band.

[0713] In the above-described third to sixth embodiments, examples have been described in which a plurality of gate trenches 142 (first gate trenches 242) extending along the m-axis direction ([1-100] direction) of the SiC single crystal are formed.

[0714] However, a plurality of gate trenches 142 (first gate trenches 242) extending along the a-axis direction ([11-20] direction) of the SiC single crystal may be formed. In this case, a plurality of source trenches 155 extending along the a-axis direction ([11-20] direction) of the SiC single crystal are formed.

[0715] In the third to sixth embodiments described above, the source electrode layer 157 is embedded in the source trench 155 with the source insulating layer 156 sandwiched therebetween. However, the source electrode layer 157 may be embedded directly in the source trench 155 without the source insulating layer 156 interposed therebetween.

[0716] In the above-described third to sixth embodiments, examples in which the source insulating layer 156 is formed along the sidewalls and bottom wall of the source trench 155 have been described.

[0717] However, the source insulating layer 156 may be formed along the sidewalls of the source trench 155 so as to expose the bottom wall of the source trench 155. The source insulating layer 156 may be formed along the sidewalls and bottom wall of the source trench 155 so as to expose a portion of the bottom wall of the source trench 155.

[0718] Furthermore, the source insulating layer 156 may be formed along the bottom wall of the source trench 155 so as to expose the side wall of the source trench 155. The source insulating layer 156 may be formed along the side wall and bottom wall of the source trench 155 so as to expose a portion of the side wall of the source trench 155.

[0719] In the third to sixth embodiments described above, examples have been described in which the gate electrode layer 149 and the gate wiring layer 150 include p-type polysilicon doped with p-type impurities. However, when increasing the gate threshold voltage Vth is not a priority, the gate electrode layer 149 and the gate wiring layer 150 may include n-type polysilicon doped with n-type impurities instead of or in addition to p-type polysilicon.

[0720] In this case, the low-resistance electrode layer 167 may be formed by silicidating a surface portion of the gate electrode layer 149 (n-type polysilicon) with a metal material. That is, the low-resistance electrode layer 167 may include n-type polycide. With such a structure, it is possible to reduce the gate resistance.

[0721] In the third to sixth embodiments, n + Instead of the SiC semiconductor substrate 106, + Alternatively, a SiC semiconductor substrate (106) of the type described above may be employed. With this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in each of the above-described embodiments, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT.

[0722] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0723] The above-described embodiments can also be applied to semiconductor devices using semiconductor materials other than SiC. The semiconductor material other than SiC may be a compound semiconductor material. The compound semiconductor material may be either or both of gallium nitride (GaN) and gallium oxide (Ga2O3).

[0724] For example, the third to sixth embodiments may be compound semiconductor devices including vertical compound semiconductor MISFETs in which a compound semiconductor material is used instead of SiC. In the compound semiconductor, magnesium may be used as a p-type impurity (acceptor). Furthermore, germanium (Ge), oxygen (O), or silicon (Si) may be used as an n-type impurity (donor).

[0725] Below are some examples of features extracted from this specification and drawings.

[0726] [A1] A SiC semiconductor device comprising: a SiC semiconductor layer including a SiC single crystal and having a first main surface as an element formation surface, a second main surface opposite the first main surface, and a side surface connecting the first main surface and the second main surface; an insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface formed flush with the side surface of the SiC semiconductor layer; an electrode formed on the insulating layer; and a modified layer formed on the side surface of the SiC semiconductor layer and modified to have properties different from those of the SiC single crystal.

[0727] According to this SiC semiconductor device, in a structure in which a modified layer is formed on the side surface of the SiC semiconductor layer, the insulating layer can improve the insulation between the side surface of the SiC semiconductor layer and the electrode, thereby improving the stability of the electrical characteristics of the SiC semiconductor layer.

[0728] [A2] The SiC semiconductor device according to A1, wherein the modified layer is formed at a midpoint in the thickness direction of the SiC semiconductor layer with a gap between the modified layer and the insulating layer.

[0729] [A3] The SiC semiconductor device according to A1 or A2, wherein the SiC semiconductor layer has a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, and the first main surface is formed by the SiC epitaxial layer, the insulating layer covers the SiC epitaxial layer, and the modified layer is formed in a region of the SiC semiconductor substrate.

[0730] [A4] The SiC semiconductor device according to A3, wherein the modified layer is formed on the SiC semiconductor substrate, avoiding the SiC epitaxial layer.

[0731] [A5] The SiC semiconductor device according to A3 or A4, wherein the SiC epitaxial layer has a thickness equal to or less than that of the SiC semiconductor substrate.

[0732] [A6] The SiC semiconductor device according to any one of A3 to A5, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[0733] [B1] A method for manufacturing a SiC semiconductor device, comprising: a step of preparing a SiC semiconductor wafer including a SiC single crystal and having a first main surface on which a device formation region having a plurality of sides is set, and a second main surface opposite the first main surface; a step of irradiating a laser beam into the interior of the SiC semiconductor wafer along the plurality of sides of the device formation region to form a plurality of modification lines modified to have properties different from those of the SiC single crystal, one layer at a time, in a one-to-one correspondence with the plurality of sides of the device formation region; and a step of cutting the SiC semiconductor wafer along the plurality of modification lines.

[0734] According to this manufacturing method, it is possible to manufacture and provide a SiC semiconductor device including a SiC semiconductor layer that includes a SiC single crystal and has a first main surface as an element formation surface, a second main surface opposite the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modification lines that are formed one on each of the side surfaces of the SiC semiconductor layer, each extending in a band shape along a tangent direction to the first main surface of the SiC semiconductor layer, and that have been modified to have properties different from those of the SiC single crystal.

[0735] [B2] The method for manufacturing a SiC semiconductor device according to B1, further comprising the step of grinding the second main surface of the SiC semiconductor wafer prior to the step of cutting the SiC semiconductor wafer.

[0736] [B3] The method for manufacturing a SiC semiconductor device according to B2, wherein the step of forming the modification line is carried out prior to the grinding step.

[0737] [B4] The method for manufacturing a SiC semiconductor device according to B2, wherein the step of forming the modification line is carried out after the grinding step.

[0738] [B5] The method for manufacturing a SiC semiconductor device according to any one of B2 to B4, wherein the SiC semiconductor wafer preparation step includes a step of preparing the SiC semiconductor wafer having a thickness exceeding 150 μm, and the grinding step includes a step of grinding the SiC semiconductor wafer until the SiC semiconductor wafer has a thickness of 40 μm or more and 150 μm or less.

[0739] [B6] The method for manufacturing a SiC semiconductor device according to any one of B1 to B5, wherein the forming step of the modification line includes a step of irradiating laser light from the first main surface side of the SiC semiconductor wafer to the inside of the SiC semiconductor wafer.

[0740] [B7] The method for manufacturing a SiC semiconductor device according to any one of B1 to B5, wherein the forming step of the modification line includes a step of irradiating laser light from the second main surface side of the SiC semiconductor wafer to the inside of the SiC semiconductor wafer.

[0741] [B8] A method for manufacturing a SiC semiconductor device, comprising: a step of preparing a SiC semiconductor wafer including a SiC single crystal and having a first main surface on which a device formation region having a plurality of sides is set, and a second main surface opposite the first main surface; a step of forming an insulating layer on the first main surface of the SiC semiconductor wafer; a step of forming an electrode on the insulating layer; a step of forming a plurality of modified layers modified to have properties different from those of the SiC single crystal by irradiating laser light into the interior of the SiC semiconductor wafer along the plurality of sides of the device formation region; and a step of cutting the SiC semiconductor wafer together with the insulating layer along the plurality of modified layers.

[0742] According to this manufacturing method, it is possible to manufacture and provide a SiC semiconductor device including: a SiC semiconductor layer that includes a SiC single crystal and has a first main surface as an element formation surface, a second main surface opposite the first main surface, and a side surface connecting the first main surface and the second main surface; an insulating layer that includes an insulating material and covers the first main surface of the SiC semiconductor layer and has an insulating side surface formed flush with the side surface of the SiC semiconductor layer; a main surface electrode layer formed on the insulating layer; and a modified layer that is formed on the side surface of the SiC semiconductor layer and has properties different from those of the SiC single crystal.

[0743] [B9] A method for manufacturing a SiC semiconductor device, comprising: a step of preparing a SiC semiconductor wafer including a SiC single crystal and having a first main surface on which a device formation region having a plurality of sides is set, and a second main surface opposite to the first main surface; a step of forming an insulating layer on the first main surface of the SiC semiconductor wafer; a step of partially removing the insulating layer and forming openings in the insulating layer that expose the plurality of sides of the device formation region; a step of irradiating a laser beam into the interior of the SiC semiconductor wafer along the plurality of sides of the device formation region to form a plurality of modified layers that have properties different from those of the SiC single crystal; and a step of cutting the SiC semiconductor wafer along the plurality of modified layers.

[0744] [B10] The method for manufacturing a SiC semiconductor device according to B8 or B9, further comprising the step of grinding the second main surface of the SiC semiconductor wafer.

[0745] [B11] The method for manufacturing a SiC semiconductor device according to B10, wherein the step of forming the modification line is carried out prior to the grinding step.

[0746] [B12] The method for manufacturing a SiC semiconductor device according to B10, wherein the step of forming the modification line is carried out after the step of grinding.

[0747] [B13] The method for manufacturing a SiC semiconductor device according to any one of B10 to B12, wherein the SiC semiconductor wafer preparation step includes a step of preparing the SiC semiconductor wafer having a thickness exceeding 150 μm, and the grinding step includes a step of grinding the SiC semiconductor wafer until the SiC semiconductor wafer has a thickness of 40 μm or more and 150 μm or less.

[0748] [C1] A SiC semiconductor device comprising: a SiC semiconductor layer including a SiC single crystal, the SiC semiconductor layer having a first main surface as an element formation surface, a second main surface opposite the first main surface, and a side surface connecting the first main surface and the second main surface; and a plurality of modified layers formed at intervals from the first main surface to the second main surface of the SiC semiconductor layer so as to expose a surface portion of the first main surface of the SiC semiconductor layer from the side surface of the SiC semiconductor layer, the modified layers having properties different from those of the SiC single crystal.

[0749] The modified layer is formed by modifying the SiC single crystal of the SiC semiconductor layer to give it different properties, so it is prone to becoming a starting point for cracks. In particular, stress tends to concentrate at the corners connecting the first principal surface and side surface of the SiC semiconductor layer, so in a structure in which the modified layer is formed at the corners of the SiC semiconductor layer, there is a higher risk of cracks occurring at the corners of the SiC semiconductor layer.

[0750] In this SiC semiconductor device, the modified layer is formed at a distance from the first main surface to the second main surface of the SiC semiconductor layer so that the surface layer portion of the first main surface of the SiC semiconductor layer is exposed from the side surface of the SiC semiconductor layer, thereby reducing the risk of cracks occurring at the corners on the first main surface side of the SiC semiconductor layer.

[0751] [C2] A SiC semiconductor device comprising: a SiC semiconductor layer including a SiC single crystal, the SiC semiconductor layer having a first main surface as an element formation surface, a second main surface opposite the first main surface, and a side surface connecting the first main surface and the second main surface; and a plurality of modified layers formed at intervals from the second main surface to the first main surface of the SiC semiconductor layer so as to expose a surface portion of the second main surface of the SiC semiconductor layer from the side surface of the SiC semiconductor layer, the modified layers having properties different from those of the SiC single crystal.

[0752] The modified layer is formed by modifying the SiC single crystal of the SiC semiconductor layer to give it different properties, so it is prone to becoming a starting point for cracks. In particular, stress tends to concentrate at the corners connecting the second principal surface and the side surface of the SiC semiconductor layer, so in a structure in which a modified layer is formed at the corners of the SiC semiconductor layer, there is a higher risk of cracks occurring at the corners of the SiC semiconductor layer.

[0753] In this SiC semiconductor device, the modified layer is formed at a distance from the second main surface to the first main surface of the SiC semiconductor layer so that the surface layer portion of the second main surface of the SiC semiconductor layer is exposed from the side surface of the SiC semiconductor layer, thereby reducing the risk of cracks occurring at corners on the second main surface side of the SiC semiconductor layer.

[0754] The reforming lines are formed by modifying the SiC single crystal of the SiC semiconductor layer to have different properties. Therefore, considering the influence of the reforming lines on the SiC semiconductor layer, it is not desirable to form multiple reforming lines across the entire side surface of the SiC semiconductor layer. Examples of the influence of the reforming lines on the SiC semiconductor layer include fluctuations in the electrical properties of the SiC semiconductor layer due to the reforming lines and the occurrence of cracks in the SiC semiconductor layer originating from the reforming lines.

[0755] The following [D1] to [D20] and [E1] to [E20] aim to provide a SiC semiconductor device that can reduce the influence of the reforming line on the SiC semiconductor layer.

[0756] [D1] A SiC semiconductor device including a SiC semiconductor layer including a SiC single crystal, the SiC semiconductor layer having a first main surface as an element formation surface, a second main surface opposite the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of reforming lines formed one on each of the side surfaces of the SiC semiconductor layer, each extending in a strip shape along a tangential direction of the first main surface of the SiC semiconductor layer, and reformed to have properties different from those of the SiC single crystal. According to this SiC semiconductor device, only one reforming line is formed on each side surface of the SiC semiconductor layer. Therefore, the influence of the reforming lines on the SiC semiconductor layer can be reduced.

[0757] [D2] The SiC semiconductor device according to D1, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

[0758] [D3] The SiC semiconductor device according to D1 or D2, wherein the second main surface of the SiC semiconductor layer is a ground surface.

[0759] [D4] The SiC semiconductor device according to any one of D1 to D3, wherein the modification lines are formed at intervals from the first main surface to the second main surface of the SiC semiconductor layer.

[0760] [D5] The SiC semiconductor device according to any one of D1 to D4, wherein each of the reforming lines is formed at an interval from the second main surface to the first main surface of the SiC semiconductor layer.

[0761] [D6] A SiC semiconductor device described in any one of D1 to D5, wherein the SiC semiconductor layer includes a corner portion connecting the two side surfaces, and the multiple reforming lines include two reforming lines connected at the corner portion of the SiC semiconductor layer.

[0762] [D7] The SiC semiconductor device according to any one of D1 to D6, wherein the plurality of reforming lines are integrally formed so as to surround the SiC semiconductor layer.

[0763] [D8] The SiC semiconductor device according to any one of D1 to D7, wherein each of the reforming lines extends in a straight line or a curved line.

[0764] [D9] A SiC semiconductor device described in any one of D1 to D8, wherein each of the modification lines extends in the normal direction of the first main surface of the SiC semiconductor layer and includes a plurality of modification portions that face each other in the tangential direction of the first main surface of the SiC semiconductor layer.

[0765] [D10] The SiC semiconductor device according to any one of D1 to D9, wherein each of the side surfaces of the SiC semiconductor layer is a cleavage plane.

[0766] [D11] The SiC semiconductor device according to any one of D1 to D10, wherein the SiC single crystal is made of a hexagonal crystal.

[0767] [D12] The SiC semiconductor device according to D11, wherein the SiC single crystal is made of a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[0768] [D13] The SiC semiconductor device according to D11 or D12, wherein the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.

[0769] [D14] The SiC semiconductor device according to any one of D11 to D13, wherein the first main surface of the SiC semiconductor layer has an off-angle inclined at an angle of 0° or more and 10° or less with respect to the c-plane of the SiC single crystal.

[0770] [D15] The SiC semiconductor device according to D14, wherein the off angle is an angle of 5° or less.

[0771] [D16] The SiC semiconductor device according to D14 or D15, wherein the off angle is greater than 0° and less than 4°.

[0772] [D17] A SiC semiconductor device according to any one of D1 to D16, wherein the SiC semiconductor layer has a layered structure including a SiC semiconductor substrate and a SiC epitaxial layer, and the first main surface is formed by the SiC epitaxial layer, and the modification line is formed in a region of the SiC semiconductor substrate.

[0773] [D18] The SiC semiconductor device according to D17, wherein the reforming line is formed in the SiC semiconductor substrate to avoid the SiC epitaxial layer.

[0774] [D19] The SiC semiconductor device according to D17 or D18, wherein the SiC epitaxial layer has a thickness equal to or less than that of the SiC semiconductor substrate.

[0775] [D20] The SiC semiconductor device according to any one of D17 to D19, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[0776] [E1] A SiC semiconductor device comprising: a SiC semiconductor layer having a stacked structure including a SiC semiconductor substrate including a SiC single crystal, the SiC semiconductor substrate having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface and each formed of a cleavage plane, and a SiC epitaxial layer forming the first main surface and a portion of the side surface; and a plurality of reforming lines formed one by one in a portion of the SiC semiconductor substrate on each of the side surfaces of the SiC semiconductor layer, spaced apart from the SiC epitaxial layer toward the second main surface, the reforming lines each extending in a band shape along a tangential direction of the first main surface of the SiC semiconductor layer, and having properties different from those of the SiC single crystal.

[0777] [E2] The SiC semiconductor device according to E1, further comprising an insulating layer covering the SiC epitaxial layer on the first main surface and having insulating sidewalls continuous with each of the side surfaces.

[0778] [E3] The SiC semiconductor device according to E2, further comprising a first electrode formed on the insulating layer and spaced inward from each of the side surfaces.

[0779] [E4] The SiC semiconductor device according to E3, further comprising a resin layer formed on the insulating layer at a distance inward from each of the side surfaces, the resin layer having an opening through which the first electrode is exposed.

[0780] [E5] The SiC semiconductor device according to any one of E1 to E4, further comprising a second electrode covering the entire second main surface.

[0781] [E6] The SiC semiconductor device according to any one of E1 to E5, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

[0782] [E7] The SiC semiconductor device according to any one of E1 to E6, wherein the second main surface of the SiC semiconductor layer is a ground surface.

[0783] [E8] The SiC semiconductor device according to any one of E1 to E7, wherein the modification lines are formed at intervals from the second main surface of the SiC semiconductor layer toward the first main surface.

[0784] [E9] A SiC semiconductor device described in any one of E1 to E8, wherein the SiC semiconductor layer includes a corner portion connecting the two side surfaces, and the multiple reforming lines include two reforming lines connected at the corner portion of the SiC semiconductor layer.

[0785] [E10] The SiC semiconductor device according to any one of E1 to E9, wherein the plurality of reforming lines are integrally formed so as to surround the SiC semiconductor layer.

[0786] [E11] The SiC semiconductor device according to any one of E1 to E10, wherein each of the reforming lines extends in a straight line or a curved line.

[0787] [E12] A SiC semiconductor device described in any one of E1 to E11, wherein each of the modification lines extends in the normal direction of the first main surface of the SiC semiconductor layer and includes a plurality of modification portions that face each other in the tangential direction of the first main surface of the SiC semiconductor layer.

[0788] [E13] The SiC semiconductor device according to any one of E1 to E12, wherein the SiC single crystal is a hexagonal crystal.

[0789] [E14] The SiC semiconductor device according to E13, wherein the SiC single crystal is made of a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.

[0790] [E15] The SiC semiconductor device according to E13 or E14, wherein the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.

[0791] [E16] The SiC semiconductor device according to any one of E13 to E15, wherein the first main surface of the SiC semiconductor layer has an off-angle inclined at an angle of 0° or more and 10° or less with respect to the c-plane of the SiC single crystal.

[0792] [E17] The SiC semiconductor device according to E16, wherein the off angle is an angle of 5° or less.

[0793] [E18] The SiC semiconductor device according to E16 or E17, wherein the off angle is greater than 0° and less than 4°.

[0794] [E19] The SiC semiconductor device according to any one of E1 to E18, wherein the SiC epitaxial layer has a thickness equal to or less than that of the SiC semiconductor substrate.

[0795] [E20] The SiC semiconductor device according to any one of E1 to E19, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[0796] [F1] A SiC semiconductor device comprising: a SiC semiconductor chip having a layered structure including a SiC semiconductor substrate and a SiC epitaxial layer, the SiC semiconductor chip having an element formation surface formed by the SiC epitaxial layer and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer; and a single modified layer formed on the side surface in a portion consisting of the SiC semiconductor substrate, spaced apart from the SiC epitaxial layer, and modified to have properties different from those of the SiC semiconductor substrate.

[0797] [F2] The SiC semiconductor device according to F1, wherein the modified layer is formed in a strip shape extending along the element formation surface.

[0798] [F3] The SiC semiconductor device according to F1 or F2, wherein the side surface is a cleavage plane.

[0799] [F4] The SiC semiconductor device according to any one of F1 to F3, wherein the SiC semiconductor chip has a back surface made of a ground surface formed by the SiC semiconductor substrate.

[0800] [F5] The SiC semiconductor device according to F4, wherein the modified layer is formed at an interval from the back surface toward the element forming surface.

[0801] [F6] The SiC semiconductor device according to any one of F1 to F5, wherein the modified layer is formed in the shape of a strip extending linearly or a strip extending curvedly.

[0802] [F7] A SiC semiconductor device described in any one of F1 to F6, wherein the modified layer is formed by a collection of multiple modified portions each extending in a normal direction of the element forming surface and facing each other in a tangential direction of the element forming surface.

[0803] [F8] The SiC semiconductor device according to any one of F1 to F7, wherein the SiC semiconductor chip is made of a hexagonal crystal.

[0804] [F9] The SiC semiconductor device according to any one of F1 to F8, wherein the SiC semiconductor chip is made of 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, or 6H-SiC single crystal.

[0805] [F10] The SiC semiconductor device according to any one of F1 to F9, wherein the element formation surface faces the c-plane of the SiC single crystal.

[0806] [F11] The SiC semiconductor device according to any one of F1 to F10, wherein the element formation surface has an off-axis angle.

[0807] [F12] The SiC semiconductor device according to F11, wherein the off angle is an angle exceeding 0° and less than 4°.

[0808] [F13] The SiC semiconductor device according to any one of F1 to F12, wherein the SiC semiconductor chip has a thickness of 40 μm or more and 200 μm or less.

[0809] [F14] The SiC semiconductor device according to any one of F1 to F13, wherein the SiC epitaxial layer has a thickness less than that of the SiC semiconductor substrate.

[0810] [F15] The SiC semiconductor device according to any one of F1 to F14, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[0811] [F16] The SiC semiconductor device according to any one of F1 to F15, further comprising an insulating layer formed on the element formation surface, and an electrode formed on the insulating layer.

[0812] [F17] The SiC semiconductor device according to F16, wherein the electrode is formed on the insulating layer at a distance from the side surface.

[0813] [F18] The SiC semiconductor device according to F16 or F17, wherein the insulating layer has an insulating side surface that is continuous with the side surface.

[0814] [F19] The SiC semiconductor device according to any one of F16 to F18, further comprising a passivation layer covering the electrode, and a resin layer covering the passivation layer.

[0815] [F20] A SiC semiconductor device comprising: an SiC semiconductor chip having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface; a first impurity region of a first conductivity type formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a second impurity region of a first conductivity type having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the first impurity region, exposed from the second main surface and the side surface, and formed in a region on the second main surface side relative to the first impurity region so as to be electrically connected to the first impurity region; and a single modified layer formed on the side surface at a distance from the first impurity region where the second impurity region is exposed, the single modified layer having properties different from those of the SiC semiconductor chip.

[0816] [G1] A SiC chip having a first main surface on one side and a second main surface and a side surface on the other side; a first conductivity type semiconductor substrate exposed from the side surface of the SiC chip; a first conductivity type semiconductor region formed on a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a pn junction region formed on a surface layer portion of the first main surface at a peripheral portion of the first main surface; and a pn junction region formed on a surface layer portion of the semiconductor region at a peripheral portion of the first main surface, A SiC semiconductor device comprising: a second conductivity type impurity region that forms a connection region; and a single reforming line that is formed on the side surface at a distance from a depth position of the pn connection region toward the second main surface, and that is reformed to have properties different from SiC, wherein the reforming line is formed on the side surface at a distance from a depth position of the substrate main surface of the semiconductor substrate toward the second main surface, and the reforming line has a plurality of reforming portions that each extend in a normal direction to the first main surface, and the reforming portions have a tapered shape that narrows toward the second main surface.

[0817] [G2] The SiC semiconductor device according to G1, wherein the pn junction region is formed at an interval from the side surface inwardly of the first main surface.

[0818] [G3] an active region provided in an inner portion of the first main surface; an outer region provided at a peripheral edge of the first main surface, The SiC semiconductor device according to G1 or G2, wherein the pn junction region is formed in the outer region.

[0819] [G4] The SiC semiconductor device according to G3, further comprising a diode structure formed on the first main surface of the active region.

[0820] [G5] The SiC semiconductor device described in G4, wherein the diode structure includes a diode region formed in a surface layer portion of the first main surface of the active region, and an electrode electrically connected to the diode region on the first main surface.

[0821] [G6] The SiC semiconductor device according to any one of G3 to G5, further including a field effect transistor structure formed on the first main surface of the active region.

[0822] [G7] The SiC semiconductor device described in G6, wherein the transistor structure includes a body region formed in a surface layer portion of the first main surface of the active region, a trench gate structure formed in the first main surface so as to penetrate the body region, and a source region formed in a region along the trench gate structure in the surface layer portion of the body region.

[0823] [G8] The SiC semiconductor device according to G7, wherein the reforming line is formed on the side surface at an interval from a depth position of the bottom wall of the trench gate structure toward the second main surface.

[0824] [G9] A SiC semiconductor device according to G7 or G8, wherein the active region has an active main surface consisting of a part of the first main surface, the outer region has an outer main surface recessed from the active main surface toward the second main surface so as to divide the active region into a plateau shape, and the pn junction region is formed in a surface layer portion of the outer main surface.

[0825] [G10] The SiC semiconductor device according to G9, wherein the outer main surface is continuous with the side surface.

[0826] [G11] The SiC semiconductor device according to claim 1, further comprising an insulating film covering said pn junction region on said first main surface.

[0827] [G12] The SiC semiconductor device according to G11, further comprising a resin layer covering the insulating film.

[0828] [G13] A SiC chip having a first main surface on one side, a second main surface on the other side, and a side surface; a first surface portion located in an inner portion of the first main surface; a second surface portion formed on a peripheral edge of the first main surface so as to be recessed from the first surface portion toward the second main surface; a plateau defined on the first main surface by a connecting sidewall connecting the first surface portion and the second surface portion; a first conductivity type semiconductor substrate exposed from the side surface of the SiC chip; a first conductivity type semiconductor region stacked on the substrate main surface of the semiconductor substrate and formed on a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a pn junction region formed in a surface layer of the semiconductor region, a second conductivity type impurity region formed in the surface layer of the semiconductor region and forming the semiconductor region and the pn junction region; and a single reformed line formed on the side surface at a distance from a depth position of the pn junction region toward the second main surface, the single reformed line having properties different from those of SiC, the reformed line being formed on the side surface at a distance from a depth position of the substrate main surface of the semiconductor substrate toward the second main surface, the reformed line having a plurality of reformed portions each extending in a normal direction of the first main surface, and the reformed portions having a tapered shape narrowing toward the second main surface.

[0829] [G14] The SiC semiconductor device according to G13, wherein the second surface portion is continuous with the side surface, and the pn junction region is formed at an interval from the side surface toward the first surface portion.

[0830] [G15] The SiC semiconductor device according to G113 or G14, further including: a body region formed in a surface layer portion of the first surface portion; a trench gate structure formed in the first surface portion so as to penetrate the body region; and a source region formed in a region along the trench gate structure in the surface layer portion of the body region.

[0831] [G16] The SiC semiconductor device according to G15, wherein the second surface portion is located closer to the second main surface than a depth position of a bottom wall of the trench gate structure.

[0832] This specification does not limit any combination of the features shown in the first to sixth embodiments. The first to sixth embodiments can be combined in any manner and in any form. In other words, the features shown in the first to sixth embodiments can be combined in any manner and in any form.

[0833] In addition, various design modifications...

Claims

1. a SiC chip having a first main surface on one side and a second main surface and a side surface on the other side; a semiconductor substrate of a first conductivity type exposed from the side surface of the SiC chip; a first conductivity type semiconductor region including an epitaxial layer stacked on a substrate main surface of the semiconductor substrate, the first conductivity type semiconductor region being formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a pn junction region formed in a surface layer portion of the first main surface at a peripheral portion of the first main surface; an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region in a peripheral portion of the first main surface, the impurity region forming the pn junction region with the semiconductor region; and a modification line formed on the semiconductor substrate other than an epitaxial layer and modified to have properties different from SiC; the side surface has a first side surface and a second side surface connected to the first side surface and extending along a direction intersecting the first side surface; the reforming line includes a first reforming line formed on the first side surface and a second reforming line formed on the second side surface, A SiC semiconductor device, wherein the thickness of the first reformed line and the thickness of the second reformed line are different from each other in a normal direction of the first main surface.

2. 2 . The SiC semiconductor device according to claim 1 , wherein a depth position of the first reformed line and a depth position of the second reformed line are different from each other in a normal direction of the first main surface.

3. The SiC semiconductor device according to claim 1 , wherein the first modification line has a portion that extends linearly along a tangential direction of the first main surface.

4. The SiC semiconductor device according to any one of claims 1 to 3, wherein the second modification line has a portion that extends linearly along a tangent direction of the first main surface.

5. 5. The SiC semiconductor device according to claim 1, wherein the pn junction region is formed at a distance from the side surface inwardly of the first main surface.

6. an active region provided in an inner portion of the first main surface; an outer region provided at a peripheral portion of the first main surface, 6. The SiC semiconductor device according to claim 1, wherein the pn junction region is formed in the outer region.

7. The SiC semiconductor device according to claim 6 , further comprising a diode structure formed on the first main surface of the active region.

8. The diode structure comprises: a diode region formed in a surface layer portion of the first main surface of the active region; an electrode electrically connected to said diode region on said first main surface;

9. The SiC semiconductor device according to claim 6 , further comprising a field effect transistor structure formed on said first main surface of said active region.

10. The transistor structure comprises: a body region formed in a surface layer portion of the first main surface of the active region; a trench gate structure formed in the first major surface so as to penetrate the body region; 10. The SiC semiconductor device according to claim 9, further comprising: a source region formed in a surface layer portion of the body region in a region along the trench gate structure.

11. The SiC semiconductor device according to claim 10 , wherein the reforming line is formed on the side surface at a distance from a depth position of the bottom wall of the trench gate structure toward the second main surface.

12. the active region has an active main surface that is a part of the first main surface, the outer region has an outer main surface recessed toward the second main surface with respect to the active main surface so as to divide the active region into a plateau shape, The SiC semiconductor device according to claim 10 , wherein the pn junction region is formed in a surface layer portion of the outer main surface.

13. The SiC semiconductor device according to claim 12 , wherein the outer main surface is continuous with the side surface.

14. The SiC semiconductor device according to any one of claims 1 to 13, further comprising an insulating film covering the pn junction region on the first main surface.

15. The SiC semiconductor device according to claim 14 , further comprising a resin layer covering the insulating film.

16. a SiC chip having a first main surface on one side and a second main surface and a side surface on the other side; a first surface portion located in an inner portion of the first main surface, a second surface portion formed on a peripheral edge portion of the first main surface so as to be recessed from the first surface portion toward the second main surface, and a plateau defined on the first main surface by a connecting sidewall connecting the first surface portion and the second surface portion; a semiconductor substrate of a first conductivity type exposed from the side surface of the SiC chip; a first conductivity type semiconductor region including an epitaxial layer stacked on a substrate main surface of the semiconductor substrate, the first conductivity type semiconductor region being formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface; a pn junction region formed in a surface layer portion of the second surface portion; an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region and forming the pn junction region with the semiconductor region; and a modification line formed on the semiconductor substrate other than an epitaxial layer and modified to have properties different from SiC; the side surface has a first side surface and a second side surface connected to the first side surface and extending along a direction intersecting the first side surface; the reforming line includes a first reforming line formed on the first side surface and a second reforming line formed on the second side surface, A SiC semiconductor device, wherein the thickness of the first reformed line and the thickness of the second reformed line are different from each other in a normal direction of the first main surface.

17. The SiC semiconductor device according to claim 16 , wherein a depth position of the first reforming line and a depth position of the second reforming line are different from each other in a normal direction of the first main surface.

18. The SiC semiconductor device according to claim 16 or 17, wherein the first modification line has a portion that extends linearly along a tangential direction of the first main surface.

19. The SiC semiconductor device according to any one of claims 16 to 18, wherein the second modification line has a portion that extends linearly along a tangent direction of the first main surface.

20. The second surface portion is continuous with the side surface, The SiC semiconductor device according to any one of claims 16 to 19, wherein the pn junction region is formed at an interval from the side surface toward the first surface portion.

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