Two phase clock generation circuit

Abstract

To provide a two phase clock generating circuit in which the relation between a leading edge and a trailing edge being a gap of non-overlapped two phase clocks is required to be uniform.SOLUTION: The two phase clock generation circuit 10 includes a logic high-side non-overlap signal generation circuit 2 and a four terminal circuit 1a, and the four terminal circuit 1a includes a first N-channel MOS transistor 11, a second N-channel MOS transistor 12 that is laid out adjacent to the first N-channel MOS transistor 11 and has substantially the same area, the same aspect ration, and the same current direction as the first N-channel MOS transistor 11, a first P-channel MOS transistor 13, and a second P-channel MOS transistor 14 that is laid out adjacent to the first P-channel MOS transistor 13 and has substantially the same area, the same aspect ration, and the same current direction as the first P-channel MOS transistor 13; And a connection of two resistors 5a, 5b or conductors having substantially equal resistance values.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a two-phase clock generation circuit. [Background technology]

[0002] There are systems in which it is necessary to make the relationship between the rising and falling edges, which are the gaps between non-overlapping two-phase clocks, equivalent, and technology has been proposed to generate complementary NRZ signals (two-phase clocks) with little skew from a single NRZ signal (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-127845 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-128988 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the adjustment mechanism in Patent Document 1 requires a complex logic circuit and is large in scale to implement. In addition, the control loop has a delay circuit, which raises concerns about increased jitter.

[0005] The circuit configuration of Patent Document 2 does not require adjustment and is smaller in scale than Patent Document 1, but the occurrence of a delay error equivalent to one stage of an inverter circuit is unavoidable.

[0006] The present invention provides a two-phase clock generation circuit that requires uniformity in the relationship between the rising edge and the falling edge, which is the gap between non-overlapping two-phase clocks. [Means for solving the problem]

[0007] The two-phase clock generation circuit of the present invention comprises a logic high-side non-overlap signal generation circuit and a four-terminal circuit, the four-terminal circuit having a first NMOS transistor, a second NMOS transistor substantially equal in area, aspect ratio and current direction to the first N-channel MOS transistor (hereinafter referred to as NMOS transistor), a first P-channel MOS transistor (hereinafter referred to as PMOS transistor), a second PMOS transistor substantially equal in area, aspect ratio and current direction to the first PMOS transistor, a positive-phase input terminal, a negative-phase input terminal, a positive-phase output terminal, a negative-phase output terminal, and a connection of two resistors or conductors having substantially equal resistance values, and the two outputs of the non-overlap signal generation circuit are connected to the positive-phase input terminal and the negative-phase output terminal of the four-terminal circuit. and a first NMOS transistor connected to the negative-phase input terminal, a source terminal connected to GND, and a drain terminal connected to the drain terminal of the first PMOS transistor, a connection between the second resistor or the conductor, and the positive-phase output terminal, a gate terminal of the second PMOS transistor connected to the second resistor or the connection between the conductor, a gate terminal of the second NMOS transistor connected to the positive-phase input terminal, a source terminal connected to GND, and a drain terminal connected to the drain terminal of the second PMOS transistor, a connection between the first resistor or the conductor, and the negative-phase output terminal, a gate terminal of the first PMOS transistor connected to the first resistor or the connection between the conductor, and the source terminals of the first PMOS transistor and the second PMOS transistor are connected to VDD. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a two-phase clock generation circuit that requires uniformity in the relationship between the rising edge and the falling edge, which are the gaps between non-overlapping two-phase clocks. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of a configuration of a two-phase clock generation circuit according to a first embodiment of the present invention. [Figure 2] 3 is a truth table of the four-terminal circuit according to the first embodiment of the present invention. [Figure 3] 1 is an example of a circuit diagram of a two-phase clock generation circuit according to a first embodiment of the present invention. [Figure 4] 4 is an example of a timing chart at the time of a rising event in the two-phase clock generation circuit according to the first embodiment of the present invention. [Figure 5] 4 is an example of a timing chart at the time of a falling event in the two-phase clock generation circuit according to the first embodiment of the present invention. [Figure 6] 5 is another example of a four-terminal circuit in the non-overlapping signal generation circuit according to the first embodiment of the present invention. [Figure 7] 5 is another example of a four-terminal circuit in the non-overlapping signal generation circuit according to the first embodiment of the present invention. [Figure 8] 1 is an example of a circuit diagram of a delay circuit according to all embodiments of the present invention; [Figure 9] 10 is a diagram illustrating an example of a configuration of a four-terminal circuit of a two-phase clock generation circuit according to a second embodiment of the present invention. [Figure 10] 10 is a truth table of the four-terminal circuit of FIG. 9 according to the second embodiment of the present invention. [Figure 11] 10 is a diagram illustrating an example of the configuration of a four-terminal circuit in a two-phase clock generation circuit according to a third embodiment of the present invention. [Figure 12] This is a circuit diagram showing MOS transistors that can achieve NOR logic. [Figure 13] 12 is a truth table of the four-terminal circuit of FIG. 11 according to the third embodiment of the present invention. [Figure 14] 12 is an example of a circuit diagram showing MOS transistors in the four-terminal circuit of FIG. 11 according to the third embodiment of the present invention. FIG. [Figure 15] 15 is an example of the layout of FIG. 14 according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] By using a two-phase clock generation circuit with the configuration described below, it is possible to easily generate two-phase clocks with uniform non-overlapping periods using a small-scale circuit. Note that in the following description, the error in the uniformity of the time from the transition edge of one node to the transition edge of the other node will be referred to as skew or skew balance.

[0011] In recent years, even in consumer products that use clocks in the tens of MHz class, there has been an increase in analog systems that require skew to be kept within tens of picoseconds, and this can be easily achieved using the present invention.

[0012] [First embodiment] A first embodiment of the present invention will be described with reference to the drawings. Fig. 1 shows a two-phase clock generation circuit 10, which is a block diagram of a two-phase clock generation circuit that achieves low skew according to the first embodiment of the present invention.

[0013] 1, non-overlap signal generation circuit 2 is a circuit that converts a clock signal input to input terminal In into a non-overlap signal on the logic high side by changing the duty ratio of the clock signal and outputs it to positive-phase input terminal In_1 and negative-phase input terminal In_0 of next-stage four-terminal circuit 1a. The pair of positive-phase and negative-phase output voltages of non-overlap signal generation circuit 2 can be any output voltage as long as they are at the positive-phase and negative-phase logic threshold voltage levels required for normal operation of next-stage four-terminal circuit 1a.

[0014] The four-terminal circuit 1a is a circuit that obtains two-phase outputs from two-phase inputs, and includes a first NMOS transistor 11 and a second NMOS transistor 12 that are voltage-current conversion elements, a first PMOS transistor 13 and a second PMOS transistor 14 that are cross-coupled to achieve latch operation, a positive-phase input terminal In_1, a negative-phase input terminal In_0, a positive-phase output terminal Out_1, a negative-phase output terminal Out_0, a second resistor 5a, and a first resistor 5b.

[0015] The connections of the four-terminal circuit 1a will be described. The gate terminal of the first NMOS transistor 11 is connected to the negative-phase input terminal In_0, the source terminal is connected to GND, the drain terminal is connected to the drain terminal of the first PMOS transistor 13, one end of the first resistor 5b, and the positive-phase output terminal Out_1, the gate terminal of the second NMOS transistor 12 is connected to the positive-phase input terminal In_1, the source terminal is connected to GND, and the drain terminal is connected to the drain terminal of the second PMOS transistor 14, one end of the second resistor 5a, and the negative-phase output terminal Out_0, the gate terminal of the second PMOS transistor 14 is connected to the other end of the first resistor 5b, the gate terminal of the first PMOS transistor 13 is connected to the other end of the second resistor 5a, and the source terminals of the first PMOS transistor 13 and the second PMOS transistor 14 are connected to VDD.

[0016] The four-terminal circuit 1a is characterized in that the first and second NMOS transistors, the first and second PMOS transistors, and the first and second resistors are arranged in close proximity and with substantially the same shape within the range of processing accuracy, and with the same direction of DC current, so that all electrical characteristics are equal to each other.As a result, when the input signals at the positive-phase input terminal In_1 and the negative-phase input terminal In_0 are both at a low level or both at a high level, and when the level of either input terminal changes to a different level, the transition states of the output signals at the positive-phase output terminal Out_1 and the negative-phase output terminal Out_0 are completely symmetrical.

[0017] The first and second resistors are components that limit the charging current of the gate capacitances of the first and second PMOS transistors and delay the time it takes to reach the logic threshold, thereby obtaining the minimum non-overlap period necessary for the normal operation of the subsequent circuit, in order to avoid problems that could occur in the circuit receiving the output of the four-terminal circuit 1a due to the non-overlap period being too narrow depending on the IC manufacturing process. The required non-overlap period is determined by the specifications of the subsequent circuit and is calculated using the time constant of the gate capacitance value of the first PMOS transistor or the second PMOS transistor and the first resistance value or the second resistance value.

[0018] That is, if you want to increase the non-overlap period, you can intentionally add new first and second capacitances in parallel to the gate capacitances of the first and second PMOS transistors, respectively. Conversely, if you want to decrease the non-overlap period, you can replace the first and second resistors with wiring made of a conductor such as aluminum.

[0019] Furthermore, as a component for delaying the operation of the first PMOS transistor and the second PMOS transistor, a delay circuit 6 is shown in FIG. 8 as an example of a delay circuit that substitutes for the first resistor and the second resistor.

[0020] The delay circuit 6 is made up of an even number of cascaded inverter logic gates 3c. The delay time of the entire delay circuit 6 is the sum of the signal delay times of the individual inverter logic gates 3c, and the delay characteristics of the individual inverter logic gates 3c do not need to be identical.

[0021] Figure 2 shows the truth table for the four-terminal circuit 1a.

[0022] 3 is a specific example of a two-phase clock generation circuit that achieves low skew according to the present invention. The non-overlapping signal generation circuit 2 on the logic high side, which has the fewest number of elements, can be realized by inverter circuits 3a and 3b and a four-terminal circuit 1b.

[0023] The inverter circuit 3a includes a third NMOS transistor 19 and a third PMOS transistor 20. The gate terminal of the third NMOS transistor 19 and the gate terminal of the third PMOS transistor 20 are connected to the input terminal In via a node N_0. The drain terminal of the third NMOS transistor 19 and the drain terminal of the third PMOS transistor 20 are connected to the inverter circuit 3b via a node N_1. The source terminal of the third NMOS transistor 19 is connected to the GND power supply. The source terminal of the third PMOS transistor 20 is connected to the VDD1 power supply. The third NMOS transistor 19 and the third PMOS transistor 20 operate as the inverter circuit 3a.

[0024] The inverter circuit 3b has a fourth NMOS transistor 21 and a fourth PMOS transistor 22. The gate terminal of the fourth NMOS transistor 21 and the gate terminal of the fourth PMOS transistor 22 are connected to a node N_1. The drain terminal of the fourth NMOS transistor 21 and the drain terminal of the fourth PMOS transistor 22 are connected to the four-terminal circuit 1b via a node N_2. The source terminal of the fourth NMOS transistor 21 is connected to GND. The source terminal of the fourth PMOS transistor 22 is connected to VDD1. The fourth NMOS transistor 21 and the fourth PMOS transistor 22 operate as the inverter circuit 3b.

[0025] The four-terminal circuit 1b includes a fifth NMOS transistor 15, a sixth NMOS transistor 16, a fifth PMOS transistor 17, and a sixth PMOS transistor 18. The gate terminal of the fifth NMOS transistor 15 is connected to node N_2, the source terminal is connected to GND, the drain terminal is connected to the drain terminal of the fifth PMOS transistor 17, the gate terminal of the sixth PMOS transistor 18, and node N_4, the gate terminal of the sixth NMOS transistor 16 is connected to node N_1, the source terminal is connected to GND, and the drain terminal is connected to the drain terminal of the sixth PMOS transistor 18, the gate terminal of the fifth PMOS transistor 17, and node N_3, and the source terminals of the fifth PMOS transistor 17 and the sixth PMOS transistor 18 are connected to VDD2.

[0026] The four-terminal circuit 1b can also be substituted with a four-terminal circuit 1c in which a seventh PMOS transistor 25 and an eighth PMOS transistor 26 are provided for limiting the through current, as shown in FIG.

[0027] Furthermore, the four-terminal circuit 1b may be a normal logic gate as shown in Figure 7. In other words, a four-terminal circuit 1d may be used, which is formed by cross-coupling a first NOR logic gate 4a and a second NOR logic gate 4b, which are not designed with emphasis on uniformity of transfer characteristics. The power supply and GND power supply of the first NOR logic gate 4a and the second NOR logic gate 4b are connected to the common VDD2 and GND terminals, respectively.

[0028] In addition, in order to increase the non-overlap period, the four-terminal circuits 1b, 1c, and 1d may be provided with a time constant circuit consisting of a resistor and a capacitor, or a delay circuit 6 consisting of a logic gate as delay means.

[0029] When the four-terminal circuit 1a shown in Figure 1, which has good left-right symmetry, is connected to the non-overlapping signal generating circuit 2 on the logic high side as described above, a two-phase clock with excellent skew balance can be easily generated. The above configuration does not have a control loop, so jitter generation is kept to a minimum. While symmetry must be emphasized for the four-terminal circuit 1a, other circuits with modified topologies can also be used.

[0030] The voltages VDD1, VDD2, and VDD can be selected according to the application.

[0031] 4 is a timing chart showing a rising event of the two-phase clock generation circuit 10a that realizes low skew according to this embodiment. FIG. 5 is a timing chart showing a falling event of the two-phase clock generation circuit 10a that realizes low skew according to this embodiment. The signal names in these timing charts correspond to nodes N_0 to N_6 in FIG. 3.

[0032] Here, concerns about impairing the symmetry of the output of the non-overlap signal generating circuit 2 in FIG. 3, that is, the changes at the nodes N_3 and N_4, will be described.

[0033] The rising edge of node N_3 at the time of the rising event in Fig. 4 is determined only by the falling edge of node N_4. That is, referring to the truth table in Fig. 2, the state transitions from State1 to State0 to State2.

[0034] On the other hand, the rising edge of node N_4 during a falling event in Figure 5 is determined by the later of the falling edge of node N_3 or the falling edge of node N_2. In actual operation, the falling edges of node N_3 and node N_2 are close in time to each other and form ramp waveforms, so neither is solely causal. Also, since the falling edge of node N_2 clearly lags behind the rising edge of node N_1, referring to the truth table in Figure 2, the state transition is State 2 → State 3 → State 1, which is clearly different from the case in Figure 4, which passes through State 0.

[0035] Therefore, the non-overlap period of the four-terminal circuit 1b will have different values ​​at the time of the rising event and the falling event of the clock input, which will impair the skew margin in a system that requires precision.

[0036] Next, consider nodes N_5 and N_6, which are the outputs of the four-terminal circuit 1a. Since nodes N_3 and N_4, which are the inputs of the four-terminal circuit 1a, have non-overlapping periods, although they vary, the condition of passing through State 0 rather than State 3 in Figure 2 is guaranteed, and the symmetry is maintained in that the rising edge of one is determined by the falling edge of the other.

[0037] As described above, the two-phase clock generation circuit of this embodiment can provide a two-phase clock generation circuit that requires uniform relationships between rising edges and falling edges, which are gaps between non-overlapping two-phase clocks.

[0038] If the non-overlap signal generating circuit 2 is a non-overlap signal on the logic low side, an inverter circuit for polarity inversion can be provided at each of the two inputs of the four-terminal circuit 1a, i.e., the negative phase input terminal In_0 and the positive phase input terminal In_1. Furthermore, if the non-overlap signal generation circuit 2 requires non-overlap on the logic high side and the two-phase clock generation circuit output requires non-overlap on the logic low side, the four-terminal circuit 1a can be configured by replacing the NMOS transistors with PMOS transistors, the PMOS transistors with NMOS transistors, VDD with GND, and GND with VDD.

[0039] [Second embodiment] A second embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the first embodiment are given the same numbers as those in the first embodiment, and descriptions thereof will be omitted.

[0040] In the second embodiment, the four-terminal circuit 1a in the two-phase clock generation circuit 10 of FIG. 1 is replaced with the four-terminal circuit 1e shown in FIG. 9, and the four-terminal circuit 1a in the two-phase clock generation circuit 10a of FIG. 3 is replaced with the four-terminal circuit 1e shown in FIG. 9.

[0041] The four-terminal circuit 1e is a circuit that obtains two-phase outputs from two-phase inputs, and includes a seventh NMOS transistor 31 and an eighth NMOS transistor 32 that are voltage-current conversion elements, a ninth PMOS transistor 33 and a tenth PMOS transistor 34 that realize a latch operation by cross-coupling, an eleventh PMOS transistor 35 and a twelfth PMOS transistor 36 that serve as switches for limiting through current, a positive-phase input terminal In_1, a negative-phase input terminal In_0, a positive-phase output terminal Out_1, a negative-phase output terminal Out_0, a second resistor 5a, and a first resistor 5b.

[0042] The connections of the four-terminal circuit 1e will be described. The gate terminal of the seventh NMOS transistor 31 is connected to the gate terminal of the eleventh PMOS transistor 35 and the inverting input terminal In_0, the source terminal is connected to GND, the drain terminal is connected to the drain terminal of the eleventh PMOS transistor 35, one terminal of the first resistor 5b, and the positive output terminal Out_1. The gate terminal of the eighth NMOS transistor 32 is connected to the gate terminal of the twelfth PMOS transistor 36 and the positive input terminal In_1, the source terminal is connected to GND, and the drain terminal is connected to the drain terminal of the twelfth PMOS transistor 36. The ninth PMOS transistor 33 has a gate terminal connected to the other terminal of the second resistor 5a, a drain terminal connected to the source terminal of the eleventh PMOS transistor 35, a gate terminal of the tenth PMOS transistor 34 connected to the other terminal of the first resistor 5b, and a drain terminal connected to the source terminal of the twelfth PMOS transistor 36, and the source terminals of the ninth PMOS transistor 33 and the tenth PMOS transistor 34 are connected to VDD.

[0043] The four-terminal circuit 1e is characterized in that the seventh NMOS transistor 31 and the eighth NMOS transistor 32, the ninth PMOS transistor 33 and the tenth PMOS transistor 34, the eleventh PMOS transistor 35 and the twelfth PMOS transistor 36, and the first resistor 5b and the second resistor 5a are arranged in close proximity and with substantially the same shape within the range of processing accuracy, and with the same direction of DC current, so that all electrical characteristics are equal to each other. Therefore, when the input signals of the positive-phase input terminal In_1 and the negative-phase input terminal In_0 are both at a low level or both at a high level, and when the level of either input terminal changes to a different level, the transition states of the output signals of the positive-phase output terminal Out_1 and the negative-phase output terminal Out_0 are completely symmetrical.

[0044] Figure 10 shows the truth table for the four-terminal circuit 1e.

[0045] As described above in conjunction with the first embodiment, the two-phase clock generation circuit of this embodiment can provide a two-phase clock generation circuit that requires uniform relationships between rising edges and falling edges, which are gaps between non-overlapping two-phase clocks.

[0046] If the non-overlap signal generating circuit 2 is a non-overlap signal on the logic low side, an inverter circuit for polarity inversion can be provided at each of the two inputs of the four-terminal circuit 1e, i.e., the negative phase input terminal In_0 and the positive phase input terminal In_1. Furthermore, if the non-overlap signal generating circuit 2 is required to be non-overlapping on the logic high side and the two-phase clock generating circuit output is required to be non-overlapping on the logic low side, the four-terminal circuit 1e may be configured by replacing the NMOS transistors with PMOS transistors, the PMOS transistors with NMOS transistors, VDD with GND, and GND with VDD. [Third embodiment] A third embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the first embodiment are given the same numbers as those in the first embodiment, and descriptions thereof will be omitted.

[0047] In the third embodiment, the four-terminal circuit 1a in the two-phase clock generation circuit 10 of FIG. 1 is replaced with the four-terminal circuit 1f shown in FIG. 11, and the four-terminal circuit 1a in the two-phase clock generation circuit 10a of FIG. 3 is replaced with the four-terminal circuit 1f shown in FIG. 11.

[0048] The four-terminal circuit 1f is a circuit that obtains a two-phase output for a two-phase input, and includes a third NOR logic gate 4c, a fourth NOR logic gate 4d, a positive phase input terminal In_1, a negative phase input terminal In_0, a positive phase output terminal Out_1, a negative phase output terminal Out_0, VDD, GND, a second resistor 5a, and a first resistor 5b.

[0049] 12 shows a circuit diagram of a typical NOR logic gate configured with MOS transistors that are components of the third NOR logic gate 4c and the fourth NOR logic gate 4d. That is, the NOR circuit 4 has a ninth NMOS transistor 41, a tenth NMOS transistor 42, a thirteenth PMOS transistor 43, a fourteenth PMOS transistor 44, an input terminal In_A, an input terminal In_B, an output terminal Out, a VDD power supply, and a GND power supply.

[0050] A feature of the NOR circuit 4 is that, compared to the duality of the two input terminals In_A and In_B, the duality of the connections of the thirteenth PMOS transistor 43 and the fourteenth PMOS transistor 44 is inferior. Therefore, the input terminals In_A and In_B are not the same, and a circuit connected by exchanging the input terminals In_A and In_B will have the same static logic but will not have the same transient electrical characteristics.

[0051] The connections of a four-terminal circuit 1f consisting of such NOR logic gates are as follows: The input terminal In_Ac of the third NOR logic gate 4c is connected to the negative-phase input terminal In_0, the input terminal In_Bc is connected to one terminal of the first resistor 5b, the output terminal Outc is connected to the positive-phase output terminal Out_1 and one terminal of the second resistor 5a, the input terminal In_Ad of the fourth NOR logic gate 4d is connected to the positive-phase input terminal In_1, the input terminal In_Bd is connected to the other terminal of the second resistor 5a, and the output terminal Outd is connected to the negative-phase output terminal Out_0 and the other terminal of the first resistor 5b. The power supplies and GND of the third NOR logic gate 4c and the fourth NOR logic gate 4d are connected to the common VDD and GND, respectively.

[0052] As described above, the four-terminal circuit 1f is characterized in that the input terminals In_A and In_B of the NOR logic gate are distinguished, and the third NOR logic gate 4c and the fourth NOR logic gate 4d, and the first resistor 5b and the second resistor 5a are connected symmetrically, so that the positive phase output terminal Out_1 and the negative phase output terminal Out_0 provide symmetrical operating outputs for all state transitions.

[0053] The necessary conditions for this are that the third NOR logic gate and the fourth NOR logic gate are arranged close to each other with substantially the same shape within the range of processing accuracy and with the same direction of the through current, and that the first resistor and the second resistor are arranged close to each other with substantially the same shape within the range of processing accuracy.

[0054] FIG. 14 is a transistor-level circuit representation of the four-terminal circuit 1f shown in FIG. 11, and FIG. 15 is a schematic diagram of the layout of the circuit of FIG.

[0055] Figure 13 shows the truth table for the four-terminal circuit 1f.

[0056] As described above in conjunction with the first embodiment, the two-phase clock generation circuit of this embodiment can provide a two-phase clock generation circuit that requires uniform relationships between rising edges and falling edges, which are gaps between non-overlapping two-phase clocks.

[0057] If the non-overlap signal generating circuit 2 is a non-overlap signal on the logic low side, an inverter circuit for polarity inversion can be provided at each of the two inputs of the four-terminal circuit 1f, i.e., the negative phase input terminal In_0 and the positive phase input terminal In_1. Furthermore, if the non-overlap signal generation circuit 2 is a logic low side non-overlap and the output of the two-phase clock generation circuit needs to be a logic low side non-overlap, the NOR logic gates that make up the four-terminal circuit 1f can be replaced with NAND logic gates.

[0058] In recent years, single-nanometer process rule products have appeared in the fields of CPUs and signal processing. In particular, in systems that require high-speed operation, the importance of setup and hold margins and signal integrity is increasing. Given this trend toward miniaturization, the mounting technology described above that minimizes two-phase clock skew is an effective means of easing the timing margin associated with two-phase clocks. [Explanation of symbols]

[0059] 1a, 1b, 1c, 1d, 1e, 1f 4-terminal circuit 2 Non-overlapping signal generation circuit 3a, 3b Inverter circuit 3c Inverter Logic Gate 4 NOR circuits 4a, 4b, 4c, 4d NOR logic gates 5a, 5b resistance 6 Delay Circuit 10, 10a Two-phase clock generation circuit 11, 12, 15, 16, 19, 21, 31, 32, 41, 42 NMOS transistors 13, 14, 17, 18, 20, 22, 33, 34, 35, 36, 43, 44 PMOS transistors In Input terminal In_0 Inverted phase input terminal In_1 Positive phase input terminal Out_0 Inverted phase output terminal Out_1 Positive Output Terminal

Claims

1. a non-overlapping signal generating circuit that prevents two output signals from simultaneously becoming a logic low level; a four-terminal circuit including a positive phase input terminal and a negative phase input terminal, to which the output signals of the non-overlap signal generation circuit are respectively input, and a positive phase output terminal and a negative phase output terminal, and connected between a first power supply and a second power supply; and The four-terminal circuit is a first N-channel MOS transistor having a source connected to the second power supply; a second N-channel MOS transistor having a source connected to the second power supply; a first P-channel MOS transistor having a drain connected to the drain of the first N-channel MOS transistor and a source connected to the first power supply; a second P-channel MOS transistor having a drain connected to the drain of the second N-channel MOS transistor and a source connected to the first power supply; a first resistor connected between the drain of the second N-channel MOS transistor and the gate of the first N-channel MOS transistor; a second resistor connected between the drain of the first N-channel MOS transistor and the gate of the second N-channel MOS transistor; Equipped with a gate of the first P-channel MOS transistor is connected to the inverting input terminal; a gate of the second P-channel MOS transistor is connected to the positive phase input terminal; a drain of the first N-channel MOS transistor is connected to the positive phase output terminal; a drain of the second N-channel MOS transistor connected to the opposite phase output terminal;

2. 2. The two-phase clock generating circuit according to claim 1, wherein the first resistor and the second resistor have the same resistance value.

3. 3. The two-phase clock generating circuit according to claim 1, wherein the first resistor and the second resistor are connected conductors.

4. the second N-channel MOS transistor is disposed adjacent to the first N-channel MOS transistor, with an area, an aspect ratio, and a current direction equal to those of the first N-channel MOS transistor; the second P-channel MOS transistor is disposed adjacent to the first P-channel MOS transistor, with an area, an aspect ratio, and a current direction equal to those of the first P-channel MOS transistor; 4. The two-phase clock generation circuit according to claim 1.

5. a non-overlapping signal generating circuit that prevents two output signals from simultaneously becoming a logic low level; a four-terminal circuit including a positive phase input terminal and a negative phase input terminal, to which the output signals of the non-overlap signal generation circuit are respectively input, and a positive phase output terminal and a negative phase output terminal, and connected between a first power supply and a second power supply; and The four-terminal circuit is a first NAND logic gate; and a second NAND logic gate; and a first resistor connected between the output terminal of the first NAND logic gate and the input terminal of the second NAND logic gate; a second resistor connected between the output terminal of the second NAND logic gate and the input terminal of the first NAND logic gate; Equipped with an output terminal of the first NAND logic gate is connected to the positive output terminal; an output terminal of the second NAND logic gate is connected to the inverted output terminal; the inverting input terminal is connected to the other input terminal of the first NAND logic gate; a positive input terminal connected to the other input terminal of the second NAND logic gate;

6. 6. The two-phase clock generating circuit according to claim 5, wherein the first NAND logic gate and the second NAND logic gate are arranged adjacent to each other.

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