Determining a bias voltage to apply to one or more memory cells in a neural network

Abstract

To provide a method for improving an analog neural memory in a deep learning artificial neural network in terms of accuracy or power consumption when temperature changes.SOLUTION: The calibration circuit 4400 configuration method includes programming a memory cell 4401, which can store any of N values, with one of the N values, passing a series of currents of increasing size through the bit line BL of the programmed memory cell, comparing the voltage of the bit line to a reference voltage VREF to generate a comparison output, and when the comparison output changes value, measuring the voltage of the control gate terminal of the memory cell and storing the CG voltage in the lookup table 4470.SELECTED DRAWING: Figure 44A

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 279,028, filed November 12, 2021, entitled "Optimization of Analog Neural Memory in a Deep Learning Artificial Neural Network as to Performance, Power, or Temperature," and U.S. Patent Application No. 17 / 585,452, filed January 26, 2022, entitled "Determination of a Bias Voltage to Apply to One or More Memory Cells in a Neural Network."

[0002] FIELD OF THE INVENTION Numerous embodiments are disclosed for improving analog neural memory in deep learning artificial neural networks with respect to performance or power in various temperature environments. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks typically contain layers of interconnected "neurons" that exchange messages between each other.

[0004] FIG. 1 shows an artificial neural network, where circles illustrate layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons and an output layer of neurons that provide the neural network's output. Neurons at each level make decisions individually or collectively based on the data received from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. Indeed, practical neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency, compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] The applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, which is incorporated by reference. The non-volatile memory array operates as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed insulated above a first portion of the channel region, and a non-floating gate disposed insulated above a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight value to generate the first plurality of outputs. <Nonvolatile memory cell>

[0007] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by hot electron source side injection (SSI) (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0011] Table 1 shows typical voltage and current ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 3 [Table 1]

[0012] Other split-gate memory cell configurations, including other types of flash memory cells, are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, meaning they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage and current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 of FIG. 3 [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 of FIG. 4 [Table 3]

[0016] 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of FIG. 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, and programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, by electrons flowing from the source region 14 toward the drain region 16, and by a read operation similar to that of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 510 of FIG. 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (ferroelectric ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable, bi-level or multi-level) and CeRAM (correlated electron ram).

[0019] In order to utilize a memory array containing one of the non-volatile memory cell types in the above artificial neural network, two modifications are made. First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array. Second, continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog, or at a minimum, capable of storing one of a number of discrete values ​​(such as 16 or 64 different values), which allows every cell in the memory array to be individually tunable with great precision, making the memory array ideal for storage and for fine tuning adjustments to the synaptic weights of neural networks. <Neural network using nonvolatile memory cell array>

[0021] 6 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and sums the outputs of the multiplications to determine a single output value, which is provided by the first synapse of CB1 to generate one pixel of layer C1's feature map. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all of layer C1's feature maps have been calculated.

[0023] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, while a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. The purpose of pooling function P1 is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for this purpose. A vector-by-matrix multiplication (VMM) array 32 contains nonvolatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of nonvolatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the nonvolatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights to be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and sums them for each output line (source line or bit line) to produce an output that becomes the input to the next layer or the input to the last layer. Having the non-volatile memory cell array 33 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also more power efficient due to in-memory computation.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output values ​​of the differential summer 38 are then provided to an activation function block 39, which rectifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The rectified output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from a previous layer of neurons or from an input layer such as an image database), and the summing op-amps 38 and activation function blocks 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, input (denoted Inputx) is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or current. The first layer's input D / A conversion can be performed by using a function or LUT (look up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which then generates an output that is provided as input to input VMM array (hidden level 2) 32c, and so on. The various layers of the VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. The example shown in FIG. 8 includes five layers (32a, 32b, 32c, 32d, and 32e): one input layer (32a), two hidden layers (32b and 32c), and two fully connected layers (32d and 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may alternatively include more than two hidden layers and more than two fully connected layers. <Vector Matrix Multiplication (VMM) Array>

[0033] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In VMM array 900, control gate lines, such as control gate line 903, run vertically (thus, row-oriented reference array 902 is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run horizontally. Here, inputs to VMM array 900 are provided to control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 900 appear on source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current in each source line (SL0, SL1, respectively) performs a function of the sum of all currents from memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, ie, memory cells 310 of VMM array 900, are preferably configured to operate in the sub-threshold region.

[0036] The nonvolatile reference memory cells and nonvolatile memory cells described herein are biased in weak inversion (sub-threshold region) as follows: Ids=Io*e(Vg-Vth) / nVt=w*Io*e(Vg) / nVt where w=e(-Vth) / nVt; where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k*T / q, k is Boltzmann's constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is proportional to (Wt / L)*u*Cox*(n-1)*Vt2, where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n*Vt*log[Ids / wp*Io] where wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector matrix multiplier VMM array with current inputs, the output current is: Iout=wa*Io*e(Vg) / nVt, i.e. Iout=(wa / wp)*Iin=W*Iin W=e(Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be adjusted to compensate for various conditions at such temperatures. The threshold voltage Vth can be expressed as:

number

[0039] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=beta*(Vgs-Vth)*Vds; beta=u*Cox*Wt / L W=α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth)

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0042] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2*beta*(Vgs-Vth)2; beta=u*Cox*Wt / L Wα(Vgs-Vth)2, i.e., weight W, is proportional to (Vgs-Vth)2

[0044] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0046] 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. The reference arrays 1001 and 1002, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1014 (only partially shown) with the current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level, which is provided by a reference mini-array matrix (not shown).

[0048] Memory array 1003 serves two purposes. First, memory array 1003 stores weights in each memory cell that are used by VMM array 1000. Second, memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert to input voltages provided to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1003, and then adds all the results (memory cell currents) to produce outputs on the respective bit lines (BL0-BLN), which serve as inputs to the next layer or the last layer. By performing the multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current in each of the bit lines BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines extend vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during a read operation. The current in each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexer 1212 includes a corresponding multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on the respective bit lines (e.g., BLR0) of the first and second non-volatile reference memory cells during each read operation, where the reference cells are tuned to a target reference level.

[0053] Memory array 1203 serves two purposes. First, memory array 1203 stores the weights used by VMM array 1200. Second, memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1201 and 1202 convert these current inputs to input voltages provided to control gates (CG0, CG1, CG2, and CG3)), and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current in each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 implements one-way tuning of the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (e.g., an incorrect value is stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (e.g., EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] FIG. 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 or first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bidirectional tuning, meaning that each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), which are applied to the memory cells in a row direction. The current outputs (neurons) are in bit lines BL0 through BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] 22 shows a neuron VMM array 2200 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In VMM array 2200, inputs INPUT0...INPUTN are received on bit lines BL0...BLN, respectively, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 23 shows a neuron VMM array 2300 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BLN.

[0060] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are received on word lines WL0, ..., WLM, respectively, and outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BLN.

[0061] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are received on word lines WL0, ..., WLM, respectively, and outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BLN.

[0062] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTn are received on vertical control gate lines CG0, ..., CGN, respectively, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 27 illustrates a neuron VMM array 2700 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTN are received at bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, which are coupled to bit lines BL0, ..., BLN, respectively. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] Figure 28 shows a neuron VMM array 2800 that is particularly suitable for memory cells 310 shown in Figure 3, memory cells 510 shown in Figure 5, and memory cells 710 shown in Figure 7, and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are received on word lines WL0, ..., WLM, respectively, and outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BLN.

[0065] 29 shows a neuron VMM array 2900 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are received on control gate lines CG0, ..., CGM. Outputs OUTPUT0, ..., OUTPUTN are generated on vertical source lines SL0, ..., SLN, respectively, with each source line SLi coupled to the source lines of all memory cells in column i.

[0066] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are received on control gate lines CG0, ..., CGM. Outputs OUTPUT0, ..., OUTPUTN are generated on vertical bit lines BL0, ..., BLN, respectively, with each bit line BLi coupled to the bit lines of all memory cells in column i. <Long and short-term memory>

[0067] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any predetermined period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] Figure 14 shows an example LSTM 1400. LSTM 1400 in this example includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives input vector x0 and generates output vector h0 and cell state vector c0. Cell 1402 receives input vector x1, output vector (hidden state) h0 from cell 1401, and cell state c0 from cell 1401, and generates output vector h1 and cell state vector c1. Cell 1403 receives input vector x2, output vector (hidden state) h1 from cell 1402, and cell state c1 from cell 1402, and generates output vector h2 and cell state vector c2. Cell 1404 receives input vector x3, output vector (hidden state) h2 from cell 1403, and cell state c2 from cell 1403, and generates output vector h3. Additional cells can be used; an LSTM with four cells is just an example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0071] FIG. 16 shows LSTM cell 1600, an example of one implementation of LSTM cell 1500. For the convenience of the reader, the same numbering scheme from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. VMM arrays, therefore, prove particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508 and adder device 1509 are implemented in digital or analog fashion. Activation function block 1602 can be implemented in digital or analog fashion.

[0072] An alternative example of LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (which includes an activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from sigmoid function block 1702, a register 1704 for storing the value f(t)*c(t−1) when that value is output from multiplier device 1703 via multiplexer 1710, a register 1705 for storing the value i(t)*u(t) when that value is output from multiplier device 1703 via multiplexer 1710, a register 1706 for storing the value o(t)*ĉ(t) when that value is output from multiplier device 1703 via multiplexer 1710, and a multiplexer 1709.

[0073] While LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in embodiments of LSTM cell 1700. LSTM cell 1700 requires less space than LSTM cell 1600 because LSTM cell 1700 requires one-quarter the space for the VMMs and activation function blocks compared to LSTM cell 1600.

[0074] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Accordingly, the embodiments described below reduce the circuitry required outside the VMM array itself. <Gated Recurrent Unit>

[0075] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are gating mechanisms within recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] 18 shows an exemplary GRU 1800. GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells can be used; a GRU with four cells is merely an example.

[0077] FIG. 19 shows an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding the two vectors, and a complement device 1908 for subtracting the input from 1 to generate the output.

[0078] FIG. 20 shows GRU cell 2000, an example of one implementation of GRU cell 1900. For convenience of the reader, the same numbering scheme as GRU cell 1900 is used in GRU cell 2000. As can be seen from FIG. 20, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that VMM arrays are particularly used in GRU cells used in specific neural network systems. Multiplier devices 1904, 1905, and 1906, adder device 1907, and complementary device 1908 are implemented in a digital or analog manner. Activation function block 2002 can be implemented in a digital or analog manner.

[0079] An alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In Figure 21, sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an adder device 2105 for adding the two vectors, a complementary device 2109 for subtracting an input from one to produce an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)*r(t) as it is output from multiplier device 2103 via multiplexer 2104, a register 2107 for holding the value h(t-1)*z(t) as it is output from multiplier device 2103 via multiplexer 2104, and a register 2108 for holding the value h^(t)*(1-z((t)) as it is output from multiplier device 2103 via multiplexer 2104.

[0080] While GRU cell 2000 includes multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 includes only one set of VMM array 2101 and activation function block 2102, which are used to represent multiple layers in embodiments of GRU cell 2100. GRU cell 2100 requires one-third the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Accordingly, the embodiments described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in which case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] For each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to implement weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to implement weight W as the average of two cells.

[0084] FIG. 31 illustrates a VMM system 3100. In some embodiments, a plurality of weights W stored in a VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 3100, half of the plurality of bit lines are designated as W+ lines, i.e., bit lines connecting to memory cells that will store a positive weight W+, and the other half of the plurality of bit lines are designated as W− lines, i.e., bit lines connecting to memory cells that implement a negative weight W−. A plurality of W− lines are interspersed alternately among the plurality of W+ lines. Subtraction operations are performed by summing circuits, such as summing circuits 3101 and 3102, that receive current from the W+ and W− lines. The outputs of the W+ and W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells of every pair of (W+, W−) lines. Although described above with respect to W- lines interspersed alternately among W+ lines, in other embodiments, the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0085] 32 shows another embodiment, in which a VMM system 3210 implements a plurality of positive weights W+ in a first array 3211 and a plurality of negative weights W− in a second array 3212 that is separate from the first array, and the resulting weights are suitably combined together by a summing circuit 3213.

[0086] Figure 33 shows a VMM system 3300. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). VMM system 3300 includes array 3301 and array 3302. Half of the bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connecting to memory cells that implement a negative weight W-. Multiple W- lines are interspersed alternately among the multiple W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 3303, 3304, 3305, and 3306, that receive current from the W+ and W- lines. The outputs on the W+ and W- lines from each array 3301, 3302 are combined together, respectively, to effectively give W = W+ - W- for each pair of (W+, W-) cells on every pair of (W+, W-) lines. Additionally, the W values ​​from each array 3301 and 3302 may be further combined via adder circuits 3307 and 3308, meaning that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from adder circuits 3307 and 3308 is one of two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system can be erased or programmed to hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate. For example, each floating gate may hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] Similarly, a read operation should be able to accurately distinguish between N different levels.

[0089] In some cases, accuracy is very important and it is desirable to improve the accuracy of the system (perhaps at the expense of power consumption). In other cases, power management is very important and it is desirable to improve the power consumption of the system (i.e., reduce power consumption) (perhaps at the expense of accuracy). In other cases, the ability to maintain accuracy as operating temperatures change is desirable. Instead of power consumption and accuracy, other characteristics, such as latency or other performance criteria, can be maximized.

[0090] It would be desirable to be able to change the characteristics of the neural network system to improve accuracy or power consumption in different temperature environments. Summary of the Invention

[0091] Numerous embodiments are disclosed for improving analog neural memories in deep learning artificial neural networks with respect to accuracy over temperature, power consumption, or other criteria. In some embodiments, a method is performed for determining, in real time, bias values ​​to apply to one or more memory cells in the neural network. In other embodiments, bias voltages are determined from a lookup table and applied to terminals of the memory cells during read operations.

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[0143] [Brief explanation of the drawings]

[0144] [Figure 1] FIG. 1 illustrates an artificial neural network. [Figure 2] 1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6]FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 8] FIG. 1 is a block diagram illustrating an exemplary artificial neural network utilizing one or more vector-matrix multiplication systems. [Figure 9] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 10] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 11] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 12] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 13] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 14] 1 shows a prior art long-term memory system. [Figure 15] 1 illustrates an exemplary cell for use in a long-term memory system. [Figure 16] 16 illustrates an embodiment of the exemplary cell of FIG. 15. [Figure 17] 16 illustrates another embodiment of the exemplary cell of FIG. 15. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates one embodiment of the exemplary cell of FIG. 19. [Figure 21] 20 illustrates another embodiment of the exemplary cell of FIG. 19. [Figure 22] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 23] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 24]1 illustrates another embodiment of a vector matrix multiplication system. [Figure 25] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 26] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 27] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 28] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 29] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 30] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 31] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 32] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 33] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 34] 1 illustrates another embodiment of a vector matrix multiplication system. [Figure 35] 1 shows performance data from a neural network. [Figure 36] A neural network method is shown. [Figure 37] 1 shows a neural network array. [Figure 38] Arrays are shown. [Figure 39] 1 shows a neural network array. [Figure 40A] Here's how. [Figure 40B] 1 shows a bias lookup table. [Figure 41] Here's how. [Figure 42] Here's how. [Figure 43] 1 shows an implementation of a scaler and an analog-to-digital converter. [Figure 44A] 1 shows a calibration circuit. [Figure 44B] Shows a calibration method. [Figure 45] Shows a bias averaging circuit. [Figure 46A] Shows a bias generation block. [Figure 46B] Shows another bias generation block. [Figure 46C] Shows another bias generation block. [Figure 47] Shows a neural network layer method. [Figure 48] Shows a neural network method. [Figure 49] Shows a neural network method. [Figure 50] Shows a neural network method.

Best Mode for Carrying Out the Invention

[0145] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array. <Overview of the VMM System>

[0146] Figure 34 shows a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high voltage decoder 3403, a column decoder 3404, a bit line driver 3405, an input circuit 3406, an output circuit 3407, control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high voltage generation block 3410 including a charge pump 3411, a charge pump regulator 3412, and a high voltage analog precision level generator 3413. The VMM system 3400 further includes a (program / erase, or weight tuning) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include special functions such as arithmetic functions, startup functions, embedded microcontroller logic, etc., without limitation), and test control logic 3417. The systems and methods described below may be implemented in the VMM system 3400.

[0147] The input circuit 3406 may include circuits such as a DAC (digital to analog converter), a DPC (digital to pulses converter, digital to time modulated pulse converter), an AAC (analog to analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse to analog level converter), or any other type of converter. The input circuit 3406 may implement normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. The output circuit 3407 may include circuits such as an ADC (analog to digital converter, for converting neuron analog outputs to digital bits), an AAC (analog to analog converter, such as a current-to-voltage converter or a logarithmic converter), an APC (analog to pulse converter, such as an analog to time modulated pulse converter), or any other type of converter. The output circuit 3407 may implement activation functions such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement statistical normalization, regularization, up / downscaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, log) of neuron outputs. The output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as the bit line output) to keep the power consumption of the array approximately constant or to increase the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same.

[0148] As mentioned above, a neural network may include many different layers, and within each layer, many calculations will be performed that require weight values ​​stored in one or more arrays within that layer. It can be appreciated that some layers will be used more than others, and that such layers will be more important to the overall accuracy of the neural network based on their frequency of use.

[0149] FIG. 35 shows a graph 3501 reflecting data collected by the inventors regarding the frequency of weight usage in an MLP (multi-layer perceptron) neural network for MNIST (Modified National Institute of Standards and Technology) digit classification. In the illustrated example, there are n levels, where each L (L, ..., L) represents a range of weights. As can be seen, lower weights are used much more frequently than other weight ranges. In this graph, as an example, L does not contribute significantly to overall network performance. Therefore, L can be set to a zero value, such as by reducing the control gate voltage applied to the array at level L, which results in lower power consumption due to the lower cell current drawn at the lower control gate voltage without significantly affecting accuracy.

[0150] Neural networks contain multiple layers. Each layer may have its own weight distribution. Therefore, different techniques may be required for different layers to improve overall network performance. For example, Ln may only contribute a small amount in the first layer, but may contribute significantly in the second layer.

[0151] The present embodiment provides a method for improving the operation of a neural network. Although the term optimization may be used, it should be understood that the method does not necessarily guarantee absolute optimization, i.e., the most complete, functional, or effective optimization possible; instead, the term optimization as used herein is simply meant as an improvement over prior art methods.

[0152] FIG. 35 also shows a table 3502 illustrating the accuracy of a read operation based on changes in the voltage VCG applied to the control gate of a memory cell during a read operation. As can be seen, lowering VCG from 1.8V to 1.6V has no impact on accuracy, and lowering VCG from 1.5V to 1.4V has a small impact on accuracy. As VCG (or VEG) decreases, the cell current decreases exponentially based on the subthreshold equation. This indicates that, in some cases, power can be saved by lowering the voltage applied to the terminals of the memory cell without sacrificing accuracy or while sacrificing accuracy to an acceptable degree. Similarly, in the linear region, a lower input row voltage results in lower current. Furthermore, changes in operating temperature can affect both accuracy and power consumption, and it can be appreciated that VCG and / or EG adjustments (i.e., increases or decreases in magnitude) can be used to obtain improved power and / or accuracy as temperature changes.

[0153] 35, it will be appreciated that different bias voltages can be determined and applied to one or more terminals of a memory cell (e.g., CG, EG, WL) to improve power consumption (e.g., by lowering the VCG used, perhaps at the expense of accuracy), improve accuracy during static temperature conditions (e.g., by increasing the VCG used, perhaps at the expense of power consumption), or improve or maintain accuracy during changing temperature conditions (e.g., by increasing the VCG as the temperature changes, perhaps at the expense of power consumption). Instead of accuracy and power consumption, other performance characteristics can be maximized.

[0154] With these concepts in mind, various methods are now described.

[0155] 36 shows a neural network layer method 3600 that is performed on a particular layer within a neural network. For example, the method may be performed on one layer (or more than one layer) that is deemed more important due to its significant impact on overall network accuracy.

[0156] In step 3601, a default voltage bias is applied to the terminals (e.g., control gate terminals) of cells in the array of layers during a read operation. This default voltage bias is typically the same as the bias value used during a verify operation when programmed weights are verified.

[0157] In step 3602, performance inference is performed.

[0158] In step 3603, baseline data is collected about the performance (e.g., accuracy) of the network when the default bias is applied to the array. This data may, for example, be data showing the accuracy of MNIST inference operations. This baseline data will serve as a reference point for performance goal checking in step 3605.

[0159] In step 3604, the bias is adjusted (eg, increased or decreased by a particular increment) and then applied to the terminals (eg, control gate terminals) of the cells in the layer of the array.

[0160] A performance goal check is performed in step 3605. If the performance data results are within the target range compared to the performance data collection performed in step 3603, the method proceeds to step 3604 until the performance goals are no longer met, at which point the method proceeds to completion of step 3606, where the method stores the previous bias conditions that were the last set of biases that resulted in performance data within the target range.

[0161] In step 3606, the previous set of biases is deemed good and is stored (such as in a look-up table) in association with that layer for future use. Optionally, the current operating temperature can be stored along with the bias levels.

[0162] 37 shows neural network array 3700. Neural network array 3700 comprises arrays 3701-0, ..., 3701-n, where n+1 is the number of arrays in neural network 3700. Neural network 3700 also comprises temperature sensors 3703-i, where i is the number of sensors that sense operating temperatures within a particular location within neural network 3700. Optionally, each array 3701-0, ..., 3701-n includes its own temperature sensor 3703 (such that i=n+1), such that each temperature sensor 3703 is associated with one of arrays 3701-0, ..., 3701-n and the memory cells included in such array. Temperature voltage bias lookup table (LUT) 3704-i (where i is the number of the voltage bias lookup table) is consulted to obtain bias voltages for one or more terminals (for example, but not limited to, control gate terminals or erase gate terminals) based on the sensed temperature. These bias voltages, referred to as temperature biases 3702, are then applied to each cell in the particular array in question. Thus, temperature bias 3702-0 is applied to array 3701-0, and so on. Each array 3701-0, ..., 3701-n forms one or more neurons in the neural network.

[0163] FIG. 38 illustrates array 3801. Array 3801 may be used, for example, for any of arrays 3701-0, 3701-n of FIG. 37. In this embodiment, different bias voltages (e.g., VCG) may be used for different subarrays 3802-0, ..., 3802-k included within the same array 3801; i.e., array 3801 is divided into multiple subarrays. For example, each subarray 3802-0, ..., 3802-k may receive its own temperature bias 3803-0, ..., 3803-k, respectively. In addition to enabling compensation based on specific operating temperatures measured at different locations within array 3801, this embodiment is also well-suited for situations in which different types of weights are stored in each subarray 3802. For example, sub-array 3802-0 may store weights for the range 0 to 30 nA, array 3801-1 may store weights for the range 30 to 60 nA, and so on, since each current range may require a different temperature bias.

[0164] This embodiment is also suitable for situations where memory cells in different arrays operate in different modes (regions). For example, cells in subarray 3802-0 may operate in subthreshold mode, while cells in subarray 3802-n may operate in linear mode, since different modes (regions) may require different temperature biases.

[0165] Figure 39 illustrates a neural network array 3900. In this embodiment, the teachings regarding Figure 38 are extended to m+1 arrays 3901-0, ..., 3901-m within the neural network array 3900. Each array 3901 is divided into k+1 arrays 3902-0a, ..., 3902-ka, where a is the array number ranging from 0 to m. Each array 3902 receives its own temperature bias 3903-0a, ..., 3903-ka, respectively. It should be further understood that each array 3901 can be divided into a different number of arrays and need not be divided into the same number of arrays as the other arrays 3901.

[0166] Figure 40A shows a neural network array 4000. In a typical neural network read (inference) operation in a single layer, digital input values ​​DIN[m:0] are applied to array 4001, resulting in digital outputs DOUT[n:0] (or alternatively, analog values). Array 4001 may be an array or a portion of an array.

[0167] Neural network 4000 uses criteria to find one or more values ​​in lookup table 4003. The criteria may include, for example, desired input and output values, the current operating temperature value, and whether it is desired to target minimum power consumption, target performance (e.g., accuracy or latency), or performance at a particular temperature. Lookup table 4003 will then provide a bias based on these criteria. The bias is then applied to array 4001 during a read operation, completing method 4000. Array 4001 may include non-volatile or volatile memory cells.

[0168] FIG. 40B shows a bias lookup table (BLUT) 4020. Array 4021 is an array or portion of an array of volatile or nonvolatile memory cells. Array 4021 receives digital inputs DIN[m:0] and outputs digital outputs DOUT[n:0]. The digital output data pattern is programmable depending on the desired output, such as, but not limited to, from linear or subthreshold memory cell relationships or from silicon characterization data. The digital output data DOUT[n:0] is then applied to a digital-to-analog converter 4022, which outputs the desired bias analog voltage to be applied to the array or subarray in question. BLUT 4020 may be used, for example, in conjunction with a temperature sensor to provide a bias value, i.e., a temperature bias, to improve the performance of a neural network.

[0169] FIG. 41 shows a bias generation circuit 4100. A temperature sensor 4101A senses the operating temperature and indicates the operating temperature with digital bits D[m:0]. Optionally, a timer 4104 can initiate temperature sensing and subsequent bias generation, such as every 10-100 ms (the time it takes silicon to increase by one degree Celsius, for example, using one degree Celsius as an acceptable temperature change that does not significantly affect network performance). These D[m:0] bits are used to perform a lookup in a lookup table 4102 to find the bias value to be applied based on the operating temperature, i.e., the appropriate temperature bias. The bias value is indicated by digital bits D[k:0], which are provided to a digital-to-analog converter 4103, which converts the digital bits to bias voltages that can then be applied to terminals (e.g., control gate terminals) of memory cells in the array during read (inference) operations.

[0170] FIG. 42 shows scaling circuit 4200. Temperature sensor 4201 senses the operating temperature and indicates it with digital bits D[n:0]. These digital bits are provided to scaler 4202, which also receives the output neuron current Ineu from the array as a result of a neuron read operation. Scaler 4202 performs a current-to-voltage conversion of Ineu and scales that signal based on D[n:0]. For example, in the subthreshold region, higher temperatures result in higher neuron currents (due to higher memory cell currents), and therefore it is desirable to scale this current down before it is applied to ADC 4203. In the linear region, higher temperatures typically result in lower neuron currents (due to lower cell currents), and therefore it is desirable to scale this current up before it is applied to ADC 4203. The result is a more balanced analog value over temperature that is provided to analog-to-digital converter 4203, resulting in digital output bits D[n:0] representing a scaled digital version of Ineu, where this scaling at least partially compensates for sensing operating temperature.

[0171] Figure 43 shows a scaling circuit 4300, which is an implementation of the scaler ITV (current-to-voltage converter) 4202 and analog-to-digital converter 4203 from Figure 42. The scaler 4202 has a programmable gain, which can be programmed by programming the R value (for ITV circuits that use R to convert neuron currents to voltages that are digitized by the ADC) or the C value (for ITV circuits that use C to convert neuron currents to voltages that are digitized by the ADC). The scaler 4202 can also be implemented as a programmable current mirror (for neuron (bit line) currents). The ADC 4203 is a programmable n-bit ADC, where n can be, for example, 4, 8, or 12 bits.

[0172] Figure 44A shows a calibration circuit 4400, and Figure 44B shows a calibration method 4450 that utilizes the calibration circuit 4400 to populate a lookup table 4470. A current digital-to-analog converter 4402 is coupled to the bit line of a memory cell 4401 and to the non-inverting input of a comparator 4403, which also receives a reference voltage VREF at its inverting input. Memory cell 4401 can be a single cell or multiple cells (e.g., from a reference array or part of a main array).

[0173] As described above, each non-volatile or volatile memory cell used in an analog neural memory system can be erased and programmed to hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256. Calibration method 4450 is performed for each of the N different values ​​that can be stored in memory cell 4401. Each time calibration method 4450 is performed, memory cell 4401 is programmed (tuned) to one of N different values, such as a read current of 10 nA (step 4451).

[0174] The voltage at the control gate of memory cell 4401 is measured according to calibration method 4450. The bit line current is varied by current digital-to-analog converter 4402 from a low current (e.g., 1 nA) to a high current (e.g., 100 nA), resulting in currents of increasing size, and the output of comparator 4403 (called the compare output) is monitored. At some point, the value of the compare output changes (e.g., from "0" to "1") (step 4452). When a flip occurs, i.e., before any change in the bit line current by current digital-to-analog converter 4402, the control gate voltage of memory cell 4401 is measured, and that control gate voltage can be stored in lookup table 4470. This method is repeated for the other N possible values ​​that can be stored in the memory cell. If more than one cell is used, the current provided by the current DAC (IDAC) needs to be adjusted accordingly; for example, if four cells are used with 1 nA in each cell (e.g., for averaging), the IDAC current is 4 nA. The resulting CG voltage is stored in a look-up table 4470 (step 4454).

[0175] In another embodiment, lookup table 4470 is further expanded to include multiple temperature values ​​within the expected operating range, such that lookup table 4470 is a temperature bias lookup table (TBLUT).

[0176] For example, in the situation where N=128 (corresponding to an 8-bit input value), the equivalent current range may be 1nA to 128nA, with each 1nA increment associated with one of N levels. Calibration circuit 4400 and calibration method 4450 are then used to populate lookup table 4470 with CG voltages for all 128 levels for each of a number of different temperatures (e.g., -40C, -39C, ..., 0C, ..., 25C, 26C, ..., 85C). For example, if 10 different temperature points are used for N=128, the lookup table will be populated with 1280 values ​​(one value for each of the 128 levels for each of the 10 different temperatures).

[0177] In another calibration method, multiple cells are used to store currents (weights) representing samples in the array. A bias current from the IDAC4402 is then applied, and CG is extracted as described above for each of the multiple cells and their corresponding stored values ​​(weights). This can be determined over temperature and stored in a lookup table, so that CG bias changes over temperature can be recalled from the lookup table for different stored values ​​(weights) and applied to the array based on the stored value for the cell in question. Optionally, this can be done in real time, with biases applied to various cells in the array during operation.

[0178] 44A, 44B can be used to calculate the average of the CG voltage applied for each of N levels for each of a number of different temperatures. For example, for each of the N values ​​and each temperature, M different readings can be taken and the average readings can be stored in lookup table 4470. For example, if 10 different temperature points are used for N=128, then 1280*M readings will be taken and 1280 different averages will be stored in lookup table 4470.

[0179] In another embodiment, instead of making measurements for all N possible values ​​for each of multiple temperatures, measurements can be made for a smaller set of possible values ​​(e.g., for 4 of the N possible values ​​instead of all N possible values), and the average of those smaller sets of possible values ​​can be stored in lookup table 4470 for the particular temperature used. Thus, if 10 different temperatures are used, lookup table 4470 will only contain 10 values ​​(one value for each of the 10 different temperatures).

[0180] In another embodiment, the EG bias voltage is also varied. Measurements of the CG voltage are taken at different EG bias voltages, and the CG and EG biases are stored in a lookup table 4470.

[0181] 45 shows a bias averaging circuit 4500 for determining an average bias based on measurements performed on n+1 different memory cells. A calibration method 4450 is performed on the n+1 different cells, each resulting in a voltage (e.g., VCG) that represents the “optimum” or average bias voltage for that cell.

[0182] Each cell is associated with a measurement block 4501, shown here as measurement blocks 4501-0 through 4501-n. Each measurement block 4501 is identical. Measurement block 4501-0 comprises operational amplifier 4502-0, PMOS transistors 4503-0 and 4504 arranged as a current mirror, NMOS transistor 4505-0, and resistor 4506-0. The other measurement blocks 4501 contain identical components. In operation, each measurement block 4501 contributes a mirror current through its PMOS transistor 4504, which is summed at the top terminal of resistor 4507, which may be a variable resistor. The output VOUT is the average of the various voltages provided as inputs to block 4501 (by appropriate ratio of the values ​​of resistor 4507 to 4506). Output voltage VOUT = (R-4507 / R-4506) * Sum of VIN0 to VINn, for example, if n = 3, R-4507 / R-4506 = 1 / 4, VOUT = (1 / 4) * (VIN0 + VIN1 + VIN2 + VIN3) = Average voltage of the four input voltages VIN0 to VINn.

[0183] The output voltage VOUT may be applied as a bias to the control gate terminals of one or more cells in the neural network memory array.

[0184] FIG. 46A shows a bias generation block 4600. The bias generation block 4600 comprises a current digital-to-analog converter 4602 coupled to the bit line of a memory cell 4601 and the non-inverting input of a comparator 4603, which also receives a reference voltage VREF at its inverting input (where VREF is the same VREF as shown in FIG. 44). A row register 4604 provides a digital value DRIN[0:7] to IDAX 4602, which converts the digital value into a current that is applied to the bit line terminal of cell 4601. When switch 4605 is closed, an external voltage VIN is applied to the CG terminal. When switch 4606 is closed, capacitor 4607 is charged to the same voltage as CG. When the output of comparator 4603 changes, switch 4606 is opened. The voltage on capacitor 4607 at that point represents the CG voltage that changed the output of comparator 4603, which is the determined bias voltage. That is, switch 4606 and capacitor 4607 form a sample-and-hold circuit. This voltage is held constant by buffer 4608 and applied to the control gates in the array. Memory cell 4601 can be operated in the subthreshold region or the linear region.

[0185] FIG. 46B shows bias generation block 4650, which is similar to bias generation block 4600, except that memory cell 4651 is diode-connected to generate the CG bias and does not use a comparator. Bias generation block 4650 can be used to generate the CG bias value for lookup table 4470 in FIG. 44A. Bias generation block 4650 includes a current digital-to-analog converter 4652 coupled to the bit line of memory cell 4651. Current digital-to-analog converter 4652 is controlled by row register 4654. The voltage at the control gate of cell 4651 is sampled by switch 4656, which then charges capacitor 4657 to that voltage, and capacitor 4657 holds that voltage after switch 4656 is opened. That is, switch 4656 and capacitor 4657 form a sample-and-hold circuit. This voltage is held constant by buffer 4658 and applied to control gates in the array. The memory cells 4651 can operate in the sub-threshold or linear region. The bias generation block 4650 converts the input digital values ​​DRIN[0:7] from the row registers 4654 into equivalent CG voltages that are applied to the array.

[0186] FIG. 46C shows a bias generation block 4680, which is similar to bias generation block 4650 except for the addition of a level shifter 4685. Bias generation block 4680 can be used to generate a CG bias value for lookup table 4470 in FIG. 44A. Bias generation block 4680 includes a current digital-to-analog converter 4652 coupled to the bit line of memory cell 4651. Current digital-to-analog converter 4652 is controlled by row register 4654. Level shifter 4685 is disposed between the output of current digital-to-analog converter 4652 and the control gate terminal of memory cell 4651 to shift the voltage by, for example, a bias voltage (e.g., 0.2V to 0.5V). The voltage at the control gate of cell 4651 is sampled by switch 4656, which then charges capacitor 4657 to that voltage, and capacitor 4657 holds that voltage after switch 4656 is opened. That is, switch 4656 and capacitor 4657 form a sample and hold circuit. This voltage is held constant by buffer 4658 and applied to the control gates in the array. Memory cells 4651 can operate in the subthreshold or linear region. Bias generation block 4650 converts the input digital value DRIN[0:7] from row register 4654 into an equivalent CG voltage that is applied to the array.

[0187] Figure 47 shows a neural network neuron method 4700 performed on a particular neuron in a neural network. In step 4701, a nominal bias is applied to the particular neuron of interest in the array. This method may be performed on neurons that are deemed more important due to their frequency of use. Steps 4702-4706 are identical to steps 3602-3606 of Figure 36.

[0188] 48 illustrates a neural network method 4800. The method 4800 includes sensing an operating temperature associated with a first set of memory cells (step 4801), determining a bias in a lookup table based on the sensed operating temperature (step 4802), applying the determined bias to terminals of the first set of memory cells (step 4803), and performing a read operation on the first set of memory cells (step 4804). Optionally, the first set of memory cells can include all cells in an array. Optionally, the first set of memory cells can include all cells in all arrays. Optionally, method 4800 further includes detecting an operating temperature associated with a second set of memory cells (step 4805), determining a bias in a lookup table based on the second detected operating temperature (step 4806), applying the determined bias to terminals of the second set of memory cells (step 4807), and performing a read operation on the second set of memory cells (step 4808).

[0189] 49 illustrates a neural network operating method 4900, which is similar to the neural network operating method 4800, except that bias calibration is performed in real time. The neural network operating method 4900 includes sensing an operating temperature associated with a first set of memory cells (step 4901), determining a bias based on the sensed operating temperature (step 4902), applying the determined bias to terminals of the first set of memory cells (step 4903), and performing a read operation on the first set of memory cells (step 4904). Optionally, the first set of memory cells can include all cells in an array. Optionally, the first set of memory cells can include all cells in all arrays. Optionally, method 4900 further includes detecting an operating temperature associated with a second set of memory cells (step 4905), determining a bias based on the second detected operating temperature (step 4906), applying the determined bias to terminals of the second set of memory cells (step 4907), and performing a read operation on the second set of memory cells (step 4908).

[0190] FIG. 50 shows a neural network method 5000, which includes the steps of programming one or more memory cells (step 5001), passing multiple currents through the programmed memory cells (step 5002), measuring the voltage at the control gate terminal of each programmed memory cell and storing the voltage as a determined bias for the cell that stores the value stored in the programmed memory cell (step 5003), applying a bias voltage to the terminals of the set of memory cells based on the determined bias for the cell that stores the value to be stored in the set of memory cells (step 5004), and performing a read operation on the set of memory cells (step 5005).

[0191] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A method for populating a bias lookup table, the method comprising: programming a memory cell capable of storing any of N values ​​with one of the N values; applying a series of currents of increasing magnitude to the bit lines of the programmed memory cells; comparing the voltage on the bit line with a reference voltage to generate a comparison output; measuring a voltage at a control gate terminal of the memory cell when the comparison output changes value and storing the voltage in a look-up table.

2. The method of claim 1 , wherein the memory cells are non-volatile memory cells.

3. The method of claim 1 , wherein the memory cells are volatile memory cells.

4. The method of claim 1 , wherein the voltage at the control gate terminal is measured using a sample and hold circuit.

5. 1. A method for a neural network, the method comprising: sensing an operating temperature; indicating the sensed operating temperature in digital bits; converting the output neuron current into a voltage; scaling the voltage in response to the digital bit.

6. A voltage averaging circuit for generating a bias, comprising: a variable resistor coupled between the output node and ground; a plurality of measurement blocks, each measurement block converting a respective input voltage to a current and mirroring the current to the output node; A voltage averaging circuit, wherein the output node provides a bias to the plurality of measurement blocks equal to an average of the input voltages.

7. 7. The voltage averaging circuit of claim 6, wherein the voltage at the output node is equal to the sum of values ​​provided by each measurement block, the value comprising the input voltage received by the measurement block multiplied by the ratio of the variable resistors, divided by the sum of the variable resistors of the measurement blocks, and multiplied by the sum of the respective input voltages.

8. 8. The voltage averaging circuit of claim 7, wherein the voltage at the output node is applied to a control gate terminal of one or more cells in a neural network memory array.

9. 1. A method for generating biases for a memory array, the method comprising: programming a memory cell to store a value; applying a series of currents of increasing magnitude to the bit lines of the programmed memory cells; measuring a voltage at a control gate terminal of the memory cell to determine the bias.

10. The method of claim 9 , further comprising the step of storing the determined bias.

11. 11. The method of claim 10, further comprising applying the bias to one or more memory cells during an operation on the one or more memory cells in an array of memory cells.

12. The method of claim 11 , wherein the array is an analog neural memory array.

13. 11. The method of claim 10, comprising performing the programming, streaming, measuring, and storing steps for a plurality of different operating temperatures of the programmed memory cell.

14. 1. A method for determining biases for a memory array in a neural network in real time, the method comprising: programming a memory cell to store a value; applying a predetermined current to the bit line of the programmed memory cell; measuring a voltage at a control gate terminal of the memory cell to determine the bias.

15. The method of claim 14 further comprising the step of storing the bias.

16. 16. The method of claim 15, further comprising applying the bias to one or more memory cells during an operation on the one or more memory cells in an array of memory cells.

17. 17. The method of claim 16, wherein the array is an analog neural memory array.

18. 16. The method of claim 15, comprising performing the programming, applying, measuring, and storing steps for a plurality of different operating temperatures of the programmed memory cell.

19. 1. A method for a neural network, the method comprising: programming the memory cells; applying a series of currents of increasing magnitude to the bit lines of the programmed memory cells; comparing the voltage on the bit line with a reference voltage to generate a comparison output; measuring a voltage at the control gate terminal of the memory cell when the comparison output changes value and storing the voltage as a determined bias; applying the determined biases to terminals of the set of memory cells; performing a read operation on the set of memory cells.

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