Semiconductor device

Abstract

To provide a semiconductor device suitable for microfabrication, a semiconductor device with high reliability, and a semiconductor device with improved operation speed.SOLUTION: A memory cell array 300 which is a semiconductor device includes a memory cell CL including first to c-th (c is a natural number of 2 or more) sub memory cells SCL, a j-th sub memory cell includes a first transistor Ta, a second transistor Tb, and a capacitor Ca, a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor each include an oxide semiconductor, and one terminal of the capacitor is electrically connected to a gate electrode included in the second transistor. A gate electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the first transistor; When j ≥ 2, the j-th sub memory cell is provided over the (j-1) th sub memory cell.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The invention relates to the manufacture or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. The present invention relates to a driving method for the above-mentioned liquid crystal display device or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "device" refers to a device in general. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. devices, storage devices, imaging devices, electro-optical devices, power generation devices (thin-film solar cells, organic thin-film solar cells) and the like), and electronic devices may include semiconductor devices. [Background technology]

[0003] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials for transistors. However, oxide semiconductors are attracting attention as other materials.

[0004] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating transistors using this method have been disclosed (see Patent Documents 1 and 2).

[0005] In recent years, with the increasing performance, miniaturization, and weight reduction of electronic devices, Demand is increasing for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that is suitable for miniaturization. Another object of the present invention is to provide a semiconductor device with a reduced circuit area. An object of one embodiment is to provide a semiconductor device with improved operation speed. An object of one embodiment of the present invention is to provide a semiconductor device with improved writing speed. Another object of one embodiment of the present invention is to provide a semiconductor device with improved read speed. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. This is one of the topics.

[0008] Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another embodiment of the present invention provides a semiconductor device including a memory element with favorable retention characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device having a novel structure. Another object of the present invention is to provide a novel semiconductor device. .

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a memory cell having first to c-th (c is a natural number of 2 or more) sub-memory cells. The jth (j is a natural number from 1 to c) sub-memory cell has a first transistor. a first semiconductor memory device including a first transistor, a second transistor, and a capacitor; The conductor layer and the second semiconductor layer of the second transistor include an oxide semiconductor. One of the terminals of the transistor is electrically connected to a gate electrode of the second transistor. The gate electrode of the first transistor is connected to the source electrode or drain electrode of the second transistor. When j≧2, the jth sub-memory cell is electrically connected to either one of the gate electrodes. It is a semiconductor device arranged on the sub-memory of -1.

[0011] Alternatively, one embodiment of the present invention is a method for manufacturing a semiconductor memory device, comprising: The jth (j is a natural number from 1 to c) sub-memory cell has a first a first transistor, a second transistor, and a capacitor; The first semiconductor layer and the second semiconductor layer of the second transistor each include an oxide semiconductor. one terminal of the capacitor is electrically connected to a gate electrode of the second transistor; The gate electrode of the second transistor is connected to the source electrode of the first transistor. is electrically connected to either one of the drain electrodes, and for j≧2, the jth sub-memory cell a semiconductor layer of the second transistor Tb_j of the (j-1)th sub-memory The semiconductor layer of the first transistor Ta_(j-1) of the cell is A second transistor Tb_ in the j-th sub-memory cell is in contact with the upper surface, and when j≧2, the gate electrode of the jth sub-memory cell and the first transistor T The gate electrode of a_(j-1) is a semiconductor device that is in contact with the lower surface of the second insulating film.

[0012] Alternatively, one embodiment of the present invention is a method for manufacturing a semiconductor memory device, comprising: The jth (j is a natural number from 1 to c) sub-memory cell has a first a first transistor, a second transistor, and a capacitance element, and the jth sub-membrane The memory cell is arranged on the j-1th sub-memory, and the first semiconductor transistor has The second semiconductor layer of the second transistor includes an oxide semiconductor. The semiconductor layer of the first transistor or the second transistor of the sub-memory cell The semiconductor layer of the third transistor is formed on the first insulating film. and the semiconductor layer of the first transistor of the c-th sub-memory cell or the semiconductor layer of the c-th sub-memory cell Any of the semiconductor layers of the second transistors of the sub-memory cells and the fourth transistor The semiconductor layer of the transistor is a semiconductor device formed on the second insulating film.

[0013] In the above configuration, the jth (j is a natural number from 1 to c) sub-memory cell has a first semiconductor layer of the first transistor included in the j-th sub-memory cell; The second semiconductor layer of the transistor is an oxide containing In, an element represented by M, and Zn. the ratio of the number of In, M, and Zn atoms in the oxide semiconductor of the first semiconductor layer is satisfies In:M:Zn=g:h:i, and the In of the oxide semiconductor contained in the second semiconductor layer, The ratio of the number of M and Zn atoms satisfies In:M:Zn=d:e:f, and g / (g+h+i) is It is preferably smaller than d / (d+e+f). [Effects of the Invention]

[0014] According to one embodiment of the present invention, a semiconductor device suitable for miniaturization can be provided. A semiconductor device with a reduced wiring area can be provided. According to one embodiment of the present invention, a semiconductor device with improved operation speed can be provided. A semiconductor device with improved writing speed can be provided. In this way, a semiconductor device with improved read speed can be provided. Therefore, a semiconductor device with low power consumption can be provided.

[0015] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device can have good electrical characteristics. According to one embodiment of the present invention, a semiconductor device including a memory element with favorable retention characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with a novel structure can be provided. Furthermore, a novel semiconductor device can be provided.

[0016] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0017] [Figure 1] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention and a circuit diagram thereof. [Figure 2] FIG. 1 is a block diagram according to one embodiment of the present invention. [Figure 3] FIG. 10 is a timing chart of a circuit according to one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Figure 5] FIG. 1 is a circuit diagram according to one embodiment of the present invention. [Figure 6] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B illustrate examples of transistors. [Figure 18] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 20] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 21] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 22] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 23] Electron diffraction pattern of CAAC-OS. [Figure 24] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 25] 1A and 1B are diagrams illustrating a band structure of a part of a transistor according to one embodiment of the present invention and a diagram illustrating a current path during conduction. [Figure 26] FIG. 1 is a circuit diagram according to an embodiment. [Figure 27] 1 shows an example of the configuration of an RF tag according to an embodiment. [Figure 28] 1 shows an example of the configuration of a CPU according to an embodiment. [Figure 29] FIG. 2 is a circuit diagram of a memory element according to an embodiment. [Figure 30] 1. An electronic device according to an embodiment. [Figure 31] 10 shows an example of how an RF tag is used according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0019] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0020] In each figure described in this specification, the size, layer thickness, or area of ​​each component is The figures may be exaggerated for clarity and are not necessarily limited to that scale. stomach.

[0021] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limitation.

[0022] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be called an "insulator." In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily an "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0023] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily a "conductor" Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0024] A transistor is a type of semiconductor device that controls the amplification of current and voltage, and conduction or non-conduction. In this specification, the transistor can be , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT) ) is included.

[0025] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0026] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0027] (Embodiment 1) In this embodiment, a memory cell included in a semiconductor device 700 according to one embodiment of the disclosed invention will be described. The circuit configuration and operation of the filter array 300 will now be described.

[0028] Note that the semiconductor device refers to a device having a semiconductor element. The semiconductor device includes a driver circuit for driving a circuit including a semiconductor element. In addition, it may also include a drive circuit, a power supply circuit, etc., which are arranged on a separate substrate.

[0029] The semiconductor device 700 also includes an inverter circuit, a NAND circuit, an AND circuit, a NOR circuit, and circuit, OR circuit, buffer, level shifter, XOR circuit, XNOR circuit, AND-NOR circuit circuit, OR-NAND circuit, AND-OR-INV circuit, OR-AND-INV circuit, analog Log switch, flip-flop, settable flip-flop, resettable flip-flop flip-flops, settable and resettable flip-flops, adders, half adders, multipliers Multiplexers, demultiplexers, registers, scan registers, retention registers, Isolators, decoders, etc. may also be included.

[0030] An example of a semiconductor device 700 according to one embodiment of the present invention is illustrated in FIG. The memory cell array 300 includes a peripheral circuit 500 for the memory cell array. The peripheral circuit 500 of the array includes a row selection driver, a column selection driver, an A / D converter, etc. The peripheral circuit 500 may also include a logic circuit. The configuration of the semiconductor device 700 is not limited to the configuration shown in FIG.

[0031] Here, the memory cell array 300, row selection drivers connected to the memory cell array, and column A configuration including the selection driver, the A / D converter, and the like may be called a storage device.

[0032] The memory cell array 300 shown in FIG. 1A has memory cells CL arranged horizontally in a plane. × b vertically (a and b are natural numbers) arranged in a matrix.

[0033] Each memory cell CL is made up of c (c is a natural number equal to or greater than 2) sub-memory cells SCL. Here, the jth (j is a natural number from 1 to c) sub-memory cell is designated as SCL_j. The memory cell SCL_j includes a first transistor Ta_j, a second transistor Tb_j, and a It has a first capacitance element Ca_j.

[0034] That is, the memory cell CL has sub-memory cells SCL_j stacked in c layers, and each sub-memory cell The memory cell SCL includes a first transistor Ta, a second transistor Tb, and a capacitance element Ca. It has.

[0035] For example, when single crystal silicon is used for the transistor Ta_j or the transistor Tb_j, In order to obtain excellent single crystal silicon, it is necessary to use a single crystal silicon substrate or the like. On the other hand, it is preferable to form transistors Ta_j and Tb When an oxide semiconductor layer is used for j, for example, a sputtering method, a CVD method, or M It can be formed by BE, PLD, ALD, etc., and can be repeatedly stacked. Therefore, it is easy to form a semiconductor layer by stacking it on a transistor. As shown in FIG. 1(A), the sub-memory cell S in the c layer is The memory cell CL can be stacked. The memory cell CL is a sub-memory cell SC stacked with c layers. L. Therefore, the capacitance per area can be increased.

[0036] As shown in FIG. 1B, in a memory cell CL consisting of c sub-memory cells SCL, Each sub-memory cell SCL_j shares a bit line BL and a source line SL.

[0037] The gate of the transistor Ta_j is connected to the write word line WWL_j. The transistor Ta_j has one of its source and drain connected to a bit line BL. A floating node FN is connected to the other of the source and drain.

[0038] The transistor Tb_j has a gate connected to a floating node FN. The transistor Tb_j has one of its source and drain connected to a bit line BL. A source line SL is connected to the other of the source and drain.

[0039] The capacitor Ca_j has one electrode connected to the floating node FN and the other electrode connected to the floating node FN. The read word line RWL_j is connected to the pole.

[0040] A word signal is applied to the write word line WWL_j.

[0041] The word signal is transmitted to the floating node FN in order to apply the potential of the bit line BL to the floating node FN. This is a signal that puts the transistor Ta_j into a conductive state.

[0042] The bit line BL is supplied with binary or multi-level data. Multi-level data is k-bit data. Specifically, if it is 2-bit data, it is 4-valued data. The data is a signal having one of four voltage levels.

[0043] A read signal is applied to the read word line RWL_j.

[0044] The read signal is applied to the capacitance element Ca_j to selectively read data from the memory cell. is the signal applied to the other electrode.

[0045] The floating node FN is connected to one electrode of the capacitor Ca_j and the transistor Ta_j. and the gate of the transistor Tb_j. corresponds to one of the nodes above.

[0046] In this specification, a node is a wiring provided for electrically connecting elements. It refers to one of the above.

[0047] In this specification, the word signal applied to the write word line WWL_j is controlled by As a result, the potential of the floating node FN becomes a potential corresponding to the potential of the bit line BL. This is called writing data to a memory cell. By controlling the read signal to be applied, the potential of the bit line BL is changed to the floating node. When the potential of the gate FN changes to a potential corresponding to the potential of the gate FN, it is said that data is read from the memory cell.

[0048] The transistor Ta_j preferably has a second gate electrode (BG). A potential lower or higher than that of the source electrode is applied to the gate electrode, and the transistor threshold voltage is The voltage can be varied in either a positive or negative direction. By shifting the threshold voltage of the transistor in the positive direction, the transistor In some cases, the transistor is in a non-conducting state (off state), which means that the transistor is normally off. The voltage applied to the second gate electrode may be variable or fixed. When the voltage applied to the second gate electrode is made variable, the circuit for controlling the voltage is connected to the second gate electrode. The second gate electrode may be connected to the first gate electrode. By connecting the second gate and the first gate and applying the same potential, the on-current is increased. Addition, reduction of initial characteristic variations, -GBT (Minus Gate Bias Tempe Suppression of degradation during stress testing and on-current at different drain voltages It is possible to suppress fluctuations in the start-up voltage.

[0049] Although not shown in FIG. 1B, the transistor Tb_j also has a second gate electrode (B G). It is preferable that the transistor Tb_j has a high on-state current. By increasing the on-current of the transistor Tb_j, for example, the read The ejection speed can be increased.

[0050] In addition, the liquid crystal element and organic EL (Electroluminescent) element electrically connected to the node FN When a display element such as a luminescence element is included, for example, one of the memory cell arrays 300 The portions may function as pixels of a display device.

[0051] The potential of the floating node FN is determined based on the data given to the bit line BL. The floating node FN is set to a non-conductive state by the transistor Ta_j. Therefore, the read voltage applied to the read word line RWL is When the voltage of the read signal is changed, the potential of the floating node FN is read back to the original potential. This potential change is added to the voltage change of the read signal. Capacitive coupling of the capacitive element Ca_j that occurs when the read signal applied to the RWL changes This is due to the following.

[0052] The transistor Ta_j switches between a conductive state and a non-conductive state to write data. The transistor Ta_j has a function as a switch that controls the input. By retaining the state, it has the function of retaining the potential based on the written data. The transistor Ta_j is also called a first transistor. The following description will be given assuming that the transistor is an n-channel type.

[0053] In addition, when the transistor Ta_j is in a non-conducting state, a current flows between the source and the drain. It is preferable to use a transistor having a low off-state current. The low value means that the voltage between the source and drain is 10 V at room temperature, and the channel width is 1 This means that the normalized off-state current per μm is 10 zA or less. An example of a transistor with low current is a transistor that has an oxide semiconductor in the semiconductor layer. can be done.

[0054] By using a transistor with a small off-state current as the transistor Ta_j, The potential of the floating node FN in the non-conducting state can be maintained for a long period of time. Therefore, the refresh frequency of the semiconductor device can be reduced, and power consumption can be reduced. A semiconductor device requiring less force can be realized.

[0055] The potential held at the floating node FN is maintained at 85°C for 10 years (3.1 5×10 8 To maintain the capacitance at 1 fF, the transistor channel width must be 1 μm. The off-state current per unit is 4.3 yA (1 yA is 10 -24 A) Less than At this time, it is preferable that the allowable fluctuation in the potential of the floating node FN is 0. It is preferable that the OFF current is less than 1.5 yA at 95°C. In the semiconductor device according to one embodiment of the present invention, the hydrogen concentration in the layer below the barrier film is preferably less than 100%. As a result, the transistor using the oxide semiconductor above the barrier film The transistor can achieve extremely low off-state current.

[0056] In addition, by increasing the capacitance, the potential can be held at the node FN for a longer period of time. In other words, the retention time can be extended.

[0057] In the configuration of the memory cell array 300 shown in FIG. 1B, by maintaining a non-conductive state, The floating node FN holds the potential based on the written data. A transistor with low off-state current is used as a switch to suppress the fluctuation of potential accompanying the movement of electric charges. It is particularly preferable to use a

[0058] The transistor Ta_j is made to have a small off-current and is kept in a non-conducting state. In this way, the memory cell array 300 can be made into a nonvolatile memory. The data written to the memory cell array 300 again turns on the transistor Ta_j. The floating node FN can continue to hold the signal until the floating node FN is reset to the normal state.

[0059] The transistor Tb_j changes its source and drain according to the potential of the floating node FN. The memory cell array 30 shown in FIG. In the configuration of 0, the current Id flowing between the source and drain of the transistor Tb_j is The current flowing between the output line BL and the source line SL is For example, a transistor using silicon for the semiconductor layer may be used. A transistor used in the semiconductor layer may be used. An example of using a transistor using an oxide semiconductor for a semiconductor layer is shown below. The transistor Tb_j is also referred to as a second transistor. The description will be given in terms of a transistor.

[0060] The transistor Ta_j and the transistor Tb_j are provided with, for example, a switching For example, a fast n-channel transistor can be used. The switching speed is less than 10 ns, preferably less than 1 ns, more preferably less than 0.1 ns. As an example, an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) A transistor including an oxide semiconductor in a channel formation region (hereinafter, a transistor using an oxide semiconductor) (also called) can be used.

[0061] Next, the operation of the memory cell array 300 shown in FIG. 1B will be described.

[0062] The timing chart shown in FIG. 3 is a timing chart showing the write word line WWL and the read word line WWL shown in FIG. The read word line RWL, the floating node FN, the bit line BL, and the source line SL This shows the changes in each signal given.

[0063] First, the write operation will be explained using FIG. 3(A). Here, binary data The memory cell array 300 is not suitable for writing binary data. The timing chart shown in FIG. 3(A) is not limited to this, and multi-value data can also be written. The figure shows a write period T4, a pause period T5, and a non-selection period T6.

[0064] In the write period T4, first, a potential V2 is applied to the write word line WWL. A potential V0 is applied to the read word line RWL. Then, binary data is written to the bit line BL. A potential corresponding to the source voltage, that is, a H level potential or a L level potential, is applied. An H-level potential is applied to the signal line SL.

[0065] Next, during the idle period T5, the read word line RWL and the write word line WWL are supplied with a voltage. Next, a potential of L level is applied to the bit line BL and the source line SL. Here, for example, the potential V0 may be set to the ground potential, and the potential V2 may be set to a positive potential. It is preferable that the absolute value of the potential V2 is greater than the potential of the H level. It is sufficient to set it to about the threshold value of Tb_j to about three times the threshold value.

[0066] Next, in the non-selection period T6, the read word line RWL and the write word line WWL are energized. Here, the potential V1 may be, for example, a negative potential. The absolute value of the potential of the bit line BL and the source An L level potential is applied to the line SL.

[0067] Next, the read operation will be described with reference to FIG. 3(B). In the timing chart, the potential of the bit line BL is precharged during a period T1, and the potential of the bit line BL is read during a period T2. 10 shows a period T2 during which the bit line BL is discharged and a period T3 during which the bit line BL is not selected.

[0068] In the period T1 shown in FIG. 3B, the potential of the bit line BL is precharged. A potential (potential H') equivalent to the H level is applied to the write line BL. A potential V1 is applied to the word line WWL. A potential V1 is applied to the read word line RWL. The floating node FN holds a potential corresponding to the data. Furthermore, an L level potential is applied to the source line SL.

[0069] At this time, the bit line BL is given a high-level potential and then goes into an electrically floating state. That is, the bit line BL is in a state where a potential fluctuation occurs due to charging or discharging of electric charges. This floating state can be achieved by turning off the switch that applies a potential to the bit line BL. This can be done.

[0070] Next, during the period T2 shown in FIG. 3(B), the bit line BL is discharged to read data. At this time, the write word line WWL is supplied with the potential V1 as in the previous period. Moreover, the read word line RWL is given an H level potential, here a potential V0. In addition, the potential of the floating node FN corresponding to the data increases. The potential of the bit line BL changes according to the potential of the floating node FN. When a low-level potential is input to the loading node FN, the bit line BL A high-level signal (potential H') is output, and a high-level potential is applied to the floating node FN. If an input is made, an L-level signal (potential L') is output to the bit line BL. Furthermore, the source line SL is supplied with an L level potential as in the previous period.

[0071] Next, the period T3 shown in FIG. 3B indicates a non-selected state. The potential of the output word line RWL is set to V1.

[0072] The memory cell array 300 may also have a circuit configuration as shown in FIG. The sub-memory cells SCL_j are alternately connected to the bit lines BL, It may be possible to increase the integration density of the ray 300. Furthermore, the memory capacity per area Here, in FIG. 4, sub-memory cells SCL_j (j=1 to c) are shown. Among them, four sub-memory cells SCL_j, j=1, 2, 3, and c, are shown. The memory cell array 300 may have a circuit configuration as shown in FIG. 5. In FIG. 5, as compared with FIG. In this case, the number of source lines SL can be reduced. Among the sub-memory cells SCL_j, four sub-memory cells SCL_j, where j=1, 2, 3, and c, are 4 and 5, the transistor Ta_j is also shown in FIG. ) may have a second gate electrode (BG) as well.

[0073] [Example of laminated structure] Next, an example of a stacked structure having the memory cell array 300 described in FIG. 1 will be described with reference to FIG. 6. explain.

[0074] The stacked structure shown in FIG. 6 is a semiconductor device having a memory cell array 300 and a peripheral circuit 500. This is an example of the device 700.

[0075] The peripheral circuit 500 includes a transistor 130a, a transistor 130b, a transistor 23 0a and transistor 230b. The transistor 230a and the transistor 230b are made of a first semiconductor material. Examples of semiconductors that can be used as the first semiconductor material include silicon and Semiconductor materials such as luminium, gallium and arsenic, silicon, germanium, gallium and arsenic Compound semiconductor materials containing silicon or aluminum, organic semiconductor materials, or oxide semiconductors Here, single crystal silicon is used as the first semiconductor material. The transistor 130a, the transistor 130b, and the transistor 230 a and transistor 230b may be either p-channel or n-channel. An appropriate transistor may be used depending on the configuration and driving method. The transistors 130a and 130b are n-channel transistors. The transistor 230a and the transistor 230b are p-channel transistors. Here, the transistor 130a and the transistor 130b have almost the same configuration. Therefore, only the transistor 130a will be described. Since the transistor 230b has a similar configuration, only the transistor 230a will be described. Do the following.

[0076] The transistor 130a is provided on a semiconductor substrate 131. a semiconductor layer 132, a gate insulating film 134, a gate electrode 135, and a source region or drain region. It has low resistance layers 133a and 133b that function as a drain region.

[0077] The region where the channel of the semiconductor layer 132 is formed and the region nearby, the source region or the drain region In the low resistance layer 133a and the low resistance layer 133b which become the drain region, a silicon-based semiconductor It is preferable that the semiconductor material contains a semiconductor such as silicon dioxide, and it is preferable that the semiconductor material contains single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). The structure may be made of strained silicon, or GaAs and GaAlAs, etc. By using the above, the transistor 130a can be made into a HEMT (High Electron Mo It may also be called a "ability transistor."

[0078] The transistor 130a has a region 17 which is an LDD (lightly doped drain) region. 6a and region 176b.

[0079] The low resistance layer 133a and the low resistance layer 133b are made of a semiconductor material applied to the semiconductor layer 132. In addition, elements that impart n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, are added. Contains elements that

[0080] The gate electrode 135 is made of an element that provides n-type conductivity, such as phosphorus, or a p-type element, such as boron. Semiconductor materials such as silicon containing elements that impart electrical conductivity, metal materials, alloy materials, or Conductive materials such as metal oxide materials can be used. In particular, It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use a ten.

[0081] The transistor 230a is provided on the semiconductor substrate 131. a semiconductor layer 232, a gate insulating film 134, a gate electrode 235, and a source region or drain region. It has low resistance layers 233a and 233b that function as a drain region.

[0082] For the semiconductor layer 232, the description of the semiconductor layer 132 may be referred to. For the low resistance layer 233b, please refer to the description of the low resistance layer 133a and the low resistance layer 133b. For the gate electrode 235, the description of the gate electrode 135 may be referred to.

[0083] For example, the transistor 130a is an n-channel transistor, and the transistor 2 When the transistor 30a is a p-channel type transistor, the low resistance layer 133a and the low resistance layer 1 For example, phosphorus is added to the low resistance layer 233a and the low resistance layer 233b, and boron is added to the low resistance layer 233a and the low resistance layer 233b. In addition, for example, the gate electrode 135 and the gate electrode 235 may be doped with a work function Different materials may be used for each.

[0084] Here, transistor 130a, transistor 130b, transistor 230a, and transistor The transistor 230b may be replaced by a transistor 190 as shown in FIG. Although FIG. 17 shows an example of an n-channel transistor, a p-channel transistor The cross section shown by the dashed line AB in FIG. 17B. The transistor 190 is formed in the semiconductor layer 132 (semiconductor The gate insulating film 134 and the gate insulating film 135 are formed on the side and top surfaces of the protruding portion of the substrate 131. and a gate electrode 135. Such a transistor 190 is formed on a protruding portion of a semiconductor substrate. It is also called a FIN type transistor because it uses the upper part of the protrusion. In addition, an insulating film may be provided which functions as a mask for forming the convex portions. In the previous section, we showed how to form a protrusion by processing a part of the semiconductor substrate. A semiconductor layer having a convex shape may be formed.

[0085] Transistor 130a, transistor 130b, transistor 230a and transistor The insulating film 136, the insulating film 137, and the insulating film 138 are laminated in this order to cover the capacitor 230b. It is being used.

[0086] The insulating film 136 is formed by insulating the low resistance layer 133a and the low resistance layer 133b in the manufacturing process of the semiconductor device. Activation of the elements that impart conductivity added to the low resistance layers 233a and 233b, etc. The insulating film 136 functions as a protective film during the process. If it is not necessary, it does not have to be provided.

[0087] When the semiconductor layer 132 and the semiconductor layer 232 are made of a silicon-based semiconductor material, the insulating film 13 The insulating film 137 containing hydrogen is preferably an insulating material containing hydrogen. 130a, transistor 130b, transistor 230a and transistor 230b By providing the insulating film 137 and performing heat treatment, hydrogen in the insulating film 137 is used to form the semiconductor layer 132 and the semiconductor layer 2 The dangling bonds in transistor 32 are terminated, and transistors 130a and 130b This can improve the reliability of the transistors 230a and 230b.

[0088] The insulating film 138 is formed on the transistors 130a, 130b, A flattening step formed by the transistor 230a and the transistor 230b is formed. The upper surface of the insulating film 138 is subjected to CMP to improve the flatness of the upper surface. Flattening using methods such as Chemical Mechanical Polishing It may be planarized by processing.

[0089] In addition, the insulating film 136, the insulating film 137, and the insulating film 138 are provided with the low resistance layer 133a and the low resistance layer 133b. 33b, plugs electrically connecting to the low resistance layer 233a and the low resistance layer 233b are embedded. It may be included.

[0090] The memory cell array 300 also includes transistors using an oxide semiconductor. 6 includes a transistor 130a, a transistor 130b, a transistor 130c, a transistor 130d, a transistor 130e, a transistor 130f, a transistor 130g, a transistor 130h, a transistor 130i, a transistor 130j ... A barrier film 1 is provided between the memory cell array 300 and the transistor 230a and the transistor 230b. It is preferred to have 11.

[0091] The barrier film 111 has a function of preventing water and hydrogen from diffusing from the lower layer to the upper layer. It is preferable that the barrier film 111 has low oxygen permeability. The barrier film 111 is provided between an electrode or wiring provided above it and an electrode or The insulating film may have an opening or a plug for electrically connecting to a wiring. A film that is difficult for atoms to diffuse into is, for example, a film that is difficult for atoms to diffuse into compared to silicon oxide, which is generally used as an insulating film. It refers to a membrane that has low permeability to water and hydrogen compared to other membranes. It is a film with low oxygen permeability compared to silicon oxide, which is used as an insulating film.

[0092] Here, it is preferable to reduce hydrogen, water, etc. as much as possible in the layer below the barrier film 111. It is preferable to suppress the desorption of gases. Hydrogen and water are released from the oxide semiconductor. This may cause fluctuations in the electrical characteristics of the barrier film 111. The barrier film 111 can prevent hydrogen and water from diffusing into the layer. There are cases where hydrogen and water diffuse into the upper layer through openings, plugs, etc. provided in 1.

[0093] In order to reduce the amount of hydrogen and water contained in each layer located below the barrier film 111, In order to suppress the desorption of gases, a proton pump is applied to the barrier film 111 before the barrier film 111 is formed or after the barrier film 111 is formed. Immediately after the opening for forming the lag is formed, hydrogen contained in the layer below the barrier film 111 is It is preferable to carry out a heat treatment to remove oxygen and water or to suppress desorption of gases. The heat resistance of the conductive film that constitutes the semiconductor device and the electrical characteristics of the transistor are not deteriorated. Specifically, for example, 450°C or higher is preferable. The temperature is preferably 490°C or higher, more preferably 530°C or higher, but is preferably 650°C or higher. It may be carried out under an inert gas atmosphere or a reduced pressure atmosphere for 1 hour or more, preferably 5 hours. It is preferable to perform the heat treatment for 10 hours or more, more preferably 10 hours or more. The heat resistance of the wiring or electrode material located below 1 should be taken into consideration when determining the thickness. For example, if the material has low heat resistance, the temperature should be 550°C or less, or 600°C or less, or 65°C or less. 0 or less, or 800°C or less. It may be performed once or more, but it is more preferable to perform it multiple times.

[0094] The insulating film provided below the barrier film 111 is analyzed by thermal desorption spectroscopy (TDS analysis). The amount of hydrogen molecules desorbed at a substrate surface temperature of 400°C measured by the At 0°C, the amount of hydrogen molecules released is preferably 130% or less, more preferably 110% or less. Alternatively, TDS analysis showed that the amount of desorption of hydrogen molecules at a substrate surface temperature of 450°C was 350 ° C., it is preferable that the amount of desorption is 130% or less, and more preferably 110% or less.

[0095] It is also preferable that the water and hydrogen contained in the barrier film 111 itself be reduced. For example, the barrier film 111 is preferably a film containing TDS molecules. The surface temperature of the substrate was measured by the analysis of hydrogen molecules (M / z=2) in the range of 20 to 600°C. The amount of desorption is 2×10 15 pieces / cm 2 Less than 1 x 10 15 pieces / cm 2 Less than, more than Preferably 5 x 10 14 pieces / cm 2 It is preferable to use a material for the barrier film 111 that has a resistance of less than 1000 MPa. Alternatively, TDS analysis shows that the water vapor deposition rate is higher in the range of 20℃ to 600℃. The desorption amount of the molecule (M / z=18) is 1×10 16 pieces / cm 2 Less than 5 x 10 1 5 pieces / cm 2 less than 2 x 10 12 pieces / cm 2 Barrier film material less than 1 It is preferable to use 11.

[0096] The heat treatment is also performed on the transistors 130a, 130b, and The silicon dangling bonds (dangling bonds) used in the semiconductor layers of the transistors 230a and 230b This process also serves as a process to terminate the bond (also called green bond) with hydrogen (also called hydrogenation process). By hydrogenation, the transistor 130a, the transistor 130b, and the transistor 130c can be The gate insulating film of the transistor 230a and the transistor 230b and the layer below the barrier film 111 A part of hydrogen contained in the other insulating film formed on the transistor 130a is released, and the transistor 130b is Diffusion in the semiconductor layers of transistor 130b, transistor 230a, and transistor 230b However, by terminating the dangling bonds in silicon, the transistor 130a, The reliability of the transistors 130b, 230a, and 230b is improved. It is possible.

[0097] Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, and the like. Titanium, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), steel titanate The so-called h, such as rontium (SrTiO3) or (Ba,Sr)TiO3 (BST) Insulating films containing igh-k materials can be used as a single layer or a laminate. The coating may be made of, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, or the like. Silicon, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, gas oxide Alternatively, these insulating films may be nitrided to form oxynitride films. The insulating film is laminated with silicon oxide, silicon oxynitride, or silicon nitride. Gallium oxide, etc. are also good. In particular, aluminum oxide has a high resistance to water and hydrogen. This is preferred because it has excellent barrier properties.

[0098] The barrier film 111 includes a layer of a material that is difficult for water and hydrogen to permeate, as well as a layer containing other insulating materials. For example, a layer containing silicon oxide or silicon oxynitride, a metal Layers containing oxides may be stacked.

[0099] Furthermore, it is preferable that the barrier film 111 is made of a material that is difficult for oxygen to permeate. The material has excellent barrier properties against oxygen as well as hydrogen and water. By using the insulating film 114j, oxygen released when the insulating film 114j is heated is lower than that of the barrier film 111. As a result, the diffusion of the ions from the insulating film 114j into the Increasing the amount of oxygen that can be supplied to the semiconductor layers of the transistors Ta_j and Tb_j It can be done.

[0100] In this way, the concentration of hydrogen and water contained in each layer located below the barrier film 111 is reduced. The barrier film 111 reduces the amount of hydrogen and water, or suppresses desorbed gases. This prevents hydrogen and water from diffusing into transistors Ta_j and Tb_j. Therefore, the insulating film 114j and the transistors Ta_j and Tb_j are The hydrogen and water content in each layer can be made extremely low. For example, an insulating film 114j, a semiconductor layer 101j of the transistor Ta_j and the transistor Tb_j, Alternatively, the hydrogen concentration in the gate insulating film 102j is set to 5×10 18 cm -3 Less than, preferably is 1 x 10 18 cm -3 less than 3×10 17 cm -3 Reduce to less than It is possible.

[0101] With the above configuration, a peripheral circuit 500 having transistors using silicon as a semiconductor layer is formed. and a memory cell array 300 including transistors using an oxide semiconductor for a semiconductor layer. This makes it possible to achieve high reliability in both cases, resulting in an extremely reliable semiconductor device. This can be achieved.

[0102] In the above example, the peripheral circuit 500 has a transistor using silicon as a semiconductor layer. The peripheral circuit 500 is made up of transistors using silicon as a semiconductor layer and oxide semiconductors. In this case, for example, a semiconductor layer may be used as a transistor. After forming a barrier film 111 on a transistor using silicon as a semiconductor layer, an oxide semiconductor A transistor using the semiconductor layer is formed by stacking it on the barrier film 111, and a peripheral circuit 5 is formed. 00 is formed on the peripheral circuit 500. The memory cell array 300 having transistors may be formed by stacking layers.

[0103] Here, a p-channel transistor using silicon as a semiconductor layer that can be applied to the peripheral circuit 500 is and a circuit configuration using an n-channel transistor with an oxide semiconductor in the semiconductor layer. An example of the configuration will be explained.

[0104] [CMOS Circuit] The circuit diagram shown in FIG. 26A includes a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. The figure shows the configuration of an OS circuit. In the figure, the transistors to which the second semiconductor material is applied are are indicated with the symbol "OS."

[0105] [Analog Switch] The circuit diagram shown in FIG. 26B shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called analog switch.

[0106] [Layer structure example 1] Next, an example of a stacked structure of a semiconductor device having a memory cell array 300 and a peripheral circuit 500 will be described. This will be described with reference to FIG. 6. A memory cell array 300 is provided on a peripheral circuit 500. The memory cell array 300 includes memory cells CL. The memory cells CL are The memory cells SCL_j have c sub-memory cells SCL_j (j is a natural number from 1 to c). 1 shows an example of a stacked structure of a sub-memory cell SCL_1 and a sub-memory cell SCL_2. Although not shown, a sub-memory cell SCL_3 is further stacked on the sub-memory cell SCL_2. The memory cells are stacked in order up to the sub-memory cell SCL_c. For the route diagram, see FIG. 1(B).

[0107] The sub-memory cell SCL_j includes a transistor Ta_j, a transistor Tb_j, and a capacitor The transistors Ta_j and Tb_j are oxide semiconductors. Here, when j=1, the transistor Tb_j and the peripheral circuit A barrier film 111 is preferably provided between the substrate 500 and the insulating film 111 .

[0108] In addition, a capacitive element Ca_j is provided on the transistor Tb_j. At least a part of the element Ca_j is provided so as to overlap with the transistor Tb_j. Here, the conductive layer 151j, which is one of the terminals of the capacitance element Ca_j, is preferably 41j and electrically connected to the gate electrode 203j of the transistor Tb_j. An insulating film 216j is provided between the transistor Tb_j and the capacitive element Ca_j.

[0109] The transistor Ta_j is provided on the capacitive element Ca_j. It is preferable that at least a part of the capacitance element Ca_j overlaps with the capacitance element Ca_j. Here, the gate electrode 203j and the conductive layer 151j are connected to the plug 141j and the plug 144j. Conductive layer 1, which serves as a source electrode or a drain electrode of transistor Ta_j through The insulating film 115j of the capacitor element Ca_j is electrically connected to the conductive layer 104j_b. The capacitor element Ca_j is sandwiched between the capacitor element Ca_j and the conductive layer 152j. An insulating film 156j is provided between the transistors Ta_j. An insulating film 116j is provided on the j.

[0110] A conductive layer 204j serving as a source electrode or a drain electrode of the transistor Tb_j The plug 143j, the conductive layer 154j, and the plug 143j are electrically connected to the source line SL. The lug 146j, the plug 148j, etc. may function as a source line SL.

[0111] A conductive layer 204j serving as a source electrode or a drain electrode of the transistor Tb_j _a is connected to the transistor Ta through the plug 142j, the conductive layer 153j, the plug 145j, etc. and the conductive layer 104j_a serving as a source electrode or a drain electrode of The conductive layer 204j_a and the conductive layer 104j_a are electrically connected to the bit line BL. Here, the plug 142j, the conductive layer 153j, the plug 145j, etc. are connected to the bit line BL. It may also function as a

[0112] In addition, the sub-memory cell SCL_j is connected to the adjacent sub-memory cell SCL_α by the plug 1. 42j, conductive layer 153j, plug 145j, plug 147j, etc. are shared. The SCL_α includes a plug 142j, a conductive layer 153j, a plug 145j, a plug 147j, etc. Similarly, the sub-memory cell SCL_j is electrically connected to the bit line BL via the adjacent a sub-memory cell SCL_β corresponding to the plug 143j, a conductive layer 154j, a plug 146j, The sub-memory cell SCL_β shares the plug 143j, the conductive layer 1 54j, and is electrically connected to the source line SL via the plug 146j, plug 148j, and the like. By sharing the plugs and conductive layers in this way, the integration degree of the memory cell array 300 can be increased. It can be done.

[0113] Here, the sub-memory cell SCL_α is a memory cell CL_α adjacent to the memory cell CL. Here, the adjacent memory cell is the sub-memory cell of x shown in FIG. In the y coordinate (x, y), it indicates that the memory cell has a different x or y value by 1. For example, The memory cell CL_α is located at a coordinate whose x coordinate is 1 smaller than that of the memory cell CL. For example, the memory cell CL_β is located at the x coordinate which is one greater than the memory cell CL. Place.

[0114] The transistor Tb_j of the sub-memory cell SCL_j is The conductive layer 204j_a is shared with the transistor Tb_α of the transistor α. 204j_a functions as either the source electrode or the drain electrode of the transistor Tb_j. and functions as either the source electrode or the drain electrode of the transistor Tb_α. The transistor Tb_j is a transistor T b_β and the conductive layer 204j_b. That is, the conductive layer 204j_b is The transistor Tb_j functions as the other of the source electrode and the drain electrode of the transistor Tb_j. This layer functions as either the source or drain electrode of Tb_β. By providing such a memory cell array 300, the degree of integration of the memory cell array 300 can be increased.

[0115] The transistor Ta_j of the sub-memory cell SCL_j is The conductive layer 104j_a is shared with the transistor Ta_α of the transistor α. 104j_a functions as either the source electrode or the drain electrode of the transistor Ta_j. and functions as either the source electrode or the drain electrode of the transistor Ta_α. By sharing the conductive layer in this manner, the integration degree of the memory cell array 300 can be increased. It is possible.

[0116] Here, the structures of the transistors Ta_j and Tb_j will be described. The transistor Ta_j and the transistor Tb_j are transistors including an oxide semiconductor. Transistors that can be used for the transistors Ta_j and Tb_j An example of the structure is shown in Figure 7.

[0117] FIG. 7B shows transistors that can be used for the transistors Ta_j and Tb_j. 7A shows a cross section taken along the dashed line AB shown in FIG. 7B. (C) shows a cross section taken along the dashed line CD in FIG. 7(B). Here, a transistor is used as an example. Although the transistor Ta_j is shown, the same structure can be applied to the transistor Tb_j. In addition, for each component of the transistor Tb_j, the description of the transistor Ta_j is For example, the semiconductor layer 201j is described in the same way as the semiconductor layer 101j. For the gate insulating film 202j, refer to the gate insulating film 102j. For 203j, refer to the gate electrode 103j. The layer 204j_b is referred to as the conductive layer 104j_a and the conductive layer 104j_b. The insulating film 214j is similar to the insulating film 114j. refers to the conductive layer 105j.

[0118] The transistor Ta_j includes a semiconductor layer 101j in contact with the upper surface of the insulating film 114j and a conductive layer 104j_a and the conductive layer 104j_b, and the gate insulating film 102j on the semiconductor layer 101j. and a gate electrode 103j overlapping the semiconductor layer 101j via a gate insulating film 102j. In addition, an insulating film is provided to cover the transistor Ta_j. However, as an insulating film covering the transistor Ta_j, for example, an insulating film 112j, an insulating film 11 The insulating film 112j, the insulating film 3j, and the insulating film 116j can be stacked. The conductive layer 104 and the insulating film 116j will be described in a manufacturing method example below. One of the j_a and the conductive layer 104j_b functions as a source electrode, and the other functions as a drain electrode. It functions as:

[0119] The transistor Ta_j shown in FIGS. 7A to 7C includes a semiconductor layer 101j_a and a semiconductor a semiconductor layer 101j_b in contact with the upper surface of the semiconductor layer 101j_a; and the conductive layer 104j_a and the conductive layer 104j_b are spaced apart in the region where they overlap with the semiconductor layer 101j_b. 04j_b, a semiconductor layer 101j_c in contact with the upper surface of the semiconductor layer 101j_b, and a semiconductor layer The gate insulating film 102j is formed on the gate insulating film 102j and the semiconductor layer 101j. and a gate electrode 103j overlapping the semiconductor layer 101j_b via a gate electrode 103c. The transistor Ta_j has a conductive layer 105j that functions as a second gate electrode. The insulating layer 114j is provided between the insulating film 114j and the semiconductor layer 101j_b. The semiconductor layer 101j_c is provided between the semiconductor layer 101j_b and the gate insulating film 102j. The conductive layer 104j_a and the conductive layer 104j_b are formed on the semiconductor layer 101j. _contacts the upper surface of b.

[0120] Also, as shown in the cross section of FIG. 7(A) in FIG. 7(D), and as shown in the cross section of FIG. 7(C) in FIG. 7(E), The insulating film 114j has a convex portion, and the semiconductor layer 101j_a and the semiconductor layer 101 j_b may be provided.

[0121] Also, as shown in FIGS. 18(A) to 18(C), for example, in the cross section of FIG. 18(C), The end portion of the semiconductor layer 101j_c may be covered with a gate insulating film 102j.

[0122] The semiconductor layer 101j of the transistor Ta_j is preferably provided on the insulating film 114j. The insulating film 114j preferably contains an oxide. Preferably, the oxide material contains a material that desorbs oxygen. It is preferable to use an oxide containing as much oxygen as possible as the second semiconductor material. In the case where the insulating film 114j is used, oxygen desorbed from the oxide semiconductor is supplied to the oxide semiconductor. It is possible to reduce oxygen vacancies in the conductor. As a result, the electrical characteristics of the second transistor are improved. This can reduce gender fluctuations and increase reliability.

[0123] The upper surface of the insulating film 114j is preferably planarized by the above-mentioned planarization process. .

[0124] The insulating film 114j is preferably made of an oxide material from which oxygen is partially released by heating. stomach.

[0125] As an oxide material that releases oxygen by heating, it is possible to It is preferable to use an oxide containing more oxygen than the stoichiometric composition. When an oxide film containing oxygen is heated, some of the oxygen is released. Oxide films containing more oxygen than The surface temperature of the membrane is measured by Esorption Spectroscopy. The temperature ranges from 100°C to 700°C, preferably from 100°C to 500°C. The amount of elementary molecules removed is 1.0 × 10 18 atoms / cm 3 or more, preferably 3.0 × 10 2 0 atoms / cm 3 The oxide film is as described above.

[0126] For example, such a material may include silicon oxide or silicon oxynitride. Alternatively, a metal oxide can be used. Aluminum, aluminum oxynitride, gallium oxide, gallium oxynitride, yttria Usable are yttrium oxide nitride, hafnium oxide, hafnium oxide nitride, etc. In this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen as its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. Indicates the material with the highest content.

[0127] Similarly, the semiconductor layer 201j of the transistor Tb_j is provided on the insulating film 214j. It is preferable that

[0128] Moreover, the transistor Ta_j preferably includes a conductive layer 105j. 5j preferably serves as the second gate of transistor Ta_j.

[0129] As shown in FIGS. 19A to 19C, the transistor Tb_j has an insulating film 214j a semiconductor layer 201j in contact with the upper surface of the conductive layer 204j_a and the conductive layer 204j_b; The gate insulating film 202j on the conductor layer 201j and the semiconductor layer 2 and a gate electrode 203j overlapping the transistor Tb_j. , an insulating film 212j, an insulating film 213j, and an insulating film 216j are provided. One of the j_a and the conductive layer 204j_b functions as a source electrode, and the other functions as a drain electrode. It functions as:

[0130] The transistor Tb_j may also include a conductive layer 205j. It may also function as the second gate of the transistor Tb_j.

[0131] Here, the conductive layer 105j of the transistor Ta_j and the conductive layer 105j of the transistor Tb_j are When a voltage is applied between the electrodes of the conductive layer 205j, the voltage may be different. Here, the difference between the voltage applied to the conductive layer 105j and the source voltage is Vbg_1, and the conductive layer 205 The difference between the voltage applied to j and the source voltage is Vbg_2. By increasing the absolute value, a lower off-state current may be achieved. If the absolute values ​​of g_1 and Vbg_2 are too large, the on-current rise voltage will become high. This allows the transistor to operate at a low circuit voltage. It is preferable to make the off-current of the transistor Ta_j lower than that of the transistor Tb_j. Therefore, for example, the absolute value of Vbg_1 should be greater than the absolute value of Vbg_2. In this way, by making the absolute values ​​of Vbg_1 and Vbg_2 different, The retention characteristics of the semiconductor device can be improved and the power consumption can be reduced. This can increase the production speed.

[0132] The semiconductor layer 101j may be formed as a single layer, or as shown in the example of FIG. The semiconductor layer 101j_a is formed by laminating a semiconductor layer 101j_b and a semiconductor layer 101j_c. Similarly, the semiconductor layer 201j may be formed as a single layer, or the semiconductor layer 20 The semiconductor layer 1j_a is formed of a laminated structure of a semiconductor layer 201j_b and a semiconductor layer 201j_c. That's fine.

[0133] The insulating film 112j may be made of a material that is difficult for water and hydrogen to diffuse, similar to the barrier film 111. In particular, it is preferable to use a material that is less permeable to oxygen for the insulating film 112j. The insulating film 112j may have a stacked structure of two or more layers. For example, the insulating film 112j has a two-layer laminate structure, and the lower layer is made of, for example, silicon oxide or silicon oxynitride. , silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, nitride oxide The upper layer may be a barrier film 111 and an aluminum nitride film. Similarly, it is preferable to use a material that is difficult for water and hydrogen to diffuse into. The insulating film 114j is an insulating film from which oxygen is released by heating, and the insulating film 102 Oxygen may also be supplied from above the semiconductor layer 101j via the oxygen supply pipe j.

[0134] By covering the semiconductor layer 101j with an insulating film 112j containing a material that is difficult for oxygen to permeate, Therefore, oxygen can be prevented from being released from the insulating layer 101j above the insulating film 112j. Furthermore, oxygen desorbed from the insulating film 114j can be trapped below the insulating film 112j. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101j can be increased. .

[0135] In addition, the insulating film 112j, which is impervious to water and hydrogen, prevents the oxide semiconductor from being exposed to the outside. This prevents the inclusion of impurities such as water and hydrogen, and improves the electrical characteristics of the transistor Ta_j. Fluctuations are suppressed, and highly reliable transistors can be realized.

[0136] In addition, below the insulating film 112j, oxygen is released by heating, similar to the insulating film 114j. and oxygen is also introduced from the upper side of the semiconductor layer 101j through the gate insulating film 102j. It may be configured to supply the

[0137] For the insulating film 212j on the transistor Tb_j, see the description of the insulating film 112j. That's fine.

[0138] As shown in FIG. 7A, the side surface of the semiconductor layer 101j_b of the transistor Ta_j is conductive. The gate electrode 103j is in contact with the conductive layer 104j_a and the conductive layer 104j_b. This allows the semiconductor layer 101j_b to be electrically surrounded (by the electric field of the conductor). The structure of a transistor that electrically surrounds a semiconductor is called a surrounded channel. This is called a nel (s-channel) structure. Therefore, the entire semiconductor layer 101j_b In the s-channel structure, a channel may be formed in the transistor (bulk). A large current can flow between the source and drain of the transistor, increasing the current (on-state current) when the transistor is conducting. It is possible.

[0139] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. Preferably, the transistor has a channel width of 20 nm or less. or 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has a region.

[0140] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on state). The source (source region or source electrode) in the region where the channel is formed. The distance between the transistor and the drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0141] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows) or the area where the channel is formed. The length of the part where the source and drain face each other is called the length of one transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0142] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in a transistor with a fine, three-dimensional structure, the upper surface of the semiconductor The ratio of the channel region formed on the side of the semiconductor to the ratio of the channel region formed on the inside of the semiconductor In this case, the apparent channel width shown in the top view may be The effective channel width where the channel is actually formed is larger than the actual channel width.

[0143] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0144] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is referred to as "Surrounded Channel Width (SCW)". In this specification, when simply referred to as the channel width, This may refer to the enclosed channel width or apparent channel width. In the detailed description, when simply referred to as a channel width, it may refer to an effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, and enclosure The channel width can be determined by acquiring a cross-sectional TEM image and analyzing the image. , values ​​can be determined.

[0145] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0146] The semiconductor layer 101j and the semiconductor layer 201j have a larger energy gap than silicon. Preferably, the semiconductor layer 101j includes an oxide semiconductor. A semiconductor with a wider energy gap and lower carrier density than silicon. The use of such a material is preferable because it can reduce the current in the off state of a transistor.

[0147] By using such materials for the semiconductor layer, fluctuations in electrical characteristics are suppressed, and reliability is improved. High-performance transistors can be realized.

[0148] The preferred oxide semiconductors applicable to the semiconductor layer and their forming methods are as follows: This will be explained in detail in a later embodiment.

[0149] In this specification and the like, when the term "substantially intrinsic" is used, the carrier density of the oxide semiconductor layer is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than 1×10 13 / cm 3 less than, 8×10 11 / cm 3 Less than 1×10 11 / cm 3 Less than or equal to 1 x 10 10 / cm 3 Not yet is 1×10 -9 / cm 3 The oxide semiconductor layer is highly purified to be intrinsic. This allows the transistor to have stable electrical characteristics.

[0150] The semiconductor layer 101j_b may be, for example, In:Ga:Zn=1:1:1, 2:1:3, 3 When using In-Ga-Zn oxides with atomic ratios of 1:1 or 4:2:3, the semiconductor The dielectric layer 101j_a or the semiconductor layer 101j_c may be, for example, In:Ga:Zn=1:3 : 2, 1:3:4, 1:3:6, 1:6:4, 1:6:8, 1:6:10, 1:9:6, or an In-Ga-Zn oxide having an atomic ratio such as 1:2:3 can be used. In addition, the atomic ratios of the semiconductor layer 101j_b, the semiconductor layer 101j_a, and the semiconductor layer 101j_c each include fluctuations of plus or minus 20% of the above atomic ratio as an error. Also, the semiconductor layer 101j_a and the semiconductor layer 101j_c may be made of the same composition material or materials of different compositions.

[0151] Also, when an In-M-Zn oxide is used as the semiconductor layer 101j_b, the target used to form the semiconductor film that becomes the semiconductor layer 101j_b, when the atomic ratio of the metal elements contained in the target is In:M:Zn = x1:y1:z1, the value of x1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less , preferably an oxide having an atomic ratio of 1 or more and 6 or less is preferably used. Note that by setting z1 / y 1 to 6 or less, the CAAC-OS film described later is likely to be formed. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 2:1:3, 3 :1:2, etc.

[0152] Also, when an In-M-Zn oxide is used as the semiconductor layer 101j_a and the semiconductor layer 101j_c, the target used to form the semiconductor film that becomes the semiconductor layer 101j_a and the semiconductor layer 101j_c, when the atomic ratio of the metal elements contained in the target is In:M:Zn = x2:y2:z2, x2 / y2 < x1 / y1, and it is preferable to use an oxide having an atomic ratio of 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. When z2 / y2 is set to 6 or less, the CAAC-OS film described later is easily formed. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn=1:3:4, Examples include 1:3:6 and 1:3:8.

[0153] When oxide semiconductors are deposited by sputtering, the atomic ratio of the target may deviate from the target atomic ratio. In particular, zinc may form a film with a higher atomic ratio than the target. Specifically, the ratio of the number of atoms of zinc contained in the target to 4 may become smaller. It may be between 0 atomic% and 90 atomic%.

[0154] The conductive layer 104j_a and the conductive layer 104j_b are made of aluminum, titanium, chromium, nickel, or the like. copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten A metal consisting of these or an alloy containing this as a main component is used as a single layer structure or a laminated structure. For example, a single layer structure of aluminum film containing silicon, or a laminated aluminum film on a titanium film Two-layer structure with aluminum film on tungsten film, two-layer structure with copper-magnesium film Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film a two-layer structure in which a copper film is laminated on a tungsten film; a titanium film or titanium nitride film; An aluminum film or a copper film is laminated on the titanium film or titanium nitride film, and then A three-layer structure in which a titanium film or titanium nitride film is formed on top of a molybdenum film or molybdenum nitride film A molybdenum film and an aluminum film or copper film are superimposed on the molybdenum film or molybdenum nitride film. Three-layer structure in which a film is laminated and then a molybdenum film or molybdenum nitride film is formed on top of that It should be noted that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used. stomach.

[0155] The gate insulating film 102j is made of, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitrogen Silicon oxide or the like may be used, and the layer may be a laminated layer or a single layer.

[0156] The gate insulating film 102j is made of hafnium silicate (HfSiO x ), nitrogen Doped hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium Aluminate (HfAl x O y N z ), using high-k materials such as yttrium oxide That's fine.

[0157] The gate insulating film 102j may be made of aluminum oxide, magnesium oxide, or silicon oxide. silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide oxides such as zinc oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide oxide insulating film, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride The insulating film can be formed using a nitride insulating film such as SiO2 or a mixture of these materials.

[0158] The gate insulating film 102j is made of a material having a stoichiometric composition similar to the insulating film 114j. It is preferable to use an oxide insulating film containing more oxygen than oxygen.

[0159] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. Like the stacked film of hafnium, a part of the gate insulating film is made of hafnium oxide, aluminum oxide, and oxide. By using a material with many electron capture levels, such as tantalum, and by using it at a higher temperature (the operating temperature of the semiconductor device), Or higher than the storage temperature, or 125°C or higher and 450°C or lower, typically 1 Under the temperature range of 50°C to 300°C, the potential of the gate electrode is set to the potential of the source electrode and drain electrode. By maintaining a higher state for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move towards the poles, and some of them are captured by the electron capture levels.

[0160] In this way, a transistor that has captured the necessary number of electrons in the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The process for adding the conductive layer may be performed during the manufacturing process of the transistor.

[0161] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After the wafer processing, or after the wafer dicing process. It is advisable to carry out this at any stage before shipping from the factory, such as after packaging. It is preferred that the subsequent exposure to temperatures above 125°C is not carried out for more than one hour.

[0162] The gate electrode 103j is made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of nickel, tungsten, or an alloy containing the above-mentioned metals; It can be formed by using an alloy combining metals such as manganese and zirconia. One or more metals selected from the group consisting of ammonium, ammonium, ammonium hydroxide, ammonium nitrate ... Semiconductors such as doped polycrystalline silicon, and silicon such as nickel silicide The gate electrode 103j may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on a titanium nitride film; a two-layer structure in which a titanium film is laminated on a titanium nitride film; Two-layer structure with tungsten film stacked on tantalum film, tantalum nitride film or tungsten nitride film Two-layer structure with tungsten film on top of titanium film, and aluminum film on top of titanium film. There are three-layer structures, such as a laminated film and a titanium film on top of that. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, an alloy film or a nitride film made by combining one or more of the above may be used.

[0163] The gate electrode 103j is made of indium tin oxide or indium containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium titanium oxide oxide, indium tin oxide, indium zinc oxide, silicon oxide A conductive material having light-transmitting properties, such as doped indium tin oxide, can also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0164] The conductive layer 105j may be formed using a material similar to that of the gate electrode 103j.

[0165] In addition, an In-Ga-Zn oxynitride film is formed between the gate electrode 103j and the gate insulating film 102j. Semiconductor film, In-Sn oxynitride semiconductor film, In-Ga oxynitride semiconductor film, In-Z n-based oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN, ZnN, etc.) may be provided. These films have a resistance of 5 eV or more, preferably 5.5 e V or more, which is larger than the electron affinity of oxide semiconductors. The threshold voltage of a transistor using a semiconductor can be shifted to the positive side, It is possible to realize a switching element with maria-off characteristics. For example, In-Ga-Zn oxynitride When a semiconductor film is used, the nitrogen concentration is at least higher than that of the semiconductor layer 101j, specifically, 7 atoms. An In-Ga-Zn-based oxynitride semiconductor film having a thickness of 100 nm or more is used.

[0166] In the configuration shown in FIG. 7A, the gate insulating film 102j and the end portion of the semiconductor layer 101j_c are The gate electrode 103j is located inside the gate insulating film. The gate insulating film 102j, the semiconductor layer 101j_c, and the gate The end of the gate electrode 103j may be processed so as to be approximately aligned. The film 102j, the semiconductor layer 101j_c, and the gate electrode are formed so that their edges do not coincide with each other. It may be processed.

[0167] As an example of a different structure of the transistor Ta_j and the transistor Tb_j, 8(D), 18(E), 19(D) and 19(E). Here, the transistor Ta_j will be described, but the same applies to the transistor Tb_j. Such a structure can be used.

[0168] When the semiconductor layer 101j_a and the semiconductor layer 101j_b are formed, the conductive film 104 is formed. After forming the conductive film 104, a resist mask is formed, and the conductive film 104 is etched. The semiconductor layer that will become j_a and the semiconductor layer that will become semiconductor layer 101j_b are formed by etching. Thereafter, the conductive film 104 is processed again to form the conductive layer 104j_a and the conductive layer 104j_b. b is formed to form a structure as shown in FIG. 18(D).

[0169] As shown in FIG. 18(E), the semiconductor layer 101j_c is formed by a conductive layer 104j_a and a conductive The conductive layer 104j_b may be provided in contact with the lower surface of the conductive layer 104j_b. The semiconductor layers 101j_a, 101j_b, and 101j_c are Each film can be deposited continuously without being exposed to the atmosphere. Therefore, it is possible to reduce the number of interface defects.

[0170] The transistor Ta_j may have a structure shown in FIG. In the example shown in FIG. 1, an opening is provided in the insulating film 116j to form a plug, and the source electrode and the drain electrode are The transistor Ta_j has an insulating film 112 under the insulating film 116j. j and insulating film 113j.

[0171] Also, as shown in FIG. 19(E), a low resistance region may be provided in the semiconductor layer 101j. After forming a semiconductor film that will become the semiconductor layer 101j on the insulating film 114j, a resist mask or the like is applied. Then, a gate insulating film 102j is formed on the semiconductor layer 101j by etching. An insulating film to be formed and a conductive film to be formed as the gate electrode 103j are formed, and a resist mask or the like is formed. Then, etching is performed to form a gate electrode 103j and a gate insulating film 102j.

[0172] Next, the low resistance region 171j_a and the low resistance region 171j_b are formed. A semiconductor layer with a high carrier density has a low resistance. For example, methods for increasing the carrier density include the addition of materials and the formation of oxygen vacancies. The elements can be added by ion implantation. argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, Candium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium Aluminum, germanium, arsenic, yttrium, zirconium, niobium, molybdenum, indium Select from aluminum, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. It is preferable to add one or more selected from the low resistance region 171j_a and the low resistance region 171j_b is, for example, a semiconductor layer 101j containing 5×10 19 ato ms / cm 3 or more, preferably 1 × 10 20 atoms / cm 3 More preferably, 2×10 20 atoms / cm 3 More preferably, 5 × 10 20 atoms / cm 3 This is an area that includes the above.

[0173] Such low resistance regions may be able to trap unwanted hydrogen, for example. By trapping unnecessary hydrogen in the low resistance layer, the hydrogen concentration in the channel region is reduced. , good characteristics can be obtained as the characteristics of the transistor Ta_j.

[0174] In the examples of the transistors shown in FIGS. 7, 18, and 19, the semiconductor layer 101j_b The semiconductor layer 101j_a and the semiconductor layer 101j_c are provided in contact with the semiconductor layer 101j_a. A configuration in which either the conductor layer 101j_a or the semiconductor layer 101j_c, or both, are not provided It may also be possible to use the following.

[0175] The above is the explanation of the transistor Ta_j and the transistor Tb_j.

[0176] The insulating film 116j covering the transistor Ta_j is a planarizing film that covers the uneven shape of the underlying layer. The insulating film 113j also functions as a protective film when the insulating film 116j is formed. The insulating film 113j may not be provided if it is not necessary.

[0177] Similarly, the insulating film 216j covering the transistor Tb_j covers the uneven shape of the underlying layer. The insulating film 213j also functions as a planarizing layer when forming the insulating film 216j. The insulating film 213j may not be provided if it is not necessary.

[0178] The insulating film 156j covering the capacitance element Ca_j is, for example, the same as the insulating film 116j. Please refer to the attached document.

[0179] The insulating film 112j, the insulating film 113j, and the insulating film 116j are electrically connected to the conductive layer 104j_a, etc. A plug 147j for electrical connection is embedded.

[0180] The insulating film 212j, the insulating film 213j, and the insulating film 216j are provided with a gate electrode 203j. Plugs 141j and the like are embedded to electrically connect to the conductive layers 151j and the like.

[0181] 6, a material similar to the barrier film 111 is formed on the insulating film 136 containing hydrogen. In this case, the insulating film 137 containing hydrogen may be provided. The upward diffusion of water and hydrogen remaining in the insulating film 136 can be effectively suppressed. In this case, the barrier layer 134 is formed before and after the insulating film 137 is formed. Before forming the film 111, a heat treatment for removing water and hydrogen is performed at least twice in total. That's fine.

[0182] The plugs 141j to 148j, the conductive layers 151j to 154j, etc. are made of a material A conductive material such as a metal material, an alloy material, or a metal oxide material can be used as the In particular, high-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use titanium nitride or titanium dioxide, and tungsten is particularly preferable. Materials such as titanium nitride and titanium may be laminated together. By doing so, it is possible to improve the adhesion to the opening. The lug 148j, the conductive layers 151j to 154j, etc. are designed to be embedded in the insulating film. Preferably, the upper surfaces of the respective electrodes are flattened.

[0183] Oxide semiconductor layers are repeatedly stacked on the transistor Ta_j and the transistor Tb_j. By forming a semiconductor layer, as shown in Figure 1(A) and Figure 6, the sub-memory of the c layer It is possible to stack the cells SCL, which increases the capacitance per area. do.

[0184] Conventional transistors using silicon, germanium, or their compounds have a particularly small size. In order to suppress the short channel effect in devices with a long channel length, the gate electric field is strengthened. It is preferable to make the gate insulating film thinner in order to strengthen the gate electric field.

[0185] On the other hand, a transistor using an oxide semiconductor film is an accumulation-type transistor in which electrons are the majority carriers. Therefore, compared to an inversion transistor with a pn junction, it has a short channel One of the effects is the Drain-Induced Barrier Lowering (DIBL) The transistor using an oxide semiconductor film has low resistance to the short-channel effect. This can also be expressed as having resistance to

[0186] Because of its high resistance to the short-channel effect, a transistor using an oxide semiconductor film It is possible to make the gate insulating film thicker than conventional transistors that use silicon, etc. For example, even in a minute transistor with a channel length and width of 50 nm or less, A thick gate insulating film of about 0 nm may be used. This can reduce the parasitic capacitance, which may improve the dynamic characteristics of the circuit. In addition, by making the gate insulating film thicker, leakage current can be reduced and power consumption can be reduced. There is a match.

[0187] In addition, as the channel length becomes smaller, the drain electric field becomes stronger, so silicon and other materials are used. In conventional transistors, hot carriers are generated especially when the channel length is very small. On the other hand, the energy gap of oxide semiconductors is For example, in the case of oxide semiconductors containing indium, gallium, and zinc, the (Top) Electrons are difficult to excite and the effective mass of holes is large, so conventional systems Compared to transistors using silicon, avalanche breakdown may be less likely to occur. Therefore, for example, it may be possible to suppress hot carrier degradation caused by avalanche breakdown. be.

[0188] By making the gate insulating film thicker, the breakdown voltage of the gate insulating film can be increased, resulting in a higher The transistor can be driven by the gate voltage. Also, hot carrier degradation is suppressed. This allows the transistor to be driven at a high drain voltage without increasing the channel length. Therefore, the reliability of the transistor can be improved in a circuit to which a high voltage is input. This allows the channel length to be reduced, thereby increasing the degree of circuit integration. do.

[0189] In addition, in a transistor using an intrinsic or substantially intrinsic oxide semiconductor film, When the distance between the source and drain electrodes is small enough, the influence of the source and drain electric fields This lowers the energy of the conduction band edge, and the conduction band energy and the Fermi level become closer. This phenomenon is called the Conduction Band Lowering Effect ( The CBL effect causes a low gate voltage near 0V in the Vg-Id characteristics. Since the drain current starts to flow from the minimum voltage, the driving voltage of the transistor can be lowered. It may be possible.

[0190] Here, a CAAC-OS film is preferably used as the oxide semiconductor film. It is preferable that the CAAC ratio of the OS film is high. By increasing the CAAC ratio, for example, The influence of carrier scattering in transistors can be reduced, resulting in high field-effect mobility. In addition, the influence of grain boundaries can be reduced, which improves the transistor The variation in ON characteristics can be reduced, thereby achieving a highly reliable semiconductor device. In addition, by using transistors with small variations, the driving voltage can be reduced. Furthermore, for example, a CAAC-OS film with low defect density can be used. It is also possible to realize a CAAC-OS film with few impurities. By reducing the defect density, it is possible to achieve, for example, extremely low off-current characteristics. The CAAC-OS film will be described later.

[0191] Here, the semiconductor layer 101j_b of the transistor Ta_j and the semiconductor layer 101j_b of the transistor Tb_ The semiconductor layer 201j_b of the semiconductor layer 10j may be formed of a different material. When In-M-Zn oxide is used for the semiconductor layer 201j_b and the semiconductor layer 201j_b, indium, Materials having different atomic ratios of element M and zinc may also be used.

[0192] In addition, transistors Ta_j and Tb_j are transistors with different structures. The channel widths of the transistors Ta_j and Tb_j may be Similarly, the channels of the transistors Ta_j and Tb_j may be different. The lengths of the lines may be different.

[0193] In addition, the semiconductor layer 101j of the transistor Ta_j and the semiconductor layer 101j of the transistor Tb_j are The semiconductor layer 201j has an oxide semiconductor containing In, an element represented by M, and Zn. The number of atoms of In, M, and Zn in the oxide semiconductor of the semiconductor layer 101j is preferably The ratio of In:M:Zn satisfies a:b:c, and the oxide semiconductor of the semiconductor layer 201j The ratio of the number of In, M, and Zn atoms is In:M:Zn=d:e:f. Here, for example, it is preferable that a / (a+b+c) is smaller than d / (d+e+f). By increasing the indium content, more s orbitals overlap, Oxides with a high indium content have higher mobility than oxides with a low indium content. Therefore, by using an oxide with a high indium content for the oxide semiconductor film, On the other hand, if the indium content is reduced, the carrier mobility can be increased. In some cases, lower currents can be achieved, which is preferable.

[0194] [Layer structure example 2] The stacked structure shown in FIG. 8 is an example of a stacked structure of a semiconductor device different from that shown in FIG. The semiconductor device shown in FIG. 8 includes a memory cell array 300 and a peripheral circuit 500. 8 indicates stacking up to j=4, but in reality, sub-memory cells of j=5 or more may be stacked. The more layers there are, the more memory integration can be achieved, which is preferable. For the circuit diagram of the memory cell array 300 shown, see, for example, FIG. 4. Here, in FIG. In order to make the drawing easier to understand, some of the film interfaces and the like are omitted.

[0195] Here, the layer 291 shown in FIG. 8 has a transistor. Also, the layer 292 and The layer 293 includes a conductive layer. The layer 294 shown in FIG. 8 includes a transistor. The layers 295 and 296 shown in FIG. 8 are conductive layers. The top views of each are shown in Figure 10.

[0196] In Figure 6, a transistor, a capacitor ... In contrast to the stacking of the sub-memory cells in Figure 8, the sub-memory cells are arranged alternately. Thus, the transistor, the capacitor, the transistor, and the capacitor are stacked in this order. The process can be simplified.

[0197] FIG. 9 is an enlarged view of a part of FIG. 8. A capacitance element Ca At least a part of the capacitance element Ca_j is connected to the transistor Tb It is preferable that a part of the capacitance element Ca_j overlaps with the adjacent capacitance element Ca_j. The transistors may be provided so as to overlap with the transistors of the corresponding sub-memory cells. In this example, the capacitance element Ca_3 of the sub-memory cell SCL_3 is The transistor Ta_2 of the memory cell array SCL_2 is provided so as to overlap with the transistor Ta_2 of the memory cell array SCL_2. The integration density of Ray 300 can be increased.

[0198] The sub-memory cells SCL_2 and SCL_3 are arranged in a left-right pair in FIG. By adopting such a structure, the sub-memory cells are arranged alternately. It is possible to form a capacitance element on the transistor of an adjacent sub-memory cell. In addition, by arranging the elements alternately, the number of elements can be increased compared to Figure 6. In other words, the sub-memory cells stacked vertically can be simultaneously More specifically, for example, the sub-memory cell SCL _j(j=m-1) and the transistor Ta_j(j=m-1) of the sub-memory cell S The transistor Tb_j(j=m) included in CL_j(j=m) is formed in the same layer. That is, for example, transistor Ta_j (j=m-1) and transistor Tb_j (j= m) is formed on and in contact with the first insulating film. a semiconductor layer 101j (j=m-1) included in a transistor Tb_j (j= The semiconductor layer 201j (j=m) included in the first insulating film is formed on and in contact with the first insulating film. The memory cell array 300 includes a semiconductor layer 101j (j=m-1) and a semiconductor layer 201j ( For example, the first insulating film is in contact with the transistor Ta_j (j=m -1) and the gate electrode 103j (j=m-1) of the transistor Tb_j (j=m A second insulating film is formed on the gate electrode 203j (j=m) of the semiconductor device 201 so as to be in contact with the gate electrode 203j (j=m). Alternatively, the memory cell array 300 may include a gate electrode 103j (j=m-1) and a gate electrode 2 The second insulating film is in contact with O3j (j=m), where m is a natural number of 2 or more.

[0199] In this way, some of the transistors of the vertically adjacent sub-memory cells are located in the same layer. By forming the memory cell array 300, it is possible to manufacture the memory cell array 300 with fewer steps. By reducing the number of manufacturing steps, the yield can be increased. Since the number of layers can be reduced, the parasitic capacitance of the entire circuit can be reduced.

[0200] In addition, as the number of layers to be stacked increases, the characteristics of, for example, insulating films, conductive films, semiconductor films, etc. The film stress may cause peeling or cracking of the film. By reducing the number of layers, it is possible to reduce failures of the semiconductor device due to film peeling or the like.

[0201] The conductive layer 151j, which is one of the terminals of the capacitance element Ca_j, is connected to a transistor via a plug 141j. It is electrically connected to the gate electrode 203j of the transistor Tb_j.

[0202] The transistor Ta_j is provided on the capacitance element Ca_j. It is preferable that at least a part of the capacitance element Ta_j overlaps with the capacitance element Ca_j. Here, the gate electrode 203j and the conductive layer 151j are connected to the plug 141j and the plug 141j. A conductor serving as the source or drain electrode of transistor Ta_j is connected through 44j. The insulating film 115j of the capacitance element Ca_j is electrically connected to the conductive layer 104j_b. The capacitor is sandwiched between the conductive layer 151j and the conductive layer 152j to form a capacitor.

[0203] A conductive layer 204j serving as a source electrode or a drain electrode of the transistor Tb_j _b is electrically connected to the source line SL.

[0204] A conductive layer 204j serving as a source electrode or a drain electrode of the transistor Tb_j _a is connected to the source electrode or drain electrode of the transistor Ta_j via the plug 142j etc. The conductive layer 104j_a functions as an electrode and is electrically connected to the conductive layer 204j_a. The conductive layer 104j_a is electrically connected to the bit line BL.

[0205] In addition, the sub-memory cell SCL_j shares a conductive layer and a plug with the adjacent sub-memory cell. For example, the transistor Tb_j of the sub-memory cell SCL_2 The conductive layer 204j_a, which functions as a source electrode or a drain electrode of the adjacent sub-layer, The source electrode or drain electrode of the transistor Ta_j of the memory cell SC_1 is shared with the Also, the source electrode or drain electrode of the transistor Ta_j of the sub-memory cell SCL_2 The conductive layer 104j_a functioning as a drain electrode is a transistor of the sub-memory cell SCL_3. The conductive layer is shared with the source electrode or drain electrode of the transistor Tb_j. By sharing, the integration degree of the memory cell array 300 can be increased.

[0206] Also, the transistors 198 and 199 shown in FIG. It is a so-called dummy transistor that is not included in the cell. and transistor 199 are generally considered unnecessary for a memory cell array. However, by providing the transistors 198 and 199, the layer 299 can be fabricated using the same mask as layer 294 etc. This reduces the number of wafers required, leading to cost savings. In particular, when forming fine patterns, changes in the distance between lines can affect the final line. Therefore, the memory cell array 300 may be fabricated using a lithography process. When used, layers 294 and 299 can be formed using the same mask, e.g. The conditions such as the distance between patterns can be made common, and fine patterns can be formed on the layers 294 and 299. This is preferable because it makes it easier to form a pattern with a uniform thickness. This is preferable because it allows the sizes of the layer, conductive layer, gate electrode, etc. to be uniform. The distance between transistors, between transistors and wiring, and between wirings does not change significantly. The interference of electric fields such as capacitance between wirings becomes uniform, reducing the variation in characteristics between sub-memories. In addition, the gates of the transistors 198 and 199 may be The electrodes and conductive layers do not need to be connected to other transistors or wirings. Although not shown in FIG. 8, the formation of the necessary plugs and wirings can be omitted. Similarly, it is preferable to provide dummy transistors on the top layer of the array 300 as well.

[0207] Here, the dummy transistors 198 and 199 are written a write word line WWL, a read word line RWL, a bit line BL, and a floating node F N and a part of the source line SL, or may not be connected to either.

[0208] For example, the dummy transistors 198 and 199 are Alternatively, it may be connected to the source line SL and the bit line BL. stomach.

[0209] Alternatively, for example, the dummy transistors 198 and 199 are , is connected to one terminal of the capacitor element, and the other terminal of the capacitor element is connected to the write word line WWL. It doesn't have to continue.

[0210] In FIG. 8, for example, layers 299 and 294 have the same number of transistors. Alternatively, it is preferable to have transistors of approximately the same shape.

[0211] Alternatively, in FIG. 8, for example, layers 299 and 294 may have the same number of semiconductor layers. It is preferable to have semiconductor layers of approximately the same shape.

[0212] Alternatively, in FIG. 8, for example, layers 299 and 294 may have the same number of gate electrodes. Alternatively, it is preferable that the gate electrodes have substantially the same shape.

[0213] [Layer structure example 3] 11 is an example of a stacked structure of a semiconductor device different from that shown in FIGS. 6 and 8. FIG. 11A is a top view of a sub-memory cell included in the memory cell array 300. Also, FIG. 11(B) shows the cross sections A-A', A'-B, and 11(A) shows a cross section taken along line B-B'. Also, FIG. 11(C) shows a cross section taken along line C-C' shown in FIG. 11(A). The semiconductor device shown in FIG. 11B includes a memory cell array 300 and a peripheral circuit 500. Although FIG. 11 shows stacking up to j=2, in reality, sub-memory cells with j=3 or more are stacked. It is preferable that the number of layers is stacked, and the more layers there are, the higher the degree of integration of the memory can be. The circuit diagram of the memory cell array 300 shown in FIG. Refer to

[0214] In the structure shown in FIG. 11B, one of the terminals of the capacitor Ca_j and the gate electrode 203j Since the above-mentioned steps can be combined, the process can be simplified.

[0215] [Layer structure example 4] 12 is a stacked structure of a semiconductor device different from those shown in FIGS. 6, 8, and 11. 12 is an example of a stacked structure of a semiconductor device different from that of FIG. The semiconductor device shown in FIG. 12 includes a memory cell array 300 and a peripheral circuit 500. Although FIG. 12 shows stacking up to j=4, in reality, sub-memory The cells may be stacked, and the more stacked the cells, the higher the memory integration density. The circuit diagram of the memory cell array 300 shown in FIG. 12 may refer to, for example, FIG. .

[0216] In the memory cell array 300 shown in FIG. 12, the sub-memory cells are arranged alternately. 12. The sub-memory cells SCL1 to SCL2 shown in FIG. In SCL2 and SCL4, the semiconductor layer 101j of the transistor Tb_j The gate electrode 203j located below the capacitor element Ca_j, that is, the bottom gate, is electrically connected to the capacitor element Ca_j. The structure differs from other structures in that it is directly connected to the transistors. In this case, the capacitance element Ca_j is located above the transistor Ta_j, and the capacitance element Ca_j is located above the transistor Ta_j. It differs from other structures in the location of the transistor Tb_j.

[0217] On the other hand, in SCL_1 and SCL_3, the upper surface of the semiconductor layer 101j of the transistor Tb_j The gate electrode 203j located at the second position is electrically connected to the capacitance element Ca_j. The stacking order of the transistors and capacitors is also such that the capacitor Ca_j is positioned above the transistor Tb_j. In the example shown in FIG. 12, the transistor Ta_j is located above the capacitance element Ca_j. In the example shown in FIG. 1, the structure of the sub-memory cell SCL_j differs depending on whether j is an odd number or an even number. In the example shown in 2, transistors Ta_j and Tb_j must be formed on the same layer. There is no difference between the semiconductor layer 101j of the transistor Ta_j and the semiconductor layer 101j of the transistor Tb_j. When the semiconductor layer 201j is formed of an oxide semiconductor layer having different constituent elements or atomic ratios, In this case, it is preferable because it is easy to manufacture.

[0218] The above is a description of the configuration example.

[0219] [Example of manufacturing method] An example of a method for manufacturing the semiconductor device shown in the above configuration example will be described below with reference to FIGS. 6 will be used to explain.

[0220] First, a semiconductor substrate 131 is prepared. The semiconductor substrate 131 is, for example, a single crystal silicon substrate. Silicon substrates (including p-type semiconductor substrates and n-type semiconductor substrates), silicon carbide and gallium nitride A compound semiconductor substrate made of silicon can be used. In the following, a single crystal silicon substrate is used as the semiconductor substrate 131. The case where the above formula is used will be explained.

[0221] Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer is formed by LOC. OS (Local Oxidation of Silicon) method or STI (Sh If the trench isolation method or mesa isolation method is used, good.

[0222] When forming p-type and n-type transistors on the same substrate, the semiconductor substrate 1 An n-well or p-well may be formed in a part of the n-type semiconductor substrate 13. 1 is doped with impurity elements such as boron to give it p-type conductivity, forming a p-well. An n-type transistor and a p-type transistor may be formed on the substrate.

[0223] Next, an insulating film that will become the gate insulating film 134 is formed on the semiconductor substrate 131. For example, The surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, the surface of the semiconductor substrate 131 is oxidized by a thermal oxidation method. After forming the silicon oxide film, a nitriding treatment is performed to nitride the surface of the silicon oxide film. By this, a stacked structure of a silicon oxide film and a silicon oxynitride film may be formed. Alternatively, silicon oxide, silicon oxynitride, or high-dielectric-constant materials (also known as high-k materials) Tantalum oxide, hafnium oxide, hafnium silicate, zirconium oxide, Metal oxides such as aluminum oxide and titanium oxide, or rare earth oxides such as lanthanum oxide Other materials may also be used.

[0224] The insulating film is formed by sputtering, CVD (Chemical Vapor Deposition), sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method , PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition) method, or PLD (Pulsed Laser Deposit) Alternatively, the film may be formed by a film formation method such as an ion method.

[0225] Subsequently, a conductive film is formed to become the gate electrode 135. The conductive film is made of tantalum, tantalum, or the like. a metal selected from the group consisting of tin, titanium, molybdenum, chromium, niobium, etc., or It is preferable to use an alloy material or a compound material whose main component is a metal. In addition, the metal nitride film and the above-mentioned polycrystalline silicon film can be used. A laminated structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. By providing a metal nitride film, the density of the metal film can be improved. This can improve adhesion and prevent peeling.

[0226] Conductive films are formed by sputtering, evaporation, CVD (thermal CVD, MOCVD, PEC It is possible to form films by methods such as VD (including VD method). It also reduces damage caused by plasma. For this purpose, thermal CVD, MOCVD or ALD is preferred.

[0227] Subsequently, a resist mask is formed on the conductive film by lithography or the like. The unnecessary part of the film is removed. Then, the resist mask is removed to reveal the gate electrode. 135 can be formed.

[0228] Here, a method for processing a film to be processed will be described. When processing a film to be processed finely, Various microfabrication techniques can be used. For example, A method of slimming the resist mask may also be used. A dummy pattern was formed by a lithography method or the like, and a sidewall was formed on the dummy pattern. After that, the dummy pattern is removed, and the remaining sidewalls are used as a resist mask. The film to be processed may be etched. In addition, when etching the film to be processed, a high aspect ratio To achieve this, it is preferable to use anisotropic dry etching. Alternatively, a hard mask made of a metal film may be used.

[0229] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6nm), H-line (wavelength 405nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Alternatively, the exposure may be performed by an immersion exposure technique. Light (EUV: Extreme Ultraviolet) or X-rays may also be used. Instead of light used for exposure, electron beams can also be used. The use of an electron beam is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0230] In addition, before forming the resist film that will become the resist mask, the film to be processed and the resist film are closely An organic resin film having a function of improving adhesion may be formed. By using a pin coating method or the like, the step of the lower layer is covered and the surface is flattened. This makes it possible to reduce variations in the thickness of the resist mask provided on the organic resin film. In particular, when fine processing is performed, the organic resin film is required to have a high resistance to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film. As the resin film, for example, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. Alternatively, it may be removed after removing the resist mask.

[0231] After the gate electrode 135 is formed, a sidewall is formed to cover the side surface of the gate electrode 135. The sidewall may be formed by depositing an insulating film thicker than the gate electrode 135, and then Anisotropic etching is performed to leave the insulating film only on the side of the gate electrode 135. It can be formed by:

[0232] FIG. 13 shows an example in which the gate insulating film is not etched when the sidewall is formed. However, when the sidewall is formed, the insulating film that will become the gate insulating film 134 is also etched at the same time. In this case, the gate insulating film 134 is formed on the lower part of the gate electrode 135 and the sidewall. is formed.

[0233] Next, the gate electrode 135 (and sidewalls) of the semiconductor substrate 131 is provided. In the region where there is no conductivity, elements such as phosphorus that give n-type conductivity or boron that give p-type conductivity are added. The element to be added is added. The cross-sectional view at this stage is shown in FIG. 13(A).

[0234] Subsequently, after forming the insulating film 136, the above-mentioned element for imparting conductivity is activated. A first heat treatment is carried out.

[0235] The insulating film 136 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon nitride. Silicon, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride The insulating film 136 may be formed by a sputtering method. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, the insulating film can be formed by a PLD method or the like. In particular, the insulating film can be formed by a CVD method, preferably a Alternatively, it is preferable to form the film by plasma CVD, since this can improve the coating property. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD or A The LD method is preferred.

[0236] The first heat treatment is performed in an inert gas atmosphere such as a rare gas or a nitrogen gas atmosphere, or in a reduced pressure atmosphere. The heating can be performed at a temperature of, for example, 400° C. or higher but lower than the strain point of the substrate.

[0237] At this stage, transistors 130a, 130b, 230a, and Transistor 230b is formed.

[0238] Next, an insulating film 137 is formed to obtain the cross section shown in FIG. Form.

[0239] The insulating film 137 may be made of a material that can be used for the insulating film 136, as well as a nitrogen containing oxygen and hydrogen. By using silicon nitride (SiNOH), the amount of hydrogen released by heating can be increased. The insulating film 138 is preferably made of a material that can be used for the insulating film 136. In addition, TEOS (Tetra-Ethyl-Ortho-Silicate) or Silicon oxide with good step coverage, formed by reacting silane with oxygen or nitrous oxide. It is preferable to use a material such as fluorine.

[0240] The insulating film 137 and the insulating film 138 are formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD, PECVD, etc.), MBE, ALD, or PLD methods are used. In particular, the insulating film can be formed by a CVD method, preferably a plasma CVD method. Therefore, forming a film is preferable because it can improve the coverage. To reduce damage, thermal CVD, MOCVD, or ALD is preferred.

[0241] Next, the upper surface of the insulating film 138 is planarized by using a CMP method or the like. In this case, it is not necessary to perform planarization by CMP or the like. The planarization film can be formed by, for example, atmospheric pressure CVD or coating. Examples of films that can be formed using the VD method include BPSG (Boron Phosphorus Glycol), Also, it can be formed using a coating method. Examples of such films include HSQ (hydrogen silsesquioxane).

[0242] Then, the dangling bonds in the semiconductor layer 132 are removed by hydrogen released from the insulating film 137. The second heat treatment is performed to terminate the layers. By desorbing the water and hydrogen contained in the fuel, the water and hydrogen contents can be reduced.

[0243] The second heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above. The conditions described for the heat treatment in 1 can be used.

[0244] Next, the barrier film 111 is formed. The barrier film 111 is formed by, for example, a sputtering method or a CV method. D method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or In particular, the insulating film can be formed by a CVD method, preferably The plasma CVD method is preferred for film formation because it can improve coverage. To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. is preferred.

[0245] Next, a conductive film that will become the conductive layer 105j, the conductive layer 153j, etc. is formed on the barrier film 111. The conductive films to be the conductive layers 105j, 153j, etc. are formed by, for example, a sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, etc. In particular, the insulating film can be formed by a CVD method, preferably a PLD method. It is preferable to form the film by plasma CVD, since this can improve the coating property. To reduce damage caused by plasma, thermal CVD, MOCVD, or AL Method D is preferred.

[0246] Next, a resist mask is formed to mask the conductive film that will become the conductive layer 105j, the conductive layer 153j, and the like. The resist mask is then removed, and the conductive layer 105j is removed. , the conductive layer 153j, etc. are formed.

[0247] Next, the insulating film 214j is formed by, for example, sputtering or CV D method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or In particular, the insulating film can be formed by a CVD method, preferably The plasma CVD method is preferred for film formation because it can improve coverage. To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. It is preferable that the insulating film 214j is made of a material other than the insulating film 114j. That's fine.

[0248] In order to make the insulating film 214j contain excess oxygen, for example, the insulating film 214j is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 214j after the film formation to remove oxygen. Alternatively, a region containing the hydroxyl group may be formed, or both methods may be combined.

[0249] For example, the insulating film 214j after film formation contains oxygen (at least oxygen radicals, oxygen atoms, oxygen ions, etc.). The oxygen introduction method involves introducing oxygen into the silicon dioxide gas to form a region containing excess oxygen. The methods include ion implantation, ion doping, plasma immersion ion implantation, Plasma treatment or the like can be used.

[0250] The oxygen introduction treatment can be performed using a gas containing oxygen. Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas. For example, a mixture of carbon dioxide, hydrogen and argon may be used. stomach.

[0251] After forming the insulating film 214j, the insulating film 214j is polished by a CMP method or the like to improve the flatness of its upper surface. A flattening process may be performed.

[0252] Next, the source electrode or drain electrode of the transistor Tb_j is formed on the conductive layer 153j or the like. A plug for connecting to the insulating film 214j may be formed. First, an opening is provided in the insulating film 214j ( (See FIG. 13(B)). Next, a conductive film 153 that will become a plug is formed so as to fill the opening. The conductive film 153 is formed by, for example, forming the conductive layer 105j. Please refer to the conductive film and the like.

[0253] Next, the conductive film 153 is subjected to planarization treatment so that the surface of the insulating film 214j is exposed. As a result, plugs 148j and the like are formed (see FIG. 13(D)).

[0254] Next, transistors such as the transistor Tb_j are formed on the insulating film 214j. The method for fabricating the transistor Ta_j can be referred to the method for fabricating the transistor Tb_j. can.

[0255] A semiconductor film that will become the semiconductor layer 201j_a etc. and a semiconductor film that will become the semiconductor layer 201j_b etc. The semiconductor films are preferably formed successively without being exposed to the air. The semiconductor that will become the semiconductor layer 201j_a and the semiconductor that will become the semiconductor layer 201j_b is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Just do that.

[0256] In addition, the semiconductors that will become the semiconductor layer 201j_a etc. and the semiconductor layers 201j_b etc. When forming an In-Ga-Zn oxide layer as a semiconductor by MOCVD, the raw material gas When trimethylindium, trimethylgallium, and dimethylzinc are used as the source, The combination of source gases is not limited to the above, and trimethylindium may be replaced with trimethylindium. Alternatively, triethylindium may be used instead of trimethylgallium. Gallium or the like may be used. Diethyl zinc or the like may be used instead of dimethyl zinc. good.

[0257] After the oxide film and the semiconductor film are formed, a fourth heat treatment is preferably performed. At a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, an inert gas The treatment may be carried out in an atmosphere containing an oxidizing gas at 10 ppm or more, or under reduced pressure. The heat treatment atmosphere is an inert gas atmosphere, and then the oxygen removed is replaced with The heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more. The process may be performed immediately after the semiconductor film is formed, or after the semiconductor film is processed to form island-shaped semiconductor layers 201j_a, 201j_b. The heat treatment may be performed after forming the insulating film 214j or the oxide film. Oxygen is supplied to the semiconductor film, and oxygen vacancies in the semiconductor film can be reduced.

[0258] After that, a resist mask is formed and unnecessary portions are removed by etching. By removing the resist mask, the island-shaped semiconductor layer 201j_a and the semiconductor layer 201j_ It is possible to form a laminated structure such as b (see FIG. 13(E)). During etching, a part of the insulating film 214j is etched, and the semiconductor layer 201j_a and the semiconductor layer The insulating film 214j in the region not covered by 201j_b etc. may become thinner. Therefore, the insulating film 214j is formed thick in advance so that it is not lost by the etching. It is preferable to keep

[0259] Thereafter, the conductive film 204j is formed by, for example, sputtering. method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD In particular, the insulating film can be formed by a CVD method, preferably a PLD method. Preferably, the film is formed by plasma CVD, which can improve the coating properties. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD or ALD methods are preferred.

[0260] Next, a resist mask is formed, and unnecessary portions of the conductive film 204j are removed by etching. Thereafter, the resist mask is removed, and the conductive layers 204j_a, 204j_b, etc. are formed. (See FIG. 14(A)). Here, when the conductive film is etched, the semiconductor layer 201j b and a part of the upper part of the insulating film 114j are etched, and the conductive layer 204j_a and the conductive layer 2 The portion that does not overlap with the semiconductor layer 201j_b may become thin. The thickness of the semiconductor film, etc., which will become b, should be made thick in advance, taking into account the depth to be etched. It is preferable that:

[0261] Next, a gate insulating film 202j and a semiconductor layer 201j_c are formed. j and the semiconductor layer 201j_c become the gate insulating film 202j and the semiconductor layer 201j_c. A film is formed, then a resist mask is formed, and the film is processed by etching. Next, a conductive film that will become the gate electrode 203j is formed. The conductive film is processed by etching, and then the resist mask is removed to form a gate An electrode 203j is formed (see FIG. 14(B)). The semiconductor that becomes the semiconductor layer 101j_c is Film formation using sputtering, CVD, MBE, PLD, ALD, etc. That's fine.

[0262] As a semiconductor for the semiconductor layer 101j_c, an In-Ga-Zn oxide layer was used. When forming a film by the VD method, trimethylindium and trimethylgallium are used as raw material gases. The combination of the source gases is not limited to the above. In addition, triethylindium or the like may be used in place of trimethylindium. Triethylgallium may be used instead of trimethylgallium. Alternatively, diethyl zinc or the like may be used.

[0263] At this stage, transistors such as transistor Tb_j are formed.

[0264] Next, the insulating film 212j is formed. The insulating film 212j can be formed by, for example, a sputtering method or a CV method. D method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or In particular, the insulating film can be formed by a CVD method, preferably The plasma CVD method is preferred for film formation because it can improve coverage. To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD methods are used. is preferred.

[0265] After the insulating film 212j is formed, a fifth heat treatment is preferably performed. Oxygen is supplied to the semiconductor layer 201j from the insulating film 214j etc., and the oxygen in the semiconductor layer 201j In addition, the oxygen released from the insulating film 214j can be used to reduce defects. The barrier film 111 and the insulating film 212j are blocked by the barrier film 111 and the insulating film 212j. Since the oxygen does not diffuse to layers above the barrier film 212j, the oxygen can be effectively trapped. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 201j can be increased, and the semiconductor layer It can effectively reduce oxygen vacancies in 201j.

[0266] The insulating film 212j may have a laminated structure of two or more layers. The film 212j has a two-layer laminate structure, and the lower layer is made of, for example, silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide The upper layer may be made of aluminum, aluminum nitride, or the like. It is preferable to use a material that is difficult for water and hydrogen to diffuse. The insulating film 214j is an insulating film from which oxygen is released by heating, and the insulating film 214j is formed through the gate insulating film 102j. Alternatively, oxygen may be supplied from above the semiconductor layer 101j.

[0267] Subsequently, an insulating film 213j is formed (see FIG. 14(C)). The insulating film 213j is, for example, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide Aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. may be used. The insulating film 113j is formed by, for example, a sputtering method or a CVD method (thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or PLD method In particular, it can be formed by a CVD method, preferably a plasma CVD method. It is preferable to form the film by plasma, since it is possible to obtain good coating properties. To reduce damage caused by the deposition, thermal CVD, MOCVD, or ALD is preferred.

[0268] To avoid complication, the insulating film is not shown in FIGS. 6 to 9, 11, 12, and 18. 112j, 113j, insulating film 212j, and insulating film 213j are not shown.

[0269] Next, an insulating film 216j is formed. The insulating film 216j is made of, for example, silicon oxide or oxynitride. silicon nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxynitride Aluminum, aluminum nitride oxide, aluminum nitride, etc. can be used, and they can be configured as a laminated or single layer. The insulating film 216j is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, etc.). The method is formed by using a method such as MBE, ALD, or PLD. In addition, when an organic insulating material such as an organic resin is used as the insulating film 216j, The insulating film 216j may be formed by using a coating method such as a spin coating method. After that, it is preferable to perform a flattening process on the upper surface. The material and the formation method of the insulating film 138 may be used.

[0270] Next, the insulating film 216j, the insulating film 213j, the insulating film 212j, the gate insulating film 202j, and Openings reaching the conductive layers 204j_a, 204j_b, etc. are provided in the semiconductor layer 201j_c. The openings are filled with plugs 141j, 142j, 143j, and so on. A conductive film is formed, and a planarization process is performed so that the surface of the insulating film 216j is exposed. Then, plugs 142j, 143j, etc. are formed (see FIG. 15(A)).

[0271] Next, conductive layers 151j, 153j, 154j, 155j, 156j, 157j, 158j, 159j, 160j, 161j, 162j, 163j, 164j, 165j, 166j, 167j, 168j, 169j, 170j, 171j, 17 A conductive film is formed to form conductive layers 151j, 154j, etc., and a mask is formed to perform etching. 3j, 154j, etc. are formed. After that, an insulating film 115j is formed (see FIG. 15(B)). The insulating film 115j can function as an insulating film for the capacitor element Ca_j. For materials that can be used for 15j, see the description of the gate insulating film 202j. good.

[0272] Next, the conductive layer 152j and the like are formed on the insulating film 115j in the same manner as the conductive layer 151j ( (See FIG. 15(C)). For the materials and the like that can be used, see the description of the conductive layer 205j, for example. , the capacitance element Ca_j can be formed.

[0273] Next, an insulating film 156j is formed on the conductive layer 152j and the insulating film 115j. The upper surface of the insulating film 156j may be flattened. Please refer to the above.

[0274] Next, the transistor Ta_j is formed on the insulating film 156j. The conductive layer 105j and the like are formed on the conductive layer 105j in the same manner as the conductive layer 205j. Next, the insulating film 114j is formed (see FIG. 16(A)). The insulating film 4j can be formed in the same manner as the insulating film 214j.

[0275] Next, openings are formed in the insulating film 156j and the insulating film 114j, and a conductive layer is formed in the openings to fill them. The surface of the conductive film is planarized so that the insulating film 114j is exposed, and the plug 144 j, plug 145j, etc. are formed.

[0276] Next, the transistor Ta_j and the like are formed (see FIG. 16(B)). For the formation of the transistor Tb_j, please refer to the description of the transistor Tb_j. As shown in B), the transistor Ta_j (j=1) of the sub-memory cell SCL_1 and the transistor Tb_j (j=2) of the sub-memory cell SCL_2 are simultaneously formed. It is possible.

[0277] Next, by repeatedly forming the capacitance element Ca_j, the transistor Ta_j, etc. in the same manner, Thus, the semiconductor element shown in FIG. 8 can be fabricated.

[0278] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0279] (Embodiment 2) In this embodiment, the transistors Ta_j and Tb_ An oxide semiconductor that can be suitably used for the transistor Tbj will be described. For the semiconductor layer 201j_a, refer to the description of the transistor Ta_j. , the semiconductor layer 201j_b and the semiconductor layer 201j_c are the semiconductor layer 101j _a, the semiconductor layer 101j_b, and the semiconductor layer 101j_c can be referred to. However, the semiconductor layer 101j_a and the semiconductor layer 201j_a do not necessarily have to be made of the same material. That is, for example, an In-MZ When using n-oxide, for example, a material with the same atomic ratio of indium, element M, and zinc is used. In addition, for example, the semiconductor layer 101j_a and the semiconductor layer 201j_a may be The semiconductor layer 101j_b and the semiconductor layer 20 do not need to be made of materials with the same gap. The same applies to the semiconductor layer 1j_b, or the semiconductor layer 101j_c and the semiconductor layer 201j_c.

[0280] Here, as shown in FIG. 6 and other examples, a semiconductor layer 101j_a is used as an oxide semiconductor. An example will be shown in which three layers, a semiconductor layer 101j_b, a semiconductor layer 101j_c, and a semiconductor layer 101j_b are stacked. The oxide semiconductor that can be used for the transistor Ta_j may be a single layer. any one of the semiconductor layer 101j_a, the semiconductor layer 101j_b, and the semiconductor layer 101j_c Alternatively, a structure that does not have either of these may be used.

[0281] The semiconductor layer 101j_b is, for example, an oxide semiconductor containing indium. For example, if O1j_b contains indium, the carrier mobility (electron mobility) increases. The semiconductor layer 101j_b preferably contains an element M. The element M is preferably an Aluminum, gallium, yttrium, or tin. Other elements M can also be used. Possible elements include boron, silicon, titanium, iron, nickel, germanium, and yttrium. Smoke, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum However, the element M can be a combination of multiple of the above elements. The element M may be, for example, an element that has a high bond energy with oxygen. For example, the element M is an element having a higher bond energy with oxygen than indium. For example, it is an element that has a function of increasing the energy gap of an oxide semiconductor. The semiconductor layer 101j_b preferably contains zinc. When an oxide semiconductor contains zinc, it becomes crystalline. It may be easier to convert.

[0282] However, the semiconductor layer 101j_b is not limited to an oxide semiconductor containing indium. The conductor layer 101j_b is made of, for example, indium tin oxide, zinc tin oxide, gallium tin oxide, or the like. oxide semiconductors containing zinc, oxide semiconductors containing gallium, and oxides containing tin It may be a semiconductor or the like.

[0283] The semiconductor layer 101j_b is made of, for example, an oxide with a large energy gap. The energy gap of the dielectric layer 101j_b is, for example, 2.5 eV or more and 4.2 eV or less. Preferably, it is 2.8 eV or more and 3.8 eV or less, and more preferably, it is 3 eV or more and 3.5 eV or less. do.

[0284] For example, the semiconductor layer 101j_a and the semiconductor layer 101j_c are an oxide semiconductor composed of one or more elements other than oxygen that constitutes the The semiconductor layer 101j_b is made of one or more elements other than oxygen. Since the layer 101j_a and the semiconductor layer 101j_c are configured, the semiconductor layer 101j_a and The interface with the semiconductor layer 101j_b, and the interface between the semiconductor layer 101j_b and the semiconductor layer 101j_c At the interface, interface states are unlikely to be formed.

[0285] The semiconductor layer 101j_a, the semiconductor layer 101j_b, and the semiconductor layer 101j_c are at least It is preferable that both layers contain indium. When the sum of In and M is 100 atomic %, preferably In is 50 atomic %. %, M is higher than 50 atomic %, and more preferably In is 25 atomic % % or less, and M is higher than 75 atomic %. In the case of M-Zn oxide, when the sum of In and M is 100 atomic %, it is preferable Preferably, In is higher than 25 atomic % and M is less than 75 atomic %, more preferably In the case of semiconductors, the In content is higher than 34 atomic % and the M content is less than 66 atomic %. When the layer 101j_c is an In-M-Zn oxide, the sum of In and M is 100 atoms. When the atomic percentage of In is c%, it is preferable that In is less than 50 atomic % and M is more than 50 atomic %. More preferably, In is less than 25 atomic % and M is more than 75 atomic %. The semiconductor layer 101j_c may be made of the same oxide as the semiconductor layer 101j_a. It's okay.

[0286] The semiconductor layer 101j_b has a higher current density than the semiconductor layer 101j_a and the semiconductor layer 101j_c. For example, the semiconductor layer 101j_b is made of an oxide having a large electron affinity. 1j_a and semiconductor layer 101j_c, the electron affinity of which is 0.07 eV or more and 1.3 eV or more. Preferably, the electron transport energy is 0.1 eV or more and 0.7 eV or less, and more preferably, 0.15 eV or more and 0. The electron affinity is determined by the energy difference between the vacuum level and the bottom of the conduction band. This is the difference between ghee.

[0287] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor layer 101j_c contains indium gallium oxide. The atomic ratio of sodium [In / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it is 90% or more.

[0288] Furthermore, the semiconductor layer 101j_c more preferably contains gallium oxide. If gallium oxide is included in O1j_c, a lower off-state current may be achieved.

[0289] When an electric field is applied to the gate electrode of the transistor, the semiconductor layer 101j_a and the semiconductor layer 10 1j_b and semiconductor layer 101j_c, the semiconductor layer 101j_b having the larger electron affinity is selected. A channel is formed.

[0290] The band structure is shown in FIG. 25(A). The energy of the bottom of the conduction band of each layer (denoted as Ec) and The energy at the top of the valence band (denoted as Ev) is shown.

[0291] Here, the semiconductor layer 101j_a and the semiconductor layer 101j_b are separated from each other by a thin film. In some cases, the semiconductor layer 101j_a and the semiconductor layer 101j_b are mixed. Between the semiconductor layer 101j_b and the semiconductor layer 101j_c, The interfacial state density is low in the interfacial region. The laminate of the conductor layer 101j_a, the semiconductor layer 101j_b, and the semiconductor layer 101j_c is In the vicinity of each interface, the energy changes continuously (also called a continuous junction). It becomes a code structure.

[0292] In FIG. 25(A), the Ec However, they may be different. For example, The semiconductor layer 101j_c may have a higher energy Ec than the semiconductor layer 101j_a.

[0293] At this time, the electrons are not in the semiconductor layer 101j_a and the semiconductor layer 101j_c, but in It mainly moves in the semiconductor layer 101j_b (see FIG. 25(B)). The interface state density at the interface between the semiconductor layer 101j_a and the semiconductor layer 101j_b, By lowering the interface state density at the interface between the layer 101j_b and the semiconductor layer 101j_c, Therefore, the movement of electrons in the semiconductor layer 101j_b is not hindered much, and the transistor The on-state current can be increased.

[0294] When the transistor has an s-channel structure, the semiconductor layer 101j_b Therefore, the thicker the semiconductor layer 101j_b, the larger the channel region. That is, the thicker the semiconductor layer 101j_b, the higher the on-current of the transistor. For example, it can be made 20 nm or more, preferably 40 nm or more, and more preferably The semiconductor layer 101j has a region with a thickness of 60 nm or more, more preferably 100 nm or more. However, since the productivity of the semiconductor device may decrease, for example, A region having a thickness of 00 nm or less, preferably 200 nm or less, and more preferably 150 nm or less. The semiconductor layer 101j_b may have a region.

[0295] In order to increase the on-current of the transistor, the thickness of the semiconductor layer 101j_c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 On the other hand, the semiconductor layer 101j_c may have a region of 101 nm or less. c is the amount of oxygen other than that constituting the adjacent insulator that is introduced into the semiconductor layer 101j_b where the channel is formed. It has the function of blocking the intrusion of foreign elements (hydrogen, silicon, etc.). Therefore, it is preferable that the semiconductor layer 101j_c has a certain thickness. a semiconductor having a region with a thickness of at least 1 nm, preferably at least 1 nm, and more preferably at least 2 nm The semiconductor layer 101j_c may be a conductor layer 101j_c. It has the property of blocking oxygen in order to suppress the outward diffusion of oxygen released from It is preferable to do so.

[0296] In order to improve reliability, the semiconductor layer 101j_a is thick and the semiconductor layer 101j_ It is preferable that c is thin. For example, it is 10 nm or more, preferably 20 nm or more, and more preferably The semiconductor layer 101 has a region with a thickness of 40 nm or more, and more preferably 60 nm or more. By increasing the thickness of the semiconductor layer 101j_a, the thickness of the adjacent insulator and the semiconductor layer 101j_a to the semiconductor layer 101j_b where the channel is formed. However, this may decrease the productivity of semiconductor devices. For example, the thickness is 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The semiconductor layer 101j_a may have the above region.

[0297] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors, generating electrons as carriers. Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove impurities to achieve high purity so that the impurities are not included as much as possible.

[0298] Note that dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film Oxygen may also decrease at the same time. The process of adding oxygen to an oxide semiconductor to compensate for the increased oxygen vacancies caused by oxidation. In this specification and the like, the case where oxygen is supplied to an oxide semiconductor film is referred to as This may be referred to as oxygenation treatment, or oxygen contained in an oxide semiconductor film may be reduced to a value higher than the stoichiometric composition. When more oxygen is used, it is sometimes referred to as hyperoxygenation treatment.

[0299] In this way, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies through oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is very close to i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that there are very few carriers derived from donors in the oxide semiconductor film. (close to zero), and the carrier density is 1×10 17 / cm 3Below, 1×10 16 / cm 3 below , 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Below It says something.

[0300] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film can be For example, a transistor using an oxide semiconductor film can be The drain current when the capacitor is off is 1×10 at room temperature (approximately 25°C). -18 Below A, Preferably 1 x 10 -21 A or less, more preferably 1×10 -24 A or below, or 85 1 x 10 at °C -15 A or less, preferably 1×10 -18 A or less, more preferably 1x 10 -21 A or less. Note that the transistor being in the off state is an n-channel In the case of a transistor of this type, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. In general, if the gate voltage is 1V or more, 2V or more, or 3V or more less than the threshold voltage, , the transistor is turned off.

[0301] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0302] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline Oxide Semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0303] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, nc-OS, etc.

[0304] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. It can also be described as a structure that has order but does not have long-range order.

[0305] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is converted into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a device that can achieve periodicity in a microscopic area. Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0306] <caac-os> First, let me explain about CAAC-OS.

[0307] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0308] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by a combined analysis image (high resolution) When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly identify the CAAC-OS. It can be said that the decrease in electron mobility caused by this is unlikely to occur.

[0309] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration correction function was used to obtain a high-resolution TEM image. In particular, it is called a Cs-corrected high-resolution TEM image. This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Denshi Co., Ltd. This can be done.

[0310] An enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 20(A) is shown in FIG. 20(B). From Figure 20(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). The surface reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0311] As shown in Figure 20(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 20(B) and Figure 20(C). Therefore, the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used for CANC (C-Axis Aligned Nanocry The oxide semiconductor may also be called an oxide semiconductor having a crystalline structure.

[0312] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 20(D)). The inclination between the pellets observed in FIG. 20(C) The location where the crack occurs corresponds to the area 5161 shown in FIG. 20(D).

[0313] In addition, Fig. 21(A) shows the Cs of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 21(A). Enlarged Cs-corrected high-resolution TEM images are shown in Fig. 21(B), Fig. 21(C), and Fig. 21(D), respectively. 21(D). From Fig. 21(B), Fig. 21(C) and Fig. 21(D), the pellet It can be seen that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0314] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When structural analysis is performed using the out-of-plane method, the results are as shown in Figure 22(A). A peak may appear at a diffraction angle (2θ) of around 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0315] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31° In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the center of the crystal grains indicate that some of the CAAC-OS grains do not have a c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0316] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 22(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in FIG. 22(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0317] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 23(A) is generated. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately on the surface to be formed or on the upper surface. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 23(B). (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also reveals It is clear that the a-axis and b-axis of the pellets contained in the CAAC-OS do not have any orientation. The first ring in FIG. 23(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane. Also, the second ring in Figure 23(B) This is thought to be due to the (110) plane.

[0318] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so we take the opposite view. CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0319] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0320] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0321] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8 × 10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a highly pure intrinsic or CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. The state density is low, that is, the oxide semiconductor has stable characteristics.

[0322] <nc-os> Next, we will explain nc-OS.

[0323] In the high-resolution TEM image, nc-OS is divided into two regions: one where crystals can be clearly seen and the other where crystals can be clearly seen. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor with a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, the grain boundaries of nc-OS are It may not be possible to clearly identify the nanocrystals. Therefore, the crystalline part of nc-OS is referred to as the pellet below. There may be cases where this happens.

[0324] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 The nc-OS has a periodic atomic arrangement in the region of 100 nm or less. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. For example, for nc-OS, there are cases where it is difficult to distinguish between X particles with a diameter larger than that of the pellet. When using X-rays, peaks indicating crystal planes are not detected in the out-of-plane analysis. In addition, for nc-OS, a probe diameter larger than the pellet (for example, 50n When electron diffraction is performed using an electron beam (over 1000 nm), a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than the pellet. When nanobeam electron diffraction is performed using an electron beam with a diameter of n, spots are observed. When nanobeam electron diffraction is performed on c-OS, a circular (ring-shaped) bright spot appears. In some cases, a ring-shaped area is observed. In addition, multiple spots are observed within the ring-shaped area. There are cases where this happens.

[0325] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0326] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0327] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0328] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0329] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0330] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). The sample is also an In-Ga-Zn oxide.

[0331] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0332] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0333] Figure 24 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of eOS grows in size according to the cumulative amount of electron irradiation. As shown in Figure 24 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was sized at 4.2 × 10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the crystals grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 24, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. You will realize something.

[0334] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC-O. It can be seen that the structure is unstable compared to S.

[0335] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0336] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0337] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0338] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0339] Consider a case where an oxide semiconductor contains indium, an element M, and zinc. is preferably aluminum, gallium, yttrium, tin, or the like. The elements that can be applied to the element M include boron, silicon, titanium, iron, nickel, and gel. Magnesium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, Hafnium, tantalum, tungsten, etc. However, as element M, the above elements Indium, element M, and A preferred range of the ratio of the numbers of zinc atoms, x:y:z, will be described below.

[0340] In the oxide with indium, element M and zinc, InMO3(ZnO) m (m is natural It is known that there exist homologous phases (homologous series) represented by the Here, consider the case where the element M is Ga as an example.

[0341] For example, compounds with a spinel-type crystal structure include ZnM2 such as ZnGa2O4. O4 is known. Also, the compounds with compositions close to ZnGa2O4, that is, x, When y and z have values ​​close to (x,y,z)=(0,1,2), the spinel type crystal is formed. Here, the oxide semiconductor is CAAC-OS. In particular, the CAAC-OS preferably does not contain a spinel-type crystal structure. It is also preferable to increase the In content in order to increase the carrier mobility. In oxide semiconductors containing indium, element M, and zinc, the s orbitals of the heavy metals are mainly carriers. By increasing the indium content, more s orbitals are Because of this overlap, oxides with a high indium content are different from oxides with a low indium content. Therefore, oxide semiconductors with a high indium content are By using the above, the carrier mobility can be increased.

[0342] For example, by increasing the atomic ratio of indium, it is possible to increase carrier mobility. For example, the number of atoms of indium, element M, and zinc contained in the oxide semiconductor is preferably When the ratio is expressed as x:y:z, it is preferable that x is 1.75 times or more of y.

[0343] In addition, in order to further increase the CAAC ratio of the oxide semiconductor, it is necessary to increase the atomic ratio of zinc. For example, it is preferable to set the atomic ratio of In-Ga-Zn oxide within a range in which a solid solution region can be obtained. By doing so, the CAAC ratio can be increased. Increasing the ratio of the number of zinc atoms to the sum of the number of zinc atoms widens the range in which the solid solution region can be formed. Therefore, the ratio of the number of zinc atoms to the sum of the number of indium and gallium atoms is increased. By doing so, it may be possible to further increase the CAAC ratio of the oxide semiconductor. For example, the ratio of the number of atoms of indium, element M, and zinc contained in the oxide semiconductor is represented by x:y:z. In this case, z is preferably 0.5 times or more of x+y. In order to increase the carrier mobility, z is preferably equal to or less than twice the sum of x and y.

[0344] As a result, the rate at which spinel-type crystal structures are observed in nanobeam electron diffraction has been reduced. Therefore, it is possible to achieve an excellent CAAC-OS. In addition, the carriers at the boundary between the CAAC structure and the spinel-type crystal structure Since scattering and the like can be reduced, when an oxide semiconductor is used in a transistor, high It is possible to realize a transistor with high field effect mobility. It is possible to realize the star.

[0345] As a result, an oxide semiconductor with a high CAAC ratio can be realized. In addition, a region where a spinel-type crystal structure is observed can be realized. It is possible to realize CAAC-OS with no or very little interference. In the case of CAAC-OS, the CAAC ratio is 50% or more, preferably 80% or more, more preferably It is preferably 90% or more, and more preferably 95% or more and 100% or less.

[0346] In addition, when oxide semiconductors are formed by sputtering, the atomic ratio of the target is different. In particular, zinc may form a film with a higher atomic ratio than the target. The atomic ratio of the film may become smaller. Specifically, the number of zinc atoms contained in the target The ratio may be between 40 atomic % and 90 atomic %.

[0347] Therefore, the atomic ratio of the target is higher than that of the oxide semiconductor obtained by sputtering. It is preferable that the ratio of the number of atoms of zinc is the highest.

[0348] The oxide semiconductor may be a laminate of a plurality of films. The C ratio may be different. In addition, at least one of the laminated films may be, for example, For example, the CAAC ratio is preferably 90% or higher, more preferably 95% or higher, It is more preferable that the ratio is 7% or more and 100% or less.

[0349] The CAAC-OS film can be formed, for example, by the following method.

[0350] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The film is formed by sputtering using the RF sputtering method, D C sputtering, AC sputtering, or the like can be used. To improve the uniformity of the distribution, film composition distribution, or crystallinity distribution, It is preferable to use DC sputtering or AC sputtering.

[0351] By increasing the substrate temperature during film formation, migration of sputtered particles after reaching the substrate is prevented. Specifically, the substrate temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher. The film is formed at a temperature of 500°C or less. By increasing the substrate temperature during film formation, the sputtering particles When the particles reach the substrate, migration occurs on the substrate, and the sputtered particles are flattened. At this time, the sputtering particles are positively charged, The ring particles repel each other while adhering to the substrate, resulting in uneven sputtering. Therefore, a CAAC-OS film with a uniform thickness can be formed without overlapping.

[0352] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0353] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100% by volume or more. Expressed as volume %.

[0354] Alternatively, the CAAC-OS film is formed by the following method.

[0355] First, a first oxide semiconductor film is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher. The temperature is set to 500°C or less, preferably 150°C to 450°C, and the oxygen ratio in the deposition gas is set to 30 The film is formed at a concentration of at least 100% by volume, preferably 100% by volume.

[0356] Next, heat treatment is performed to convert the first oxide semiconductor film into a first CAAC-OS film having high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is 1 minute to 24 hours, preferably 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. Alternatively, heat treatment is performed in an inert atmosphere, and then heat treatment is performed in an oxidizing atmosphere. By the heat treatment in the atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be carried out at a pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The step of removing the oxide semiconductor film from the first oxide semiconductor film may be performed under a reduced pressure of 1 Pa or less. can be reduced in an even shorter time.

[0357] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm. Compared with a thickness of 0 nm or more, it can be easily crystallized by heat treatment.

[0358] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm or more. The second oxide semiconductor film is formed to a thickness of 0 nm or less by sputtering. Specifically, the substrate temperature is set to 100°C or higher and 500°C or lower, preferably 150°C or higher and 450°C or lower. The temperature is set to 0°C or lower, and the oxygen ratio in the film-forming gas is set to 30% by volume or more, preferably 100% by volume. To film.

[0359] Next, heat treatment is performed to form a second oxide semiconductor film from the first CAAC-OS film by solid-phase growth. The second CAAC-OS film was obtained by heating at a temperature of 350 The temperature is set to 740°C or higher, preferably 450°C or higher and 650°C or lower. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is carried out in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the nitride semiconductor film can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor film by the heat treatment. The oxygen deficiency can be reduced by heat treatment in a reactive atmosphere. It may be carried out under reduced pressure of 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be reduced in a shorter time. Cut.

[0360] In this manner, a CAAC-OS film having a total thickness of 10 nm or more is formed. can be done.

[0361] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0362] (Embodiment 3) In this embodiment, a memory device such as the memory cell array 300 exemplified in the above embodiment is The RF tag including the memory device will be explained with reference to FIG. 27. A configuration including a row selection driver, a column selection driver, an A / D converter, etc. Good too.

[0363] The RF tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. It stores information and transmits and receives information to and from the outside using non-contact means, such as wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems, etc. Extremely high reliability is required.

[0364] The structure of an RF tag will be described with reference to Fig. 27. Fig. 27 shows an example of the structure of an RF tag. FIG.

[0365] As shown in FIG. 27, an RF tag 800 includes a communicator 801 (such as an interrogator, reader / writer, etc.). 803 is transmitted from an antenna 802 connected to The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 804, and a 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectifying action included in the demodulation circuit 807 is sufficiently suppressed. A material capable of controlling the temperature, such as an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linearity. The data transmission format is a pair of coils arranged facing each other and communicating by mutual induction. electromagnetic coupling method, which communicates by induced electromagnetic fields; electromagnetic induction method, which communicates by using radio waves; The RF tag 800 shown in this embodiment is compatible with any of these methods. It can also be used in formulas.

[0366] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 adjusts the input AC signal generated by receiving a radio signal with the antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is averaged by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by smoothing the input voltage. A limiter circuit may be provided on the output side. When the internally generated voltage is large, power above a certain level is not input to the subsequent circuit. This is a circuit for controlling the

[0367] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0368] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0369] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for doing this.

[0370] The above-mentioned circuits can be selected or removed as needed.

[0371] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. Furthermore, the memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance between when reading and writing data. and suppressing malfunctions or erroneous writing caused by a power shortage when writing data. This can be done.

[0372] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the manufacturer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to all the RF tags produced, we will assign a unique number to only the good products that are shipped. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' needs after products are shipped.

[0373] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0374] (Fourth embodiment) In this embodiment, at least the memory cell array 300 etc. described in the embodiment are included. A CPU including a memory device will be explained. Here, the memory device is connected to a memory cell array. It may include a configuration including a row selection driver, a column selection driver, an A / D converter, and the like.

[0375] FIG. 28 shows an example of a CPU that uses the storage device described in the previous embodiment as at least a part thereof. FIG. 1 is a block diagram showing the configuration of the

[0376] The CPU shown in FIG. 28 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 28 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their use. For example, the CPU or the configuration including the arithmetic circuit shown in FIG. 28 is regarded as one core, and the core is divided into multiple It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a calculation circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0377] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0378] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0379] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals that control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generator generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0380] In the CPU shown in FIG. 28, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0381] In the CPU shown in FIG. 28, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0382] FIG. 29 is a circuit diagram of an example of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. The transistor 1209 is an oxide semiconductor. Preferably, the transistor has a channel formed in the semiconductor layer.

[0383] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0384] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 3 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on-state or off-state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD input to the first terminal determines whether or not the first terminal is electrically connected to the second terminal. The on or off state of transistor 1214 is selected.

[0385] One of the source and drain of the transistor 1209 is connected to one of the pair of electrodes of the capacitor 1208. The gate of the transistor 1210 is electrically connected to one of the gates of the transistor 1210. The part is designated as node M2. One of the source and drain of the transistor 1210 is connected to the low power supply voltage. The other is electrically connected to a wiring (for example, a GND line) that can supply a voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (one of the terminals of the transistor 1214) is electrically connected to the The other of the source and drain) is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) the input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor 1207. , are electrically connected. Here, the connection point is referred to as node M1. The other electrode of the pair may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND The capacitor element 12 may be configured to receive a high power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.). The other of the pair of electrodes 08 is connected to a wiring (e.g., GN D line).

[0386] The capacitors 1207 and 1208 are formed by using parasitic capacitances of transistors and wirings. It is also possible to omit this by actively using

[0387] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive state or non-conductive state between the first terminal and the second terminal, and one When the first terminal and the second terminal of the switch are in a conductive state, the first terminal of the other switch and The second terminals are in a non-conductive state.

[0388] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 29, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0389] In FIG. 29, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is passed through the logic element 1206 and the circuit 1220. Although an example of inputting the signal to the circuit 1201 is shown, this is not limiting. The signal output from the other of the source and drain of the transistor 1213 is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0390] In addition, in FIG. 29, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed on a layer or substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed in oxide semiconductor layers. Alternatively, the storage element 1200 may be a transistor 1209 or a In addition, a transistor in which a channel is formed in an oxide semiconductor layer may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor formed by

[0391] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0392] In the semiconductor device of one embodiment of the present invention, while power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to a capacitor 1208 provided in the circuit 1202. Therefore, it can be retained.

[0393] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer increases depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 is maintained for a long period of time. In this way, the memory element 1200 can maintain its stored contents ( It is possible to retain the data.

[0394] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the operation, after the power supply voltage is supplied again, the circuit 1201 This can shorten the time it takes to restore the original data.

[0395] In the circuit 1202, the signal held by the capacitor 1208 is transferred to the transistor. Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the capacitor 1208 is opened, the signal held by the capacitor 1208 is transferred to the transistor 1210 (ON state or OFF state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0396] Such a storage element 1200 may be a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one of the components of the processor, In addition, power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. can be suppressed.

[0397] In this embodiment, the storage element 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSIs such as LSIs and PLDs (Programmable Logic Devices), Also compatible with RF-ID (Radio Frequency Identification) It is available.

[0398] For example, in this specification and the like, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, metal substrates, stainless steel substrates, stainless steel foils Substrate with tungsten foil, tungsten substrate, substrate with tungsten foil, flexible substrate, adhesive Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, and base films include glass. Examples include polyethylene terephthalate (PET), polyethylene terephthalate (PE ... Plastics such as polyethylene naphthalate (PEN) and polyethersulfone (PES) For example, synthetic resin such as acrylic resin is used. Examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy, and inorganic vapor deposition. Films or papers, etc. In particular, semiconductor substrates, single crystal substrates, or SOI substrates, etc. By manufacturing transistors using this method, variations in characteristics, size, shape, etc. can be reduced. This allows the manufacture of transistors with low resistance, high current capability, and small size. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated. This can be achieved.

[0399] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic film such as a tungsten film and a silicon oxide film. It uses a laminated film structure or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0400] That is, a transistor is formed using one substrate, and then a transistor is formed on another substrate. The transistor may be transposed and placed on another substrate. For example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more flexible device.

[0401] For example, in this specification, when it is explicitly stated that X and Y are connected, , when X and Y are electrically connected, and when X and Y are functionally connected, , and the case where X and Y are directly connected. For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applied to the connections shown in the drawings or text. This also includes things other than relationships.

[0402] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, layer, etc.).

[0403] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state) and allows current to flow. The switch has the function of controlling whether or not current flows. It has the function to switch between them.

[0404] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (synthesis circuit, memory circuit, control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if the signal is transmitted to Y.

[0405] When it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (i.e., there is another element or circuit between X and Y.) X and Y are functionally connected (i.e., there is another circuit between X and Y) When X and Y are functionally connected across the , when X and Y are connected without any other element or circuit between them) In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. The same applies if it is explicitly stated that the

[0406] For example, if the source (or first terminal, etc.) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. It may be electrically connected to Y through Z2 (or not), or the source of the transistor may be The first terminal (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When a part of Z2 is directly connected to Y, and another part of Z2 is directly connected to Y, it can be expressed as follows: It can be manifested.

[0407] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" 2 terminals) are electrically connected to each other, and X, the source (or The first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and the Y are electrically connected in this order. "It is connected to the source (or The first terminal (or the drain of the transistor) is electrically connected to X, and the second terminal (or the drain of the transistor) is electrically connected to ) is electrically connected to Y, and X is the source (or first terminal, etc.) of the transistor, The drains (or second terminals, etc.) of the transistors, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." and the drain (or second terminal, etc.) is electrically connected to Y, and X, The source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor, For example, Y is provided in this order. By specifying the order of connections in a circuit configuration using various representation methods, The source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor are separated. The technical scope can be determined separately. Note that these methods of expression are merely examples. The expression method is not limited to these. Here, X, Y, Z1, and Z2 are the (device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.).

[0408] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0409] (Embodiment 5) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, and the like. Image playback device (typically DVD: Digital Versatile Disk) c) a device having a display that can play back a recording medium such as a In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras cameras such as digital still cameras, goggle-type displays (head-mounted displays), Play), navigation systems, sound reproduction equipment (car audio, digital audio copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. show.

[0410] FIG. 30A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 30(A) has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. stomach.

[0411] FIG. 30(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit The first display unit 91 has a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 913 and the second display unit 912. and a display having a function as a position input device added to at least one of the first display unit 914 and the second display unit 915. The function as a position input device can be achieved by touching the display device. Alternatively, the function as a position input device can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel section of the display device. This can be done.

[0412] FIG. 30C shows a notebook personal computer, which includes a housing 921, a display portion 922, It has a keyboard 923, a pointing device 924, and the like.

[0413] FIG. 30(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and a It has 33 etc.

[0414] FIG. 30(E) shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. , operation keys 944, a lens 945, a connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0415] FIG. 30(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, It has Light 954 etc.

[0416] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0417] (Sixth embodiment) In this embodiment, an example of use of an RF tag according to one embodiment of the present invention will be described with reference to FIG. RF tags are used in a wide range of applications, including banknotes, coins, securities, and unregistered Bonds, certificates (driver's licenses, resident cards, etc., see Figure 31(A)), packaging containers (wrapping paper (See Fig. 31(C)), recording media (See Fig. 31(B)) (See Figure 31(D)), vehicles (bicycles, etc.), personal belongings (bags, glasses, etc.), food, Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices ( LCD displays, EL displays, televisions, or mobile phones) or other items It can be attached to tags (see Figure 31(E) and Figure 31(F)) that are attached to each item. can.

[0418] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. It is fixed to the object. For example, if it is a book, it is embedded in the paper and the packaging is made of organic resin. If so, the RF tag according to one aspect of the present invention is embedded in the organic resin and fixed to each article. The GU4000 is small, thin, and lightweight, so even after it is fixed to an object, it does not lose its shape. It does not impair the design of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one embodiment of the present invention to a document or the like, an authentication function is provided. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention can be applied to vessels, recording media, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching an RF tag according to one aspect, the efficiency of a system such as an inspection system can be improved. Furthermore, even in the case of vehicles, the RF tag according to one aspect of the present invention can be attached. This can improve security against theft and the like.

[0419] As described above, the RF tag according to one embodiment of the present invention can be used for each of the applications described in this embodiment. This reduces the operating power consumption, including the writing and reading of information, thereby extending the maximum communication distance. It is also possible to store information for an extremely long period of time even when the power is cut off. Therefore, it can be used for applications where the frequency of writing and reading is low. Cut.

[0420] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0421] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the form, and / or one or more other implementations The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. You can do things like drawing.

[0422] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0423] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. , another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part thereof) described in other embodiments of the present invention, This allows for even more diagrams to be constructed.

[0424] In addition, regarding the contents not specified in the drawings or text in the specification, Alternatively, it is possible to define an upper limit for a certain value. When a numerical range is stated, such as a lower and upper limit, the range may be arbitrarily narrowed. By excluding one point in the scope, it is possible to define an embodiment of the invention that excludes a part of the scope. By these, for example, it is possible to determine whether the prior art falls within the technical scope of one aspect of the present invention. It may be stipulated that the

[0425] As a specific example, a circuit diagram using first to fifth transistors in a circuit is shown below. In this case, the circuit does not have a sixth transistor. Or, the circuit does not have a capacitance element. Furthermore, it is possible to specify that the circuit has a specific connection structure. The invention can be stipulated as not having a sixth transistor as described above. Or, the circuit is defined as not having a capacitance element with a specific connection structure. For example, the gate of the first transistor may be connected to the gate of the second transistor. It is possible to provide the invention as not having a sixth transistor connected to it. Alternatively, for example, a capacitor element having a first electrode connected to the gate of the third transistor may be It is possible to define an invention as not having

[0426] Another example is, for a certain value, for example, "a certain voltage is between 3V and 10V." In that case, for example, if a certain voltage is -2 It is possible to specify one aspect of the invention as excluding cases where the voltage is greater than or equal to V and less than or equal to 1 V. For example, one aspect of the invention may be defined as excluding cases where the voltage is 13 V or higher. It is possible to specify the invention as a voltage between 5V and 8V. It is also possible to define the invention as having a voltage of approximately 9V. For example, the voltage is between 3V and 10V, but excluding the case where it is 9V. It is also possible to define an invention by saying that a certain value is within a certain range. "It is preferable that these conditions are met," etc. However, certain values ​​are not limited to those descriptions. However, even if the invention is described as such, it is not necessarily limited to such description.

[0427] As another specific example, regarding a certain value, for example, "a certain voltage is preferably 10V" In that case, for example, if a certain voltage is between -2V and 1V, It is possible to define one aspect of the invention as "except in the following cases." It is possible to specify one aspect of the invention as excluding cases where the voltage applied is 13 V or higher.

[0428] Another specific example is when describing the properties of a substance, for example, "a certain film is an insulating film." In this case, for example, except when the insulating film is an organic insulating film, Alternatively, for example, the insulating film may be made of an inorganic material. It is possible to define one aspect of the invention as excluding the case where the insulating film is an insulating film. It is possible to define one aspect of the invention as excluding cases where the film is a conductive film. Alternatively, for example, one aspect of the invention may be defined as excluding cases where the film is a semiconductor film. It is possible.

[0429] As another specific example, regarding a certain laminated structure, for example, "between film A and film B, there is a film In that case, for example, if the film has four or more layers, It is possible to define the invention as excluding the case of a laminated film. It is possible to define the invention as excluding cases where a conductive film is provided between the film and the conductive film. do.

[0430] It should be noted that one aspect of the invention described in this specification etc. may be practiced by various people. However, the implementation may involve multiple people. For example, in the case of a transmission and reception system, Company A manufactures and sells the transmitter, and Company B manufactures the receiver. Another example is the manufacture and sale of devices that have transistors and light-emitting elements. In the case of a light-emitting device, the semiconductor device in which the transistor is formed is manufactured and sold by Company A. Company B then purchases the semiconductor device and manufactures a light-emitting element in the semiconductor device. In some cases, the light-emitting device is completed by coating the light-emitting element with a film.

[0431] In such a case, there is no invention that can be used to assert patent infringement against either Company A or Company B. In other words, it is possible to construct an invention that can only be implemented by Company A. It is possible to construct an invention that is only implemented by Company B as a separate invention. In addition, it is possible to assert a patent infringement claim against Company A or Company B. It can be determined that one aspect of the invention that can be achieved is clear and described in the present specification, etc. For example, in the case of a transmission and reception system, it is possible to describe only the transmitter and the receiver. Even if the description of the transmitter alone is not included in this specification, the transmitter alone constitutes one aspect of the invention. The receiver alone can constitute an aspect of another invention, and the aspects of those inventions can be The manner is clear and can be judged as being described in the present specification. In the case of a light-emitting device having a transistor and a light-emitting element, The description of only a semiconductor device having a light emitting element or the description of only a light emitting device having a light emitting element are omitted. Even if not stated in the specification, a semiconductor device having a transistor formed thereon alone is an embodiment of the invention. One embodiment of the present invention can be constituted by a light-emitting device having only a light-emitting element. It can be determined that one aspect of the invention is clear and described in the present specification, etc. This can be done.

[0432] In this specification, the terms "active elements (transistors, diodes, etc.)" and "passive elements" are used interchangeably. For all terminals of elements (capacitance elements, resistance elements, etc.), the connection destination must be specified. Even if the invention is not so simple, a person skilled in the art may be able to construct one aspect of the invention. Even if the connection destination is not specified, one aspect of the invention can be said to be clear. When the content of the above is described in this specification, etc., one aspect of the invention that does not specify a connection destination is the present invention. In some cases, it may be possible to determine that the information is written in the detailed instructions, etc. In particular, if the terminals are connected to multiple If the above case is considered, there is no need to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations of only some of the terminals possessed by the invention, It may be possible to configure an embodiment of the present invention.

[0433] In this specification, if at least the connection destination of a certain circuit is specified, the circuit is considered to be a A person skilled in the art may be able to identify the invention. A person skilled in the art may be able to identify an invention by simply specifying its functions. In other words, if a function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an invention. The invention is disclosed as an embodiment and can be implemented as an embodiment of the invention. Regarding a certain circuit, even if the connection destination is not specified, specifying the function is considered as one aspect of the invention. and can constitute one aspect of the invention.

[0434] In this specification, etc., in a drawing or text described in a certain embodiment, Therefore, it is possible to extract a part of it and use it to constitute an aspect of the invention. If a drawing or text describing a certain part is included, the drawing or text of that part may be omitted. The content of the invention is also disclosed as one aspect of the invention and constitutes one aspect of the invention. It is possible to make such a claim. One aspect of the invention is therefore clear. For example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitance elements, etc.) , resistor elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation In drawings or text that describe singular or multiple methods, manufacturing methods, etc., a part of It is possible to extract N pieces (N From a circuit diagram having circuit elements (such as transistors, capacitive elements, etc.) of (where is an integer), M (where M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) can be extracted to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (where N is an integer) layers, M (where M is an integer and M < N) layers can be extracted to constitute one aspect of the invention. As yet another example, from a flowchart composed of N (where N is an integer) elements, M (where M is an integer and M < N) elements can be extracted to constitute one aspect of the invention. As yet another example, from a sentence described as "A has B, C, D, E, or F", by arbitrarily extracting some elements, "A has , B and E", "A has E and F", "A has C, E and F", , or "A has B, C, D and E", etc. can be used to constitute one aspect of the invention. It is possible.

[0435] In this specification etc., in the figure or sentence described in a certain embodiment, when at least one specific example is described, it is easily understood by those skilled in the art to derive the superordinate concept of that specific example. Therefore, in the figure or sentence described in a certain embodiment, when at least one specific example is described, the superordinate concept of that specific example is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And that one aspect of the invention can be said to be clear.

[0436] In this specification etc., at least the content described in the figure (even a part of the figure) is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if a certain content is shown in a diagram, it can be explained in writing. Even if there is no such content, the content is disclosed as one aspect of the invention, and one aspect of the invention Similarly, even if a part of the drawings is taken out, it is possible to construct the invention. and can constitute one embodiment of the invention. One aspect of the invention is clear. [Explanation of symbols]

[0437] 101j Semiconductor layer 101j_a Semiconductor layer 101j_b Semiconductor layer 101j_c Semiconductor layer 102j Gate insulating film 103j Gate electrode 104 Conductive film 104j_a Conductive layer 104j_b Conductive layer 105j conductive layer 111 Barrier Film 112j Insulating film 113j Insulating film 114j Insulating film 115j Insulating film 116j Insulating film 130a transistor 130b transistor 131 Semiconductor substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 gate electrode 136 Insulating Film 137 Insulating Film 138 insulating film 141j plug 142j plug 143j plug 144j plug 145j plug 146j plug 147j plug 148j plug 151j conductive layer 152j conductive layer 153 Conductive film 153j Conductive layer 154j conductive layer 156j Insulating film 171j_a Low resistance area 171j_b Low resistance region 176a area 176b area 190 transistors 198 transistors 199 transistors 201j Semiconductor layer 201j_a Semiconductor layer 201j_b Semiconductor layer 201j_c Semiconductor layer 202j Gate insulating film 203j Gate electrode 204j Conductive film 204j_a Conductive layer 204j_b Conductive layer 205j conductive layer 212j Insulating film 213j Insulating film 214j Insulating film 216j Insulating film 230a transistor 230b transistor 232 Semiconductor layer 233a Low resistance layer 233b Low resistance layer 235 gate electrode 300 memory cell array 500 Peripheral Circuits 700 Semiconductor devices 800 RF tags 801 Communication Device 802 antenna 803 wireless signal 804 antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 2100 transistors 2200 transistors 4000 RF tags 5100 pellets 5120 board 5161 area

Claims

[Claim 1] a memory cell having first to c-th (c is a natural number of 2 or more) sub-memory cells; a jth (j is a natural number from 1 to c) sub-memory cell includes a first transistor, a second transistor, and a capacitance element; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor each contain an oxide semiconductor; one terminal of the capacitance element is electrically connected to a gate electrode of the second transistor; the gate electrode of the second transistor is electrically connected to either a source electrode or a drain electrode of the first transistor; A semiconductor device, wherein, for j≧2, the j-th sub-memory cell is arranged above the j−1-th sub-memory cell.

Images