Amplification device and amplification method, amplification system, comparison device, and ad conversion device

Abstract

To provide an amplifier or the like which consumes less current and has a lower offset than a conventional technique.SOLUTION: A control circuit of a dynamic amplification device connects a load circuit and a current source to a differential amplifier, short-circuits and then opens each input terminal and each inverting output terminal of the differential amplifier, and holds each input voltage and an error of the differential amplifier in each sampling capacitor. A sampling operation of canceling an error of the differential amplifier, a reset operation of disconnecting the load circuit and the current source and connecting each inverting output terminal to a fixed potential, and an amplification operation of amplifying a difference between input voltages after the sampling operation by connecting the differential amplifier to the current source, setting each inverting output terminal of the differential amplifier to a high impedance, and integrating each output capacitor of the differential amplifier by either charging or discharging according to each input voltage of the differential amplifier are executed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an amplifier device and an amplification method suitable for, for example, a low-power AD conversion device, an amplifier system including the amplifier device, a comparison device including the amplifier device, and an AD conversion device including the comparison device. Regarding comparators. [Background technology]

[0002] FIG. 36 is a circuit diagram showing the configuration of a double tail latch type comparator according to the first conventional example.

[0003] The configuration of the double-tail latch type comparator in Fig. 36 is the configuration reported in Non-Patent Document 1, and since the publication of Non-Patent Documents 2 and 3, which applied it to successive approximation type AD converters, it has been widely used in low-power AD converters up to the present day because it is suitable for low-power operation. This double-tail latch type comparator is composed of a two-stage amplifier consisting of a dynamic type first-stage preamplifier and a post-stage latch, where a MOS transistor M 101 ~M 111 Here, the "dynamic" type refers to a comparator that does not perform comparison operation all the time, but rather controls the comparison phase and reset phase by a clock signal.

[0004] The first-stage dynamic preamplifier in Figure 36 is a differential voltage amplification stage that amplifies and outputs the input differential voltage. Its operation differs from that of a normal amplifier in that it operates dynamically. When the clock signal Clk is at L level, it is in the reset phase, and the output voltages (Out+, Out-) are precharged to the power supply. After that, the clock Clk is set to H level to transition to the comparison phase, in which the differential output voltage is discharged according to the input voltage difference, amplifying the input voltage. The discharge time is the integration time of the input differential voltage, and this integral gain is the gain of the dynamic amplifier.

[0005] The rear latch section in Figure 36 is called a "regenerative latch," a configuration widely used in comparators in AD converters and sense amplifiers in memory readout circuits. When the clock signal Clk is at L level, it is in the reset phase, and resetting is achieved by setting the output voltage to ground potential. After that, the clock Clk is set to H level to transition to the comparison phase, where the input voltage is amplified by the differential input transistor section, and the output voltage amplitude is further amplified rail-to-rail to above the CMOS logic level through positive feedback of the output voltage.

[0006] In AD converters, comparators are used as quantizers. An ideal comparator would output a logic level of H or L depending on whether the input differential voltage is positive or negative, but in reality, an offset occurs due to manufacturing process variations in the input and load differential pair. This comparator offset not only appears in the AD conversion result, but also degrades linearity because it is dependent on the input common voltage. To reduce the offset, it is necessary to increase the size of the input and load differential pair and reduce pair variations. Increasing the size increases the area and parasitic capacitance, making high-speed operation more difficult, and there is a trade-off in that the charge and discharge current required for control and drive increases, resulting in increased current consumption.

[0007] In particular, in successive approximation AD converters, the comparator input becomes high impedance because a capacitive DA converter is connected to the comparator. Increasing the size of the input differential pair leads to (1) signal attenuation due to increased comparator input capacitance, (2) degradation of linearity due to the voltage dependence of the comparator input capacitance, and (3) an increase in kickback noise that affects the input via parasitic capacitance between the input and output of the first-stage preamplifier when transitioning from the reset phase to the comparison phase. Furthermore, because the offset and input capacitance are temperature dependent, the performance trade-off with increasing size is severe. To reduce these effects, high-resolution AD converters often use a differential configuration and have an offset cancellation mechanism in the entire AD converter or in the comparator.

[0008] Patent Document 1 discloses a double-tail latch type comparator with offset calibration, which self-calibrates the offset without increasing the input differential pair of the comparator in the AD converter, and as shown in Patent Document 1, various methods for comparator offset correction have been proposed.

[0009] Fig. 37 is a circuit diagram showing the configuration of a successive approximation type AD converter using a comparator with auto-zero according to Prior Art 2. This successive approximation type AD converter was reported in Non-Patent Document 4 for use in CMOS image sensors. In Fig. 37, this comparator has a three-stage configuration in which a latch A103 is connected to a two-stage preamplifier with auto-zero described as A101 and A102. The capacitive DA converter is also provided with a power-saving mode in which only the latch portion operates by operating the capacitive DA converter at low resolution, turning off the two-stage preamplifier of the comparator, and turning on switches SW106 and SW107.

[0010] During normal operation, first, SW101 to SW104 are turned on before AD conversion, and then SW101 and SW102 are turned off, so that the offset of the first-stage preamplifier is stored in C101 and the SAR type DA converter with its polarity reversed so that it is canceled by the output voltage of the first-stage preamplifier. As a result, the offset of the first-stage preamplifier is canceled by 1 / (A101+1) in input conversion, assuming that the gain is A101. Next, by turning off SW103 and SW104, the remaining offset of the first-stage preamplifier stored in capacitors C103 and C104 is removed, and the offset of the subsequent-stage preamplifier is also canceled by being stored with its polarity reversed, just like the first-stage preamplifier. Finally, the offset of the first-stage preamplifier is removed, and the offset of the subsequent-stage preamplifier is reduced to 1 / (A101(A102+1)) in input conversion, assuming that the gain is A102.

[0011] In this way, shorting the input and output of an amplifier, then opening them, and storing the offset by reversing the polarity of the capacitance connected to the input of the amplifier so that the offset is canceled at the output of the amplifier is called "input offset storage."Furthermore, connecting the input of the amplifier to a fixed potential, shorting one end of a capacitance connected to the output of the amplifier to the fixed potential on the side not connected to the amplifier, then opening it, and storing the offset in a capacitance connected to the output so that the other end of the capacitance is output and the offset is removed is called "output offset storage."

[0012] In the first-stage preamplifier, offset is removed by input offset storage and output offset storage, and in the second-stage preamplifier, offset is canceled by input offset storage. Note that the offset of the latch section is reduced to 1 / (A101 x A102) due to the gain of the first-stage preamplifier when converted into input. During AD conversion, comparison operations are performed with the offset of the second-stage preamplifier canceled. In addition, correlated double sampling (CDS) is also performed by inputting the pixel reset voltage as the input voltage for the AD converter before AD conversion, and inputting the signal voltage during AD conversion. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-109937 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-244759 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-318457 [Patent Document 4] Japanese Patent Application Laid-Open No. 2011-228799 [Non-patent literature]

[0014] [Non-Patent Document 1] D. Schinkel et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup + Hold Time," ISSCC Dig. Tech. Papers, pp.314-315, Feb. 2007. [Non-patent document 2] M. van Elzakker et al., "A 1.9μW 4.4fJ / Conversion-step 10b 1MS / s charge-redistribution ADC", IEEE ISSCC Dig. Tech. Papers, Feb. 2008. [Non-patent document 3] M. van Elzakker et al., "A 10-bit Charge-redistribution ADC consuming 1.9μW at 1MS / s", IEEE JSSC, vol.45, no.5, pp.1007-1015, May 2010. [Non-patent document 4] Shiro Saiko et al., "Study on an Event Detection CMOS Image Sensor Using Deep Learning (2) - Low-Resolution, Low-Power A / D Converter," ITE Technical Report, Vol. 45, No. 21, Aug. 2021. [Non-patent document 5] B. Razavi, "The Strong ARM Latch [A Circuit for All Seasons]", in IEEE Solid-State Circuits Magazine, Spring, vol. 7, no. 2, pp. 12-17, 2015. Summary of the Invention [Problem to be solved by the invention]

[0015] In power-saving mode, the two-stage preamplifier with auto-zero function is bypassed and operates as a latch only, and no steady-state current flows, enabling low-power operation. However, there were the following issues: (1) There is no auto-zero, so the offset is large. (2) The latch is directly connected to the comparator input, resulting in a large kickback noise. (3) Linearity degradation occurs due to the parasitic capacitance of the mode changeover switches SW106 and SW107 connected to the comparator input. (4) Compared to normal operation, the comparator input impedance is different, resulting in a difference in the signal transfer function. (5) The clamp voltage of the comparator input in correlated double sampling (CDS) changes from that during normal operation.

[0016] In a system in which multiple AD converters are connected in parallel, such as the image sensor application in Non-Patent Document 4, it is possible to perform offset correction as in Patent Document 1, but because each AD converter requires an offset correction circuit, a comparator with auto-zero that does not have a correction circuit and can perform correlated double sampling (CDS) and offset cancellation in the analog domain is often used.

[0017] The above-mentioned double-tail latch dynamic comparator has the problem that to reduce the offset, the input differential pair must be enlarged or a correction circuit must be added. Also, the comparator with auto-zero function has the problem that it is difficult to reduce current consumption because a steady current flows in the preamplifier. Note that Patent Documents 2 to 4 have similar problems.

[0018] An object of the present invention is to solve the above problems and to provide an amplifier device and an amplification method that consume less current and have a lower offset than conventional techniques, an amplifier system including the amplifier device, a comparison device including the amplifier device, and an AD conversion device including the comparison device. [Means for solving the problem]

[0019] An amplifier according to one aspect of the present invention comprises: a differential amplifier having first and second input terminals and first and second inverting output terminals; first and second sampling capacitors connected to the first and second input terminals of the differential amplifier, respectively; first and second switches that respectively short-circuit the first and second input terminals and the first and second inverting output terminals of the differential amplifier; and a control circuit for controlling the operation of the amplifier device, The differential amplifier an input differential pair including a pair of transistors; a current source; a third switch inserted between the source of the input differential pair and the current source; first and second output capacitors connected to the first and second inverting output terminals of the differential amplifier, respectively; The amplifier device comprises: a load circuit connected to the first and second inverting output terminals of the differential amplifier; fourth and fifth switches for connecting the first and second inverting output terminals of the differential amplifier to a predetermined fixed potential; sixth and seventh switches for connecting or disconnecting the load circuit to the first and second inverting output terminals of the differential amplifier; The control circuit (1) a sampling operation in which the third switch and the sixth and seventh switches are controlled to connect the load circuit and the current source to the differential amplifier, the first and second switches are controlled to short-circuit the first and second input terminals and the first and second inverting output terminals of the differential amplifier and then open them, and the first and second input voltages and an error of the differential amplifier are held in the first and second sampling capacitors, thereby canceling out the error of the differential amplifier; (2) after the sampling operation, a reset operation of controlling the third switch and the sixth and seventh switches to disconnect the load circuit from the current source, and controlling the fourth and fifth switches to connect the first and second inverting output terminals to a fixed potential; (3) after the reset operation, the third switch is controlled to connect the differential amplifier to the current source, and the first and second inverting output terminals of the differential amplifier are an amplifying operation of amplifying a difference between a second input voltage and a first input voltage after the sampling operation by setting the first and second output capacitors of the differential amplifier to a high impedance and integrating by either charging or discharging the first and second output capacitors of the differential amplifier according to the first and second input voltages of the differential amplifier; Execute. [Effects of the Invention]

[0020] Therefore, according to the amplifier device of the present invention, a dynamic amplifier device is operated as an amplifier during auto-zero mode, the offset of the input differential pair is stored in the input capacitance, and the offset is cancelled during comparison operation to perform dynamic operation, thereby making it possible to provide an amplifier device or the like that consumes less current and has a lower offset than conventional technology. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a circuit diagram showing a configuration example of a dynamic amplifier circuit 1 with input offset storage according to a first embodiment. [Figure 2] 2 is a circuit diagram showing a detailed configuration of a differential amplifier unit 2 of FIG. 1. [Figure 3] 1. FIG. 4 is a circuit diagram showing the configuration of a load circuit 3A according to a modified example of the load circuit 3 of FIG. [Figure 4] 2 is a timing chart of each signal showing the operation of the dynamic amplifier circuit 1 of FIG. [Figure 5] 2 is a block diagram showing a single-ended configuration for explaining an error in the differential amplifier section 2 of FIG. 1. FIG. [Figure 6]FIG. 10 is a circuit diagram showing a configuration of a differential amplifier section 2A according to a modified example. [Figure 7] 7 is a timing chart of each signal showing the operation of the differential amplifier unit 2A of FIG. 6. [Figure 8] FIG. 10 is a circuit diagram showing a configuration of an offset adjustment circuit 5 according to a second embodiment. [Figure 9] FIG. 9 is a circuit diagram showing the configuration of the variable resistance circuit of FIG. 8. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of a dynamic amplifier circuit 1B according to a second embodiment. [Figure 11] 11 is a flowchart showing an offset comparison process executed by the control circuit 10B of FIG. [Figure 12] 11 is a flowchart showing an offset correction process executed by the control circuit 10B of FIG. [Figure 13] 13 is a flowchart showing an offset correction process that is a first modification of the offset correction process of FIG. 12. [Figure 14] 13 is a flowchart showing an offset correction process that is a second modification of the offset correction process of FIG. [Figure 15] 13 is a flowchart showing an offset correction process that is a third modification of the offset correction process of FIG. [Figure 16] 17 is a timing chart of each signal showing the operation of the dynamic amplifier circuit 1C (FIG. 17) according to the third embodiment. [Figure 17] 10 is a circuit diagram showing a configuration example of a dynamic amplifier circuit 1C according to a third embodiment. FIG. [Figure 18] 18 is a circuit diagram showing a detailed configuration of a differential amplifier section 2C of FIG. 17. FIG. [Figure 19] 18 is a timing chart of each signal showing the operation of the differential amplifier unit 2C of FIG. 17. [Figure 20] FIG. 10 is a circuit diagram showing a configuration example of a strong-arm latch type dynamic comparison circuit 2D with input offset storage according to a fourth embodiment. [Figure 21]21 is a timing chart of each signal showing the operation of the dynamic comparison circuit 2D of FIG. 20. [Figure 22] FIG. 10 is a circuit diagram illustrating a configuration example of a double-tail latch type comparator circuit with input offset storage according to a fifth embodiment. [Figure 23] FIG. 13 is a circuit diagram showing a configuration example of a comparison circuit according to a sixth embodiment. [Figure 24] 24 is a timing chart of each signal showing the operation of the comparison circuit of FIG. 23. [Figure 25] FIG. 11 is a circuit diagram showing a configuration example of a dynamic amplifier circuit according to a seventh embodiment. [Figure 26] FIG. 13 is a circuit diagram showing a configuration example of a comparison circuit according to an eighth embodiment. [Figure 27] 27 is a timing chart of each signal showing the operation in the normal mode in the comparison circuit of FIG. 26. [Figure 28] 27 is a timing chart of each signal showing the operation of the comparison circuit of FIG. 26 in a low-power operation mode. [Figure 29] 2 is a flowchart showing a signal amplification process executed by the control circuit 10 of the dynamic amplifier circuit 1 of FIG. [Figure 30] FIG. 13 is a circuit diagram illustrating a configuration example of a successive approximation type AD conversion device according to a ninth embodiment. [Figure 31] FIG. 20 is a circuit diagram showing a configuration example of a successive approximation type AD conversion device according to a tenth embodiment. [Figure 32] FIG. 20 is a circuit diagram showing an example of the configuration of a successive approximation type AD conversion device according to an eleventh embodiment. [Figure 33] FIG. 22 is a circuit diagram illustrating a configuration example of an AD conversion device according to a twelfth embodiment. [Figure 34] FIG. 22 is a circuit diagram illustrating a configuration example of an AD conversion device according to a thirteenth embodiment. [Figure 35] FIG. 22 is a circuit diagram showing an example of the configuration of an AD conversion device according to a fourteenth embodiment. [Figure 36] FIG. 1 is a circuit diagram showing a configuration of a double tail latch type comparator according to Conventional Example 1. [Figure 37]FIG. 10 is a circuit diagram showing the configuration of a successive approximation type AD converter using a comparator with auto-zero according to Conventional Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0023] (Embodiment 1) 1 is a circuit diagram showing an example of the configuration of a dynamic amplifier circuit 1 with input offset storage according to the first embodiment. In FIG. 1, the dynamic amplifier circuit 1 with input offset storage includes a differential amplifier section 2 and an input voltage V p ,V m and a sampling capacitor C for sampling the offset of the differential amplifier section 2. sp ,C sm and a switch SW that shorts the amplifier input and inverting output to store the offset voltage at the input. azpm ,SW azmp and switch SW azpm ,SW azmp and a control circuit 10 that controls the operation of the differential amplifier section 2.

[0024] In Figure 1, the input voltage V p is the sampling capacitor C sp is input to the non-inverting input terminal of the differential amplifier 2 via the m is the sampling capacitor C sm The inverting output terminal of the differential amplifier 2 is connected to the switch SW azpm The non-inverting input terminal of differential amplifier 2 is connected to the non-inverting input terminal via switch SW azmp It is connected to the inverting input terminal via the switch SW azpm ,SW azmp is controlled to be turned on or off by an auto-zero control signal AZ from the control circuit 10, and here, the switch SW azpm ,SWazmp is turned on, while the switch SW azpm ,SW azmp is turned off.

[0025] The control circuit 10 generates control signals DPAEN and DPACK to control the operation of the differential amplifier section 2. The control signal DPAEN is an enable signal for the dynamic amplifier operation of the differential amplifier section 2, and is a control signal for switching the load on and off during auto-zero. The control signal DPACK is a control signal for switching the reset / amplification operation of the differential amplifier section 2. The CK signal input to the control circuit 10 is a clock signal for dynamic operation that controls the reset operation at L level and the amplification operation at H level. The input voltage to the non-inverting input terminal of the differential amplifier section 2 is V ip and the input voltage of the inverting input terminal is V im In addition, the output voltage from the inverting input terminal of the differential amplifier section 2 is V om and the output voltage from the non-inverting input terminal is V op Let's say.

[0026] FIG. 2 is a circuit diagram showing a detailed configuration of the differential amplifier unit 2 of FIG.

[0027] In FIG. 2, the differential amplifier section 2 includes: (1) Input voltage V ip ,V im an input differential pair of MOS transistors M1 and M2 connected to a non-inverting input terminal and an inverting input terminal to which the (2) Connect the switch SW to the common source of the input differential pair MOS transistors M1 and M2. tail The tail current I connected through tail A tail current source I tail and, (3) a load circuit 3 connected to the drains of the input differential pair MOS transistors M1 and M2; (4) Output voltage V op ,V om A switch SW is provided between each output terminal and the power supply voltage VDD, and is controlled by the control signal / DPACK.op ,SW om and, (5) Output voltage V op ,V om The output load capacitor C connected to each output terminal is LP ,C LM and, The device is configured to include:

[0028] When the control signal DPAEN is at H level or the inverted control signal / DPAEN is at L level, the switch SW op ,SW om On the other hand, when the control signal DPAEN is at L level or the inverted control signal / DPAEN is at H level, the switch SW op ,SW om When the control signal DPACK is at H level or the inverted control signal / DPACK is at L level, the switch SW load1 ,SW load2 ,SW tail On the other hand, when the control signal DPACK is at L level or the inverted control signal / DPACK is at H level, the switch SW load1 ,SW load2 ,SW tail Turn off.

[0029] Here, the tail current source I tail On / off is by switch SW tail Without using the tail current source I tail In the example of FIG. 2, the load circuit 3 includes a PMOS transistor M 11 ,M 12 and a PMOS current mirror circuit including switches SW controlled by control signals / DPAEN and DPAEN. load1 ,SW load2 The present invention is configured to include the following.

[0030] 3 is a circuit diagram showing the configuration of a load circuit 3A according to a modification of the load circuit 3 of FIG. 2. In addition to the example of FIG. 2, the load circuit 3 may have a configuration that is folded back via a current source, a resistor, a diode-connected MOS transistor, and a current mirror circuit. Also, as shown in FIG. 3, a switch SWload1 ,SW load2 MOS transistor M 11 ,M 12 Alternatively, the drain of the transistor 10 may be connected in series to the drain of the transistor 10.

[0031] 4 is a timing chart of each signal showing the operation of the dynamic amplifier circuit 1 of FIG. 4. In FIG. 4, first, the input voltage V p and V m and the initial voltage V pinit ,V minit For example, when using differential amplification, both voltages (V pinit =V minit ) to the input common voltage V cm or reference voltage V ref Alternatively, the pixel reset voltage V may be set to a divided or multiplied voltage or a fixed potential such as VSS. rst The initial voltage V pinit and the input voltage V m is the reference voltage V that is set to the input range depending on the DA conversion circuit used. ref The initial voltage V minit In Figure 4, the input voltage V p ,V m The hatched portion indicates a transition portion of the input voltage before and after.

[0032] Next, the auto-zero control signal AZ is set to H level, shorting each input terminal of the differential amplifier 2 to its corresponding inverted output terminal, clamping each input terminal to the corresponding inverted output voltage including the offset error. The control signal DPAEN is set to L level, and the control signal DPACK is set to H level to amplify the differential amplifier 2, and the input voltage V of the differential amplifier 2 is ip ,V im After the output voltage is settled to the inverted output voltage with the output shorted, the auto-zero control signal AZ is set to L level, and the sampling capacitor C is set to C so that the offset error voltage of the differential amplifier 2 is canceled at each inverted output terminal. sp , C sm Then, the polarity is reversed and the input voltage Vp ,V m V p1 ,V m1 For example, when using differential amplification, the differential signal is set to the input voltage V p , V m When used in a single-ended AD conversion circuit, the input voltage V p , V m Either the input signal V sig is applied to the other side, and the output voltage V of the DA conversion circuit is applied to the other side. dac is applied.

[0033] This results in an initial voltage V pinit ,V minit and the input voltage V p1 ,V p2 ,V m1 ,V m2 The difference between these two is input to the differential amplifier 2, and correlated double sampling (CDS) is performed, whereby the error components that are correlated with each other are cancelled. In the example of the PMOS current mirror load circuit 3, the clamp voltage of the CDS is 11 ,M 12 The gate-source voltage is

[0034] Next, the control signal DPAEN is set to H level to turn off the load circuit 3 so that it has high impedance with respect to the output terminal. Then, the control signal DPACK is set to L level to precharge and reset the output terminal from the power supply voltage VDD. After that, the control signal DPACK is set to H level to reset the differential output voltage V om ,V op is discharged according to the input voltage difference, ip ,V im Amplify.

[0035] The discharge time during the H level period of the control signal DPACK is the integral time T int The integral gain is the gain a of the dynamic amplifier circuit 1. ind Then, the discharge current I o is the transconductance of the input differential pair, gmd It is expressed by the following equation using

[0036] I o =g md ×V ind

[0037] Output voltage V after integration time has elapsed od is expressed by the following equation:

[0038] V od =I o ×T int / C L

[0039] where C L is the load capacitance. Therefore, the gain a is expressed by the following equation.

[0040] a=V od / V ind =g md / C L ×T int

[0041] However, the output common voltage V ocom is the tail current I tail It is expressed by the following equation using

[0042] V ocom =VDD-I tail / (2×C L )×t

[0043] Here, the power supply voltage VDD drops over time, and when it reaches near the ground level, the gain becomes insufficient. Therefore, the H level width of the control signal DPACK can be adjusted according to the load capacitance, or the output common voltage V ocom The tail current source I tailis used to equalize the offset voltages by making the gate-source voltages of the input differential pair MOS transistors M1 and M2 equal to that during auto-zero, thereby maximizing the amount of offset cancellation. Also, if a decrease in the frequency band where errors are canceled in CDS can be tolerated and high impedance can be maintained at both input terminals of the differential amplifier section 2, the reset and amplification operations can be repeated by setting the control signal DPACK to L level / H level from the second time onwards, as shown in Figure 4.

[0044] Figure 5 is a block diagram showing a single-ended configuration to explain the error of the differential amplifier section 2 in Figure 1. For offset error analysis, Figure 5 shows a model in which the input is grounded and an input-referred offset error is introduced into the amplifier. When the auto-zero control signal AZ is at H level, the input-referred error of the differential amplifier section 2 in amplifying operation is e, and its voltage gain is Av=A, then the amplifier input voltage V during auto-zero is iaz is expressed by the following equation:

[0045] V iaz =V oaz =-A×(V iaz +e) =-A / (1+A)×e

[0046] After that, the auto-zero control signal AZ is set to L level, and the sampling capacitance C s The offset error is stored with its polarity reversed. The offset error components during amplification in auto-zero mode are divided into the input differential pair MOS transistors M1 and M2 and the load circuit 3 and calculated as follows. The input-referred offset error of the input differential pair MOS transistors M1 and M2 is e = e osdiff and the gain of the differential amplifier section 2 during amplification in dynamic operation is a, the output voltage V oosdiff is expressed by the following equation:

[0047] V oosdiff =-a×(V iaz +e osdiff ) =-a / (1+A)×e osdiff

[0048] Its input-equivalent offset voltage V irosdiff is expressed by the following equation:

[0049] V irosdiff =V oosdiff / (-a) =1 / (1+A)×e osdiff

[0050] The amplifier operation during auto-zero cancels the error component of the input differential pair to 1 / (1+A). Next, the input-referred offset error of the differential pair load circuit 3 during auto-zero is e = e osload Then, the output voltage V oosload is expressed by the following equation:

[0051] V oosload =-a×V iaz = a×A / (1+A)×e osload

[0052] Its input-equivalent offset voltage V irosload is expressed by the following equation:

[0053] V irosload =V oosload / (-a1) =-A / (1+A)×e osload

[0054] The offset component of the differential pair load during AZ stored in the input of the differential amplifier section 2 is not canceled. The input-equivalent offset voltage V of the entire dynamic amplifier iros is expressed as the square root of the sum of squares as follows, since the offsets of the input differential pair MOS transistors M1, M2 and the load circuit 3 vary independently due to mismatch components of the differential pair.

[0055]

number

[0056] From the above, it can be seen that the error of the dynamic amplifier circuit 1 according to this embodiment is determined by the offset error of the load circuit 3 during auto-zero operation, because the offset error due to the input differential pair of MOS transistors M1 and M2 is canceled out. Compared to the input differential pair of MOS transistors M1 and M2, increasing the size of the load circuit 3 of the dynamic amplifier circuit 1 does not increase the input capacitance of the differential amplifier section 2, and there is little trade-off with input capacitance-induced characteristics such as signal attenuation and increased kickback noise, making it easy to reduce offset by increasing the size. Furthermore, even when an offset correction circuit is added to the output stage, the size of the correction circuit can easily be reduced.

[0057] As described above, the dynamic amplifier circuit 1 according to this embodiment can reduce the offset without increasing the size of the input differential pair MOS transistors. Furthermore, even when an offset correction circuit is used, the scale of the circuit can be reduced.

[0058] 29 is a flowchart showing the signal amplification process executed by the control circuit 10 of the dynamic amplifier circuit 1 shown in FIG. sp ,C sm The offset is then stored in the buffer, and then dynamically amplified by an integral action.

[0059] In FIG. 29, first, in step S31, the differential amplifier input / output switch SW azpm ,SW azmp By turning on the input voltage V p ,V m and its inverted output voltage, V om ,V op The output voltage V of the differential amplifier section 2 is om ,V opThe inverted error voltages -Ve1 and -Ve2 are output from the capacitors C connected to the two input terminals of the differential amplifier 2, respectively. sp , C sm via the input voltage V p , V m The first voltage V1 and the second voltage V2 are input as

[0060] Next, in step S32, the switch SW azpm ,SW azmp By turning off the differential amplifier 2 and opening the input / output terminals, the potential difference between the inverted error voltages -Ve1, -Ve2 and the input voltages V1, V2 is sp ,C sm Each of them is held in

[0061] Then, in step S33, the input voltage V p and V m The third voltage V3 and the fourth voltage V4 are input as the differential amplifier section 2, and the input differential pair transistors M1 and M2 and the tail current source I tail , in the load circuit 3, the switch SW tail By turning off the tail current source I tail current supply to the load1 ,SW load2 By turning off the load circuit 3, the load circuit 3 is released from the output terminal, and the switch SW op ,Sw om By turning on the output terminal, the output load capacitance is reset by connecting the output terminal to a predetermined fixed potential.

[0062] Then, in step S34, the switch SW tail By turning on the switch SW1 and flowing a tail current, the input differential pair MOS transistors M1 and M2 are activated, and the switch SW2 op ,SW omBy turning off the resistor R1, the output terminal set to a fixed potential is opened, and the input voltages V3-Ve1-V1 and V4-Ve2-V2 of the differential amplifier unit 2 are converted into voltages and currents by the input differential pair MOS transistors M1 and M2. The errors generated in the differential amplifier unit 2 are offset by the converted currents of the -Ve1 and -Ve2 terms, and the output load capacitance is charged or discharged with the converted currents and integrated for amplification.

[0063] As described above, in the signal amplification process according to this embodiment, by performing the auto-zero operation before the reset / amplification operation, the offset can be reduced without increasing the size of the input MOS transistor.

[0064] Fig. 6 is a circuit diagram showing the configuration of a differential amplifier section 2A according to a modified example, which is characterized in that the NMOS input differential amplifier section is changed to a PMOS input differential amplifier section in comparison with the differential amplifier section 2 of Fig. 2.

[0065] FIG. 7 is a timing chart of each signal showing the operation of the differential amplifier section 2A of FIG.

[0066] In Figure 7, similar to the operation in Figure 4, first, the input voltage V p and V m The initial voltage V pinit ,V minit Next, the auto-zero control signal AZ is set to H level to short-circuit the input terminal and inverted output terminal of the differential amplifier 2A, and each input terminal is clamped to each inverted output voltage. The control signal DPAEN is set to L level, and the control signal DPACK is set to H level to amplify the differential amplifier 2A, and after the input voltage has settled, the auto-zero control signal AZ is set to L level to cancel the offset of the differential amplifier 2A at the output terminal. sp , C sm Then, the polarity is reversed and the input voltage V p ,V m respectively, the input voltage V p1 ,V m1Next, the control signal DPAEN is set to H level, turning off the load circuit 3 so that it has high impedance with respect to the output terminal. Then, the control signal DPACK is set to L level, discharging the output terminal to ground and resetting it. After that, the control signal DPACK is set to H level, and the input voltage is amplified by charging the differential output voltage according to the input voltage difference.

[0067] As described above, by changing the differential amplifier unit 2A from an NMOS input differential amplifier to a PMOS input differential amplifier, the input voltage range and the output voltage range can be changed.

[0068] (Embodiment 2) Fig. 8 is a circuit diagram showing the configuration of an offset adjustment circuit 5 according to embodiment 2. Fig. 8 shows a configuration in which an offset adjustment circuit 5 is added to the load circuit 3 of Fig. 2. The offset adjustment circuit 5 is configured by inserting variable resistance circuits VR1 and VR2 on the power supply voltage VDD side of the differential pair load. A control signal OSCTRL is a digital control signal for offset adjustment.

[0069] 9 is a circuit diagram showing the configuration of the variable resistance circuits VR1 and VR2 in FIG. 8. In FIG. 9, the variable resistance circuits VR1 and VR2 are configured by resistors R u This can be easily achieved by switching the unit resistance value with a switch. u As a result, the resistance value R u In this example, the resistance value can be adjusted from 0.1 to 4Ru. The type of resistor used may be either a polysilicon resistor or an on-resistance of a MOS transistor, depending on the configuration of the load circuit 3 and the bias current value.

[0070] FIG. 10 is a block diagram showing an example of the configuration of a dynamic amplifier circuit 1B according to the second embodiment. In FIG. 10, the dynamic amplifier circuit 1B is characterized in that an offset adjustment circuit is added to the dynamic amplifier circuit 1 of FIG. 1. The offset adjustment circuit includes: (1) Sampling capacitor C sp The voltage input to the input voltage V p and the input common voltage Vcm and sampling capacitor C sm The voltage input to the input voltage V m and the input common voltage V cm Input signal selector switch SW inp ,SW inm and, (2) Output voltage V om ,V op and a comparator 12 that compares the two and outputs a comparison result signal to the control circuit 10B. (3) a control circuit 10B that controls the operation of the differential amplifier unit 2 and the offset adjustment circuit; (4) a memory 11 connected to the control circuit 10B; The device is configured to include: The differences will be explained below.

[0071] In Figure 10, the input signal selector switch SW inp ,SW inm is the control signal SSW from the control circuit 10B inp ,SSW inm Based on this, the capacitor C sp ,C sm Connect one end of each to the input common voltage V cm where the input common voltage V cm may be at ground level or another potential as long as each differential input terminal is short-circuited. Comparator 12 compares whether the offset of the amplifier differential output voltage of differential amplifier unit 2 is positive or negative, and outputs a comparison result signal to control circuit 10B. Control circuit 10B adjusts the offset of differential amplifier unit 2 based on the comparison result signal of comparator 12. Memory 11 stores the offset correction value (calibration value) from control circuit 10B and outputs it to control circuit 10B.

[0072] Fig. 11 is a flowchart showing the offset comparison process executed by the control circuit 10B of Fig. 10. In the offset correction, the offset of each output voltage of the differential amplifier section 2 is compared so that the load resistance value when imbalance occurs due to a mismatch in the impedance of the differential pair MOS transistors M1, M2 and the load circuit 3 balances with the impedance of the differential pair MOS transistors M1, M2, and the control circuit 10B adjusts the offset of each output voltage of the differential amplifier section 2 to approach zero by adjusting the offset adjustment resistors based on the comparison result signal. The offset comparison process in the offset correction is carried out by connecting each differential input terminal of the differential amplifier section 2 to the input signal selector switch SW inp ,SW inm In the state where the voltages are set to the same potential, the amplifiers are amplified by dynamic operation from auto-zero as in normal operation, and the differential output voltages are compared by the comparator 12.

[0073] In step S1 of FIG. 11, first, the control signal DPAEN is set to L level, and the control signal DPACK is set to H level to operate the differential amplifier unit 2, and the input / output switch SW azpm ,SW azmp By turning on the input voltage V ip ,V im Each terminal and its inverted output voltage V om ,V op By shorting each terminal of the differential amplifier section 2, the output voltage V om ,V op The inverted error voltages -Ve1 and -Ve2 are output as the capacitors C sp ,C sm Connect one end of each of the input signal selector switches S winp ,S winm This causes the common voltage V cm Connect to.

[0074] Next, in step S2, the switch SW azpm ,SW azmp By turning off the differential amplifier 2 and opening the input / output terminals, the inverted error voltages -Ve1 and -Ve2 and the common voltage V cm The potential difference between the capacitor C sp ,Csm Each of them is held in

[0075] Then, in step S3, the control signal DPAEN is set to H level, and the control signal DPACK is set to L level to reset the differential amplifier unit 2. After that, in step S4, the control signal DPACK is set to H level, and the inverted error voltages −Ve1 and −Ve2 of the differential amplifier unit 2 are voltage-current converted by the input differential pair MOS transistors M1 and M2, and the components of the error generated in the differential amplifier unit 2 that are not canceled out are amplified by charging or discharging the output load capacitance with the converted current and integrating it, thereby outputting the output voltage V op ,V om Output as

[0076] Finally, in step S5, the comparator 12 detects the differential output voltage V op and V om Here, if the noise of the comparator 12 is large, the number of offset comparison processes may be increased, and the comparison result signals may be integrated to make a majority decision according to the number of comparisons, thereby improving the comparison accuracy.

[0077] Fig. 12 is a flowchart showing the offset correction process executed by the control circuit 10B of Fig. 10. In the offset correction process of Fig. 12, the offset correction process is performed by incrementing or decrementing the offset adjustment value OSCTRL.

[0078] 12, first, the control circuit 10B sets the offset adjustment value OSCTRL to 0 and initializes the offset comparison count N to 0. Next, in step S12, an offset comparison process is performed, and in step S13, the control circuit 10B determines whether N>0 or the comparison result of the comparison result signal is different from the previous comparison result, and updates the value of the offset adjustment value OSCTRL by incrementing or decrementing by -1 based on the comparison result of step S14 (S15, S16). Thereafter, in step S17, the offset comparison count N is incremented by +1, and the offset adjustment value OSCTRL and the comparison result are saved in memory 11.

[0079] Next, the process returns to step S12, and an offset comparison process is performed. The offset correction is performed by repeating steps S14 to S17, S12, and S13 until the comparison result of step S13 becomes YES, which indicates that the offset correction has been completed. After the offset correction process is completed, the differential amplifier unit 2 operates using the offset correction value stored in the memory 11.

[0080] Fig. 13 is a flowchart showing an offset correction process that is a first modification of the offset correction process of Fig. 12. The offset correction process of Fig. 13 differs from the offset correction process of Fig. 12 in the following points. (1) Instead of step S11, step S11A is included. (2) The processes of steps S12, S13, S16, and S17 are included. The differences will be explained below.

[0081] 13, in step S11A, the offset adjustment value OSCTRL is set to the minimum value, and the offset comparison count is initialized to 0. Next, the processes of steps S12, S13, S16, and S17 are executed. As a result, the resistance control value by the offset adjustment value OSCTRL is incremented from the minimum value, and the offset correction process is executed.

[0082] Fig. 14 is a flowchart showing an offset correction process that is a second modification of the offset correction process of Fig. 12. The offset correction process of Fig. 14 differs from the offset correction process of Fig. 12 in the following points. (1) Instead of step S11, step S11B is included. (2) The processes of steps S12, S13, S15, and S17 are included. The differences will be explained below.

[0083] 14, in step S11B, the offset adjustment value OSCTRL is set to the maximum value, and the offset comparison count is initialized to 0. Next, the processes of steps S12, S13, S15, and S17 are executed. As a result, the resistance control value by the offset adjustment value OSCTRL is decremented from the maximum value, and the offset correction process is executed.

[0084] Fig. 15 is a flowchart showing an offset correction process which is a third modification of the offset correction process of Fig. 12. The offset correction process of Fig. 15 is a correction process using a binary search.

[0085] 15, the control circuit 10B sets the offset adjustment value OSCTRL to 0 and initializes the offset comparison count N to 0. Here, the range of the offset adjustment value OSCTRL is -α≦OSCTRL<α, where α is a positive integer. Next, in step S22, an offset comparison process is performed, and in step S23, V op >V om If the result is YES, proceed to step S24, and if the result is NO, proceed to step S25. Here, based on the comparison result of step S23, the offset adjustment value OSCTRL is set to +α / 2 so as to sequentially halve the range α. N+1 Increment by or -α / 2 N+1(S24, S25). Thereafter, in step S26, the offset comparison count N is incremented by +1, and the comparison result is stored in the memory 11 with the offset adjustment value OSCTRL (S26). Subsequently, similarly, the offset comparison process of step S22 is performed, and the offset adjustment value OSCTRL is updated until the offset comparison count N exceeds the number of bits of the offset adjustment value OSCTRL (S27), thereby performing offset correction.

[0086] As described above, the dynamic amplifier circuit 1B including the offset correction circuit according to the second embodiment can correct the offset of the load circuit 3 relative to the differential pair of MOS transistors. Here, the offset correction process using increment or decrement has a simple configuration, allowing for a small circuit size. Furthermore, the offset correction process using binary search requires fewer comparisons than a search using increment or decrement, allowing for faster correction.

[0087] (Embodiment 3) Fig. 16 is a timing chart of each signal showing the complete dynamic operation of the dynamic amplifier circuit 1C (Fig. 17) according to embodiment 3. Fig. 17 is a circuit diagram showing an example of the configuration of the dynamic amplifier circuit 1C according to embodiment 3, and Fig. 18 is a circuit diagram showing the detailed configuration of the differential amplifier section 2C of Fig. 17.

[0088] The dynamic amplifier circuit 1C of Figures 16 to 18 is characterized in that by changing the control signal in embodiment 1 or 2, the operating mode can be switched between a fully dynamic operating mode for low current consumption operation and an amplifier mode with auto-zero that does not perform dynamic operation for high-precision operation.

[0089] 16, in order to reduce current consumption during fully dynamic operation, the differential amplifier unit 2C is reset by setting the control signal DPAEN to H level and fixing the control signal DPACK to L level during the auto-zero period in Fig. 4. For this reason, auto-zero is not performed and only CDS is performed.

[0090] Here, as shown in FIG. 17, in order to change the clamp voltage during CDS, the clamp voltage V for CDS is controlled by the control signal LPM from the control circuit 10C during full dynamic operation. clamp Switch SW for connecting to ipmm ,SW ipmp Auto-zero switch SW azpm ,SW azmp In addition, when the clamp voltage during CDS is set to the output voltage of the differential amplifier section 2C during full dynamic operation, the selector switch SW ipmm ,SW ipmp The configuration of Figure 1 may be used, omitting the tail current source I tail The operation is the same as in Figure 4 except that the tail current source I tail The amount of current in the tail current source I tail In parallel with switch SW ipmtail may be inserted and turned on and bypassed by the control signal LPM during full dynamic operation.

[0091] Figure 19 is a timing chart of each signal showing the operation of the differential amplifier unit 2C of Figure 17 without dynamic operation. Compared to the differential amplifier unit 2 of Figure 2, the dynamic operation clock CK is set to L level, the control signal DPAEN is set to L level, and the control signal DPACK is fixed to H level, so that the differential amplifier unit 2C operates as a normal amplifier with auto-zero without dynamic operation. In this way, the operating mode can be switched simply by changing the control signals.

[0092] As described above, according to the third embodiment, in a fully dynamic operation, the error of the amplifier differential pair cannot be canceled as compared with the first or second embodiment, but current consumption can be reduced by stopping the amplifier operation during auto-zero.

[0093] In the normal auto-zero unmode without dynamic operation, current consumption increases compared to the first or second embodiment, but the offset or low-frequency error of the load circuit 3 can be canceled, allowing the differential amplifier unit 2C to be used with high precision. Furthermore, since the input impedance does not change significantly when switching between operation modes, the difference in signal transfer function can be reduced. Furthermore, the clamp voltage in the CDS does not change when switching between modes.

[0094] As described above, according to the third embodiment, the control signal is used to switch between an operation mode with low power consumption and low accuracy, or a mode with high power consumption and high accuracy, thereby making it possible to select the optimum current consumption and accuracy for the system.

[0095] (Embodiment 4) 20 is a circuit diagram showing a configuration example of a strong-arm latch type dynamic comparison circuit 2D with input offset storage according to the fourth embodiment. The dynamic comparison circuit 2D of FIG. 20 has the following configuration for the output stage of the dynamic amplifier circuit 1: (1) MOS transistor M 21 ,M 22 ,M 31 ,M 32 a latch circuit 22 that outputs a comparison result voltage of the input differential voltages; (2) A reset switch SW for resetting the latch circuit 22 latm ,SW latp and, (3) A switch SW that separates the latch circuit 22 from the output terminal of the dynamic amplifier circuit 1 during auto-zero. om ,SW op and, It is characterized by the addition of the following.

[0096] The dynamic comparison circuit 2D in FIG. 20 uses a sampling capacitor C sp ,C sm , switch SW azpm ,SW azmp , and load circuit 3 during auto-zero, tail current source I tailIt has a configuration in which the following is added.

[0097] In the dynamic comparison circuit 2D configured as described above, the above components are added to the output stage of the dynamic amplifier circuit 1, but the above components may also be added to the output stage of the dynamic amplifier circuits 1B and 1C according to embodiments 2 and 3. In this case, the offset correction circuit does not require an additional comparator because the configuration in Fig. 20 itself serves as a comparator. Also, instead of the comparator 12 in the dynamic amplifier circuit 1B according to embodiment 2, the voltage input latch circuit 22 in Fig. 20 may be added.

[0098] FIG. 21 is a timing chart of each signal showing the operation of the dynamic comparison circuit 2D of FIG.

[0099] In FIG. 21, during auto-zero, the dynamic amplifier circuit 1 operates in the same sequence as in FIG. 4, and the added latch circuit 22 is disconnected from the output stage of the differential amplifier section 2 when the clock CK is at L level, and its output voltage (comparison result voltage) V olatp ,V olatm is reset to the power supply voltage VDD. Then, the operation shifts to dynamic operation, and in the reset phase, both the differential amplifier unit 2 and the latch circuit 22 are reset so that their output voltages become the power supply voltage VDD. In the next amplification phase, the output voltage V of the differential amplifier unit 2 op ,V om is amplified by the discharge of the differential current and is discharged to a differential voltage (VDD-Vth) (where Vth is a predetermined threshold voltage), the output voltage V of the latch circuit 22 olatp ,V olatm The comparison operation is performed by further amplifying the output amplitude to a rail-to-rail CMOS logic level or higher through a positive feedback operation using the amplifier. In addition, to ensure amplification time so as to increase the gain of the dynamic amplifier circuit 1 during dynamic operation, the rising edge of the clock CK that controls the latch circuit 22 during amplification may be delayed from the control signal DPACK.

[0100] As described above, according to the dynamic comparison circuit 2D of the fourth embodiment, a sampling capacitor C sp ,C sm , switch SW azpm ,SW azmp , and load circuit 3 during auto-zero, tail current source I tail By adding this, the offset can be reduced without increasing the size of the input differential pair. Also, if an offset correction circuit is used, the size of the circuit can be reduced.

[0101] (Embodiment 5) 22 is a circuit diagram showing a configuration example of a double-tail latch type comparator circuit with input offset storage according to embodiment 5. The comparator circuit in FIG. 22 is characterized in that it uses the dynamic amplifier circuit 1 in FIG. 1 as a first-stage preamplifier and adds a voltage input latch circuit 23 in the subsequent stage.

[0102] Here, the dynamic amplifier circuit 1B or 1C of FIG. 10 or FIG. 17 may be used as the first-stage preamplifier. In the offset correction circuit of FIG. 10, the configuration of FIG. 22 itself serves as a comparison circuit, so an additional comparison circuit is not required. Also, a voltage input latch circuit 23 of FIG. 22 may be added instead of the comparator 12 of FIG. 10. Furthermore, the voltage input latch circuit 23 may have any configuration as long as it has a differential input, and the above-mentioned strong arm latch (see Non-Patent Document 5) or a regenerative latch at the subsequent stage of the double tail latch type comparison circuit of Non-Patent Document 1 may be used.

[0103] In the comparison circuit configured as described above, the first-stage preamplifier operates in the same sequence as the dynamic amplifier circuit 1 in FIG. 1, and the added voltage input latch circuit 23 is reset when the clock CK is at the L level. Then, the dynamic operation is started, and in the reset phase, both the dynamic amplifier circuit 1 and the voltage input latch circuit 23 are reset. In the next amplification phase, the output voltage V of the dynamic amplifier circuit 1 is op ,V omis amplified by the discharge of the difference current, and when it is discharged to the operating threshold voltage of the downstream voltage input latch circuit 23, the comparison operation is performed by further amplifying the output amplitude to a rail-to-rail CMOS logic level or higher through the positive feedback operation of the voltage input latch circuit 23. Note that, as in the fourth embodiment, the rising timing of the clock CK that controls the voltage input latch circuit 23 during amplification may be delayed from the control signal DPACK in order to ensure an amplification time so that the gain of the dynamic amplifier circuit 1 during dynamic operation is large.

[0104] As described above, the comparator circuit according to the fifth embodiment can reduce the offset in a widely used double-tail latch type comparator circuit without increasing the size of the input differential pair. Furthermore, even when an offset correction circuit is used, the scale of the circuit can be reduced.

[0105] (Embodiment 6) Fig. 23 is a circuit diagram showing a configuration example of a comparison circuit according to embodiment 6. The comparison circuit in Fig. 23 is characterized in that the dynamic amplifier circuit 1 in Fig. 1 is used as a first-stage preamplifier, and the dynamic comparison circuit 2D in Fig. 20 is connected to the subsequent stage to form a preamplifier by cascading the dynamic amplifier circuits 1 in two stages, and a comparison circuit including a latch circuit 22 in the final stage is configured.

[0106] Although the comparator circuit in Fig. 23 uses the dynamic amplifier circuit 1 in Fig. 1, it may also use the dynamic amplifier circuit 1B or 1C in Fig. 10 or 17. Also, although the dynamic comparator circuit 2D in Fig. 20 is used, it may also use the double tail latch type comparator circuit in Fig. 22.

[0107] FIG. 24 is a timing chart of each signal illustrating the operation of the comparison circuit of FIG. 23. The subscript "1" of the control signals indicates the control signal within the dynamic amplifier circuit 1 of the first-stage preamplifier, and the subscript "2" indicates the control signal within the subsequent-stage dynamic comparison circuit 2D. That is, in the dynamic amplifier circuit 1 of the first-stage preamplifier, the control circuit 10 outputs the auto-zero control signal AZ1, the control signal DPAEN1, and the control signal DPACK1. In the subsequent-stage dynamic comparison circuit 2D, the control circuit 10 of the dynamic amplifier circuit 1 within the dynamic comparison circuit 2D outputs the auto-zero control signal AZ2, the control signal DPAEN2, and the control signal DPACK2. Here, the rising timing of the control signal DPACK2 and the control clock CK of the latch circuit 22 is delayed from the control signal DPACK1 so that the comparison operation does not occur before the amplification operation of the first stage.

[0108] In FIG. 24, first, the auto-zero control signal AZ1 to the dynamic amplifier circuit 1 in the first stage and the auto-zero control signal AZ2 to the dynamic amplifier circuit 1 in the dynamic comparison circuit 2D in the second stage are set to H level to short-circuit the input terminal and inverting output terminal of the internal differential amplifier section 2, the control signals DPAEN1 and DPAEN2 are set to L level, and the control signals DPACK1 and DPACK2 are set to H level to cause the differential amplifier sections 2 in the first and second stages to perform amplification operations. Next, the auto-zero control signal AZ1 is set to L level to cancel the offset of the first stage as in the dynamic amplifier circuit 1 in FIG. 1. Next, the control signal DPAEN1 is set to H level and the control signal DPACK1 is set to L level to reset the differential amplifier section 2 in the first stage. If the dynamic amplifier circuit 1 in the first stage does not perform a reset here, the sampling capacitor C in the second stage sp ,C smHowever, since the gain differs between auto-zero and amplification and the offset is not removed, output offset storage is not performed and the first-stage differential amplifier section 2 is reset. Next, the auto-zero control signal AZ2 is set to L level, which cancels the offset in the subsequent stages as well as the first stage. Next, the control signal DPAEN2 is set to H level and the control signal DPACK2 is set to L level to reset the subsequent-stage differential amplifier section 2. Thereafter, the first-stage amplification operation and the subsequent-stage comparison operation are performed in the same manner as in Figures 1 and 20.

[0109] As described above, the comparison circuit according to the sixth embodiment allows the selection of optimal current consumption and accuracy for the system by switching between low power consumption and low accuracy and high power consumption and high accuracy in the initial and subsequent stages using a control signal. Compared to the dynamic comparison circuit of FIG. 20 according to the fourth embodiment and the double-tail latch comparison circuit of FIG. 22 according to the fifth embodiment, the comparison circuit according to the sixth embodiment can improve accuracy by cascading auto-zero in the initial and subsequent stages. Note that, while the comparison circuit of FIG. 23 is added to the output stage of the dynamic amplifier circuit 1 as a comparison circuit, any one of the dynamic amplifier circuits 1, 1B, and 1C according to the first to third embodiments may be cascaded to the output of the dynamic amplifier circuit 1 in place of the comparison circuit to operate as an amplifier.

[0110] (Embodiment 7) 25 is a circuit diagram showing an example of the configuration of a dynamic amplifier circuit according to a seventh embodiment. The dynamic amplifier circuit of FIG. 25 is characterized by being configured by adding a preamplifier circuit with input offset storage to the front stage of the dynamic amplifier circuit of FIG. 1. Here, the preamplifier circuit includes a known differential amplifier 1P (which, unlike the dynamic amplifier circuit 1 of FIG. 1, does not have an operation changeover switch using the control signals DPAEN and DPACK, but has an auto-zero control signal AZP), a sampling capacitor C sp ,C sm and amplifier input / output short-circuit switch SW azpm ,SW azmpThe control circuit 10D generates an auto-zero control signal AZP to control the auto-zero timing of the added preamplifier.

[0111] In the dynamic amplifier circuit configured as described above, first, the auto-zero control signal AZP of the differential amplifier 1P (preamplifier) ​​and the auto-zero control signal AZ of the dynamic amplifier circuit 1 in the subsequent stage are set to H level to short-circuit the input terminal and its inverted output terminal of each amplifier. Next, the control signal DPAEN of the dynamic amplifier circuit 1 in the subsequent stage is set to L level and the control signal DPACK is set to H level to cause the dynamic amplifier circuit 1 in the subsequent stage to perform amplification. Next, the auto-zero control signal AZP of the differential amplifier 1P (preamplifier) ​​is set to L level to cancel the offset of the differential amplifier 1P by input offset storage. Furthermore, the auto-zero control signal AZ of the dynamic amplifier circuit 1 in the subsequent stage is set to L level to cancel the capacitor C sp and C sm The remaining offset of differential amplifier 1P stored in is removed by output offset storage, and at the same time, input offset storage is performed in the subsequent stage, canceling the offset of the subsequent stage. After that, differential amplifier 1P, which is the first-stage preamplifier, continues its amplification operation, and dynamic amplifier circuit 1 performs an amplification or comparison operation after being reset as in Figure 4.

[0112] As described above, according to the seventh embodiment, the remaining load offset in the dynamic amplifier circuit 1 of Fig. 1 can be reduced to 1 / gain in input conversion by the differential amplifier 1P, which is the preamplifier in the preceding stage, thereby eliminating the need for offset correction in the dynamic amplifier circuit 1 in the following stage. Furthermore, compared to when differential amplifiers are cascaded, current consumption can be reduced by dynamically operating the amplifier in the following stage.

[0113] Although the dynamic amplifier circuit of FIG. 25 uses the dynamic amplifier circuit 1 of FIG. 1, the dynamic amplifier circuit 1B or 1C of FIG. 10 or FIG. 17, or the comparison circuit of FIG. 20, FIG. 22 or FIG. 23 may also be used. When the latter comparison circuit is used, the entire circuit becomes a comparison circuit. Also, a preamplifier circuit with output offset storage may be used instead of the preamplifier circuit with input offset storage in the first stage, and the capacitor C sp ,C sm and amplifier input / output short-circuit switch SW azpm ,SW azmp may be used both as an offset storage capacitor and an offset sampling switch in the output section of the preamplifier circuit with output offset storage.

[0114] (Embodiment 8) 26 is a circuit diagram showing an example of the configuration of a comparison circuit according to the eighth embodiment. The comparison circuit in FIG. 26 includes the following components in the subsequent stage of the dynamic amplifier circuit 1 in FIG. (1) Add a differential amplifier 1PA, which is a preamplifier with input offset storage, (2) A voltage input latch circuit 23 that operates in accordance with a clock CK is connected to the rear stage. The differences will be explained below.

[0115] In FIG. 26, the differential amplifier 1PA with input offset storage is a differential amplifier 1P in the previous stage of FIG. 25, which is provided with a low power consumption mode changeover switch SW lpmpm ,SW lpmmp Equipped with a selector switch SW lpmpm ,SW lpmmp By turning on this, the second stage amplifier is turned off and bypassed in low power consumption mode. Also, in the differential amplifier 1PA, in order to clarify that the elements and input voltage are different from those of the other stages, C sp2 ,C sm2 ,SW azpm2 ,SW azmp2 ,AZ2,V ip2 ,V im2The subscript "2" is added. Here, the control signal LPM is a signal that enables the low power consumption mode. When it is at H level, it turns off the operation of the differential amplifier 1PA and sets the output terminal to high impedance, and the switch SW lpmpm ,SW lpmmp By turning on the control signal AZ2, the second-stage differential amplifier 1PA is bypassed. The control circuit 10E also generates the control signal AZ2 and the control signal LPM to control the preamplifier 1PA with the added input offset storage.

[0116] Fig. 27 is a timing chart of each signal showing the operation of the comparison circuit in normal mode (LPM=L) in Fig. 26. Here, the suffix "1" is added to the auto-zero control signal AZ to clarify that it is a control signal within the dynamic amplifier circuit 1 in the first stage.

[0117] In FIG. 27, the control signal DPAEN of the first-stage dynamic amplifier circuit 1 is set to L level, and the control signal DPACK is fixed to H level, so that the amplifier operates as a normal amplifier with auto-zero function without dynamic operation. First, the auto-zero control signals AZ1 and AZ2 are set to H level, shorting the input terminal and inverting output terminal of each amplifier. Next, the auto-zero control signal AZ1 is set to L level, canceling the offset of the first-stage dynamic amplifier circuit 1. Next, the auto-zero control signal AZ2 is set to L level, eliminating any offset remaining in the first-stage dynamic amplifier circuit 1, and canceling the offset of the second-stage differential amplifier 1PA as in the first stage. Thereafter, the voltage input latch circuit 23 in the subsequent stage performs reset and comparison operations in response to the clock CK.

[0118] FIG. 28 is a timing chart of each signal showing the operation of the comparison circuit of FIG. 26 in the low-power operation mode (LPM=H).

[0119] 28, in the low power consumption mode, the output terminal of the second-stage differential amplifier 1PA is in a high-impedance state, turning off its operation and bypassing the differential amplifier 1PA, as compared with FIG. 27. The operation of other parts is the same as that of the comparison circuit of FIG. 22 of the fifth embodiment.

[0120] The comparator circuit according to the eighth embodiment configured as described above can selectively switch between a first operation mode with low power consumption and low accuracy and a second operation mode with high power consumption and high accuracy using the control signal LPM, thereby enabling the circuit system to select and achieve optimal current consumption and accuracy. Furthermore, since the input impedance does not change significantly when the operation mode is switched, differences in signal transfer functions can be reduced. Furthermore, the clamp voltage in the CDS does not change when the mode is switched.

[0121] (Embodiment 9) 30 is a circuit diagram showing a configuration example of a successive approximation type AD conversion device according to embodiment 9. The successive approximation type AD conversion device of FIG. (1) A comparison circuit 33 according to the fourth embodiment; (2) a successive approximation control logic circuit (SAR control logic circuit) 34 connected to the downstream of the comparison circuit 33; (3) Sampling capacitor C of the first stage of the comparison circuit 33 sm a capacitive DA conversion circuit 40 replacing the The device is configured to include:

[0122] Here, the capacitance DA conversion circuit 40 may be of a charge scaling type as in Non-Patent Document 5, or may be of another type. When the capacitance DA conversion circuit 40 is of a charge scaling type, a plurality of capacitors C o ~C n and each capacitor C0 to C n Reference voltage V refp or V refm Multiple n+1 switches SW0 to SW n and switches SW0 to SW n and a control circuit 10F that controls the reference voltage V refp ,V refm is V refp >V refm is.

[0123] In Figure 30, the input voltage V pas a fixed potential V r is input, and each input terminal of the differential amplifier section 2 and each inverted output terminal thereof are shorted and then opened, thereby sp A fixed potential V is input to one end of r and sampling capacitor C sp The clamp voltage V, which includes the offset error voltage of the differential amplifier 2, is applied to the other end of clamp and the capacitance DA conversion circuit 40. o ~C n The control circuit 10F supplies a reference voltage V refp and the output voltage V of the capacitive DA conversion circuit 40 im The clamp voltage V, which includes the offset error voltage of the differential amplifier part 2, is clamp and the plurality of capacitors C o ~C n The clamp voltage V clamp is the output voltage including the offset error voltage when each input terminal and each inverting output terminal of the differential amplifier section 2 are shorted during auto-zero. Also, the fixed potential V r The pixel reset voltage V rst and common voltage V cm Alternatively, the control circuit 10F may be set to o ~C n The voltage to be set is determined by the input range of the AD conversion device. o ~C n Each reference voltage V refp ,V refm Either of the above may be set.

[0124] Next, the input voltage V p as the signal voltage V sig is input and the comparator circuit 33 is reset. After that, the control circuit 10F outputs the DA conversion voltage V dac is the voltage (V refp -V refm) / 2, and the input voltage V ip ,V im are V clamp +V sig -V r ,V clamp -V dac Here, the DA conversion voltage V dac is the reference voltage V controlled by the control circuit 10F. refp ,V refm Next, the comparator circuit 33 compares the input voltage V of the differential amplifier unit 2 with the ip ,V im Then, the SAR control logic circuit 34 converts the comparison reference voltage of the comparison circuit 33 for the next bit conversion into the DA conversion voltage V of the capacitive DA conversion circuit 40 via the control circuit 10F based on the conversion result of the MSB. dac voltage (V refp -V refm ) / 2±(V refp -V refm ) / 4. Thereafter, the reset operation, comparison operation, and DA conversion voltage V of the capacitive DA conversion circuit 40 are performed in the same manner up to the least significant bit LSB. dac The input voltage V of the differential amplifier 2 is updated. ip and V im That is, the DA conversion voltage V of the capacitive DA conversion circuit 40 dac is the fixed potential V r and signal voltage V sig The CDS input voltage V in =V r -V sig The SAR control logic circuit 34 performs AD conversion processing by sequentially performing binary search based on the comparison result so that the signal is equal to the signal.

[0125] As described above, according to the AD conversion device of the ninth embodiment, the characteristic trade-off of the input differential pair of the comparison circuit 33 is alleviated, allowing for a smaller size and a smaller input capacitance, which in turn reduces signal attenuation at the input terminal of the comparison circuit 33 and kickback noise of the comparison circuit 33. Furthermore, similar to the eighth embodiment, by selectively switching the operation mode of the comparison circuit 33 depending on the desired accuracy, it is possible to select the optimum current consumption and accuracy for the circuit system. If high accuracy is not required, the offset correction circuit required for a successive approximation type AD conversion circuit using a dynamic comparison circuit can be eliminated.

[0126] In the above-described embodiment 9, the comparison circuit 33 according to embodiment 4 may be replaced with the comparison circuit according to embodiment 5, the comparison circuit according to embodiment 6, the comparison circuit according to a modified example of embodiment 7, or the comparison circuit according to embodiment 8.

[0127] (Embodiment 10) Fig. 31 is a circuit diagram showing an example of the configuration of a successive approximation type AD conversion apparatus according to embodiment 10. The successive approximation type AD conversion apparatus of Fig. 31 differs from the successive approximation type AD conversion apparatus of Fig. 30 in the following points. (1) The input voltage Vin is connected to the capacitive DA conversion circuit 41 through the switches SW0 to SW n Configure it to input via (2) Input voltage V of comparator circuit 33 p to the common voltage V cm was changed to. The differences will be explained below.

[0128] In FIG. 31, the input terminals of the differential amplifier section 2 and the inverting output terminals thereof are short-circuited and then opened, respectively, thereby sp The common voltage V is input to one end of cm and sampling capacitor C sp The clamp voltage V, which includes the offset error voltage of the differential amplifier 2, is applied to the other end of clamp and simultaneously sample the input voltage V inThe switches SW0 to SW n and the capacitance DA conversion circuit 41 includes a plurality of capacitors C o ~C n The input voltage V in and the output voltage V of the capacitance DA conversion circuit 41. im The clamp voltage V, which includes the offset error voltage of the differential amplifier part 2, is clamp and the plurality of capacitors C o ~C n simultaneously sampled, auto-zeroed, and input signal V in Sampling is performed simultaneously.

[0129] Next, the control circuit 10G controls the plurality of capacitors C o ~C n are switches SW0 to SW n By controlling the input voltage V in After that, the control circuit 10G controls the DA conversion voltage V dac is the voltage (V refp -V refm ) / 2, and the input voltage V ip , V im are V clamp ,V clamp -V in +V dac After auto-zero, the input common voltage V cm at another fixed potential V shift connected to the input voltage V ip V clamp -V cm +V shift The input range of the AD conversion device may be changed by changing the comparison voltage as follows. After that, the comparison operation and the update of the capacitive DA conversion circuit 41 are performed in the same manner as in the ninth embodiment, and the input voltage V in is the DA conversion voltage V dac The SAR control logic circuit 34 performs AD conversion processing by sequentially performing binary search based on the comparison result so that the signal is equal to the signal.

[0130] As described above, in the AD conversion device according to the tenth embodiment, the input voltage and the input voltage of the reference voltage of the DA conversion circuit 41 are the same, so that the transfer functions up to each input terminal of the comparison circuit 33 are equal, thereby making it possible to reduce gain errors in the AD conversion device.

[0131] (Embodiment 11) Fig. 32 is a circuit diagram showing an example of the configuration of a successive approximation type AD conversion device according to embodiment 11. The successive approximation type AD conversion device in Fig. 32 differs from the successive approximation type AD conversion device in Fig. 31 in the following points. (1) In the successive approximation type AD converter shown in FIG. 31, the sampling capacitor C sp The input circuit on the input side is replaced with a capacitive DA conversion circuit 41, thereby making it differential. The differences will be explained below.

[0132] In FIG. 32, as in the tenth embodiment, the input voltage V inm ,V inp In each of the capacitance DA conversion circuits 41 and the comparison circuit 33 connected to the inm ,V inp and each capacitance DA conversion circuit 41 is sampled at the same time, and the input voltage V inm ,V inp Then, the DA conversion voltages V of the respective capacitive DA conversion circuits 41 are dacp ,V dacm is the voltage (V refp -V refm ) / 2, and the input voltage V ip , V im are V clamp -V inm +V dacp ,V clamp -V inp +V dacm Thereafter, the comparison operation and updating of each capacitive DA conversion circuit 41 are performed in the same manner as in the tenth embodiment, and V inm -V dacp and V inp -V dacm is equal to the differential input voltage V inp -Vinm is the differential output V of each capacitive DA conversion circuit 41 dacp -V dacm The SAR control logic circuit 34 performs AD conversion processing by sequentially performing binary search based on the comparison result so that the signal is equal to the signal.

[0133] As described above, the successive approximation type AD conversion device according to the eleventh embodiment can eliminate common mode signals by differentiating the circuit configuration, thereby increasing resistance to disturbances caused by fluctuations in the power supply voltage VDD, ground, reference voltage, etc. Furthermore, the input signal voltage at each input terminal of the comparator circuit 33 is doubled by differentiation, thereby increasing the signal-to-noise ratio (SNR).

[0134] (Embodiment 12) Fig. 33 is a circuit diagram showing an example of the configuration of an AD conversion apparatus according to embodiment 12. The AD conversion apparatus in Fig. 33 differs from the successive approximation type AD conversion apparatus in Fig. 30 in the following points. (1) A control logic circuit 35 that replaces the successive approximation type control logic circuit 34; (2) Sampling capacitor C of the comparison circuit 33 instead of the capacitance DA conversion circuit 40 sm and, (3) Input voltage V of comparator circuit 33 m a DA conversion circuit 42 provided in the front stage of the The device is configured to include: The differences will be explained below.

[0135] In Figure 33, (1) The plurality of capacitors C in the capacitance DA conversion circuit 40 of FIG. o ~C n Instead, the sampling capacitor C sm Use (2) The output voltage of the capacitive DA conversion circuit 42 is used instead of the DA conversion voltage of the capacitive DA conversion circuit 40, (3) AD conversion is performed in the same manner as in the ninth embodiment shown in FIG. The search algorithm may be a binary search as in the ninth embodiment, or may be a search by incrementing and decrementing from the minimum and maximum values.

[0136] The AD conversion device configured as above can apply a DA conversion circuit of another type instead of the capacitive DA conversion circuit, and has the same effects as those of the ninth embodiment shown in FIG.

[0137] In the above-described embodiment 12, the comparison circuit 33 according to embodiment 4 may be replaced with the comparison circuit according to embodiment 5, the comparison circuit according to embodiment 6, the comparison circuit according to a modified example of embodiment 7, or the comparison circuit according to embodiment 8.

[0138] (Embodiment 13) Fig. 34 is a circuit diagram showing a configuration example of an AD conversion device according to embodiment 13. The AD conversion device in Fig. 34 differs from the AD conversion device in Fig. 31 in the following points. (1) A control logic circuit 35 that replaces the successive approximation type control logic circuit 34; (2) The first stage sampling capacitor C of the comparison circuit 33, which replaces the capacitance DA conversion circuit 41 sm and a DA conversion circuit 42; (3) Input voltage V of comparator circuit 33 m On the side, the control signal SSW in is controlled according to the input voltage V m , the output voltage V of the DA conversion circuit 42 dac and the input voltage V in Switch SW to selectively switch between in and, The device is configured to include: The differences will be explained below.

[0139] In Figure 34, (1) The plurality of capacitors C o ~C n , switches SW0~SW n Instead of these, sampling capacitors C sm and switch SW in Use (2) DA conversion voltage V of the capacitive DA conversion circuit 41 dac Instead, the output voltage V of the DA conversion circuit 42 dacUse (3) AD conversion is performed in the same manner as in the tenth embodiment shown in FIG. The search algorithm may be a binary search as in the tenth embodiment, or may be a search by incrementing and decrementing from the minimum and maximum values.

[0140] The AD conversion device configured as above can apply a DA conversion circuit of another type instead of the capacitive DA conversion circuit, and has the same effects as those of the tenth embodiment shown in FIG.

[0141] In the above-described embodiment 13, the comparison circuit 33 according to embodiment 4 may be replaced with the comparison circuit according to embodiment 5, the comparison circuit according to embodiment 6, the comparison circuit according to a modified example of embodiment 7, or the comparison circuit according to embodiment 8.

[0142] (Embodiment 14) 35 is a circuit diagram showing a configuration example of an AD conversion apparatus according to the fourteenth embodiment. Compared with the AD conversion apparatus according to the eleventh embodiment shown in FIG. 32, the AD conversion apparatus shown in FIG. 35 has the following features: (1) A control logic circuit 35 that replaces the successive approximation type control logic circuit 34; (2) Input voltage V inm The sampling capacitance C of the comparison circuit 33 is used instead of the capacitance DA conversion circuit 41 on the side. sp and a DA conversion circuit 42; (3) Input voltage V inp The sampling capacitance C of the comparison circuit 33 is used instead of the capacitance DA conversion circuit 41 on the side. sm and a DA conversion circuit 42; (4) Input voltage V of comparator circuit 33 p On the side, the control signal SSW inm is controlled according to the input voltage V p As the input voltage V p The output voltage V of the DA conversion circuit 42 on the dacp and the input voltage V inm Switch SW to selectively switch between inm and, (4) Input voltage V of comparator circuit 33 m On the side, the control signal SSW inpis controlled according to the input voltage V m As the input voltage V m The output voltage V of the DA conversion circuit 42 on the dacm and the input voltage V inp Switch SW to selectively switch between inp and, The device is configured to include: The differences will be explained below.

[0143] In Figure 35, (1) Input voltage V in Figure 32 inm The plurality of capacitors C o ~C n , switches SW0~SW n Instead of these, sampling capacitors C sp , switch SW inm Use (2) Input voltage V inp The plurality of capacitors C o ~C n , switches SW0~SW n Instead of these, sampling capacitors C sm , switch SW inp Use (3) DA conversion voltage V of each capacitive DA conversion circuit 41 dacp、 V dacm Instead of the output voltage V dacp、 V dacm Use (4) AD conversion is performed in the same manner as in the eleventh embodiment shown in FIG. The search algorithm may be a binary search as in the tenth embodiment, or may be a search by incrementing and decrementing from the minimum and maximum values.

[0144] The AD conversion device configured as above can apply a DA conversion circuit of another type instead of the capacitive DA conversion circuit, and has the same effects as those of the eleventh embodiment shown in FIG.

[0145] In the above-described embodiment 14, the comparison circuit 33 according to embodiment 4 may be replaced with the comparison circuit according to embodiment 5, the comparison circuit according to embodiment 6, the comparison circuit according to a modified example of embodiment 7, or the comparison circuit according to embodiment 8.

[0146] (Variation) In the above embodiment, MOS transistors are used, but the present invention is not limited to this, and other types of transistors such as bipolar transistors may also be used. [Industrial Applicability]

[0147] As described above in detail, the amplifier device according to the present invention can provide an amplifier device with lower current consumption and lower offset than conventional techniques, a comparison device including the amplifier device, and an AD conversion device including the comparison device. The amplifier device is suitable for semiconductor devices equipped with multi-channel AD converters such as column-parallel AD converters. [Explanation of symbols]

[0148] 1 Dynamic amplifier circuit 1P,1PA differential amplifier 2, 2A~2C Differential amplifier section 2D dynamic comparison circuit 3,3A load circuit 4 Adder 5 Offset adjustment circuit 10, 10A~10G control circuit 11. Memory 12 Comparators 22 Latch circuit 23 Voltage input latch circuit 33 Comparison circuit 34 SAR control logic circuit 35 Control Logic Circuit 40 Capacitive DA conversion circuit 41 Capacitive DA conversion circuit 42 DA conversion circuit C sp ,C sm ,C LP ,C LM,C s ,C sp2 ,C sm2 ,C0~C n , capacitor I tail Tail Current Source M1~M 32 MOS transistor SW azpm ,SW azmp ,SW load1 ,SW load2 ,SW tail ,SW in ,SW inp ,SW inm ,SW inp ,SW inm ,SW ipmp ,SW ipmm ,SW iptail ,SW latp ,SW latm ,SW om ,SW op ,SW azpm2 ,SW azmp2 ,SW lpmpm ,SW lpmmp ,SW0~SW n switch

Claims

1. a differential amplifier having first and second input terminals and first and second inverting output terminals; first and second sampling capacitors connected to the first and second input terminals of the differential amplifier, respectively; first and second switches for short-circuiting the first and second input terminals and the first and second inverting output terminals of the differential amplifier, respectively; and a control circuit for controlling the operation of the amplifier device, The differential amplifier an input differential pair including a pair of transistors; a current source; a third switch inserted between the source of the input differential pair and the current source; first and second output capacitors connected to the first and second inverting output terminals of the differential amplifier, respectively; The amplifier device comprises: a load circuit connected to the first and second inverting output terminals of the differential amplifier; fourth and fifth switches for connecting the first and second inverting output terminals of the differential amplifier to a predetermined fixed potential; sixth and seventh switches for connecting or disconnecting the load circuit to the first and second inverting output terminals of the differential amplifier; The control circuit (1) a sampling operation that cancels an error of the differential amplifier by controlling the third switch and the sixth and seventh switches to connect the load circuit and the current source to the differential amplifier, controlling the first and second switches to short-circuit and then open the first and second input terminals and the first and second inverting output terminals of the differential amplifier, and holding the first and second input voltages and an error of the differential amplifier in the first and second sampling capacitors; (2) after the sampling operation, a reset operation of controlling the third switch and the sixth and seventh switches to disconnect the load circuit from the current source, and controlling the fourth and fifth switches to connect the first and second inverting output terminals to a fixed potential; (3) after the reset operation, controlling the third switch to connect the differential amplifier to the current source, setting the first and second inverting output terminals of the differential amplifier to high impedance, and integrating the first and second output capacitors of the differential amplifier by either charging or discharging according to the first and second input voltages of the differential amplifier, thereby amplifying the difference between the second input voltage and the first input voltage after the sampling operation; An amplification device that performs the above.

2. The load circuit further comprises a variable resistance circuit.

2. The amplifier device according to claim 1.

3. The amplification device further comprises: a comparator that compares first and second inverted output voltages from the first and second inverted output terminals of the differential amplifier and outputs a comparison result signal; the control circuit adjusts the variable resistor circuit based on the comparison result signal of the comparator to calibrate the offset voltage of the differential amplifier and output a calibrated value; The amplification device further comprises: a storage device that stores a calibration value from the control circuit and reads out the calibration value after the calibration; 3. The amplifier according to claim 2.

4. After the operations from the sampling operation to the integration, the control circuit (1) resetting the differential amplifier during the sampling operation, and amplifying the differential amplifier from the sampling operation to integration; (2) the sampling operation and an amplifying operation of amplifying the first and second input voltages by connecting the load circuit and the current source after the sampling operation; Switch to at least one of the following actions: An amplifier device according to any one of claims 1 to 3.

5. An amplifier device according to any one of claims 1 to 3; a differential latch circuit connected to the first and second inverting output terminals of the differential amplifier, for comparing first and second inverting output voltages from the first and second inverting output terminals of the differential amplifier and outputting a comparison result voltage; A comparison device comprising:

6. After the operations from the sampling operation to the integration, the control circuit (1) resetting the differential amplifier during the sampling operation, and amplifying the differential amplifier from the sampling operation to integration; (2) the sampling operation and an amplifying operation of amplifying the first and second input voltages by connecting the load circuit and the current source after the sampling operation; Switch to at least one of the following actions: The comparison device according to claim 5 .

7. An amplifier device according to any one of claims 1 to 3; a comparison device according to claim 5 connected to a stage subsequent to the amplification device; A comparison device comprising:

8. An amplifier device according to any one of claims 1 to 3; another amplifier device, which is the amplifier device according to any one of claims 1 to 3, connected to a downstream stage of the amplifier device; An amplification system comprising:

9. An amplifier device according to any one of claims 1 to 3; a preamplifier connected in front of the amplifier; An amplification system comprising:

10. (Embodiment 7) a comparison device according to claim 5; a preamplifier connected in front of the amplifier; A comparison device comprising:

11. a first amplifier device which is the amplifier device according to any one of claims 1 to 3; a second amplifying device connected to a subsequent stage of the first amplifying device, the second amplifying device including a differential amplifier; a differential latch circuit connected to the first and second inverting output terminals of the differential amplifier of the second amplifying device, for comparing first and second inverting output voltages from the first and second inverting output terminals of the differential amplifier and outputting a comparison result voltage; Equipped with the control circuit further includes a switch means for switching whether or not the second amplifying device is bypassed; A comparison device.

12. a comparison device according to claim 5; a capacitive DA conversion circuit provided in place of the second sampling capacitor, which converts a digital input signal into a predetermined analog output voltage and outputs the analog output voltage to a second input terminal of the differential amplifier; an AD conversion device comprising a successive approximation control logic circuit that generates the digital input signal for controlling the capacitive DA conversion circuit based on a comparison result voltage of the comparison device, the AD conversion device holds an input voltage in the first sampling capacitor; the comparison device compares the input voltages of the differential amplifier and outputs a comparison result voltage; AD conversion device.

13. a comparison device according to claim 5; a capacitive DA conversion circuit provided in place of the second sampling capacitor, which holds a potential difference between a second inverted output voltage of the differential amplifier during the sampling operation and an input voltage as a hold voltage, converts a digital input signal into a predetermined analog output voltage based on the input voltage, adds the hold voltage and the analog output voltage, and outputs the sum to a second input terminal of the differential amplifier; an AD conversion device comprising a successive approximation control logic circuit that generates the digital input signal for controlling the capacitive DA conversion circuit based on a comparison result voltage of the comparison device, the AD conversion device holds a first inverted output voltage of the differential amplifier in the first sampling capacitor during the sampling operation; the comparator compares the input voltages of the differential amplifier and outputs a comparison result voltage; AD conversion device.

14. a comparison device according to claim 5; first and second capacitive DA conversion circuits, which, instead of the first and second sampling capacitors, hold potential differences between first and second inverted output voltages of the differential amplifier and first and second input voltages in the sampling operation as first and second holding voltages, convert the first and second digital input signals into predetermined first and second analog voltages based on the input voltages, add the first and second analog voltages and the first and second holding voltages, and output the sums to the first and second input terminals of the differential amplifier, respectively; a successive approximation control logic circuit that generates the first and second digital input signals for controlling the first and second capacitive DA converter circuits based on a comparison result voltage of the comparator, the comparison device compares the input voltages of the differential amplifier and outputs a comparison result voltage; AD conversion device.

15. a comparison device according to claim 5; a DA conversion circuit that converts a digital input signal into a predetermined analog output voltage and outputs the analog output voltage to the comparison device; a control logic circuit that generates the digital input signal for controlling the DA conversion circuit based on a comparison result voltage of the comparison device; the comparator compares an input voltage with the analog output voltage of the DA converter circuit and outputs a comparison result voltage; AD conversion device.

16. a comparison device according to claim 5; a DA conversion circuit that converts a digital input signal into a predetermined analog output voltage and outputs the analog output voltage to the comparison device; an AD conversion device comprising: a control logic circuit that generates the digital input signal for controlling the DA conversion circuit based on a comparison result voltage of the comparison device; The AD conversion device holding a first inverted output voltage of the differential amplifier in the sampling operation in the first sampling capacitor; a potential difference between a second inverted output voltage of the differential amplifier and an input voltage during the sampling operation is held in the second sampling capacitor; the comparison device compares the input voltages of the differential amplifier and outputs a comparison result voltage; AD conversion device.

17. a comparison device according to claim 5; first and second DA conversion circuits that convert first and second digital input signals into predetermined first and second analog output voltages, respectively, and output the analog output voltages to the comparison device; a control logic circuit that generates the first and second digital input signals to control the first and second DA conversion circuits based on the first and second comparison result voltages of the comparison device, The AD conversion device a potential difference between a first inverted output voltage of the differential amplifier and a first input voltage during the sampling operation is held in the first sampling capacitor; a potential difference between a second inverted output voltage of the differential amplifier and a second input voltage during the sampling operation is held in the second sampling capacitor; the comparator compares the input voltages of the differential amplifier and outputs a comparison result voltage; AD conversion device.

18. a differential amplifier having first and second input terminals and first and second inverting output terminals; first and second sampling capacitors connected to the first and second input terminals of the differential amplifier, respectively; first and second switches for short-circuiting the first and second input terminals and the first and second inverting output terminals of the differential amplifier, respectively; and a control circuit for controlling the operation of the amplifier device, The differential amplifier an input differential pair including a pair of transistors; a current source; a third switch inserted between the source of the input differential pair and the current source; first and second output capacitors connected to the first and second inverting output terminals of the differential amplifier, respectively; The amplifier device comprises: a load circuit connected to the first and second inverting output terminals of the differential amplifier; fourth and fifth switches for connecting the first and second inverting output terminals of the differential amplifier to a predetermined fixed potential; sixth and seventh switches for connecting or disconnecting the load circuit to the first and second inverting output terminals of the differential amplifier; The control circuit (1) controlling the third switch and the sixth and seventh switches to connect the load circuit and the current source to the differential amplifier, controlling the first and second switches to short-circuit and then open the first and second input terminals and the first and second inverting output terminals of the differential amplifier, and holding the first and second input voltages and an error of the differential amplifier in the first and second sampling capacitors, thereby performing a sampling operation to cancel out the error of the differential amplifier; (2) after the sampling operation, executing a reset operation of controlling the third switch and the sixth and seventh switches to disconnect the load circuit from the current source, and controlling the fourth and fifth switches to connect the first and second inverting output terminals to a fixed potential; (3) after the reset operation, controlling the third switch to connect the differential amplifier to the current source, setting the first and second inverting output terminals of the differential amplifier to high impedance, and integrating the first and second output capacitors of the differential amplifier by either charging or discharging according to the first and second input voltages of the differential amplifier, thereby performing an amplification operation to amplify the difference between the second input voltage and the first input voltage after the sampling operation; An amplification method comprising:

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