Array substrate and display device

Abstract

To prevent deterioration in characteristics of a transistor.SOLUTION: The array substrate 21 includes the transistor 35 having the first electrode 35A, the semiconductor element 35A disposed to overlap the first electrode 35D, the second electrode 35D connected to the semiconductor element 35B, and the third electrode 35D connected to the semiconductor element 35C, the first insulating film 29 provided on the upper layer side of the first electrode 35A and on the lower layer side of the semiconductor element 35D, the second insulating film 30 provided on the upper layer side of the second electrode and the third electrode, and the light reflection portion 38 provided on the upper layer side of the second insulating film 30. 35B 35C, the second insulating film 30 is provided with the first recess 35A at a position that does not overlap the first electrode 35D and the semiconductor element 30A, the light-reflecting part 38 includes the overlapping portion 35A that overlaps the first electrode 35D and the semiconductor element 38A and the non-overlapping portion 35A that does not overlap the first electrode 35D and the semiconductor element 38B, and the non-overlapping portion includes the first filled part 39 that fills the first recess. 38B 30A.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an array substrate and a display device whose characteristics are less likely to deteriorate. [Background technology]

[0002] Conventionally, one example of a transistor provided in a display device is known, which is described in Patent Document 1 below. The transistor described in Patent Document 1 includes a first gate electrode, a second electrode facing the first gate electrode, an oxide semiconductor layer provided between the first gate electrode and the second gate electrode, and a source electrode and a drain electrode connected to the oxide semiconductor layer, respectively, the oxide semiconductor layer having a channel formation region, a source region, and a drain region, and light irradiation regions whose resistance is reduced by irradiation with light are provided between the channel formation region and the source region and between the channel formation region and the drain region, respectively, and the first gate electrode and the second gate electrode have different lengths. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-28988 Summary of the Invention [Problem to be solved by the invention]

[0004] In the transistor described in Patent Document 1, if a positive charge is repeatedly applied to the gate electrode, the threshold voltage of the transistor will shift in the positive direction over time, and there is a concern that the characteristics will deteriorate.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to make transistor characteristics less susceptible to degradation. [Means for solving the problem]

[0006] (1) An array substrate related to the technology described in this specification includes a transistor having a first electrode, a semiconductor portion provided above the first electrode and overlapping the first electrode, a second electrode provided above the semiconductor portion and connected to the semiconductor portion, and a third electrode provided above the semiconductor portion, spaced apart in a first direction from the second electrode and connected to the semiconductor portion; a first insulating film provided above the first electrode and below the semiconductor portion, a second insulating film provided above the second electrode and the third electrode, and a light reflecting portion provided above the second insulating film, wherein the second insulating film has a first recess at a position where it does not overlap the first electrode and the semiconductor portion, and the light reflecting portion has an overlapping portion overlapping the first electrode and the semiconductor portion and a non-overlapping portion connected to the overlapping portion and not overlapping the first electrode and the semiconductor portion, and the non-overlapping portion includes a first filling portion that fills the first recess.

[0007] (2) In addition to (1), the array substrate may be configured such that the second insulating film is arranged such that the first recess is spaced apart in the first direction from at least one of the second electrode and the third electrode, the non-overlapping portion includes a first non-overlapping portion arranged alongside the overlapping portion along the first direction, and the first filling portion is included in the first non-overlapping portion.

[0008] (3) In addition to (2), the array substrate may be configured such that the second insulating film is arranged in pairs so that the first recess is arranged at a position spaced apart from the second electrode in the first direction and at a position spaced apart from the third electrode in the first direction, the first non-overlapping portions are arranged in pairs so as to sandwich the overlapping portion in the first direction, and the first filling portion is included in each of the paired first non-overlapping portions.

[0009] (4) In addition to (2) or (3), the array substrate may be configured such that the second insulating film is arranged so that the first recess extends along a second direction that is along the main surface of the first electrode and intersects with the first direction, and the first filling portion is arranged so that it extends along the second direction.

[0010] (5) In addition to the above-mentioned array substrate (4), the second electrode and the third electrode may each extend along the second direction and be drawn out to the outside of the semiconductor portion.

[0011] (6) In addition to any one of (2) to (5), the array substrate may be configured such that the semiconductor portion is shorter in the first direction than the first electrode.

[0012] (7) In addition to any one of (2) to (6) above, the array substrate may also include a second non-overlapping portion arranged in parallel with the overlapping portion along a main surface of the first electrode and a second direction intersecting the first direction.

[0013] (8) In addition to the above (7), the array substrate may be configured such that the semiconductor portion is shorter in the second direction than the first electrode.

[0014] (9) In addition to any one of (2) to (8) above, the array substrate may be arranged so that the second electrode and the third electrode do not overlap with both ends of the semiconductor portion in the first direction.

[0015] (10) In addition to any one of (1) to (9), the array substrate may have the first recess penetrating the second insulating film, the first insulating film has a second recess communicating with the first recess at a position overlapping the first recess, and the non-overlapping portion includes a second filling portion connected to the first filling portion and filled into the second recess.

[0016] (11) A display device relating to the technology described in this specification comprises an array substrate described in any one of (1) to (10) above, a display area for displaying an image, and a non-display area in which the image is not displayed, wherein a first wiring is arranged in the display area of ​​the array substrate, and a circuit unit connected to the first wiring is arranged in the non-display area of ​​the array substrate, and the transistor is included in the circuit unit. [Effects of the Invention]

[0017] According to the technology described in this specification, it is possible to make the characteristics of a transistor less susceptible to degradation. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a plan view of a liquid crystal panel, a driver, and a flexible substrate according to a first embodiment; [Figure 2] 1 is a cross-sectional view of a liquid crystal panel, a driver, and a flexible substrate according to Embodiment 1. [Figure 3] 1 is a plan view showing a pixel array of a liquid crystal panel according to a first embodiment; [Figure 4] 1 is a cross-sectional view of a pixel TFT provided in a display area of ​​an array substrate that constitutes a liquid crystal panel according to Embodiment 1. [Figure 5] 1 is a plan view of a non-pixel TFT included in a circuit portion provided in a non-display area of ​​an array substrate according to Embodiment 1. FIG. [Figure 6] 6 is a cross-sectional view of the array substrate according to the first embodiment taken along line vi-vi in ​​FIG. 5 . [Figure 7] 7 is a cross-sectional view of the array substrate according to the first embodiment taken along line vii-vii in FIG. 5 . [Figure 8] 1 is a graph showing changes in transistor characteristics when a positive voltage is applied to a non-pixel gate electrode in a non-pixel TFT not including a light-reflecting portion according to embodiment 1. [Figure 9] 1 is a graph showing changes in transistor characteristics when a negative voltage is applied to a non-pixel gate electrode without irradiating light in a non-pixel TFT having a light reflecting portion according to embodiment 1. [Figure 10]1 is a graph showing changes in transistor characteristics when a negative voltage is applied to a non-pixel gate electrode while irradiating light in a non-pixel TFT having a light reflecting portion according to embodiment 1. [Figure 11] 7 is a cross-sectional view taken along the same line as FIG. 6, illustrating a state in which a first interlayer insulating film is formed in a fifth step according to the first embodiment; [Figure 12] 7 is a cross-sectional view taken along the same line as FIG. 6, illustrating a state in which the gate insulating film and the first interlayer insulating film are patterned in a fifth step according to the first embodiment. [Figure 13] 7 is a cross-sectional view of a non-pixel TFT in an array substrate according to a second embodiment, taken at the same cutting position as FIG. 6; [Figure 14] 10 is a cross-sectional view of a non-pixel TFT in an array substrate according to a third embodiment, taken along the same cutting line as FIG. 6; [Figure 15] FIG. 10 is a plan view of a non-pixel TFT on an array substrate according to a fourth embodiment. [Figure 16] 16 is a cross-sectional view of the array substrate according to the fourth embodiment taken along line xvi-xvi in ​​FIG. 15 . [Figure 17] 10 is a cross-sectional view of a pixel TFT on an array substrate according to a fifth embodiment. [Figure 18] 10 is a cross-sectional view showing a connection portion of a source line and an overlapping line in an array substrate according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] <Embodiment 1> Embodiment 1 will be described with reference to Figures 1 to 12. In this embodiment, a liquid crystal display device 10 will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in parts of each drawing, and each axis direction is depicted as being in the direction shown in each drawing. Also, the upper side of Figures 2, 4, 6, 7, 11, and 12 is the front side, and the lower side of the drawings is the back side.

[0020] As shown in Fig. 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back surface) of the liquid crystal panel 11 and includes a light source (e.g., an LED) that emits white light and optical components that convert the light from the light source into planar light by applying an optical effect. The central portion of the main surface of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, a frame-shaped outer peripheral portion of the main surface of the liquid crystal panel 11 that surrounds the display area AA is a non-display area NAA where no image is displayed.

[0021] As shown in Fig. 1, a circuit section (peripheral circuit section, gate circuit section) 14 is provided in the non-display area NAA of the liquid crystal panel 11. A pair of circuit sections 14 are arranged so as to sandwich the display area AA from both sides in the X-axis direction. The circuit section 14 is provided in a strip-shaped range extending along the Y-axis direction. The circuit section 14 is for supplying scanning signals to gate wiring 26 (described later), and is provided monolithically on an array substrate 21 (described later). The circuit section 14 is a GDM (Gate Driver Monolithic) circuit. The circuit section 14 includes a shift register circuit that outputs scanning signals at predetermined timing, a buffer circuit that amplifies the scanning signals, and the like.

[0022] The liquid crystal panel 11 will be described with reference to FIG. 1 and FIG. 2. As shown in FIGS. 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. The front side of the pair of substrates 20 and 21 is the counter substrate 20, and the back side is the array substrate 21. The counter substrate 20 and the array substrate 21 are both formed by laminating various films on the inner surface of a glass substrate. A liquid crystal layer 22 containing liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied, is disposed between the pair of substrates 20 and 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral edges of the pair of substrates 20 and 21. The seal portion 23 is formed in a rectangular frame shape so as to surround the liquid crystal layer 22. A polarizing plate 15 is attached to the outer surface of each of the substrates 20 and 21.

[0023] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 so that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally from the counter substrate 20 and is exposed. The entire exposed portion 21A is a non-display area NAA, and a driver 12 and a flexible substrate 13 for supplying various signals are mounted on the exposed portion 21A.

[0024] The driver 12 is an LSI chip with an internal drive circuit. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 using COG (Chip On Glass) technology. The driver 12 processes various signals transmitted by the flexible substrate 13. As shown in FIGS. 1 and 2, the driver 12 is disposed adjacent to one side of the display area AA in the Y-axis direction, sandwiched between the display area AA and the flexible substrate 13 (described below). The driver 12 has a horizontally elongated rectangular shape in plan view. The driver 12 can supply various signals to the source lines 27 and other signals provided on the array substrate 21. The flexible substrate 13 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). One end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (e.g., a control board).

[0025] Next, the configuration of the display area AA of the array substrate 21 will be described with reference to FIG. 3. As shown in FIG. 3, at least pixel TFTs (pixel transistors, pixel switching elements) 24 and pixel electrodes 25 are provided on the inner surface of the display area AA of the array substrate 21. The pixel TFTs 24 and pixel electrodes 25 are arranged in a matrix (row and column) with multiple pixels spaced apart along the X-axis direction and the Y-axis direction. Gate wiring (first wiring, scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 are arranged around these pixel TFTs 24 and pixel electrodes 25, intersecting each other at right angles (intersecting). The gate wiring 26 extends along the X-axis direction, with multiple pixels spaced apart along the Y-axis direction. The source wiring 27 extends along the Y-axis direction, with multiple pixels spaced apart along the X-axis direction. The pixel TFT 24 includes a pixel gate electrode 24A connected to the gate line 26, a pixel source electrode 24B connected to the source line 27, a pixel drain electrode 24C connected to the pixel electrode 25, and a pixel semiconductor portion 24D made of a semiconductor material and connected to the pixel source electrode 24B and the pixel drain electrode 24C. The pixel TFT 24 is driven based on a scanning signal supplied to the pixel gate electrode 24A by the gate line 26. This scanning signal includes a potential higher than the threshold voltage of the pixel TFT 24. This generates a channel region in the pixel semiconductor portion 24D, allowing charge to move between the pixel source electrode 24B and the pixel drain electrode 24C via the channel region. Therefore, a potential related to an image signal (data signal) supplied to the pixel source electrode 24B by the source line 27 is supplied to the pixel drain electrode 24C via the pixel semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential related to the image signal. The pixel electrode 25 is disposed in a region surrounded by the gate line 26 and the source line 27, and has a planar shape that is, for example, a vertically long, substantially rectangular shape.

[0026] In addition, a plurality of color filters are provided in the display area AA of the counter substrate 20 at positions facing each pixel electrode 25 on the array substrate 21 side. The color filters are composed of three colors, R (red), G (green), and B (blue), repeatedly arranged in a predetermined order, and together with the pixel electrodes 25, form pixels of each color (red pixels, green pixels, and blue pixels). The three pixels, red, green, and blue pixels, form display pixels capable of displaying a predetermined color gradation. In addition, a light-shielding portion (black matrix) is formed between each color filter to prevent color mixing. Note that an alignment film (not shown) is formed on the innermost surface (top layer) of both substrates 20 and 21 that contacts the liquid crystal layer 22 to align the liquid crystal molecules contained in the liquid crystal layer 22.

[0027] Next, various films laminated on the glass substrate (substrate) 21GS of the array substrate 21 will be described in detail using Figure 4. Figure 4 illustrates a cross-sectional configuration of a pixel TFT 24. As shown in Figure 4, the glass substrate 21GS of the array substrate 21 is laminated with, in order from the lower layer side (glass substrate 21GS side), a first metal film (first conductive film), a gate insulating film (first insulating film) 29, a semiconductor film, a second metal film (second conductive film), a first interlayer insulating film (second insulating film) 30, a third metal film (third conductive film), a second interlayer insulating film 31, a planarizing film 32, a first transparent electrode film, a third interlayer insulating film 33, a second transparent electrode film, and an alignment film. Of these, the configuration consisting of the third metal film is illustrated in Figures 6 and 7, etc.

[0028] The first metal film, second metal film, and third metal film are each a single layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials, and thus have conductivity and light-blocking properties. The first metal film constitutes the gate line 26, the pixel gate electrode 24A of the pixel TFT 24, etc. The second metal film constitutes the source line 27, the pixel source electrode 24B, the pixel drain electrode 24C, etc. of the pixel TFT 24. The third metal film constitutes the light reflecting section 38, etc., which will be described later. The first transparent electrode film and the second transparent electrode film are made of a transparent electrode material (e.g., ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). The first transparent electrode film constitutes the common electrode 34, etc., which will be described later. The second transparent electrode film constitutes the pixel electrode 25, etc.

[0029] The semiconductor film is made of an oxide semiconductor material and constitutes the pixel semiconductor portion 24D of the pixel TFT 24. The semiconductor film may contain at least one metal element selected from the group consisting of In, Ga, and Zn, and may be, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). The In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and examples include In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, and In:Ga:Zn=1:1:2. The In-Ga-Zn-O-based semiconductor used in the semiconductor film may be amorphous or crystalline. The semiconductor film may contain other oxide semiconductors instead of the In-Ga-Zn-O-based semiconductor. For example, an In—Sn—Zn—O based semiconductor (e.g., In2O3—SnO2—ZnO; InSnZnO) may be included. The In—Sn—Zn—O based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may contain an In-W-Zn-O-based semiconductor containing W (tungsten), an In-W-Sn-Zn-O-based semiconductor, an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, an In-Ga-Zn-Sn-O-based semiconductor, etc. The oxide semiconductor material of the semiconductor film has a characteristic of having a higher resistance value when no voltage is applied (off state) compared to polysilicon semiconductor materials. Furthermore, the oxide semiconductor material of the semiconductor film has higher electron mobility than the amorphous silicon semiconductor material.

[0030] The gate insulating film 29, the first interlayer insulating film 30, the second interlayer insulating film 31, and the third interlayer insulating film 33 are all made of inorganic materials (inorganic resin materials) such as SiO2 (silicon oxide, silicon oxide) and SiN x(silicon nitride) or the like. The planarization film 32 is an organic insulating film made of an organic material such as PMMA (acrylic resin). The thickness of the planarization film 32 is much greater than the thicknesses of the gate insulating film 29, the first interlayer insulating film 30, the second interlayer insulating film 31, and the third interlayer insulating film 33. The planarization film 32 flattens the inner surface of the array substrate 21 (the surface on the liquid crystal layer 22 side).

[0031] The structure of the pixel TFT 24 will be described in detail. As shown in FIG. 4, the pixel gate electrode 24A of the pixel TFT 24 is formed by widening a portion of the gate wiring 26 near the intersection with the source wiring 27. The pixel source electrode 24B of the pixel TFT 24 is formed by widening a portion of the source wiring 27 near the intersection with the gate wiring 26. The pixel source electrode 24B extends along the X-axis direction, and its end opposite to the source wiring 27 is connected to the pixel semiconductor portion 24D. The pixel drain electrode 24C of the pixel TFT 24 is disposed at a distance from the pixel source electrode 24B in the X-axis direction. The pixel drain electrode 24C extends along the X-axis direction, and one end (on the left side of FIG. 4, on the pixel source electrode 24B side) is connected to the pixel semiconductor portion 24D, and the other end (on the right side of FIG. 4) is connected to the pixel electrode 25. A pixel contact hole CH1 is provided in communication with the first interlayer insulating film 30, the second interlayer insulating film 31, the planarizing film 32, and the third interlayer insulating film 33, which are interposed between the pixel drain electrode 24C and the pixel electrode 25, at a position that overlaps both the pixel drain electrode 24C and the pixel electrode 25. The pixel drain electrode 24C and the pixel electrode 25 are connected to each other through the pixel contact hole CH1.

[0032] As shown in FIG. 4, the pixel semiconductor portion 24D constituting the pixel TFT 24 is disposed extending along the X-axis direction. The pixel semiconductor portion 24D has a smaller dimension in the X-axis direction than the pixel gate electrode 24A. The pixel semiconductor portion 24D overlaps the pixel gate electrode 24A via a gate insulating film 29. One end of the pixel semiconductor portion 24D in the X-axis direction is connected to the pixel source electrode 24B. The other end of the pixel semiconductor portion 24D in the X-axis direction is connected to the pixel drain electrode 24C. A channel region is generated in a portion of the pixel semiconductor portion 24D that is sandwiched between the pixel source electrode 24B and the pixel drain electrode 24C in the X-axis direction when the pixel TFT 24 is driven. The channel region is a portion of the pixel semiconductor portion 24D that overlaps with the pixel gate electrode 24A but does not overlap with the pixel source electrode 24B and the pixel drain electrode 24C.

[0033] The common electrode 34, which is made of the first transparent electrode film, has a size equivalent to the display area AA as a whole. As shown in FIG. 4, the common electrode 34 is disposed below all of the pixel electrodes 25, with the third interlayer insulating film 33 interposed therebetween. A common potential (reference potential) is supplied to the common electrode 34. The pixel electrodes 25, which are disposed above the common electrode 34 and overlap each other with the third interlayer insulating film 33 interposed therebetween, have slits. When the pixel electrodes 25 are charged to a potential based on the image signals transmitted to the source lines 27 as the pixel TFTs 24 are driven based on the scanning signals transmitted through the gate lines 26, a potential difference is generated between the pixel electrodes 25 and the common electrode 34. This generates a fringe electric field (oblique electric field) between the edge of the slit in the pixel electrode 25 and the common electrode 34, which includes a component normal to the main surface of the array substrate 21 in addition to a component along the main surface of the array substrate 21. Therefore, by utilizing this fringe electric field, the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled, and a predetermined display is produced based on the alignment state of the liquid crystal molecules. In other words, the liquid crystal panel 11 according to this embodiment operates in FFS (Fringe Field Switching) mode.

[0034] The gate insulating film 29 insulates the first metal film on the lower layer from the semiconductor film and second metal film on the upper layer. For example, the gate insulating film 29 insulates the intersection of the gate wiring 26 made of the first metal film and the source wiring 27 made of the second metal film. In the pixel TFT 24, the gate insulating film 29 also insulates the overlapping portion of the pixel gate electrode 24A made of the first metal film and the pixel semiconductor portion 24D made of the semiconductor film. The first interlayer insulating film 30 insulates the semiconductor film and second metal film on the lower layer from the third metal film on the upper layer. The second interlayer insulating film 31 covers the third metal film from above. The second interlayer insulating film 31 and the planarizing film 32 insulate the third metal film on the lower layer from the first transparent electrode film on the upper layer. The third interlayer insulating film 33 keeps the first transparent electrode film on the lower layer side and the second transparent electrode film on the upper layer side in an insulated state. For example, the common electrode 34 made of the first transparent electrode film and the pixel electrode 25 made of the second transparent electrode film are kept in an insulated state by the third interlayer insulating film 33.

[0035] The circuit unit 14 provided in the non-display area NAA of the array substrate 21 includes various circuit elements, including at least a non-pixel TFT (transistor) 35 shown in FIGS. 5 to 7. The configuration of the non-pixel TFT 35 will be described in detail below. As shown in FIGS. 5 to 7, the non-pixel TFT 35 includes a non-pixel gate electrode (first electrode) 35A, a non-pixel source electrode (second electrode) 35B, a non-pixel drain electrode (third electrode) 35C, and a non-pixel semiconductor portion (semiconductor portion) 35D. The non-pixel gate electrode 35A, like the pixel gate electrode 24A, is made of a part of a first metal film. The non-pixel source electrode 35B and the non-pixel drain electrode 35C, like the pixel source electrode 24B and the pixel drain electrode 24C, are each made of a part of a second metal film. The non-pixel semiconductor portion 35D, like the pixel semiconductor portion 24D, is made of a part of a semiconductor film.

[0036] As shown in FIG. 5 , the non-pixel gate electrode 35A of the non-pixel TFT 35 has a horizontally elongated rectangular shape in a plan view. A wiring (not shown) in the circuit unit 14 is connected to the non-pixel gate electrode 35A, and a signal for driving the non-pixel TFT 35 is supplied via the wiring. The non-pixel source electrode 35B of the non-pixel TFT 35 extends along the Y-axis direction, with one end connected to the non-pixel semiconductor portion 35D and the other end extending outside the non-pixel semiconductor portion 35D and connected to a first circuit wiring 36 in the circuit unit 14. A predetermined signal is input to the non-pixel source electrode 35B via the first circuit wiring 36. Like the non-pixel source electrode 35B, the first circuit wiring 36 is made of a part of the second metal film. The non-pixel source electrode 35B is biased toward one end (the left side in FIG. 5 ) of the non-pixel semiconductor portion 35D in the X-axis direction. Specifically, the non-pixel source electrode 35B is disposed closer to the non-pixel drain electrode 35C (to be described later) (to the right in FIG. 5) than one end position (the left end position in FIG. 5) of the non-pixel semiconductor portion 35D.

[0037] As shown in FIG. 5 , the non-pixel drain electrode 35C of the non-pixel TFT 35 extends along the Y-axis direction, with one end connected to the non-pixel semiconductor portion 35D and the other end extending outside the non-pixel semiconductor portion 35D and connected to a second circuit wiring 37 of the circuit portion 14. The non-pixel drain electrode 35C is extended toward the opposite side of the non-pixel source electrode 35B in the Y-axis direction (the lower side in FIG. 5 ). A signal from the non-pixel source electrode 35B is output from the non-pixel drain electrode 35C to the second circuit wiring 37. Like the non-pixel drain electrode 35C, the second circuit wiring 37 is made of a part of the second metal film. The non-pixel drain electrode 35C is disposed at a distance from the non-pixel source electrode 35B in the X-axis direction (first direction). The non-pixel drain electrode 35C is disposed biased toward the other end of the non-pixel semiconductor portion 35D in the X-axis direction (the right side in FIG. 5 ). Specifically, the non-pixel drain electrode 35C is disposed closer to the non-pixel source electrode 35B (left side in FIG. 5) than the other end position (right end position in FIG. 5) of the non-pixel semiconductor portion 35D.

[0038] As shown in FIG. 5 , the non-pixel semiconductor portion 35D constituting the non-pixel TFT 35 has a horizontally elongated rectangular shape in a plan view, similar to the non-pixel gate electrode 35A. The non-pixel semiconductor portion 35D is smaller than the non-pixel gate electrode 35A in both the X-axis direction and the Y-axis direction. The non-pixel semiconductor portion 35D is disposed concentrically with the non-pixel gate electrode 35A in the X-axis direction and the Y-axis direction. Therefore, as shown in FIGS. 6 and 7 , the entire region of the non-pixel semiconductor portion 35D overlaps the non-pixel gate electrode 35A via the gate insulating film 29. In other words, the entire region of the non-pixel semiconductor portion 35D is covered by the non-pixel gate electrode 35A from the rear side (rear side, backlight device side). One end portion of the non-pixel semiconductor portion 35D in the X-axis direction is connected to the non-pixel source electrode 35B. The other end portion of the non-pixel semiconductor portion 35D in the X-axis direction is connected to the non-pixel drain electrode 35C. A portion of the non-pixel semiconductor portion 35D that is sandwiched between the non-pixel source electrode 35B and the non-pixel drain electrode 35C in the X-axis direction is a channel-forming portion 35D1 where a channel region is generated when the non-pixel TFT 35 is driven. The channel-forming portion 35D1 is a portion of the non-pixel semiconductor portion 35D that overlaps with the non-pixel gate electrode 35A and does not overlap with the non-pixel source electrode 35B or the non-pixel drain electrode 35C in the X-axis direction. Furthermore, both end portions 35D2 and 35D3 of the non-pixel semiconductor portion 35D in the X-axis direction do not overlap with the non-pixel source electrode 35B or the non-pixel drain electrode 35C.

[0039] In the non-pixel TFT 35 configured as described above, when a voltage equal to or greater than the threshold voltage is applied to the non-pixel gate electrode 35A, a channel region is generated in the channel-forming portion 35D1 of the non-pixel semiconductor portion 35D, which is disposed above the non-pixel gate electrode 35A via the gate insulating film 29. Charges can then be transferred between the non-pixel source electrode 35B and the non-pixel drain electrode 35C through the channel region. Because the non-pixel TFT 35 is a circuit element constituting the circuit unit 14, a positive voltage is predominantly applied to the non-pixel gate electrode 35A. Repeated application of a positive voltage to the non-pixel gate electrode 35A can shift the threshold voltage of the non-pixel TFT 35 in the positive direction, as shown in FIG. 8, potentially degrading the characteristics of the non-pixel TFT 35. FIG. 8 is a graph showing the change in transistor characteristics when a positive voltage is applied to the non-pixel gate electrode of a non-pixel TFT that does not include a light-reflecting portion 38 (described below). The vertical axis of the graph in FIG. 8 is the drain current Id (unit: "A"), which is the current flowing through the channel region of the non-pixel semiconductor portion, and the horizontal axis of the graph in FIG. 8 is the gate voltage Vg (unit: "V"), which is the voltage applied to the non-pixel gate electrode. In FIG. 8, the dashed line shows the transistor characteristics when a positive gate voltage Vg is first applied (the state before electrical stress is applied), and the solid line shows the transistor characteristics when the positive gate voltage Vg is repeatedly applied and electrical stress is applied. FIG. 8 shows that the transistor characteristics when electrical stress is applied are shifted in the positive direction (to the right in FIG. 8) compared to the transistor characteristics before electrical stress is applied.

[0040] Therefore, as shown in FIGS. 5 to 7, the array substrate 21 according to this embodiment is provided with a light-reflecting section 38 that is arranged to cover the non-pixel TFTs 35 from above. The light-reflecting section 38 is made of a third metal film and has high light reflectivity and light-blocking properties. The light-reflecting section 38 is arranged on the upper side of the first interlayer insulating film 30. The light-reflecting section 38 is covered and protected by the second interlayer insulating film 31 that is arranged on its upper side. In this embodiment, the light-reflecting section 38 is not connected to the electrodes 35A to 35C that constitute the non-pixel TFTs 35 and is electrically isolated.

[0041] As shown in FIGS. 5 to 7 , the light-reflecting portion 38 has an overlapping portion 38A that overlaps the non-pixel gate electrode 35A and the non-pixel semiconductor portion 35D, and a non-overlapping portion 38B that is continuous with the overlapping portion 38A and does not overlap the non-pixel gate electrode 35A and the non-pixel semiconductor portion 35D. Specifically, the light-reflecting portion 38 has a horizontally elongated rectangular shape in a plan view. The light-reflecting portion 38 is larger than the non-pixel gate electrode 35A in both the X-axis direction and the Y-axis direction. The light-reflecting portion 38 is disposed concentrically with the non-pixel semiconductor portion 35D and the non-pixel gate electrode 35A in both the X-axis direction and the Y-axis direction. Therefore, the central portion of the light-reflecting portion 38 forms the overlapping portion 38A that overlaps the non-pixel semiconductor portion 35D and the non-pixel gate electrode 35A. The overlapping portion 38A is a portion that overlaps both the non-pixel semiconductor portion 35D and the non-pixel gate electrode 35A, and includes a portion that overlaps with a portion of the non-pixel gate electrode 35A that does not overlap with the non-pixel semiconductor portion 35D. In contrast, the outer peripheral end portion of the light reflecting portion 38 that surrounds the overlapping portion 38A is a non-overlapping portion 38B that does not overlap with the non-pixel semiconductor portion 35D and the non-pixel gate electrode 35A. The non-overlapping portion 38B is a portion that does not overlap with both the non-pixel semiconductor portion 35D and the non-pixel gate electrode 35A, and also does not overlap with a portion of the non-pixel gate electrode 35A that does not overlap with the non-pixel semiconductor portion 35D. In this way, the light reflecting portion 38 covers the entire non-pixel semiconductor portion 35D and the non-pixel gate electrode 35A from above, and also surrounds and covers the periphery of the non-pixel semiconductor portion 35D and the non-pixel gate electrode 35A from above. As a result, when light from the backlight device is irradiated onto the array substrate 21 from the rear side (the side below the non-pixel gate electrode 35A), the light can be reflected by the non-overlapping portion 38B of the light reflecting portion 38 and directed toward the non-pixel semiconductor portion 35D. This allows the threshold voltage of the non-pixel TFT 35 to be shifted in the negative direction, making it possible to make the characteristics of the non-pixel TFT 35 less susceptible to degradation.

[0042] In this embodiment, as shown in FIG. 6 , the first interlayer insulating film 30 has a first recess 30A at a position that does not overlap the non-pixel gate electrode 35A and the non-pixel semiconductor portion 35D. The non-overlapping portion 38B includes a first filling portion 39 that fills the first recess 30A. In this embodiment, the first recess 30A is provided to penetrate the first interlayer insulating film 30, and the first filling portion 39 fills the first recess 30A to the entire depth, which is a through-hole. The first filling portion 39 that fills the first recess 30A is disposed so as to protrude downward from the surface of the first interlayer insulating film 30. Therefore, light from the backlight device can be efficiently reflected by the first filling portion 39 that fills the first recess 30A and directed toward the non-pixel semiconductor portion 35D. Light reflected by the non-overlapping portion 38B including the first filling portion 39 is repeatedly reflected between the overlapping portion 38A of the light reflecting portion 38 that overlaps the non-pixel gate electrode 35A and the non-pixel gate electrode 35A, and is thereby efficiently irradiated onto the channel forming portion 35D1 of the non-pixel semiconductor portion 35D. This allows the threshold voltage of the non-pixel TFT 35 to be efficiently shifted in the negative direction, thereby preventing the characteristics of the non-pixel TFT 35 from deteriorating. In particular, in this embodiment, the non-pixel semiconductor portion 35D is shorter in the X-axis direction than the non-pixel gate electrode 35A, making it difficult for light from the backlight device to be directly irradiated onto the non-pixel semiconductor portion 35D. In this regard, by reflecting light from the backlight device by the first non-overlapping portion 38B1 including the first filling portion 39, the reflected light can be efficiently irradiated onto the channel forming portion 35D1 of the non-pixel semiconductor portion 35D. This allows the threshold voltage of the non-pixel TFT 35 to be more efficiently shifted in the negative direction.

[0043] As shown in FIG. 6 , the first interlayer insulating film 30 includes a pair of first recesses 30A, one at a position spaced apart from the non-pixel source electrode 35B on the opposite side of the non-pixel drain electrode 35C in the X-axis direction from the non-pixel source electrode 35B, and the other at a position spaced apart from the non-pixel drain electrode 35C on the opposite side of the non-pixel source electrode 35B in the X-axis direction from the non-pixel drain electrode 35C. Meanwhile, the non-overlapping portion 38B includes a first non-overlapping portion 38B1 arranged side by side with the overlapping portion 38A along the X-axis direction. The first non-overlapping portion 38B1 is arranged side by side with the overlapping portion 38A on one side in the X-axis direction and on the other side in the X-axis direction. That is, the first non-overlapping portion 38B1 is arranged in pairs to sandwich the overlapping portion 38A in the X-axis direction. A first filling portion 39 is included in each of the pair of first non-overlapping portions 38B1. The pair of first filling portions 39 fills each pair of first recesses 30A in the first interlayer insulating film 30. With this configuration, light irradiated from the backlight device onto the array substrate 21 is reflected by the pair of non-overlapping portions 38B that sandwich the overlapping portion 38A in the X-axis direction. Because the pair of non-overlapping portions 38B each include a first filling portion 39 that fills the pair of first recesses 30A, the light reflected by the pair of first filling portions 39 can be guided toward the non-pixel source electrode 35B and the non-pixel drain electrode 35C along the X-axis direction while efficiently irradiating the channel component portion 35D1 of the non-pixel semiconductor portion 35D from both sides. This allows the threshold voltage of the non-pixel TFT 35 to be shifted more efficiently in the negative direction.

[0044] As shown in FIGS. 5 and 6 , the first interlayer insulating film 30 is provided with a first recess 30A extending along the Y-axis direction (a second direction that runs along the main surface of the non-pixel gate electrode 35A and intersects the first direction). The first filling portion 39, like the first recess 30A, is also provided to extend along the Y-axis direction. The first recess 30A and the first filling portion 39 are provided over the entire length of the light reflecting portion 38 in the Y-axis direction. Therefore, the first recess 30A and the first filling portion 39 are spaced apart laterally from the non-pixel semiconductor portion 35D over the entire length in the Y-axis direction. This configuration allows the first filling portion 39 filling the first recess 30A to have a surface 39A extending along the Y-axis direction, which can more efficiently reflect light and irradiate it onto the channel portion 35D1 of the non-pixel semiconductor portion 35D. This allows the threshold voltage of the non-pixel TFT 35 to be more efficiently shifted in the negative direction. On the other hand, as described above, the non-pixel source electrode 35B and the non-pixel drain electrode 35C each extend along the Y-axis direction and are drawn out to the outside of the non-pixel semiconductor portion 35D. In this way, the non-pixel source electrode 35B and the non-pixel drain electrode 35C extend parallel to the first recess 30A and are drawn out to the outside of the non-pixel semiconductor portion 35D, so that the non-pixel source electrode 35B and the non-pixel drain electrode 35C are prevented from physically interfering with the first recess 30A and the first filling portion 39.

[0045] As shown in FIGS. 5 and 7 , the non-overlapping portion 38B includes a second non-overlapping portion 38B2 arranged alongside the overlapping portion 38A along the Y-axis direction. The second non-overlapping portion 38B2 is arranged alongside the overlapping portion 38A on one side in the Y-axis direction and on the other side in the Y-axis direction. That is, the second non-overlapping portion 38B2 is arranged in pairs to sandwich the overlapping portion 38A in the Y-axis direction. In this manner, in addition to the first non-overlapping portion 38B1 including the first filling portion 39, the second non-overlapping portion 38B2 also reflects light and causes it to travel along the Y-axis direction, thereby efficiently irradiating the channel component 35D1 of the non-pixel semiconductor portion 35D. This efficiently shifts the threshold voltage of the non-pixel TFT 35 in the negative direction. In particular, in this embodiment, the non-pixel semiconductor portion 35D is shorter in the Y-axis direction than the non-pixel gate electrode 35A, making it difficult for light from the backlight device to directly irradiate the non-pixel semiconductor portion 35D. In this regard, by reflecting light irradiated from the lower layer side of the non-pixel gate electrode 35A by the second non-overlapping portion 38B2, the reflected light can travel along the Y-axis direction and be efficiently irradiated onto the channel forming portion 35D1 of the non-pixel semiconductor portion 35D, thereby more efficiently shifting the threshold voltage of the non-pixel TFT 35 in the negative direction.

[0046] As shown in FIG. 6 , the gate insulating film 29, which is disposed below the first interlayer insulating film 30, has a second recess 29A at a position overlapping the first recess 30A penetrating the first interlayer insulating film 30. The second recess 29A is connected to the first recess 30A. The non-overlapping portion 38B includes a second filling portion 40 that is connected to the first filling portion 39 and fills the second recess 29A. In this embodiment, the second recess 29A is provided penetrating the gate insulating film 29, and the second filling portion 40 fills the second recess 29A, which is a through-hole, to the entire depth. The second filling portion 40 that fills the second recess 29A is disposed so as to protrude downward from the surface of the gate insulating film 29. Therefore, together with the first filling portion 39, the second filling portion 40 that fills the second recess 29A can efficiently reflect light from the backlight device and direct it toward the non-pixel semiconductor portion 35D. This allows the threshold voltage of the non-pixel TFT 35 to be shifted more efficiently in the negative direction.

[0047] 5 to 7, the second recesses 29A are arranged in pairs, similar to the first recesses 30A, at positions spaced apart from the non-pixel source electrode 35B in the X-axis direction and at positions spaced apart from the non-pixel drain electrode 35C in the X-axis direction, and both extend along the Y-axis direction. Similar to the first filling portions 39, the second filling portions 40 are arranged in pairs to sandwich the overlapping portion 38A in the X-axis direction, and both extend along the Y-axis direction.

[0048] 5 and 6, the non-pixel source electrode 35B and the non-pixel drain electrode 35C are arranged so as not to overlap with both end portions 35D2 and 35D3 of the non-pixel semiconductor portion 35D in the X-axis direction. With this configuration, both end portions 35D2 and 35D3 of the non-pixel semiconductor portion 35D in the X-axis direction are exposed and not covered by the non-pixel source electrode 35B and the non-pixel drain electrode 35C. Therefore, light reflected by the first non-overlapping portion 38B1 including the first filling portion 39 can be directly irradiated onto the end portions 35D2 and 35D3 of the non-pixel semiconductor portion 35D in the X-axis direction. This allows light to be efficiently irradiated onto the channel-forming portion 35D1 of the non-pixel semiconductor portion 35D.

[0049] 9 and 10 are graphs showing changes in transistor characteristics when a negative voltage is applied to the non-pixel gate electrode 35A in the non-pixel TFT 35 having the above-described light-reflecting portion 38. FIG. 9 is a graph showing the case where light from the backlight device is not irradiated onto the array substrate 21. FIG. 10 is a graph showing the case where light from the backlight device is irradiated onto the array substrate 21, and the illuminance of the light irradiated onto the array substrate 21 is approximately 3000 lx (lux). As with FIG. 8, the vertical axes of the graphs in FIGS. 9 and 10 represent the drain current Id (unit: "A"), which is the current flowing through the channel region of the non-pixel semiconductor portion 35D, and the horizontal axes of the graphs in FIGS. 9 and 10 represent the gate voltage Vg (unit: "V"), which is the voltage applied to the non-pixel gate electrode 35A, as with FIG. 8. In Figures 9 and 10, the dashed lines show the transistor characteristics when a negative gate voltage Vg is first applied, and the solid lines show the transistor characteristics when the negative gate voltage Vg is repeatedly applied and electrical stress is applied.

[0050] 9 shows that, when no light is applied, the transistor characteristics after electrical stress are applied hardly shift compared to the transistor characteristics before electrical stress are applied. This means that the transistor characteristics of the non-pixel TFT 35 do not change significantly even when a negative gate voltage Vg is applied. FIG. 10 shows that, when light is applied, the transistor characteristics after electrical stress are significantly shifted in the negative direction (to the left in FIG. 10) compared to the transistor characteristics before electrical stress are applied. The amount of shift in the transistor characteristics shown in FIG. 10 is presumably the result of the negative shift of the transistor characteristics caused by the repeated application of a negative gate voltage Vg being accelerated by light irradiation. Therefore, in the non-pixel TFT 35 having the light-reflecting portion 38 according to this embodiment, even if a positive voltage is repeatedly applied to the non-pixel gate electrode 35A, when light is irradiated from the backlight device, the light is reflected by the first filling portion 39 and the second filling portion 40 of the light-reflecting portion 38, and can be efficiently irradiated onto the channel component portion 35D1 of the non-pixel semiconductor portion 35D, thereby suppressing a shift in the transistor characteristics in the positive direction.

[0051] The liquid crystal panel 11 according to this embodiment has the above-described structure, and its manufacturing method will now be described. The manufacturing method of the liquid crystal panel 11 includes a counter substrate manufacturing process (counter substrate manufacturing process) for manufacturing the counter substrate 20, an array substrate manufacturing process (array substrate manufacturing process) for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and array substrate 21 together. Of these processes, the array substrate manufacturing process will be described below.

[0052] The array substrate manufacturing process includes at least the following steps: a first step of depositing and patterning a first metal film; a second step of depositing a gate insulating film 29; a third step of depositing and patterning a semiconductor film; a fourth step of depositing and patterning a second metal film; a fifth step of depositing and patterning a first interlayer insulating film 30; a sixth step of depositing and patterning a third metal film; a seventh step of depositing a second interlayer insulating film 31 and a planarizing film 32; an eighth step of depositing and patterning a first transparent electrode film; a ninth step of depositing and patterning a third interlayer insulating film 33; a tenth step of depositing and patterning a second transparent electrode film; and an eleventh step of depositing an alignment film.

[0053] The term "patterning" used above refers to film processing based on a general photolithography method. Specifically, a photoresist film is formed on the film to be processed, the photoresist film is exposed to light by an exposure device through a photomask having a predetermined opening pattern, the photoresist film is developed, and etching is performed through the developed photoresist film, thereby processing the film to be processed, i.e., patterning the film.

[0054] The fifth step included in the array substrate manufacturing process will be described below with reference to FIGS. 11 and 12 . In the fifth step, a first interlayer insulating film 30 is formed, and in the circuit section 14, as shown in FIG. 11 , the non-pixel source electrode 35B and the non-pixel drain electrode 35C made of the second metal film are covered from above by the first interlayer insulating film 30. The formed first interlayer insulating film 30, together with the gate insulating film 29, is patterned by the general photolithography method described above. After patterning, as shown in FIG. 12 , the first interlayer insulating film 30 is selectively etched to form a first recess 30A. Furthermore, a portion of the gate insulating film 29 exposed through the first recess 30A is selectively etched to form a second recess 29A communicating with the first recess 30A. The first recesses 30A provided in the first interlayer insulating film 30 penetrate the first interlayer insulating film 30 and are arranged in pairs at positions sandwiching the non-pixel semiconductor portion 35D from both sides in the X-axis direction. The second recesses 29A provided in the gate insulating film 29 penetrate the gate insulating film 29 and are arranged in pairs at positions sandwiching the non-pixel semiconductor portion 35D from both sides in the X-axis direction. Thereafter, a sixth step is performed, and the deposited third metal film is patterned, whereby a light reflecting portion 38 is provided in the circuit unit 14, as shown in FIG. 6. The first filling portion 39 included in the non-overlapping portion 38B of the light reflecting portion 38 is filled in the first recess 30A, and the second filling portion 40 is filled in the second recess 29A.

[0055] As described above, the array substrate 21 of this embodiment includes the non-pixel TFT (transistor) 35, which includes the non-pixel gate electrode (first electrode) 35A, the non-pixel semiconductor portion (semiconductor portion) 35D that is provided above the non-pixel gate electrode 35A and overlaps the non-pixel gate electrode 35A, the non-pixel source electrode (second electrode) 35B that is provided above the non-pixel semiconductor portion 35D and connected to the non-pixel semiconductor portion 35D, and the non-pixel drain electrode (third electrode) 35C that is provided above the non-pixel gate electrode 35A and arranged at an interval from the non-pixel source electrode 35B in the first direction and connected to the non-pixel semiconductor portion 35D, and the non-pixel TFT (transistor) 35, which is provided above the non-pixel gate electrode 35A and below the non-pixel semiconductor portion 35D. a gate insulating film (first insulating film) 29 disposed between the non-pixel source electrode 35B and the non-pixel drain electrode 35C, a first interlayer insulating film (second insulating film) 30 disposed on the upper side of the non-pixel source electrode 35B and the non-pixel drain electrode 35C, and a light reflecting portion 38 disposed on the upper side of the first interlayer insulating film 30, wherein the first interlayer insulating film 30 is provided with a first recess 30A at a position where it does not overlap with the non-pixel gate electrode 35A and the non-pixel semiconductor portion 35D, and the light reflecting portion 38 has an overlapping portion 38A that overlaps with the non-pixel gate electrode 35A and the non-pixel semiconductor portion 35D and a non-overlapping portion 38B that is continuous with the overlapping portion 38A and does not overlap with the non-pixel gate electrode 35A and the non-pixel semiconductor portion 35D, and the non-overlapping portion 38B includes a first filling portion 39 that is filled in the first recess 30A.

[0056] When a voltage equal to or higher than the threshold voltage of the non-pixel TFT 35 is applied to the non-pixel gate electrode 35A, a channel region is generated in the non-pixel semiconductor portion 35D that is arranged above the non-pixel gate electrode 35A via the gate insulating film 29, and charges can move between the non-pixel source electrode 35B and the non-pixel drain electrode 35C via the channel region. However, if a positive voltage is repeatedly applied to the non-pixel gate electrode 35A, the threshold voltage of the non-pixel TFT 35 may shift in the positive direction, which may degrade the characteristics of the non-pixel TFT 35.

[0057] In this regard, the light reflecting portion 38 provided on the upper side of the non-pixel source electrode 35B has a non-overlapping portion 38B that does not overlap with the non-pixel gate electrode 35A and the non-pixel semiconductor portion 35D, so that when light is irradiated from below the non-pixel gate electrode 35A, the light can be reflected by the non-overlapping portion 38B of the light reflecting portion 38 and directed toward the non-pixel semiconductor portion 35D. Furthermore, the first interlayer insulating film 30 provided on the upper side of the non-pixel source electrode 35B and the non-pixel drain electrode 35C has a first recess 30A at a position that does not overlap with the non-pixel gate electrode 35A and the non-pixel semiconductor portion 35D, and the non-overlapping portion 38B of the light reflecting portion 38 has a first filling portion 39 that fills the first recess 30A. The first filling portion 39 filling the first recess 30A is disposed so as to protrude downward from the surface of the first interlayer insulating film 30, and therefore can efficiently reflect light irradiated from below the non-pixel gate electrode 35A and direct it toward the non-pixel semiconductor portion 35D. The light reflected by the non-overlapping portion 38B including the first filling portion 39 is repeatedly reflected between the non-pixel gate electrode 35A and the overlapping portion 38A of the light reflecting portion 38 that overlaps with the non-pixel gate electrode 35A, and thereby efficiently irradiated onto a portion of the non-pixel semiconductor portion 35D that will become a channel region (a portion sandwiched between the non-pixel source electrode 35B and the non-pixel drain electrode 35C). This efficiently shifts the threshold voltage of the non-pixel TFT 35 in the negative direction, thereby making it difficult for the characteristics of the non-pixel TFT 35 to deteriorate.

[0058] Furthermore, the first interlayer insulating film 30 is provided such that the first recess 30A is disposed at a position spaced apart in the first direction from at least one of the non-pixel source electrode 35B and the non-pixel drain electrode 35C, and the non-overlapping portion 38B includes a first non-overlapping portion 38B1 disposed adjacent to the overlapping portion 38A along the first direction, and the first filling portion 39 is included in the first non-overlapping portion 38B1. With this configuration, light reflected by the first non-overlapping portion 38B1 including the first filling portion 39 can be guided toward the non-pixel source electrode 35B and the non-pixel drain electrode 35C along the first direction, while efficiently irradiating a portion of the non-pixel semiconductor portion 35D that will become a channel region. This allows the threshold voltage of the non-pixel TFT 35 to be efficiently shifted in the negative direction.

[0059] Furthermore, the first interlayer insulating film 30 is provided in pairs with the first recesses 30A arranged at positions spaced apart from the non-pixel source electrode 35B in the first direction and at positions spaced apart from the non-pixel drain electrode 35C in the first direction, and the first non-overlapping portions 38B1 are arranged in pairs to sandwich the overlapping portion 38A in the first direction, and the first filling portions 39 are included in each of the paired first non-overlapping portions 38B1. With this configuration, light reflected by the first non-overlapping portions 38B1 including the first filling portions 39 can be efficiently irradiated from both sides in the first direction onto the portion of the non-pixel semiconductor portion 35D that becomes the channel region. This allows the threshold voltage of the non-pixel TFT 35 to be shifted more efficiently in the negative direction.

[0060] Furthermore, the first interlayer insulating film 30 is provided such that the first recess 30A extends along a second direction that is along the main surface of the non-pixel gate electrode 35A and intersects with the first direction, and the first filling portion 39 extends along the second direction. Because the first filling portion 39 that fills the first recess 30A has a surface 39A that extends along the second direction, light can be more efficiently reflected by the surface 39A and irradiated onto a portion of the non-pixel semiconductor portion 35D that will become a channel region. This allows the threshold voltage of the non-pixel TFT 35 to be more efficiently shifted in the negative direction.

[0061] Furthermore, the non-pixel source electrode 35B and the non-pixel drain electrode 35C each extend along the second direction and are drawn out to the outside of the non-pixel semiconductor portion 35D. In this way, the non-pixel source electrode 35B and the non-pixel drain electrode 35C extend parallel to the first recess 30A and are drawn out to the outside of the non-pixel semiconductor portion 35D, so that the non-pixel source electrode 35B and the non-pixel drain electrode 35C are prevented from physically interfering with the first recess 30A and the first filling portion 39.

[0062] Furthermore, the non-pixel semiconductor portion 35D is shorter in the first direction than the non-pixel gate electrode 35A. With this configuration, light irradiated from below the non-pixel gate electrode 35A is less likely to directly irradiate the non-pixel semiconductor portion 35D. In this regard, by reflecting the light irradiated from below the non-pixel gate electrode 35A by the first non-overlapping portion 38B1 including the first filling portion 39, the reflected light can be efficiently irradiated onto a portion of the non-pixel semiconductor portion 35D that will become a channel region. This makes it possible to more efficiently shift the threshold voltage of the non-pixel TFT 35 in the negative direction.

[0063] The non-overlapping portion 38B also includes a second non-overlapping portion 38B2 that is arranged alongside the overlapping portion 38A along the main surface of the non-pixel gate electrode 35A and in a second direction that intersects with the first direction. In addition to the first non-overlapping portion 38B1 that includes the first filling portion 39, the second non-overlapping portion 38B2 also reflects light, allowing the light to be efficiently irradiated onto a portion of the non-pixel semiconductor portion 35D that will become a channel region. This allows the threshold voltage of the non-pixel TFT 35 to be efficiently shifted in the negative direction.

[0064] Furthermore, the non-pixel semiconductor portion 35D is shorter in the second direction than the non-pixel gate electrode 35A. With this configuration, light irradiated from below the non-pixel gate electrode 35A is less likely to directly irradiate the non-pixel semiconductor portion 35D. In this regard, by reflecting light irradiated from below the non-pixel gate electrode 35A by the second non-overlapping portion 38B2, the reflected light travels along the second direction and can be efficiently irradiated onto the portion of the non-pixel semiconductor portion 35D that will become the channel region. This makes it possible to more efficiently shift the threshold voltage of the non-pixel TFT 35 in the negative direction.

[0065] Furthermore, the non-pixel source electrode 35B and the non-pixel drain electrode 35C are arranged so as not to overlap with both end portions 35D2 and 35D3 of the non-pixel semiconductor portion 35D in the first direction. With this configuration, both end portions 35D2 and 35D3 of the non-pixel semiconductor portion 35D in the first direction are exposed and not covered by the non-pixel source electrode 35B and the non-pixel drain electrode 35C. Therefore, light reflected by the first non-overlapping portion 38B1 including the first filling portion 39 can be directly irradiated onto the end portions of the non-pixel semiconductor portion 35D in the first direction. This allows light to be efficiently irradiated onto the portion of the non-pixel semiconductor portion 35D sandwiched between the non-pixel source electrode 35B and the non-pixel drain electrode 35C, i.e., the portion that becomes the channel region.

[0066] The first interlayer insulating film 30 is provided with a first recess 30A penetrating therethrough, the gate insulating film 29 is provided with a second recess 29A in a position overlapping the first recess 30A and communicating with the first recess 30A, and the non-overlapping portion 38B includes a second filling portion 40 that is connected to the first filling portion 39 and fills the second recess 29A. The second filling portion 40 filling the second recess 29A is arranged to protrude downward from the surface of the gate insulating film 29, and thus together with the first filling portion 39, can more efficiently reflect light irradiated from the lower layer side of the non-pixel gate electrode 35A and direct it toward the portion of the non-pixel semiconductor portion 35D that will become the channel region. This allows the threshold voltage of the non-pixel TFT 35 to be more efficiently shifted in the negative direction.

[0067] The liquid crystal panel (display device) 11 according to this embodiment includes the array substrate 21 described above, a display area AA for displaying an image, and a non-display area NAA where no image is displayed. Gate wiring (first wiring) 26 is arranged in the display area AA of the array substrate 21, and a circuit unit 14 connected to the gate wiring 26 is arranged in the non-display area NAA of the array substrate 21. The non-pixel TFTs 35 are included in the circuit unit 14. When the circuit unit 14 operates, signals are supplied to the gate wiring 26 arranged in the display area AA of the array substrate 21. While a large amount of light for display is present in the display area AA of the array substrate 21, there is not as much light present in the non-display area NAA of the array substrate 21. For this reason, the non-pixel TFTs 35 included in the circuit unit 14 arranged in the non-display area NAA of the array substrate 21 tend to irradiate an insufficient amount of light onto the non-pixel semiconductor portions 35D. In this regard, the first filling portion 39 filled in the first recess 30A is arranged to protrude downward from the surface of the first interlayer insulating film 30, and therefore can efficiently reflect light irradiated from the lower side of the non-pixel gate electrode 35A and direct it toward the portion of the non-pixel semiconductor portion 35D that will become the channel region. This makes it possible to efficiently shift the threshold voltage of the non-pixel TFT 35 in the negative direction even when the amount of light present in the non-display area NAA of the array substrate 21 is small, and makes it difficult for the characteristics of the non-pixel TFT 35 to deteriorate.

[0068] <Embodiment 2> A second embodiment will be described with reference to Fig. 13. In this second embodiment, the second recess 29A and the second filling portion 40 of the first embodiment are omitted. Note that a redundant description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0069] As shown in FIG. 13 , the first interlayer insulating film 130 according to this embodiment has a first recess 130A. In contrast, the second recess 29A (see FIG. 6 ) shown in the first embodiment is not provided in the gate insulating film 129 at a position overlapping the first recess 130A. The non-overlapping portion 138B of the light reflecting portion 138 includes the first filling portion 139 that fills the first recess 130A, but does not include the second filling portion 40 (see FIG. 6 ) shown in the first embodiment. Even with this configuration, the first filling portion 139 that fills the first recess 130A reflects light emitted from the backlight device, allowing the light to be sufficiently and efficiently irradiated onto the channel forming portion 135D1 of the non-pixel semiconductor portion 135D.

[0070] <Embodiment 3> Embodiment 3 will be described with reference to Fig. 14. In this embodiment 3, the number of first recesses 230A, second recesses 229A, first non-overlapping portions 238B1, first filling portions 239, and second filling portions 240 is changed from that of embodiment 1 described above. Note that redundant explanations of the structure, action, and effects similar to those of embodiment 1 described above will be omitted.

[0071] As shown in FIG. 14 , the first interlayer insulating film 230 and the gate insulating film 229 according to this embodiment have a first recess 230A and a second recess 229A, respectively, spaced apart from the non-pixel source electrode 235B on the opposite side of the non-pixel drain electrode 235C in the X-axis direction. The first recess 230A and the second recess 229A are not formed in the first interlayer insulating film 230 and the gate insulating film 229 on the opposite side of the non-pixel drain electrode 235C from the non-pixel source electrode 235B in the X-axis direction. The first non-overlapping portion 238B1 is arranged on only one side of the overlapping portion 238A in the X-axis direction (the left side in FIG. 14 ), and is not arranged on the other side of the overlapping portion 238A in the X-axis direction (the right side in FIG. 14 ). The first filling portion 239 and the second filling portion 240 are each included in the first non-overlapping portion 238B1. The first filling portion 239 and the second filling portion 240, one each, are filled in the first recess 230A and the second recess 229A, respectively, which are arranged in the first interlayer insulating film 230 and the gate insulating film 229. Even in this configuration, the first filling portion 239 and the second filling portion 240, which are filled in the first recess 230A and the second recess 229A, reflect light emitted from the backlight device, and the light can be sufficiently and efficiently irradiated onto the channel forming portion 235D1 of the non-pixel semiconductor portion 235D.

[0072] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 15 or 16. In this fourth embodiment, the size of the light reflecting portion 338 is changed from that of the first embodiment. Note that redundant explanations of the structure, action, and effects similar to those of the first embodiment will be omitted.

[0073] As shown in FIGS. 15 and 16 , the light reflecting portion 338 according to this embodiment is larger in dimension in the X-axis direction than the non-pixel gate electrode 335A, but smaller in dimension in the Y-axis direction. The central portion of the light reflecting portion 338 in the X-axis direction is the overlapping portion 338A, while the opposite end portions in the X-axis direction are the paired non-overlapping portions 338B. The non-overlapping portion 338B does not include the second non-overlapping portion 38B2 (see FIG. 7 ) described in the first embodiment. The opposite end portions of the non-pixel gate electrode 335A in the Y-axis direction are exposed and not covered by the light reflecting portion 338. Even with this configuration, the same functions and effects as those of the first embodiment can be obtained.

[0074] <Embodiment 5> The fifth embodiment will be described with reference to Fig. 17 or 18. In this fifth embodiment, the configuration of the display area AA on the array substrate 421 is changed from that of the first embodiment. Note that redundant explanations of the structure, actions, and effects similar to those of the first embodiment will be omitted.

[0075] As shown in FIG. 17, the display region AA of the array substrate 421 according to this embodiment is provided with superimposed wiring (redundant wiring, spare wiring) 41 arranged to overlap the source wiring 427. Like the light reflecting portion 38 (see FIG. 6), the superimposed wiring 41 is made of a part of the third metal film. The superimposed wiring 41 is arranged to overlap the source wiring 427 on the upper layer side via a first interlayer insulating film 430. The superimposed wiring 41 extends parallel to the source wiring 427 and overlaps with the source wiring 427 over substantially the entire length thereof. A source contact hole CH2 is opened in the first interlayer insulating film 430 interposed between the superimposed wiring 41 and the source wiring 427 at a position overlapping both the superimposed wiring 41 and the source wiring 427. The superimposed wiring 41 and the source wiring 427 are connected to each other through the source contact hole CH2. In this way, since the parallel overlapping wiring 41 is connected to the source wiring 427, the wiring resistance is reduced, redundancy is provided in case of a break, and the yield is improved.

[0076] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0077] (1) The non-pixel gate electrodes 35A and 335A may be electrically connected to the light-reflecting portions 38, 138, and 338. In this case, a signal for driving the non-pixel TFT 35 is supplied to the light-reflecting portions 38, 138, and 338 at the same timing as the non-pixel gate electrodes 35A and 335A. In other words, the light-reflecting portions 38, 138, and 338 function as "upper-layer non-pixel gate electrodes," and the non-pixel TFT 35 has a double-gate structure. When driven, channel regions are generated on the lower side (the non-pixel gate electrode 35A and 335A side) and the upper side (the light-reflecting portion 38, 138, and 338 side) of the non-pixel semiconductor portions 35D, 135D, and 235D in the Z-axis direction.

[0078] (2) The non-pixel semiconductor portions 35D, 135D, and 235D may have a larger dimension in the X-axis direction than the non-pixel gate electrodes 35A and 335A. Also, the non-pixel semiconductor portions 35D, 135D, and 235D may have a larger dimension in the Y-axis direction than the non-pixel gate electrodes 35A and 335A.

[0079] (3) The non-pixel source electrode 35B, 235B may cover the end 35D2 of the non-pixel semiconductor portion 35D, 135D, 235D. The non-pixel drain electrode 35C, 235C may cover the end 35D3 of the non-pixel semiconductor portion 35D, 135D, 235D.

[0080] (4) The light reflecting portions 38, 138, 338 may be exposed without being covered by the second interlayer insulating film 31.

[0081] (5) The first filling portion 39, 139, 239 may be provided partially in the light reflecting portion 38, 138, 338 in the Y-axis direction. In this case, the first recess 30A, 130A, 230A may be formed over the same range in the Y-axis direction as the first filling portion 39, 139, 239, or may be provided over the entire length of the light reflecting portion 38, 138, 338 in the Y-axis direction. Furthermore, a plurality of first filling portions 39, 139, 239 may be provided side by side at intervals in the Y-axis direction.

[0082] (6) In the configurations described in the first, third to fifth embodiments, the second filling portion 40, 240 may be provided partially in the light reflecting portion 38, 338 in the Y-axis direction. In this case, the second recess 29A may be formed over the same range in the Y-axis direction as the second filling portion 40, 240, or may be provided over the entire length of the light reflecting portion 38, 338 in the Y-axis direction. Furthermore, a plurality of second filling portions 40, 240 may be provided side by side at intervals in the Y-axis direction.

[0083] (7) In the configurations described in the first, third to fifth embodiments, the second recess 29A may be provided as a recess that does not penetrate the gate insulating film 29, 229. In this case, the depth of the second recess 29A and the second filling portion 40, 240 is smaller than the film thickness of the gate insulating film 29, 229.

[0084] (8) In the configuration described in the second embodiment, the second recess 29A may be provided in the gate insulating film 129 at a position that overlaps one of the first recesses 130A.

[0085] (9) In the configuration described in the second embodiment, the first recess 130A may be provided as a recess that does not penetrate the first interlayer insulating film 130. In this case, the depth of the first recess 130A and the first filling portion 139 is smaller than the film thickness of the first interlayer insulating film 130.

[0086] (10) In the configuration described in embodiment 3, each of the first recess 230A, the second recess 229A, the first filling portion 239, and the second filling portion 240 may be arranged at a position spaced apart from the non-pixel drain electrode 235C on the opposite side of the non-pixel source electrode 235B in the X-axis direction.

[0087] (11) In the configuration described in embodiment 4, the difference between the dimension of the light reflecting portion 338 in the Y-axis direction and the dimension of the non-pixel gate electrode 335A in the Y-axis direction can be changed as appropriate to a value other than that shown in the drawings. Furthermore, the light reflecting portion 338 may be unevenly distributed in the Y-axis direction relative to the non-pixel gate electrode 335A.

[0088] (12) In the configuration described in the fifth embodiment, the superimposed wiring 41 may be disconnected from the source wiring 427. In this case, for example, if the source wiring 427 is disconnected, the superimposed wiring 41 may be short-circuited to the source wiring 427 by performing repair work such as irradiation with laser light.

[0089] (13) In addition to the above (12), if the liquid crystal panel 11 has a touch panel function, a touch signal may be supplied to the superimposed wiring 41. In this case, the common electrode 34 may be divided into a plurality of touch electrodes, and the superimposed wiring 41 may be connected to the touch electrodes.

[0090] (14) The configuration described in the second embodiment may be appropriately combined with the configurations described in the third to fifth embodiments.

[0091] (15) The configuration described in the third embodiment can be appropriately combined with the configuration described in the fourth or fifth embodiment.

[0092] (16) The configuration described in the fourth embodiment can be appropriately combined with the configuration described in the fifth embodiment.

[0093] (17) When the array substrate 21, 421 is provided with a switch circuit (SSD (Source Shared Driving) circuit) that distributes image signals supplied from the driver 12 to multiple source lines 27, 427, the non-pixel TFT 35 may be included in the switch circuit. Alternatively, the non-pixel TFT 35 may be provided as part of various circuits provided on the array substrate 21, 421.

[0094] (18) Instead of the circuit unit 14, a gate driver may be mounted on the array substrate 21, 421.

[0095] (19) The driver 12 may be mounted on the flexible substrate 13 by COF (Chip On Film) which is mounted on the array substrate 21, 421 by FOG (Film On Glass).

[0096] (20) The planar shape of the liquid crystal panel 11 may be a vertically long rectangle, a square, a circle, a semicircle, a vertically long oval, an ellipse, a trapezoid, or the like.

[0097] (21) The material of the semiconductor film provided on the array substrate 21, 421 may be an amorphous silicon material, a polycrystalline polysilicon material, or the like.

[0098] (22) The display mode of the liquid crystal panel 11 may be, other than the FFS mode, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, or the like.

[0099] (23) The display device may be other than the liquid crystal panel 11 (such as an organic EL (Electro Luminescence) display panel) or an EPD (microcapsule electrophoretic display panel). [Explanation of symbols]

[0100] 11...liquid crystal panel (display device), 14...circuit section, 21, 421...array substrate, 26...gate wiring (first wiring), 29, 129, 229...gate insulating film (first insulating film), 29A, 229A...second recess, 30, 130, 230, 430...first interlayer insulating film (second insulating film), 30A, 130A, 230A...first recess, 35...non-pixel TFT (transistor), 35A, 335A...non-pixel gate electrode (first electrode), 35B, 235B...non-pixel source electrode (second electrode), 35C, 235C... non-pixel drain electrode (third electrode), 35D, 135D, 235D... non-pixel semiconductor portion (semiconductor portion), 35D2, 35D3... end portion, 38, 138, 338... light reflecting portion, 38A, 238A, 338A... overlapping portion, 38B, 138B, 338B... non-overlapping portion, 38B1, 238B1... first non-overlapping portion, 38B2... second non-overlapping portion, 39, 139, 239... first filling portion, 40, 240... second filling portion, AA... display area, NAA... non-display area

Claims

1. A first electrode; a semiconductor portion provided above the first electrode and overlapping the first electrode; a second electrode provided on an upper layer side of the semiconductor portion and connected to the semiconductor portion; a transistor having a third electrode provided on an upper layer side of the semiconductor portion, arranged at an interval in the first direction from the second electrode, and connected to the semiconductor portion; a first insulating film provided above the first electrode and below the semiconductor portion; a second insulating film provided on an upper layer side of the second electrode and the third electrode; a light reflecting portion provided on an upper layer side of the second insulating film, a first recess is provided in the second insulating film at a position not overlapping the first electrode and the semiconductor portion; the light reflecting portion has an overlapping portion that overlaps with the first electrode and the semiconductor portion, and a non-overlapping portion that is continuous with the overlapping portion and does not overlap with the first electrode and the semiconductor portion, The array substrate, wherein the non-overlapping portion includes a first filling portion that is filled in the first recess.

2. the second insulating film is provided such that the first recess is disposed at a position spaced apart from at least one of the second electrode and the third electrode in the first direction; the non-overlapping portion includes a first non-overlapping portion arranged alongside the overlapping portion along the first direction, The array substrate according to claim 1 , wherein the first filling portion is included in the first non-overlapping portion.

3. the second insulating film is provided in pairs such that the first recesses are arranged at positions spaced apart from the second electrode in the first direction and at positions spaced apart from the third electrode in the first direction; the first non-overlapping portions are arranged in pairs to sandwich the overlapping portion in the first direction, 3. The array substrate according to claim 2, wherein the first filling portion is included in each of the pair of first non-overlapping portions.

4. the second insulating film is provided such that the first recess extends along a major surface of the first electrode and along a second direction intersecting the first direction; 4. The array substrate according to claim 2, wherein the first filling portion is provided so as to extend along the second direction.

5. 5. The array substrate according to claim 4, wherein the second electrode and the third electrode each extend in the second direction and are drawn out of the semiconductor portion.

6. 4. The array substrate according to claim 2, wherein the semiconductor portion is shorter than the first electrode in the first direction.

7. 4. The array substrate according to claim 2, wherein the non-overlapping portion includes a second non-overlapping portion arranged in parallel with the overlapping portion along a main surface of the first electrode and a second direction intersecting the first direction.

8. The array substrate according to claim 7 , wherein the semiconductor portion is shorter than the first electrode in the second direction.

9. 4. The array substrate according to claim 2, wherein the second electrode and the third electrode are arranged so as not to overlap with both ends of the semiconductor portion in the first direction.

10. the first recess is formed through the second insulating film; a second recess is provided in the first insulating film at a position overlapping the first recess and communicating with the first recess; 4. The array substrate according to claim 1, wherein the non-overlapping portion includes a second filling portion that is continuous with the first filling portion and that fills the second recess.

11. An array substrate according to any one of claims 1 to 3; a display area for displaying an image; a non-display area in which the image is not displayed, a first wiring is arranged in the display region of the array substrate; A display device in which a circuit section connected to the first wiring is arranged in the non-display area of ​​the array substrate, and the transistor is included in the circuit section.

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