Differential amplifier

Abstract

To provide a differential amplifier capable of suppressing the instability of a circuit while relaxing the limitation of the degree of freedom of layout more than before.SOLUTION: A solid-state imaging device is provided with: a pair of amplification transistors, one of the output terminals of which is connected in common; a direct-current voltage detection circuit which detects a first potential difference between the input terminal of the one transistor and the other of the output terminals of the one transistor and a second potential difference between the input terminal of the other transistor and the other of the output terminals of the other transistor; and one variable capacitor provided between the input terminal of the one transistor and the other of the output terminals of the other transistor and a second variable capacitor provided between the input terminal of the other transistor and the other of the output terminals of the one transistor. The DC voltage detection circuit sets the capacitances of the one variable capacitor and the second variable capacitor so as to increase the circuit stability index.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a differential amplifier. [Background technology]

[0002] As is well known, in the technical field of differential amplifiers, a technique is adopted to suppress circuit instability by positive feedback caused by capacitance between the gate and drain of a common-source transistor. A specific example of this technique is a cross-coupling capacitor structure in which capacitance is provided between the gate terminal and the drain terminal on the opposite phase side of the common-source transistor.

[0003] For example, Non-Patent Document 1 below discloses a differential amplifier that uses diode-connected transistors as the capacitance. In this differential amplifier, the capacitance changes in accordance with the voltage dependency between the gate and drain, thereby suppressing circuit instability. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] A 2 GHz high-gain differential InGaP HBT driver amplifier matched for high IP3 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the background art, a transistor of the same size as the common source transistor must be used as a capacitance, which limits the degree of freedom in layout.

[0006] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide a differential amplifier that can suppress circuit instability while alleviating restrictions on layout freedom compared to conventional techniques. [Means for solving the problem]

[0007] In order to achieve the above object, the present invention provides a differential amplifier as a first solution, a pair of amplifier transistors having one output terminal connected in common; The amplifier circuit includes a DC voltage detection circuit that detects a first potential difference between the input terminal of one of the amplifier transistors and the other of the output terminals of the one amplifier transistor and a second potential difference between the input terminal of the other amplifier transistor and the other of the output terminals of the other amplifier transistor, and a variable resistor provided between each of the input terminals of the pair of amplifier transistors, and / or one variable capacitor provided between the input terminal of one of the amplifier transistors and the other of the output terminals of the other amplifier transistor, and a second variable capacitor provided between the input terminal of the other amplifier transistor and the other of the output terminals of the one amplifier transistor, and the DC voltage detection circuit employs means for setting the capacitance of the one variable capacitor based on the first potential difference so that a circuit stability index becomes large, and setting the capacitance of the second variable capacitor based on the second potential difference so that the circuit stability index becomes large, and / or setting the resistance value of the variable resistor based on the first potential difference and the second potential difference so that the circuit stability index becomes large.

[0008] The present invention employs a second solution relating to a differential amplifier, which is the same as the first solution, in which the DC voltage detection circuit sets the capacitance of the one variable capacitor and the capacitance of the second variable capacitor so that the circuit stability index is maximized.

[0009] The present invention provides a third solution related to a differential amplifier, in which in the first or second solution, the DC voltage detection circuit sets the resistance value of the variable resistor to a small value, thereby setting the circuit stability index to a large value.

[0010] The present invention employs, as a fourth solution relating to the differential amplifier, any one of the first to third solutions, in which a cascade transistor is connected to each of the pair of amplifying transistors.

[0011] The present invention employs, as a fifth solution related to the differential amplifier, a solution in which, in any one of the first to fourth solutions, one of the output terminals of the pair of amplifying transistors is commonly connected to a ground potential. [Effects of the Invention]

[0012] According to the present invention, it is possible to provide a differential amplifier that can suppress instability of the circuit while alleviating restrictions on the degree of freedom of layout compared to conventional techniques. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a circuit diagram of a differential amplifier according to an embodiment of the present invention; [Figure 2] 4 is a characteristic diagram showing the operation of a differential amplifier according to one embodiment of the present invention; [Figure 3] 4 is a characteristic diagram showing the operation of a differential amplifier according to one embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the differential amplifier A of this embodiment includes a pair of input terminals T1 and T2, an input transformer 1, a variable resistor 2, a pair of amplifying transistors 3 and 4, a pair of cascade transistors 5 and 6, a pair of bias terminals T3 and T4, an output transformer 7, a pair of variable capacitors 8 and 9, a pair of output terminals T5 and T6, and a DC voltage detection circuit 10.

[0015] The pair of input terminals T1 and T2 are connection terminals that receive high-frequency signals with frequencies of several GHz to several tens of GHz from an external signal source. Of the pair of input terminals T1 and T2, one input terminal T1 is connected to one of a pair of input ends of the input transformer 1. The other input terminal T2 is connected to the other of the pair of input ends of the input transformer 1.

[0016] The input transformer 1 is a four-terminal element in which a primary winding and a secondary winding are magnetically coupled. In this input transformer 1, one end of the primary winding is one of the above-mentioned input terminals, and the other end of the primary winding is the other of the above-mentioned input terminals. That is, in this input transformer 1, one end of the primary winding is connected to one input terminal T1, and the other end of the primary winding is connected to the other input terminal T2.

[0017] One end of the secondary winding of this input transformer 1 is connected to one end of the variable resistor 2, the gate terminal of one amplifying transistor 3, one end of one variable capacitor 8, and a first input terminal IN1 of a DC voltage detection circuit 10. The other end of the secondary winding of this input transformer 1 is connected to the other end of the variable resistor 2, the gate terminal of the other amplifying transistor 4, one end of the other variable capacitor 9, and a second input terminal IN2 of the DC voltage detection circuit 10.

[0018] Such an input transformer 1 transforms a high-frequency signal input from a pair of input terminals T1, T2 to both ends of the primary winding in accordance with the turns ratio between the primary winding and the secondary winding, and outputs the signal from both ends of the secondary winding to one end of a variable resistor 2, the gate terminal of one amplifying transistor 3, one end of one variable capacitor 8, a first input terminal IN1 of a DC voltage detection circuit 10, the other end of the variable resistor 2, the gate terminal of the other amplifying transistor 4, one end of the other variable capacitor 9, and a second input terminal IN2 of the DC voltage detection circuit 10.

[0019] Here, the high-frequency signal output from one end of the secondary winding of the input transformer 1 has the same amplitude but opposite phase to the high-frequency signal output from the other end of the secondary winding of the input transformer 1. In other words, the input transformer 1 outputs a pair of high-frequency signals with the same amplitude but opposite phase.

[0020] The variable resistor 2 is a three-terminal element whose resistance value can be freely changed. One end of this variable resistor 2 is connected to one end of the secondary winding in the input transformer 1, the gate terminal of one amplifying transistor 3, one end of one variable capacitor 8, and a first input terminal IN1 of a DC voltage detection circuit 10. The other end of this variable resistor 2 is connected to the other end of the secondary winding in the input transformer 1, the gate terminal of the other amplifying transistor 4, one end of the other variable capacitor 9, and a second input terminal IN2 of the DC voltage detection circuit 10.

[0021] Furthermore, the control terminal of this variable resistor 2 is connected to the first output terminal OUT1 of the DC voltage detection circuit 10. The resistance value (variable resistance value) between one terminal and the other terminal of such variable resistor 2 is set based on a first setting signal input to the control terminal from the first output terminal OUT1 of the DC voltage detection circuit 10. As will be described in detail later, the variable resistance value of the variable resistor 2 is set to improve the stability of the differential amplification operation in the pair of amplification transistors 3 and 4, that is, to suppress instability of the circuit.

[0022] As shown in the figure, the pair of amplifying transistors 3 and 4 are MOS (Metal Oxide Semiconductor) type transistors, each of which has a gate terminal, a source terminal, and a drain terminal.

[0023] Here, the gate terminals of the pair of amplifying transistors 3 and 4 correspond to the input terminals of the pair of amplifying transistors of the present invention. Also, the source terminals of the pair of amplifying transistors 3 and 4 correspond to one of the output terminals of the pair of amplifying transistors of the present invention. Furthermore, the drain terminals of the pair of amplifying transistors 3 and 4 correspond to the other of the output terminals of the pair of amplifying transistors of the present invention.

[0024] Of the pair of amplifying transistors 3, 4, one amplifying transistor 3 has a gate terminal connected to one end of the secondary winding of the input transformer 1, one end of the variable resistor 2, one end of one variable capacitor 8, and a first input terminal IN1 of a DC voltage detection circuit 10. In addition, one amplifying transistor 3 has a source terminal grounded as shown, and a drain terminal connected to the source terminal of one cascade transistor 5, the other end of the other variable capacitor 9, and a third input terminal IN3 of the DC voltage detection circuit 10.

[0025] On the other hand, the other amplifying transistor 4 has a gate terminal connected to the other end of the secondary winding of the input transformer 1, the other end of the variable resistor 2, one end of the other variable capacitor 9, and a second input terminal IN2 of the DC voltage detection circuit 10. In addition, the other amplifying transistor 4 has a source terminal grounded as shown, and a drain terminal connected to the source terminal of the other cascade transistor 6, the other end of the first variable capacitor 8, and a fourth input terminal IN4 of the DC voltage detection circuit 10.

[0026] The pair of amplifier transistors 3 and 4 are common-source transistors whose source terminals (one of the output terminals) are commonly connected to ground potential (GND). The pair of amplifier transistors 3 and 4 differentially amplify high-frequency signals input to their gate terminals from both ends of the secondary winding of the input transformer 1, and output the amplified signals from their respective drain terminals (the other of the output terminals).

[0027] That is, the differentially amplified high-frequency signal output from the drain terminal of one amplifying transistor 3 has the same amplitude but the opposite phase to the differentially amplified high-frequency signal output from the drain terminal of the other amplifying transistor 4. That is, the pair of amplifying transistors 3 and 4 output a pair of high-frequency signals that have the same amplitude but opposite phases.

[0028] The pair of cascade transistors 5, 6 are MOS transistors, similar to the pair of amplifying transistors 3, 4, and each has a gate terminal, a source terminal, and a drain terminal. Of the pair of cascade transistors 5, 6, one cascade transistor 5 has a gate terminal connected to the first bias terminal T3, and a source terminal connected to the drain terminal of one amplifying transistor 3, the other end of the other variable capacitor 9, and the third input terminal IN3 of the DC voltage detection circuit 10. In addition, the drain terminal of one cascade transistor 5 is connected to one end of the primary winding of the output transformer 7.

[0029] The other cascade transistor 6 has a gate terminal connected to the second bias terminal T4, and a source terminal connected to the drain terminal of the other amplifying transistor 4, the other end of one variable capacitor 8, and the fourth input terminal IN4 of the DC voltage detection circuit 10. The other cascade transistor 6 has a drain terminal connected to the other end of the primary winding of the output transformer 7.

[0030] Such a pair of cascade transistors 5, 6 is provided between the pair of amplifier transistors 3, 4 and the output transformer 7 in order to increase the output impedance of the pair of amplifier transistors 3, 4. In other words, the pair of cascade transistors 5, 6 suppresses deterioration of frequency characteristics by increasing the output impedance.

[0031] The pair of bias terminals T3 and T4 are connection terminals that receive a predetermined bias voltage from an external bias power supply. One of the pair of bias terminals T3 and T4, the bias terminal T3, is connected to the gate terminal of one cascade transistor 5, and the other bias terminal T4 is connected to the gate terminal of the other cascade transistor 6.

[0032] The bias voltage is applied to the gate terminal of one cascade transistor 5 via one bias terminal T3, and is also applied to the gate terminal of the other cascade transistor 6 via the other bias terminal T4. That is, the same gate voltage is applied to the pair of cascade transistors 5 and 6 via the pair of bias terminals T3 and T4.

[0033] The output transformer 7 is a four-terminal element in which the primary winding and secondary winding are magnetically coupled. One end of the primary winding of this output transformer 7 is connected to the drain terminal of one cascade transistor 5, and the other end of the primary winding is connected to the drain terminal of the other cascade transistor 6. Furthermore, one end of the secondary winding of this output transformer 7 is connected to one output terminal T5, and the other end of the secondary winding is connected to the other output terminal T6.

[0034] Such an output transformer 7 transforms the differentially amplified high-frequency signal input from the pair of cascade transistors 5 and 6 to both ends of the primary winding in accordance with the turns ratio between the primary winding and the secondary winding, and outputs the result as an output signal from both ends of the secondary winding to a pair of output terminals T5 and T6.

[0035] The pair of variable capacitors 8, 9 are three-terminal elements whose capacitance value can be freely changed. One end of one of the pair of variable capacitors 8, 9, the variable capacitor 8, is connected to one end of the secondary winding of the input transformer 1, one end of the variable resistor 2, the gate terminal of one amplifying transistor 3, and the first input terminal IN1 of the DC voltage detection circuit 10.

[0036] The other end of one variable capacitor 8 is connected to the drain terminal of the other amplifying transistor 4, the source terminal of the other cascade transistor 6, and the fourth input terminal IN4 of the DC voltage detection circuit 10. Furthermore, the control terminal of one variable capacitor 8 is connected to the second output terminal OUT2 of the DC voltage detection circuit 10.

[0037] The capacitance (first variable capacitance) between one end and the other end of one variable capacitor 8 is set based on a second setting signal input to the control end from the second output end OUT2 of the DC voltage detection circuit 10. As will be described in detail later, the first variable capacitance is set to improve the stability of the differential amplification operation in the pair of amplification transistors 3 and 4, that is, to suppress instability of the circuit.

[0038] On the other hand, one end of the other variable capacitor 9 is connected to the other end of the secondary winding of the input transformer 1, the other end of the variable resistor 2, the gate terminal of the other amplifying transistor 4, and the second input terminal IN2 of the DC voltage detection circuit 10. The other end of the other variable capacitor 9 is connected to the drain terminal of one amplifying transistor 3, the source terminal of one cascade transistor 5, and the third input terminal IN3 of the DC voltage detection circuit 10, and its control terminal is connected to the third output terminal OUT3 of the DC voltage detection circuit 10.

[0039] The other variable capacitor 9 has a capacitance (second variable capacitance) set between one end and the other end based on a third setting signal input to the control end from the third output end OUT3 of the DC voltage detection circuit 10. Like the above-mentioned first variable capacitance, this second variable capacitance is set to improve the stability of the differential amplification operation in the pair of amplification transistors 3 and 4, that is, to suppress instability of the circuit.

[0040] The pair of output terminals T5, T6 are connection terminals for outputting output signals to an external subsequent circuit. Of the pair of output terminals T5, T6, one output terminal T5 is connected to one end of the secondary winding of the output transformer 7, and the other output terminal T6 is connected to the other end of the secondary winding of the output transformer 7. Such a pair of output terminals T5, T6 outputs a pair of output signals (high-frequency signals after differential amplification) in an opposite phase relationship to the subsequent circuit.

[0041] The DC voltage detection circuit 10 is a DC voltage detection circuit having first to fourth input terminals IN1 to IN4 and first to third output terminals OUT1 to OUT3. The first input terminal IN1 of this DC voltage detection circuit 10 is connected to one end of the secondary winding of the input transformer 1, one end of the variable resistor 2, the gate terminal of one amplifying transistor 3, and one end of one variable capacitor 8.

[0042] Furthermore, the second input terminal IN2 of this DC voltage detection circuit 10 is connected to the other end of the secondary winding of the input transformer 1, the other end of the variable resistor 2, the gate terminal of the other amplifying transistor 4, and one end of the other variable capacitor 9. Furthermore, the third input terminal IN3 of this DC voltage detection circuit 10 is connected to the drain terminal of one amplifying transistor 3, the source terminal of one cascade transistor 5, and the other end of the other variable capacitor 9. Furthermore, the fourth input terminal IN4 of this DC voltage detection circuit 10 is connected to the drain terminal of the other amplifying transistor 4, the source terminal of the other cascade transistor 6, and the other end of one variable capacitor 8.

[0043] Furthermore, the DC voltage detection circuit 10 has a first output terminal OUT1 connected to the control terminal of the variable resistor 2, and outputs a first setting signal from the first output terminal OUT1 to the control terminal of the variable resistor 2. Furthermore, the DC voltage detection circuit 10 has a second output terminal OUT2 connected to the control terminal of one of the variable capacitors 8, and outputs a second setting signal from the second output terminal OUT2 to the control terminal of one of the variable capacitors 8. Furthermore, the DC voltage detection circuit 10 has a third output terminal OUT3 connected to the control terminal of the other variable capacitor 9, and outputs a third setting signal from the third output terminal OUT3 to the control terminal of the other variable capacitor 9.

[0044] Such a DC voltage detection circuit 10 detects the gate-drain voltage of one of the amplifying transistors 3 as a first potential difference based on the DC voltage input to the first input terminal IN1, i.e., the gate voltage of one of the amplifying transistors 3, and the DC voltage input to the third input terminal IN3, i.e., the drain voltage of one of the amplifying transistors 3.

[0045] In addition, the DC voltage detection circuit 10 detects the gate-drain voltage of the other amplifying transistor 4 as a second potential difference based on the DC voltage input to the second input terminal IN2, i.e., the gate voltage of the other amplifying transistor 4, and the DC voltage input to the fourth input terminal IN4, i.e., the drain voltage of the other amplifying transistor 4.

[0046] Furthermore, the DC voltage detection circuit 10 generates first to third setting signals based on the first potential difference and the second potential difference. That is, the DC voltage detection circuit 10 generates the first to third setting signals so as to stabilize the differential amplification operation of the pair of amplification transistors 3 and 4, that is, to prevent destabilization of the differential amplifier A.

[0047] Next, the operation of the differential amplifier A according to this embodiment will be described with reference to FIGS.

[0048] In the differential amplifier A of this embodiment, a high-frequency signal input from a signal source to a pair of input terminals T1 and T2 is transformed by an input transformer 1 and then differentially amplified by a pair of amplifying transistors 3 and 4. The differential amplifier A then transforms the high-frequency signal after differential amplification by inputting it to an output transformer 7 via a pair of cascade transistors 5 and 6, and outputs the signal to a subsequent circuit as a pair of output signals from a pair of output terminals T5 and T6.

[0049] In such basic operation of the differential amplifier A, the variable resistor 2, the pair of variable capacitors 8 and 9, and the DC voltage detection circuit 10 function (act) to stabilize the differential amplification operation of the pair of amplifying transistors 3 and 4, i.e., to prevent the differential amplifier A from becoming unstable.

[0050] That is, the DC voltage detection circuit 10 detects the gate-drain voltage of one of the amplification transistors 3 as a first potential difference based on the gate voltage of one of the amplification transistors 3 and the drain voltage of one of the amplification transistors 3, and detects the gate-drain voltage of the other amplification transistor 4 as a second potential difference based on the gate voltage of the other amplification transistor 4 and the drain voltage of the other amplification transistor 4.

[0051] The DC voltage detection circuit 10 generates a first setting signal based on the average value of the first potential difference and the second potential difference, and also generates a second setting signal based on the first potential difference and a third setting signal based on the second potential difference.

[0052] Here, the second setting signal and the third setting signal are used to set the variable capacitances of the pair of variable capacitors 8 and 9 so as to increase the "k factor," which is known as a circuit stability index of a high-frequency amplifier circuit, as shown in Fig. 2. In other words, the second setting signal and the third setting signal are used to set the variable capacitances of the pair of variable capacitors 8 and 9 so that the "k factor" is at its maximum value.

[0053] In contrast, the first setting signal sets the variable resistance value of the variable resistor 2 so that the "k factor" becomes larger, as shown in Figure 3. In other words, the first setting signal sets the variable resistance value of the variable resistor 2 to a smaller value, thereby setting the "k factor" to a larger value.

[0054] The differential amplifier A of this embodiment includes a pair of amplifying transistors 3 and 4 whose source terminals (one of the output terminals) are commonly connected, a DC voltage detection circuit 10 (direct-current voltage detection circuit) that detects a first potential difference between the gate terminal (input terminal) of one amplifying transistor 3 and the drain terminal (the other of the output terminals) of one amplifying transistor 3 and a second potential difference between the gate terminal (input terminal) of the other amplifying transistor 4 and the drain terminal (the other of the output terminals) of the other amplifying transistor 4, a variable resistor 2 provided between the gate terminals (input terminals) of the pair of amplifying transistors 3 and 4, one variable capacitor 8 provided between the gate terminal (input terminal) of one amplifying transistor 3 and the drain terminal (the other of the output terminals) of the other amplifying transistor 4, and the other variable capacitor 9 provided between the gate terminal (input terminal) of the other amplifying transistor 4 and the drain terminal (the other of the output terminals) of one amplifying transistor 3.

[0055] Furthermore, in the differential amplifier A according to this embodiment, the DC voltage detection circuit 10 (direct current voltage detection circuit) sets the capacitance of one variable capacitor 8 based on the first potential difference so that the k factor (circuit stability index) becomes large, sets the capacitance of the other variable capacitor 9 based on the second potential difference so that the k factor (circuit stability index) becomes large, and sets the resistance value of the variable resistor 2 based on the first potential difference and the second potential difference so that the k factor (circuit stability index) becomes large.

[0056] According to this embodiment, the DC voltage detection circuit 10 (direct current voltage detection circuit) sets the capacitances of the first and second variable capacitors 8 and 9 and the resistance value of the variable resistor 2 so that the k factor (circuit stability index) becomes large based on the first potential difference and the second potential difference, so there is no need to provide a transistor of the same size as the pair of amplification transistors 3 and 4 (common source transistors) as capacitance near the pair of amplification transistors 3 and 4 (common source transistors).

[0057] The DC voltage detection circuit 10 (DC voltage detection circuit) in this embodiment inputs and outputs a DC voltage and first to third setting signals, and does not need to be provided near the pair of amplification transistors 3 and 4 (common-source transistors). Therefore, this embodiment can provide a differential amplifier A that can suppress circuit instability while alleviating restrictions on the degree of freedom of layout compared to conventional devices.

[0058] Furthermore, in the differential amplifier A according to this embodiment, the DC voltage detection circuit 10 (direct current voltage detection circuit) sets the capacitance of one variable capacitor 8 and the capacitance of the other variable capacitor 9 so that the k factor (circuit stability index) is maximized. According to this embodiment, it is possible to minimize circuit instability while alleviating restrictions on the degree of freedom of layout compared to conventional techniques.

[0059] In the differential amplifier A according to this embodiment, cascade transistors 5 and 6 are connected to the pair of amplifying transistors 3 and 4. According to this embodiment, it is possible to suppress instability of the circuit while alleviating restrictions on the degree of freedom of layout compared to conventional techniques, and also to suppress deterioration of frequency characteristics.

[0060] Furthermore, in the differential amplifier A according to this embodiment, the source terminals (one of the output terminals) of the pair of amplifying transistors 3 and 4 are commonly connected to the ground potential (GND). According to this embodiment, it is possible to suppress instability of the circuit while alleviating restrictions on the degree of freedom of layout compared to conventional techniques, and it is also possible to differentially amplify high frequency signals with a small number of components.

[0061] The present invention is not limited to the above-described embodiment, and the following modifications are possible. (1) In the above embodiment, the variable resistor 2 is provided in addition to the first and second variable capacitors 8 and 9 to increase the k factor (circuit stability index), but the present invention is not limited to this. The variable resistor 2 may be omitted as necessary, and circuit instability may be suppressed only by adjusting the variable capacitance of the first and second variable capacitors 8 and 9. Furthermore, of the first and second variable capacitors 8 and 9 and the variable resistor 2, the first and second variable capacitors 8 and 9 may be omitted, and circuit instability may be suppressed only by adjusting the variable resistance value of the variable resistor 2.

[0062] (2) Although the differential amplifier A has been described as having a configuration in which the source terminals (one of the output terminals) of a pair of amplifying transistors 3 and 4 (common-source transistors) are commonly connected to the ground potential (GND), the present invention is not limited to this. The present invention can also be applied to a differential amplifier having a configuration in which a resistor or a constant current source is commonly connected to the source terminals (one of the output terminals) of the common-source transistors.

[0063] (3) In the above embodiment, MOS transistors are used as the pair of amplification transistors 3 and 4 (common-source transistors), but the present invention is not limited to this. Bipolar transistors or unipolar transistors other than MOS transistors may also be used as the pair of amplification transistors in the present invention.

[0064] (4) In the above embodiment, a pair of cascade transistors 5 and 6 is provided between the pair of amplifier transistors 3 and 4 (common-source transistors) and the output transformer 7, but the present invention is not limited to this. The pair of cascade transistors 5 and 6 may be omitted as necessary. In other words, the pair of amplifier transistors 3 and 4 (common-source transistors) and the output transformer 7 may be directly connected. [Explanation of symbols]

[0065] A differential amplifier, T1, T2 input terminals, T3, T4 bias terminals, T5, T6 output terminals, 1 input transformer, 2 variable resistor, 3, 4 amplifying transistors, 5, 6 cascade transistors, 7 output transformer, 8, 9 variable capacitors, 10 DC voltage detection circuit (direct current voltage detection circuit)

Claims

1. a pair of amplifier transistors having one output terminal connected in common; a DC voltage detection circuit that detects a first potential difference between the input terminal of one of the amplifier transistors and the other of the output terminals of the one of the amplifier transistors and a second potential difference between the input terminal of the other of the amplifier transistors and the other of the output terminals of the other of the amplifier transistors; a variable resistor provided between each of the input terminals of the pair of amplifier transistors, or / and one variable capacitor provided between the input terminal of one of the amplifier transistors and the other of the output terminals of the other amplifier transistor, and a second variable capacitor provided between the input terminal of the other amplifier transistor and the other of the output terminals of the one amplifier transistor, The DC voltage detection circuit sets the capacitance of one of the variable capacitors based on the first potential difference so that the circuit stability index becomes larger, sets the capacitance of the second variable capacitor based on the second potential difference so that the circuit stability index becomes larger, and / or sets the resistance value of the variable resistor based on the first potential difference and the second potential difference so that the circuit stability index becomes larger.

2. 2. The differential amplifier according to claim 1, wherein the DC voltage detection circuit sets the capacitance of the one variable capacitor and the capacitance of the second variable capacitor so that the circuit stability index is maximized.

3. 3. The differential amplifier according to claim 1, wherein the DC voltage detection circuit sets the circuit stability index to a large value by setting the resistance value of the variable resistor to a small value.

4. 3. The differential amplifier according to claim 1, wherein a cascade transistor is connected to each of the pair of amplifier transistors.

5. 3. The differential amplifier according to claim 1, wherein one of the output terminals of the pair of amplifying transistors is commonly connected to a ground potential.

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