Display driver and display device

Abstract

PURPOSE: To provide a display driver and a display device capable of suppressing flicker.CONSTITUTION: The present invention employs, as each of first to k-th gamma amplifier circuits that output first to k-th compensation reference gamma voltages obtained by amplifying first to k-th reference gamma voltages in accordance with a predetermined gamma characteristic, a gamma amplifier circuit including a differential amplifier circuit and an offset cancellation circuit described below. That is, the differential amplifier circuit flows a pair of currents corresponding to the difference between the reference gamma voltage and the compensation reference gamma voltage to the pair of nodes, and outputs the voltage of at least one node as the compensation reference gamma voltage. The offset cancellation circuit receives a voltage of a common electrode of the display panel as a feedback common voltage, and causes a pair of currents corresponding to a difference between a difference between the reference common voltage and the compensation reference gamma voltage and a difference between the feedback common voltage and the reference gamma voltage to flow through a pair of nodes of the differential amplifier circuit. Thus, the offset cancel circuit causes the differential amplifier circuit to output, as the compensation reference gamma voltage, a voltage obtained by superimposing the voltage variation on the common electrode on the reference gamma voltage.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a display driver that drives a display panel in response to a video signal, and a display device. [Background technology]

[0002] Recently, gaming monitors have been attracting attention as LCD display devices with performance suited to playing games comfortably. Gaming monitors display images at a higher refresh rate than regular monitors, thereby reducing display delay and realizing smooth image display.

[0003] By the way, video sources used in PC games, for example, where each frame is generated through real-time rendering, are what is known as variable frame rate video, meaning that the time it takes to render each frame varies depending on the rendering load at the time. Therefore, if the refresh rate of the monitor receiving such a video source is fixed, an incorrect image will be displayed.

[0004] Therefore, gaming monitors equipped with a variable refresh rate synchronization function that can dynamically change the refresh rate to follow a variable frame rate video source are now mainstream.

[0005] However, when the refresh rate on the gaming monitor changes dynamically, the brightness of the entire screen changes due to fluctuations in the gamma characteristics that accompany the change in refresh rate, which can be seen as flickering.

[0006] Therefore, a liquid crystal display device has been proposed that detects the refresh rate, reads out from memory the gamma value of the image that is optimal for that refresh rate, and changes the gamma characteristics using the read gamma value to suppress flicker (see, for example, Patent Document 1). In this liquid crystal display device, a timing controller included therein receives an enable signal and a clock signal that indicate the display timing along with the display data, and detects the refresh rate based on these enable and clock signals. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-330292

[0008] [overview] However, the liquid crystal display device described in Patent Document 1 has a problem in that a change in refresh rate causes a fluctuation in the voltage of a common electrode provided in common to each pixel of the display panel, resulting in flicker, which is an instantaneous change in display brightness.Furthermore, even in organic EL (Electro Luminescence) display devices in which such voltage fluctuations in the common electrode are likely to occur, there is a problem in that flicker occurs due to the voltage fluctuations in the common electrode.

[0009] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a display driver and a display device that are capable of suppressing the occurrence of flicker.

[0010] A display driver according to the present invention is a display driver for driving a display panel having a plurality of data lines on each of which a plurality of display cells are arranged and a common electrode connected in common to the plurality of display cells, and includes: first to k-th gamma amplifier circuits (k is an integer of 2 or more) that receive first to k-th reference gamma voltages (where k is an integer of 2 or more) according to predetermined gamma characteristics, and output first to k-th compensated reference gamma voltages by individually amplifying the first to k-th reference gamma voltages; a grayscale voltage generation circuit that generates a plurality of grayscale voltages based on the first to k-th compensated reference gamma voltages; and a D / A conversion unit that selects, from the plurality of grayscale voltages, a grayscale voltage corresponding to a display data piece for each of the display cells indicated by a video signal, and supplies a plurality of drive voltages obtained by amplifying the plurality of grayscale voltages selected for each of the display data pieces to the plurality of data lines; Each of the 1st to kth gamma amplifier circuits includes a differential amplifier circuit that receives the reference gamma voltage it receives and the compensated reference gamma voltage it outputs at a pair of input terminals thereof, flows a pair of currents corresponding to the difference between the two into a pair of nodes, and outputs the voltage of at least one of the pair of nodes as the compensated reference gamma voltage; and an offset cancellation circuit that takes in the voltage of the common electrode from the display panel as a feedback common voltage, and flows a pair of currents corresponding to the difference between a difference between a predetermined reference common voltage and the compensated reference gamma voltage and the difference between the feedback common voltage and the reference gamma voltage into the pair of nodes of the differential amplifier circuit, thereby causing the differential amplifier circuit to output a voltage in which a voltage fluctuation occurring in the common electrode is superimposed on the reference gamma voltage as the compensated reference gamma voltage.

[0011] Further, a display device according to the present invention is a display device comprising: a display panel having a plurality of data lines, each having a plurality of display cells arranged thereon, and a common electrode connected in common to the plurality of display cells; and a display driver for driving the display panel based on a video signal, wherein the display driver comprises: a common voltage generation unit that receives a reference common voltage, generates a common voltage having a voltage value of the reference common voltage, and applies the generated common voltage to the common electrode; first to k-th gamma amplifier circuits that receive first to k-th (k is an integer of 2 or more) reference gamma voltages according to a predetermined gamma characteristic, and output first to k-th compensated reference gamma voltages by individually amplifying the first to k-th reference gamma voltages; a grayscale voltage generation circuit that generates a plurality of grayscale voltages based on the first to k-th compensated reference gamma voltages; and a grayscale voltage generation circuit that selects, from the plurality of grayscale voltages, a grayscale voltage corresponding to a display data piece for each of the display cells indicated by a video signal, and generates a grayscale voltage for each of the display data pieces. and a DA conversion unit that supplies a plurality of drive voltages obtained by amplifying a plurality of the gradation voltages to the plurality of data lines, wherein each of the first to kth gamma amplifier circuits includes a differential amplifier circuit that receives the reference gamma voltage it receives and the compensated reference gamma voltage it outputs at a pair of input terminals thereof, flows a pair of currents corresponding to the difference between the reference gamma voltages and the compensated reference gamma voltage to a pair of nodes, and outputs the voltage of at least one of the pair of nodes as the compensated reference gamma voltage; and an offset cancellation circuit that takes in the voltage of the common electrode from the display panel as a feedback common voltage, and flows a pair of currents corresponding to the difference between the difference between the reference common voltage and the compensated reference gamma voltage and the difference between the feedback common voltage and the reference gamma voltage to the pair of nodes of the differential amplifier circuit, thereby causing a voltage in which a voltage fluctuation occurring in the common electrode is superimposed on the reference gamma voltage to be output from the differential amplifier circuit as the compensated reference gamma voltage. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram showing a configuration of a display device 100 including a display driver according to the present invention. [Figure 2] FIG. 2 is a circuit diagram showing an example of an equivalent circuit of a display cell PC. [Figure 3]FIG. 2 is a block diagram showing the internal configuration of a data driver 13. [Figure 4] 10 is a block diagram showing an example of the internal configuration of a grayscale voltage generating section 133. FIG. [Figure 5] FIG. 2 is a circuit diagram showing the internal configuration of a gamma amplifier circuit GA1. [Figure 6] 10 is a time chart showing the transition of the contents of switch signals S1 to S9. [Figure 7A] FIG. 10 is a schematic circuit diagram in which the on / off states of the switch elements SW1 to SW9 of the gamma amplifier circuit GA1 and the current paths are indicated by thick solid lines in the first step. [Figure 7B] FIG. 10 is a schematic circuit diagram in which the on / off states of the switch elements SW1 to SW9 of the gamma amplifier circuit GA1 and the current paths are indicated by thick solid lines in the second step. [Figure 8] 4 is a waveform diagram showing an example of the waveforms of a feedback common voltage Vcom_FB and compensation reference gamma voltages G_UH, G_UL, G_LH, and G_LL. FIG.

[0013] [Detailed explanation] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0014] FIG. 1 is a block diagram showing the configuration of a display device 100 according to the present invention.

[0015] The display device 100 is, for example, a liquid crystal display device or an organic EL (Electro Luminescence) display device with a variable refresh rate synchronization function, and has a drive control unit 11, a scanning driver 12, a display panel 20, a data driver 13 as a display driver according to the present invention, and a common voltage generation unit 14.

[0016] The display panel 20 is arranged with crossing scan lines SL1 to SLm (m is an integer of 2 or greater), each extending in the horizontal direction of the two-dimensional screen, and data lines D1 to Dn (n is an integer of 2 or greater), each extending in the vertical direction of the two-dimensional screen. Display cells PC, which are liquid crystal display elements or organic EL display elements, are formed at the intersections of the scan lines and data lines. Furthermore, the display panel 20 is formed with a plate-shaped common electrode CE, a terminal TM0 for inputting a common voltage to the common electrode CE, and a terminal TM1 for extracting the voltage from the common electrode CE.

[0017] FIG. 2 is an equivalent circuit diagram that extracts a display cell PC formed at the intersection of a data line D1 and a scan line SL1 and equivalently represents the configuration of the display cell PC, which is made up of, for example, a liquid crystal display element.

[0018] 2, each display cell PC includes a pixel electrode EL and a liquid crystal layer LC stacked on a common electrode CE, and a MOS thin-film transistor TR serving as a pixel switch. The pixel electrode EL is a transparent electrode provided independently for each display cell PC, and the common electrode CE is a single transparent electrode formed corresponding to the formation area of ​​all display cells PC on the display panel 20. The gate of the transistor TR is connected to a scan line SL1, and the source of the transistor TR is connected to a data line D1. Furthermore, the drain of the transistor TR is connected to the pixel electrode EL.

[0019] 1, a drive control unit 11 receives a video signal VS, detects a horizontal synchronization signal from the video signal VS, and supplies the detected horizontal synchronization signal to a scan driver 12. Based on the video signal VS, the drive control unit 11 generates a video data signal VPD including horizontal and vertical synchronization signals, a string of display data pieces that represent the luminance level of each display cell PC in, for example, 8-bit gradation, and various control signals, and supplies this to a data driver 13. The drive control unit 11 adjusts the length of the vertical blanking period within each frame of the video data signal VPD so that it follows the frequency of the vertical synchronization signal of the video signal VS.

[0020] The scan driver 12 sequentially and selectively applies a selection signal including a selection pulse to each of the scan lines SL1 to SLm in response to a horizontal synchronization signal.

[0021] The data driver 13 converts each of n display data pieces for one horizontal scan in the series of display data pieces included in the video data signal VPD into a gradation voltage corresponding to the luminance level represented by the display data piece. The data driver 13 then amplifies the gradation voltages corresponding to the n display data pieces to generate n drive voltages G1 to Gn, which are applied to the data lines D1 to Dn of the display panel 20, respectively.

[0022] Furthermore, the data driver 13 receives the reference common voltage Vcom_RF and also takes in the voltage on the common electrode CE as a feedback common voltage Vcom_FB from the terminal TM1 of the display panel 20. Then, the data driver 13 adjusts the voltage value of the grayscale voltage based on the difference between the reference common voltage Vcom_RF and the feedback common voltage Vcom_FB.

[0023] The data driver 13 is formed on a single semiconductor chip or is divided into a plurality of semiconductor chips.

[0024] The common voltage generation unit 14 receives a reference common voltage Vcom_RF and generates, based on the reference common voltage Vcom_RF, a DC common voltage Vcom that is an intermediate voltage within the range of voltage values ​​that can be used as a gradation voltage, i.e., a voltage that is the boundary between the positive and negative voltage values ​​of the gradation voltage. The common voltage generation unit 14 supplies the common voltage Vcom to a terminal TM0 of the display panel 20. As a result, the common voltage Vcom is applied to all display cells PC formed in the display panel 20 via the common electrode CE. The common voltage generation unit 14 is formed on a semiconductor chip separate from the semiconductor chip on which the data driver 13 is formed. Note that the common voltage generation unit 14 may also be formed within the semiconductor chip on which the data driver 13 is formed.

[0025] FIG. 3 is a block diagram showing an example of the internal configuration of the data driver 13. As shown in FIG.

[0026] As shown in FIG. 3, the data driver 13 includes a data latch unit 131, a DA conversion unit 132, and a grayscale voltage generation unit 133.

[0027] The data latch unit 131 takes in every n pieces of display data included in the video data signal VPD for one horizontal scan, and supplies them to the DA conversion unit 132 as display data P1 to Pn.

[0028] The grayscale voltage generation unit 133 generates a set of 256 positive voltages, each having a different voltage value higher than the common voltage Vcom, and a set of 256 negative voltages, each having a different voltage value lower than the common voltage Vcom. The grayscale voltage generation unit 133 supplies the generated set of 256 positive voltages to the DA conversion unit 132 as grayscale voltages V0 to V255, each having a positive voltage value that represents the luminance level in 256 steps. Furthermore, the grayscale voltage generation unit 133 supplies the generated set of 256 negative voltages to the DA conversion unit 132 as grayscale voltages Y0 to Y255, each having a negative voltage value that represents the luminance level in 256 steps. The grayscale voltages V0 to V255 and Y0 to Y255 each have a voltage value that conforms to a predetermined gamma characteristic.

[0029] The grayscale voltage generation unit 133 receives the reference common voltage Vcom_RF and the feedback common voltage Vcom_FB, and adjusts the voltage values ​​of the grayscale voltages V0 to V255 and Y0 to Y255 based on the difference between the reference common voltage Vcom_RF and the feedback common voltage Vcom_FB.

[0030] The DA conversion unit 132 includes n decoders (DEC). Each decoder (DEC) is provided corresponding to each of the display data P1 to Pn, and receives grayscale voltages V0 to V255 and Y0 to Y255. Each decoder selects one grayscale voltage from the grayscale voltages V0 to V255 and Y0 to Y255 that corresponds to the luminance level indicated by the display data P received by that decoder, amplifies the selected grayscale voltage, and applies the amplified voltage to the corresponding data line D of the display panel 20 as a drive voltage.

[0031] That is, for each of the display data P1 to Pn, the DA conversion unit 132 selects a gradation voltage corresponding to the luminance level represented by the display data P from among the gradation voltages V0 to V255 and Y0 to Y255. Then, the DA conversion unit 132 individually amplifies the n gradation voltages obtained by selecting for each of the display data P1 to Pn, and outputs the amplified voltages as the above-mentioned drive voltages G1 to Gn to the data lines D1 to Dn of the display panel.

[0032] Next, the configurations of the above-mentioned grayscale voltage generating section 133 and common voltage generating section 14 will be described in detail.

[0033] FIG. 4 is a block diagram showing the internal configuration of the grayscale voltage generating section 133 and the common voltage generating section 14. As shown in FIG.

[0034] 4, the common voltage generating unit 14 includes an amplifier 1340 configured, for example, by an operational amplifier having a voltage follower configuration. The amplifier 1340 amplifies the reference common voltage Vcom_RF and outputs the amplified voltage as the common voltage Vcom. On the other hand, the grayscale voltage generating unit 133 includes a control circuit 1330, a reference gamma voltage generating unit 1331, a gamma amplifier unit 1332, and a grayscale voltage generating circuit 1333, as shown in FIG.

[0035] The control circuit 1330 generates switch signals S1 to S9, each of which specifies ON or OFF, for controlling the operation of an offset cancellation circuit (described later), and supplies the signals to the gamma amplifier unit 1332.

[0036] The reference gamma voltage generation unit 1331 generates a reference gamma voltage G_UL_RF, which is higher than the reference common voltage Vcom_RF and has a voltage value in accordance with the predetermined gamma characteristic. The reference gamma voltage generation unit 1331 also generates a reference gamma voltage G_UH_RF, which is higher than the reference gamma voltage G_UL_RF and has a voltage value in accordance with the predetermined gamma characteristic. The reference gamma voltage generation unit 1331 also generates a reference gamma voltage G_LH_RF, which is lower than the reference common voltage Vcom_RF and has a voltage value in accordance with the predetermined gamma characteristic. The reference gamma voltage generation unit 1331 also generates a reference gamma voltage G_LL_RF, which is lower than the reference gamma voltage G_LH_RF and has a voltage value in accordance with the predetermined gamma characteristic.

[0037] That is, the reference gamma voltage generation unit 1331 generates the following: G_UH_RF>G_UL_RF>Vcom_RF>G_LH_RF>G_LL_RF Hereinafter, the reference gamma voltages G_UH_RF and G_UL_RF that are higher than the reference common voltage Vcom_RF are treated as positive voltages, and the reference gamma voltages G_LH_RF and G_LL_RF that are lower than the reference common voltage Vcom_RF are treated as negative voltages.

[0038] The reference gamma voltage generation unit 1331 supplies the reference gamma voltages G_UH_RF, G_UL_RF, G_LH_RF, and G_LL_RF generated as described above to the gamma amplifier unit 1332.

[0039] The gamma amplifier unit 1332 receives the reference gamma voltages G_UH_RF, G_UL_RF, G_LH_RF, and G_LL_RF, as well as the switch signals S1 to S9, the reference common voltage Vcom_RF, and the feedback common voltage Vcom_FB.

[0040] The gamma amplifier unit 1332 includes gamma amplifier circuits GA1 to GA4, each equipped with an offset cancellation function. The gamma amplifier circuits GA1 to GA4 individually receive the above-mentioned reference gamma voltages G_UH_RF, G_UL_RF, G_LH_RF, and G_LL_RF. Furthermore, each of the gamma amplifier circuits GA1 to GA4 commonly receives the above-mentioned switch signals S1 to S9, the reference common voltage Vcom_RF, and the feedback common voltage Vcom_FB.

[0041] The gamma amplifier circuits GA1 to GA4 amplify the reference gamma voltages G_UH_RF, G_UL_RF, G_LH_RF and G_LL_RF, and generate compensated reference gamma voltages G_UH, G_UL, G_LH and G_LL based on the reference common voltage Vcom_RF and the feedback common voltage Vcom_FB, compensating for the voltage fluctuations in the common voltage Vcom that occur therein.

[0042] The gamma amplifier unit 1332 supplies the compensated reference gamma voltages G_UH, G_UL, G_LH, and G_LL generated by the gamma amplifier circuits GA1 to GA4 to the grayscale voltage generation circuit 1333.

[0043] FIG. 5 is a circuit diagram showing the internal configuration of the gamma amplifier circuit GA1 selected from the gamma amplifier circuits GA1 to GA4.

[0044] As shown in FIG. 5, the gamma amplifier circuit GA1 includes a differential amplifier circuit OPA and an offset cancellation circuit OFC.

[0045] The differential amplifier circuit OPA includes N-channel transistors Q1 and Q2, P-channel transistors Q5 and Q6, a current source Id, and an output stage Ba.

[0046] The transistor Q1 receives at its gate the reference gamma voltage G_UH_RF supplied from the reference gamma voltage generation unit 1331 via a node nd1 serving as a first input terminal of the differential amplifier circuit OPA. The source of the transistor Q1 is connected to the source of the transistor Q2 and the current source Id, and the drain is connected to the drain of the transistor Q6 via a node nd11.

[0047] The drain of the transistor Q2 is connected to the drain and gate of the transistor Q5 via the node nd12, and the gate of the transistor Q2 is connected to one end of each of the switch elements SW1 and SW2 via the node nd2 serving as the second input end of the differential amplifier circuit OPA.

[0048] A current source Id generates a predetermined constant current Igma and sinks the constant current Igma from the junction of the sources of transistors Q1 and Q2.

[0049] Therefore, the transistors Q1 and Q2 form a differential pair (Q1, Q2) of the differential amplifier circuit OPA.

[0050] The gates of the transistors Q5 and Q6 are connected to each other, and the sources of the transistors Q5 and Q6 receive the power supply voltage VDD, forming a so-called current mirror circuit. That is, the current mirror circuit outputs a current that is a copy of the current flowing through the input node nd12 to the output node nd11. At this time, the voltage generated at the output node nd11 is output as the compensated reference gamma voltage G_UH via the output stage Ba.

[0051] With the above-described configuration, the differential amplifier circuit OPA outputs a voltage obtained by amplifying the reference gamma voltage G_UH_RF received at its first input terminal (nd1) as the compensated reference gamma voltage G_UH.

[0052] On the other hand, the offset cancellation circuit OFC includes N-channel transistors Q3 and Q4, a current source Is, switch elements SW1 to SW9, and capacitors Ca and Cb.

[0053] The drain of the transistor Q3 is connected to the node nd12 on the input side of the differential amplifier circuit OPA, and the gate of the transistor Q3 is connected to one end of each of the switch elements SW3 and SW7 via the node nd3. The source of the transistor Q3 is connected to the source of the transistor Q4 and the current source Is.

[0054] The transistor Q4 has its gate connected to the node nd4 and its drain connected to a node nd11 on the output side of the differential amplifier circuit OPA.

[0055] The current source Is generates a predetermined constant current Ivcom and draws the constant current Ivcom from the junction between the sources of the transistors Q3 and Q4. In order to accurately superimpose the voltage change of the feedback common voltage Vcom_FB-reference common voltage Vcom_RF on the compensation reference gamma voltages G_UH, G_UL, G_LH, and G_LL, the constant current Ivcom generated by the current source Is must be equal to the constant current Igma generated by the current source Id.

[0056] Therefore, the transistors Q3 and Q4 form a differential pair (Q3, Q4) of the offset cancellation circuit OFC.

[0057] The switch element SW1 receives a switch signal S1 and is set to an on or off state in accordance with the switch signal S1. When the switch element SW1 is set to an on state, it short-circuits the nodes nd1 and nd2 together.

[0058] The switch element SW2 receives the switch signal S2 and is set to an on or off state in accordance with the switch signal S2. When the switch element SW2 is set to an on state, it supplies the compensated reference gamma voltage G_UH described above to the gate of the transistor Q2.

[0059] The switch element SW3 receives a switch signal S3 and is set to an on or off state in accordance with the switch signal S3. When the switch element SW3 is set to an on state, the switch element SW3 supplies the compensated reference gamma voltage G_UH to the gate of the transistor Q3 via the node nd3.

[0060] The switch element SW4 receives a switch signal S4 and is set to an on or off state in accordance with the switch signal S4. When set to an on state, the switch element SW4 supplies the reference gamma voltage G_UH_RF to the gate of the transistor Q4 via a node nd4.

[0061] The switch element SW5 receives a switch signal S5 and is set to an ON or OFF state in accordance with the switch signal S5. When the switch element SW5 is set to an ON state, it supplies the compensated reference gamma voltage G_UH to one end of the capacitor Cb.

[0062] The switch element SW6 receives a switch signal S6 and is set to an on or off state in accordance with the switch signal S6. When the switch element SW6 is set to an on state, it supplies one end of the capacitor Cb to the gate of the transistor Q4 via the node nd4. The switch element SW7 receives a switch signal S7 and is set to an on or off state in accordance with the switch signal S7. When the switch element SW7 is set to an on state, it supplies one end of the capacitor Ca to the gate of the transistor Q3 via the node nd3. The other end of the capacitor Ca is supplied with the above-mentioned reference common voltage Vcom_RF.

[0063] The switch element SW8 receives a switch signal S8 and is set to an ON or OFF state in accordance with the switch signal S8. When the switch element SW8 is set to an ON state, it supplies the reference common voltage Vcom_RF to the other end of the capacitor Cb. The switch element SW9 receives a switch signal S9 and is set to an ON or OFF state in accordance with the switch signal S9. When the switch element SW9 is set to an ON state, it supplies the above-mentioned feedback common voltage Vcom_FB to the other end of the capacitor Cb. Thus, these switch elements SW8 and SW9 operate as a selector SEL that selects one of the reference common voltage Vcom_RF and the feedback common voltage Vcom_FB in accordance with the switch signals S8 and S9 and supplies the selected one to the other end of the capacitor Cb.

[0064] With the above-described configuration, the offset cancellation circuit OFC superimposes the voltage fluctuation occurring in the common voltage Vcom onto the reference gamma voltage G_UH_RF, and outputs the result as the compensated reference gamma voltage G_UH from the differential amplifier circuit OPA.

[0065] The compensation operation of the gamma amplifier unit 1332 for voltage fluctuations in the common voltage Vcom will be described in detail below.

[0066] First, as shown in FIG. 6, the control circuit 1330 generates switch signals S1 to S9 that specify the on / off states of the switch elements SW1 to SW9 included in the offset cancellation circuit OFC in response to the video data signal VPD.

[0067] For example, the control circuit 1330 generates switch signals S1 to S9 according to the first step shown in FIG. 6 for each predetermined period in the video data signal VPD, over the time points t0 to t1 within the predetermined period.

[0068] That is, in this first step, the control circuit 1330 supplies switch signals S1, S3, S4, and S8 specifying an ON state to switch elements SW1, SW3, SW4, and SW8 included in each of the gamma amplifier circuits GA1 to GA4, respectively. Furthermore, in this first step, the control circuit 1330 supplies switch signals S2 and S9 specifying an OFF state to switch elements SW2 and SW9 included in each of the gamma amplifier circuits GA1 to GA4.

[0069] Then, in the second step after time t1, the control circuit 1330 supplies switch signals S1, S3, S4, and S8 specifying the OFF state to the above-mentioned switch elements SW1, SW3, SW4, and SW8, respectively, as shown in FIG. 6, and supplies switch signals S2 and S9 specifying the ON state to the switch elements SW2 and SW9, respectively.

[0070] The control circuit 1330 supplies switch signals S6 and S7 to the switch elements SW6 and SW7 included in each of the gamma amplifier circuits GA1 to GA4, respectively, to set both of them in an ON state at all times.Furthermore, the control circuit 1330 supplies a switch signal S5 to the switch element SW5 included in each of the gamma amplifier circuits GA1 to GA4, to set it in an OFF state at all times.

[0071] Next, the compensation operation for the voltage fluctuation of the common voltage Vcom, which is performed in each of the gamma amplifier circuits GA1 to GA4 in response to the switch signals S1 to S9, will be explained using the gamma amplifier circuit GA1 as a representative.

[0072] [Operation in the first step] FIG. 7A is a schematic circuit diagram in which the on / off states of the switch elements SW1 to SW9 of the gamma amplifier circuit GA1 in the first step shown in FIG. 6 and the current paths are indicated by thick solid lines.

[0073] As shown in FIG. 7A, in the first step, the switch elements SW1, SW3, SW4, SW6 to SW8 are in the ON state, and the switch elements SW2, SW5 and SW9 are in the OFF state.

[0074] As a result, the gates of the transistors Q1 and Q2 are shorted together via the switch element SW1, as shown by the thick solid line in Fig. 7A. Therefore, the gates of the transistors Q1 and Q2 that form a differential pair of the differential amplifier circuit are shorted together, and the difference in the differential pair becomes zero.

[0075] 7A, the compensated reference gamma voltage G_UH is supplied to the gate of the transistor Q3 via the switch element SW3, and the reference gamma voltage G_UH_RF is supplied to the gate of the transistor Q4 via the switch element SW4. As a result, the differential pair (Q3, Q4) draws out a pair of currents corresponding to the difference between the compensated reference gamma voltage G_UH and the reference gamma voltage G_UH_RF from the nodes nd12 and nd11 of the differential amplifier circuit OPA so that the voltage values ​​of the compensated reference gamma voltage G_UH and the reference gamma voltage G_UH_RF match.

[0076] 7A, the compensated reference gamma voltage G_UH is supplied to one end of the capacitor Ca via the switch elements SW3 and SW7. At this time, the reference common voltage Vcom_RF is supplied to the other end of the capacitor Ca, so that the capacitor Ca holds the voltage (|G_UH-Vcom_RF|) that is the difference between the compensated reference gamma voltage G_UH and the reference common voltage Vcom_RF.

[0077] 7A, the reference gamma voltage G_UH_RF is supplied to one end of the capacitor Cb via the switch elements SW4 and SW6, and the reference common voltage Vcom_RF is supplied to the other end of the capacitor Cb via the switch element SW8. As a result, the capacitor Cb holds the voltage (|G_UH_RF-Vcom_RF|) that is the difference between the reference gamma voltage G_UH_RF and the reference common voltage Vcom_RF. After the first step is completed, the control circuit 1330 turns off the switch elements SW3 and SW4 using the switch signals S3 and S4 to hold the charges stored in the capacitors Ca and Cb.

[0078] [Operation in the second step] FIG. 7B is a schematic circuit diagram in which the on / off states of the switch elements SW1 to SW9 of the gamma amplifier circuit GA1 and the current paths are indicated by thick solid lines in the second step shown in FIG.

[0079] As shown in FIG. 7B, in the second step, the switch elements SW1, SW3, SW4, SW5, and SW8 are turned off, and the switch elements SW2, SW6, SW7, and SW9 are turned on.

[0080] As a result, as shown by the thick solid line in FIG. 7B, the compensated reference gamma voltage G_UH is supplied to the gate of the transistor Q2 of the differential pair via the switch element SW2. At this time, the reference gamma voltage G_UH_RF is supplied to the transistor Q1. Therefore, the differential pair (Q1, Q2) of the differential amplifier circuit OPA passes a pair of currents corresponding to the difference between the compensated reference gamma voltage G_UH and the reference gamma voltage G_UH_RF through the nodes nd11 and nd12. As a result, the compensated reference gamma voltage G_UH having a voltage value corresponding to the reference gamma voltage G_UH_RF is output from the output stage Ba.

[0081] In the second step, one end of the capacitor Ca is connected to the gate of the transistor Q3 via the switch element SW7, so that the voltage (|G_UH-Vcom_RF|) held in the capacitor Ca in the first step is supplied to the gate of the transistor Q3 via the switch element SW7, as shown by the thick solid line in FIG.

[0082] Furthermore, in the second step, one end of capacitor Cb is connected to the gate of transistor Q3 via switch element SW6, and the feedback common voltage Vcom_FB is supplied to the other end of capacitor Cb via switch element SW9, as shown by the thick solid line in Fig. 7B. As a result, the held voltage of capacitor Cb becomes voltage (|G_UH_RF-Vcom_FB|), which is supplied to the gate of transistor Q4 via switch element SW6, as shown by the thick solid line in Fig. 7B.

[0083] Therefore, in the second step, the differential pair (Q3, Q4) generates the difference between the voltage (|G_UH-Vcom_RF|) and the voltage (|G_UH_RF-Vcom_FB|), that is, Voltage (G_UH-Vcom_RF-G_UH_RF+Vcom_FB) A pair of currents corresponding to the above flows through the nodes nd11 and nd12 of the differential amplifier circuit OPA.

[0084] The differential amplifier circuit OPA makes the compensated reference gamma voltage G_UH equal to the reference gamma voltage G_UH_RF. Therefore, in reality, a pair of currents corresponding to the difference between the feedback common voltage Vcom_FB and the reference common voltage Vcom_RF flows through the nodes nd11 and nd12 of the differential amplifier circuit OPA.

[0085] As a result, the differential amplifier circuit OPA superimposes the difference (|Vcom_FB-Vcom_RF|) between the feedback common voltage Vcom_FB and the reference common voltage Vcom_RF on the reference gamma voltage G_UH_RF supplied from the reference gamma voltage generation unit 1331, and outputs the result as the compensated reference gamma voltage G_UH.

[0086] 4, each of the gamma amplifier circuits GA2 to GA4 other than the gamma amplifier circuit GA1 also employs a configuration including an offset cancellation circuit OFC and a differential amplifier circuit OPA similar to that of the gamma amplifier circuit GA1. As a result, the gamma amplifier circuits GA2 to GA4 output, based on the reference gamma voltages G_UL_RF, G_LH_RF, and G_LL_RF that they individually receive, a voltage (Vcom_FB-Vcom_RF) superimposed thereon, as compensated reference gamma voltages G_UL, G_LH, and G_LL.

[0087] In short, the offset cancellation circuit OFC included in each of the gamma amplifier circuits GA1 to GA4 first receives the voltage of the common electrode CE from the display panel 20 as a feedback common voltage Vcom_FB. Then, the offset cancellation circuit OFC passes a pair of currents corresponding to the difference between the difference between the reference common voltage Vcom_RF and the compensated reference gamma voltages (G_UH, G_UL, G_LH, G_LL) and the difference between the feedback common voltage Vcom_FB and the reference gamma voltage (e.g., G_UH_RF) to a pair of nodes (nd11, nd12) of the differential amplifier circuit OPA. As a result, the offset cancellation circuit OFC superimposes a voltage fluctuation occurring at the common electrode CE on the reference gamma voltages (G_UH_RF, G_UL_RF, G_LH_RF, and G_LL_RF), and outputs the superimposed voltage as the compensated reference gamma voltages (G_UH, G_UL, G_LH, and G_LL) from the differential amplifier circuit OPA.

[0088] 8 is a waveform diagram showing an example of the waveforms of the feedback common voltage Vcom_FB and the compensated reference gamma voltages G_UH, G_UL, G_LH, and G_LL, which are subject to voltage fluctuations. Fig. 8 illustrates the waveforms of each voltage during a vertical blanking period VBP in one frame of the video signal and during a normal display period NDP in which the data driver 13 supplies drive voltages G1 to Gn to the display panel 20.

[0089] As shown in Figure 8, if there is a fluctuation in the feedback common voltage Vcom_FB actually taken in from the display panel 20 relative to the reference common voltage Vcom_RF, which has a constant voltage value, the voltage fluctuation (Vcom_FB-Vcom_RF) is reflected in each of the compensated reference gamma voltages G_UH, G_UL, G_LH, and G_LL.

[0090] Therefore, the above-mentioned voltage fluctuation (Vcom_FB-Vcom_RF) is also superimposed on each of the positive polarity gray scale voltages V0 to V255 and negative polarity gray scale voltages Y0 to Y255 generated by the gray scale voltage generation circuit 1333 based on these compensation reference gamma voltages G_UH, G_UL, G_LH, and G_LL.

[0091] Therefore, the above-mentioned voltage fluctuation (Vcom_FB-Vcom_RF) is also superimposed on each of the drive voltages G1 to Gn generated by the DA conversion unit 132 using the gradation voltages V0 to V255 and Y0 to Y255, and the drive voltages G1 to Gn on which this voltage fluctuation is superimposed are supplied to the data lines D1 to Dn of the display panel 20. In other words, the voltage fluctuation occurring in the feedback common voltage Vcom_FB is also reflected in each of the drive voltages G1 to Gn.

[0092] As a result, as shown in Fig. 8, the difference Vf1 between the voltage (Vcom_FB) of the common electrode CE and the drive voltages (G1 to Gn), which determines the luminance level of each display cell PC during the normal display period NDP, has the above-mentioned voltage fluctuations offset and remains constant throughout the normal display period NDP. Furthermore, the difference Vf2 between the voltage (Vcom_FB) on the common electrode CE and the drive voltages (G1 to Gn) during the vertical blanking period VBP shown in Fig. 8 also has the above-mentioned voltage fluctuations offset and remains a constant voltage equal to the difference Vf1 throughout the vertical blanking period VBP.

[0093] Therefore, according to the gamma amplifier unit 1332, even if a voltage fluctuation occurs in the common electrode CE of the display panel 20, which is made of liquid crystal, organic EL, etc., due to a change in refresh rate or various other factors, the brightness of each display cell PC does not change due to the voltage fluctuation, making it possible to suppress the occurrence of flicker.

[0094] In the above embodiment, the number of reference gamma voltages (G_UH_RF, G_UL_RF, G_LH_RF, G_LL_RF) used to generate the grayscale voltages V0 to V255 and Y0 to Y255 is four, and the number of gamma amplifier circuits (GA1 to GA4) that amplify each of them individually is also four. However, the number of reference gamma voltages and gamma amplifier circuits is not limited to four, and may be at least two or more.

[0095] 5 includes a switch element SW5 that is fixed to an off state and switch elements SW6 and SW7 that are fixed to an on state as shown in Fig. 6, but these switch elements SW5 to SW7 may be deleted, and node nd3 may be directly connected to capacitor Ca, and node nd4 may be directly connected to capacitor CB. In other words, the offset cancellation circuit OFC only needs to include a switch circuit consisting of at least switch elements SW1 to SW4 and selector SEL (SW8, SW9).

[0096] In short, the display driver according to the present invention may include the following common voltage generating section, first to k-th gamma amplifier circuits (k is an integer of 2 or more), a grayscale voltage generating circuit, and a DA converting section.

[0097] The common voltage generator 14 receives the reference common voltage Vcom_RF, generates a common voltage Vcom having the same voltage value as the reference common voltage, and applies the generated common voltage Vcom to the common electrode CE of the display panel 20.

[0098] The first to kth gamma amplifier circuits (e.g., GA1 to GA4) receive the first to kth reference gamma voltages (e.g., G_UH_RF, G_UL_RF, G_LH_RF, G_LL_RF) that conform to predetermined gamma characteristics, and output the first to kth compensated reference gamma voltages (e.g., G_UH, G_UL, G_LH, G_LL) by individually amplifying these first to kth reference gamma voltages.

[0099] The gradation voltage generation circuit (1333) generates a plurality of gradation voltages (V0 to V255, Y0 to Y255) based on the 1st to kth compensated reference gamma voltages. The DA conversion unit (132) selects, from the plurality of gradation voltages, gradation voltages corresponding to the display data fragments (P1 to Pn) for each display cell (PC) indicated by the video signal (VPD), and supplies a plurality of drive voltages (G1 to Gn) obtained by amplifying the plurality of gradation voltages selected for each display data fragment to a plurality of data lines (D1 to Dn).

[0100] Each of the first to k-th gamma amplifier circuits includes the following differential amplifier circuit and offset cancel circuit.

[0101] The differential amplifier circuit (OPA) receives a reference gamma voltage (e.g., G_UH_RF) that it receives and a compensated reference gamma voltage (e.g., G_UH) that it outputs at a pair of input terminals (nd1, nd2), passes a pair of currents corresponding to the difference between the two to a pair of nodes (nd11, nd12), and outputs the voltage of at least one of the pair of nodes as the compensated reference gamma voltage (e.g., G_UH).

[0102] The offset cancellation circuit (OFC) receives the voltage of the common electrode (CE) from the display panel (20) as a feedback common voltage (Vcom_FB). The offset cancellation circuit (OFC) then passes a pair of currents corresponding to the difference between the difference between the reference common voltage (Vcom_RF) and the compensated reference gamma voltage (e.g., G_UH) and the difference between the difference between the feedback common voltage (Vcom_FB) and the reference gamma voltage (e.g., G_UH_RF) to a pair of nodes (nd11, nd12) of the differential amplifier circuit. As a result, the offset cancellation circuit (OFC) causes the differential amplifier circuit (OPA) to output a voltage obtained by superimposing a voltage fluctuation occurring in the common electrode (CE) on the reference gamma voltage as the compensated reference gamma voltage.

[0103] As described above, in the display driver according to this embodiment, each gamma amplifier circuit receives a reference gamma voltage conforming to a predetermined gamma characteristic and a voltage occurring at the common electrode of the display panel as a feedback common voltage. Each gamma amplifier circuit then superimposes the difference between the feedback common voltage and the reference common voltage on the reference gamma voltage, amplifies the result, and outputs the result as a compensated reference gamma voltage that compensates for voltage fluctuations occurring at the common electrode. This allows the display driver to convert display data fragments into analog grayscale voltages using multiple grayscale voltages generated based on the compensated reference gamma voltages, and then supplies the amplified voltages as drive voltages to each display cell of the display panel. Therefore, with this display driver, even if voltage fluctuations occur at the common electrode of a display panel made of liquid crystal, organic electroluminescence, or the like due to changes in refresh rate or various other factors, the voltage fluctuations are offset within each display cell, preventing any change in brightness associated with the voltage fluctuations, thereby suppressing flicker. [Explanation of symbols]

[0104] 13 Data Driver 14 Common voltage generator 20 Display panel 132 DA conversion section 133 Gradation voltage generation unit 1330 Control circuit 1331 Reference Gamma Voltage Generator 1332 Gamma amplifier section 1333 Gradation voltage generation circuit GA1~GA4 Gamma amplifier circuit OFC Offset Cancellation Circuit OPA Differential Amplifier Circuit

Claims

1. A display driver for driving a display panel having a plurality of data lines on each of which a plurality of display cells are arranged and a common electrode connected in common to the plurality of display cells, first to k-th gamma amplifier circuits each receiving first to k-th (k is an integer of 2 or more) reference gamma voltages according to a predetermined gamma characteristic and amplifying the first to k-th reference gamma voltages individually to output first to k-th compensated reference gamma voltages; a grayscale voltage generating circuit that generates a plurality of grayscale voltages based on the first to kth compensation reference gamma voltages; a D / A converter that selects, from the plurality of grayscale voltages, a grayscale voltage corresponding to a display data piece for each of the display cells indicated by a video signal, and supplies a plurality of drive voltages obtained by amplifying the plurality of grayscale voltages selected for each of the display data pieces to the plurality of data lines; Each of the first to kth gamma amplifier circuits comprises: a differential amplifier circuit that receives the reference gamma voltage it receives and the compensated reference gamma voltage it outputs at a pair of input terminals it receives, flows a pair of currents corresponding to the difference between the two voltages through a pair of nodes, and outputs a voltage of at least one node of the pair of nodes as the compensated reference gamma voltage; an offset cancellation circuit that takes in the voltage of the common electrode from the display panel as a feedback common voltage, and flows a pair of currents corresponding to the difference between a predetermined reference common voltage and the compensated reference gamma voltage and the difference between the feedback common voltage and the reference gamma voltage into the pair of nodes of the differential amplifier circuit, thereby causing the differential amplifier circuit to output a voltage in which a voltage fluctuation occurring in the common electrode is superimposed on the reference gamma voltage as the compensated reference gamma voltage.

2. 2. The display driver according to claim 1, further comprising a common voltage generator configured to receive the reference common voltage, generate a common voltage having a voltage value of the reference common voltage, and apply the common voltage to the common electrode.

3. a control circuit for controlling the offset cancellation circuit included in each of the first to kth gamma amplifier circuits; The offset cancellation circuit a differential pair that causes a pair of currents corresponding to a difference between voltages received at a pair of input terminals of the differential pair to flow to the pair of nodes of the differential amplifier circuit; a first capacitance element having one end connected to one of the pair of input ends of the differential pair and receiving the reference common voltage at the other end; a second capacitance element having one end connected to the other of the pair of input ends of the differential pair; a selector that selects one of the reference common voltage and the feedback common voltage and supplies the selected voltage to the other end of the second capacitance element; a switch circuit that, in an on state, shorts the pair of input terminals of the differential amplifier circuit, and supplies the reference gamma voltage to the one terminal of the second capacitance element and the other input terminal of the differential pair, while supplying the compensated reference gamma voltage to the one input terminal of the differential pair and one terminal of the first capacitance element, The display driver described in claim 1 or 2, characterized in that the control circuit sequentially executes a first step of setting the switch circuit to an on state and setting the selector to a state that selects the reference common voltage, and a second step of switching the switch circuit to an off state and switching the selector to a state that selects the feedback common voltage.

4. The switch circuit a first switch element that short-circuits the pair of input terminals of the differential amplifier circuit when in an on state; a second switch element that supplies the reference gamma voltage to the one end of the second capacitive element and the other input end of the differential pair when in an on state; 4. The display driver according to claim 3, further comprising: a third switch element that, when in an on state, supplies the compensation reference gamma voltage to the one input terminal of the differential pair and one terminal of the first capacitance element.

5. A display device comprising: a display panel having a plurality of data lines, each of which has a plurality of display cells arranged thereon, and a common electrode connected in common to the plurality of display cells; and a display driver that drives the display panel based on a video signal, The display driver a common voltage generator configured to receive a reference common voltage, generate a common voltage having a voltage value of the reference common voltage, and apply the common voltage to the common electrode; first to k-th gamma amplifier circuits each receiving first to k-th (k is an integer of 2 or more) reference gamma voltages according to a predetermined gamma characteristic and amplifying the first to k-th reference gamma voltages individually to output first to k-th compensated reference gamma voltages; a grayscale voltage generating circuit that generates a plurality of grayscale voltages based on the first to kth compensation reference gamma voltages; a D / A converter that selects, from the plurality of grayscale voltages, a grayscale voltage corresponding to a display data piece for each of the display cells indicated by a video signal, and supplies a plurality of drive voltages obtained by amplifying the plurality of grayscale voltages selected for each of the display data pieces to the plurality of data lines; Each of the first to kth gamma amplifier circuits comprises: a differential amplifier circuit that receives the reference gamma voltage it receives and the compensated reference gamma voltage it outputs at a pair of input terminals it receives, flows a pair of currents corresponding to the difference between the two voltages through a pair of nodes, and outputs a voltage of at least one node of the pair of nodes as the compensated reference gamma voltage; and an offset cancellation circuit that takes in the voltage of the common electrode from the display panel as a feedback common voltage, and flows a pair of currents corresponding to the difference between the difference between the reference common voltage and the compensated reference gamma voltage and the difference between the difference between the feedback common voltage and the reference gamma voltage into the pair of nodes of the differential amplifier circuit, thereby causing the differential amplifier circuit to output a voltage in which a voltage fluctuation occurring in the common electrode is superimposed on the reference gamma voltage as the compensated reference gamma voltage.

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