Chip resistor and method of manufacturing the same

Abstract

To provide a chip resistor having lower electric resistance and more stable quality.SOLUTION: The chip resistor 1 includes a metallic resistor 10, a first plated electrode 21, and a second plated electrode 22. The metal resistor 10 includes a first bottom plate portion 11, a second bottom plate portion 12, a top plate portion 13, a first inclined leg portion 14, and a second inclined leg portion 15. The first plating electrode 21 is disposed on the bottom surface of the first bottom plate portion 11, the bottom surface of the first inclined leg portion 14, and the bottom surface of the top plate portion 13. The second plating electrode 22 is disposed on the bottom surface of the second bottom plate portion 12, the bottom surface of the second inclined leg portion 15, and the bottom surface of the top plate portion 13.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a chip resistor and a method for manufacturing the same. [Background technology]

[0002] International Publication No. 2012 / 157435 (Patent Document 1) discloses a chip resistor including a resistor portion, a first electrode, and a second electrode. The first electrode is bent and welded to one end of the resistor portion. The second electrode is bent and welded to the other end of the resistor portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2012 / 157435

[0004] [overview] An object of the present disclosure is to provide a chip resistor with lower electrical resistance and more consistent quality.

[0005] The chip resistor of the present disclosure includes a metal resistor element, a first plated electrode, and a second plated electrode. The metal resistor element includes a first bottom plate portion, a second bottom plate portion, a top plate portion disposed between the first and second bottom plate portions, a first inclined leg portion connected to the first bottom plate portion and the top plate portion, and a second inclined leg portion connected to the second bottom plate portion and the top plate portion. The first plated electrode is disposed on the bottom surface of the first bottom plate portion, on the bottom surface of the first inclined leg portion, and on the bottom surface of the top plate portion. The second plated electrode is disposed on the bottom surface of the second bottom plate portion, on the bottom surface of the second inclined leg portion, and on the bottom surface of the top plate portion. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a chip resistor according to a first embodiment. [Figure 2] FIG. 2 is a schematic bottom view of the chip resistor according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view of the chip resistor according to the first embodiment taken along the cross-sectional line III-III shown in FIG. [Figure 4] FIG. 4 is a flowchart showing the method for manufacturing the chip resistors according to the first to third embodiments. [Figure 5] FIG. 5 is a flowchart showing steps for forming the first stack according to the first embodiment. [Figure 6] FIG. 6 is a schematic perspective view showing one step of the method for manufacturing the chip resistor according to the first embodiment. [Figure 7] FIG. 7 is a schematic perspective view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing the chip resistor according to the first embodiment. [Figure 8] FIG. 8 is a schematic perspective view showing a step subsequent to the step shown in FIG. 7 in the method for manufacturing the chip resistor according to the first embodiment. [Figure 9] FIG. 9 is a schematic perspective view showing a step subsequent to the step shown in FIG. 8 in the method for manufacturing the chip resistor according to the first embodiment. [Figure 10] FIG. 10 is a schematic perspective view showing a step subsequent to the step shown in FIG. 9 in the method for manufacturing the chip resistor according to the first embodiment. [Figure 11] FIG. 11 is a schematic plan view of the chip resistor according to the second embodiment. [Figure 12] FIG. 12 is a schematic bottom view of the chip resistor according to the second embodiment. [Figure 13] 13 is a schematic cross-sectional view of the chip resistor according to the second embodiment taken along the cross-sectional line XIII-XIII shown in FIG. [Figure 14] FIG. 14 is a flowchart showing steps for forming the first stack according to the second embodiment. [Figure 15] FIG. 15 is a schematic perspective view showing one step of the method for manufacturing the chip resistor according to the second embodiment. [Figure 16] FIG. 16 is a schematic perspective view showing a step subsequent to the step shown in FIG. 15 in the method for manufacturing the chip resistor according to the second embodiment. [Figure 17]FIG. 17 is a schematic perspective view showing a step subsequent to the step shown in FIG. 16 in the method for manufacturing the chip resistor according to the second embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of the chip resistor according to the third embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view of a circuit board on which the chip resistor of the third embodiment is mounted. [Figure 20] FIG. 20 is a flowchart showing steps for forming a first stack according to the third embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view showing one step of the method for manufacturing the chip resistor according to the third embodiment. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 21 in the method for manufacturing the chip resistor according to the third embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 22 in the method for manufacturing the chip resistor according to the third embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view of a chip resistor according to a modification of the third embodiment. [Figure 25] FIG. 25 is a schematic cross-sectional view of a circuit board on which a chip resistor according to a modification of the third embodiment is mounted. [Figure 26] FIG. 26 is a flowchart showing steps for forming a first stack according to a modification of the third embodiment.

[0007] [Detailed explanation] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be combined in any manner.

[0008] (Embodiment 1) A chip resistor 1 according to a first embodiment will be described with reference to Figures 1 to 3. The chip resistor 1 is, for example, a shunt resistor. A shunt resistor is used, for example, to measure the magnitude of a current. The chip resistor 1 includes a metal resistive element 10, a first plated electrode 21, and a second plated electrode 22.

[0009] 1 to 3, the metal resistor 10 is formed of, for example, a copper-manganese (CuMn) alloy, a copper-nickel (CuNi) alloy, or a nickel-chromium (NiCr) alloy. The metal resistor 10 includes a first bottom plate portion 11, a second bottom plate portion 12, a top plate portion 13, a first inclined leg portion 14, and a second inclined leg portion 15. The top plate portion 13 is disposed between the first bottom plate portion 11 and the second bottom plate portion 12. The first inclined leg portion 14 is connected to the first bottom plate portion 11 and the top plate portion 13. The second inclined leg portion 15 is connected to the second bottom plate portion 12 and the top plate portion 13.

[0010] The metal resistor 10 has a top surface 16, a bottom surface 17 opposite to the top surface 16, a first end surface 18, and a second end surface 19 opposite to the first end surface 18.

[0011] The top surface 16 and the bottom surface 17 are both end surfaces of the metal resistor 10 in the thickness direction. The top surface 16 is formed by the top surface of the first bottom plate portion 11, the top surface of the second bottom plate portion 12, the top surface of the top plate portion 13, the top surface of the first inclined leg portion 14, and the top surface of the second inclined leg portion 15. The bottom surface 17 is formed by the bottom surface of the first bottom plate portion 11, the bottom surface of the second bottom plate portion 12, the bottom surface of the top plate portion 13, the bottom surface of the first inclined leg portion 14, and the bottom surface of the second inclined leg portion 15. When the chip resistor 1 is mounted on a circuit board, the bottom surface 17 faces the circuit board, and the bottom surfaces of the first inclined leg portion 14 and the second inclined leg portion 15 are fixed to the circuit board. The bottom surface 17 is the mounting surface of the chip resistor 1. The first bottom plate portion 11 has a first end surface 18 of the metal resistor 10. The second bottom plate portion 12 has a second end surface 19 of the metal resistor 10.

[0012] The first end face 18 and the second end face 19 are connected to the top face 16 and the bottom face 17, respectively. The first end face 18 and the second end face 19 are both longitudinal end faces of the metal resistor 10. The first end face 18 is one end face of the metal resistor 10 in the direction in which the first plated electrode 21 and the second plated electrode 22 are spaced apart from each other. The second end face 19 is the other end face of the metal resistor 10 in the direction in which the first plated electrode 21 and the second plated electrode 22 are spaced apart from each other.

[0013] The first plated electrode 21 and the second plated electrode 22 are electrodes formed by plating. The first plated electrode 21 and the second plated electrode 22 are made of a material having a lower electrical resistivity than the metal resistor 10. The first plated electrode 21 and the second plated electrode 22 are made of, for example, copper (Cu) or a copper-based alloy.

[0014] The first plating electrode 21 and the second plating electrode 22 are spaced apart from each other. The first plating electrode 21 and the second plating electrode 22 are disposed on the bottom surface 17 of the metal resistor 10. Specifically, the first plating electrode 21 is disposed on the bottom surface of the first bottom plate portion 11, on the bottom surface of the first inclined leg portion 14, and on the bottom surface of the top plate portion 13. The second plating electrode 22 is disposed on the bottom surface of the second bottom plate portion 12, on the bottom surface of the second inclined leg portion 15, and on the bottom surface of the top plate portion 13.

[0015] An example of a method for manufacturing the chip resistor 1 of this embodiment will be described with reference to FIGS.

[0016] 4 to 8, the first laminate 36 is formed (step S1). Forming the first laminate 36 includes forming a first plating layer 37 on the first main surface 31 of the metal resistor plate 30.

[0017] 5 and 6, a metal resistor plate 30 is prepared (step S11). The metal resistor plate 30 is made of the same material as the metal resistor 10 (see FIGS. 1 to 3). The metal resistor plate 30 has a first main surface 31 and a second main surface 32 opposite to the first main surface 31.

[0018] 5 and 6, a mask 35 is formed on the second main surface 32 of the metal resistor plate 30 (step S12). The mask 35 is made of an insulating material such as resist. The first main surface 31 of the metal resistor plate 30 is exposed from the mask 35.

[0019] 5 and 7, a first plating layer 37 is formed on the first main surface 31 of the metal resistor plate 30 by plating (step S13). The first plating layer 37 is made of the same material as the first plating electrode 21 (see FIGS. 2 and 3) and the second plating electrode 22 (see FIGS. 2 and 3). In addition to the first main surface 31, the first plating layer 37 may also be formed on the side surfaces of the metal resistor plate 30 that are connected to the first main surface 31 and the second main surface 32 and that are exposed from the mask 35.

[0020] 5 and 8, the mask 35 is removed (step S15). In this way, the first laminate 36, which is a laminate of the metal resistor plate 30 and the first plating layer 37, is formed.

[0021] 4 and 9, a portion of the first laminate 36 is removed (step S2). Specifically, a portion of the first plating layer 37 is removed from the first laminate 36. A groove 40 is formed in the first laminate 36. In the groove 40, the first main surface 31 of the metal resistor plate 30 is exposed from the first plating layer 37. A method for removing the portion of the first laminate 36 is, for example, machining such as cutting using a cutting tool 42 or milling.

[0022] 4 and 10, the first laminate 36 from which the portion has been removed is punched out by punching or the like to form a second laminate 43 (step S3). The first laminate 36 is punched out so as to cross the grooves 40. The first laminate 36 is punched out, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching out the first laminate 36, the metal resistor 10 is formed from the metal resistor plate 30, and the first plated electrode 21 and the second plated electrode 22 are formed from the first plating layer 37. The bottom surface 17 of the metal resistor 10 is part of the first main surface 31 of the metal resistor plate 30. The top surface 16 of the metal resistor 10 is part of the second main surface 32 of the metal resistor plate 30. In this way, the second laminate 43 is formed, which is a laminate of the metal resistor 10, the first plated electrode 21, and the second plated electrode 22.

[0023] Referring to FIG. 4, the second laminate 43 is folded (step S4). By folding the second laminate 43, the metal resistor 10 is formed with a first bottom plate portion 11, a second bottom plate portion 12, a top plate portion 13, a first inclined leg portion 14, and a second inclined leg portion 15. The first plating electrode 21 is disposed on the bottom surface of the first bottom plate portion 11, the bottom surface of the first inclined leg portion 14, and the bottom surface of the top plate portion 13. The second plating electrode 22 is disposed on the bottom surface of the second bottom plate portion 12, the bottom surface of the second inclined leg portion 15, and the bottom surface of the top plate portion 13. In this manner, the chip resistor 1 of this embodiment shown in FIGS. 1 to 3 is obtained.

[0024] The operation of the chip resistor 1 of this embodiment will be described in comparison with a chip resistor of a comparative example. The chip resistor of the comparative example has a configuration similar to the chip resistor 1 of this embodiment, but has a first electrode and a second electrode instead of the first plated electrode 21 and the second plated electrode 22. The first electrode is bent and welded to one end of the metal resistor 10. The second electrode is bent and welded to the other end of the metal resistor 10.

[0025] In the chip resistor of the comparative example, the distance between the first and second electrodes cannot be reduced to avoid the adverse effects of heat during welding. Furthermore, voids and other defects occur in the first welded portion between the first electrode and the metal resistor 10 and in the second welded portion between the second electrode and the metal resistor 10. The electrical resistance of the first welded portion and the electrical resistance of the second welded portion increase. As a result, the electrical resistance of the chip resistor of the comparative example increases. Furthermore, when welding the first and second electrodes to the metal resistor 10, at least one of the metal resistor 10, the first electrode, and the second electrode deforms, and the amount of voids generated varies from chip resistor to chip resistor of the comparative example. Therefore, the quality of the chip resistor of the comparative example is unstable.

[0026] In contrast, in the chip resistor 1 of this embodiment, the first plated electrode 21 and the second plated electrode 22 are formed on the metal resistor 10 by plating. Because there is no adverse effect of heat during welding, the distance between the first plated electrode 21 and the second plated electrode 22 can be reduced. A portion of the first plated electrode 21 and a portion of the second plated electrode 22 can be disposed on the bottom surface of the top plate portion 13. Furthermore, no voids are generated due to welding. Therefore, the electrical resistance of the chip resistor 1 of this embodiment can be reduced. When the chip resistor 1 is a shunt resistor, it is possible to measure a larger current using the chip resistor 1. Furthermore, no voids or deformation of at least one of the metal resistor 10, the first plated electrode 21, or the second plated electrode 22 due to welding occurs. Therefore, the chip resistor 1 of this embodiment has more stable quality.

[0027] The effects of the chip resistor 1 of this embodiment and the manufacturing method thereof will be described.

[0028] The chip resistor 1 of this embodiment includes a metal resistor 10, a first plated electrode 21, and a second plated electrode 22. The metal resistor 10 includes a first bottom plate portion 11, a second bottom plate portion 12, a top plate portion 13 disposed between the first bottom plate portion 11 and the second bottom plate portion 12, a first inclined leg portion 14 connected to the first bottom plate portion 11 and the top plate portion 13, and a second inclined leg portion 15 connected to the second bottom plate portion 12 and the top plate portion 13. The first plated electrode 21 is disposed on the bottom surface of the first bottom plate portion 11, on the bottom surface of the first inclined leg portion 14, and on the bottom surface of the top plate portion 13. The second plated electrode 22 is disposed on the bottom surface of the second bottom plate portion 12, on the bottom surface of the second inclined leg portion 15, and on the bottom surface of the top plate portion 13.

[0029] In the chip resistor 1 of this embodiment, the first plated electrode 21 and the second plated electrode 22 are formed on the metal resistor 10 by plating. Because there is no adverse effect of heat during welding, the distance between the first plated electrode 21 and the second plated electrode 22 can be reduced. It is possible to position a portion of the first plated electrode 21 and a portion of the second plated electrode 22 on the bottom surface of the top plate portion 13. Furthermore, no voids are generated due to welding. Therefore, the chip resistor 1 of this embodiment has lower electrical resistance. Furthermore, no voids or deformation of at least one of the metal resistor 10, the first plated electrode 21, or the second plated electrode 22 due to welding occurs. Therefore, the chip resistor 1 of this embodiment has more stable quality.

[0030] The chip resistor 1 of this embodiment is a shunt resistor.

[0031] The chip resistor 1 of this embodiment has a lower electrical resistance, and therefore, according to the chip resistor 1 of this embodiment, it is possible to provide a shunt resistor that can measure a larger current.

[0032] In the manufacturing method of the chip resistor 1 of this embodiment, the chip resistor 1 includes a metal resistor element 10 having a top surface 16 and a bottom surface 17, a first plated electrode 21 disposed on the bottom surface 17, and a second plated electrode 22 disposed on the bottom surface 17. The manufacturing method of the chip resistor 1 of this embodiment includes forming a first laminate 36 (step S1). Forming the first laminate 36 includes forming a first plating layer 37 on the first main surface 31 of the metal resistor plate 30 (step S13). The manufacturing method of the chip resistor 1 of this embodiment includes removing a portion of the first laminate 36 (step S2). Removing the portion of the first laminate 36 includes removing a portion of the first plating layer 37 from the first laminate 36. The manufacturing method of the chip resistor 1 of this embodiment includes punching out the first laminate 36 from which the portion has been removed to form a second laminate 43 (step S3). By punching the first laminate 36, the metal resistor 10 is formed from the metal resistor plate 30, and the first plated electrode 21 and the second plated electrode 22 are formed from the first plating layer 37. The manufacturing method for the chip resistor 1 of this embodiment includes bending the second laminate 43 (step S4) to form the chip resistor 1. By bending the second laminate 43, the metal resistor 10 is formed with a first bottom plate portion 11, a second bottom plate portion 12, a top plate portion 13 disposed between the first bottom plate portion 11 and the second bottom plate portion 12, a first inclined leg portion 14 connected to the first bottom plate portion 11 and the top plate portion 13, and a second inclined leg portion 15 connected to the second bottom plate portion 12 and the top plate portion 13. The first plated electrode 21 is disposed on the bottom surface of the first bottom plate portion 11, the bottom surface of the first inclined leg portion 14, and the bottom surface of the top plate portion 13. The second plating electrode 22 is disposed on the bottom surface of the second bottom plate portion 12 , on the bottom surface of the second inclined leg portion 15 , and on the bottom surface of the top plate portion 13 .

[0033] In the manufacturing method of the chip resistor 1 of this embodiment, the first plated electrode 21 and the second plated electrode 22 are formed on the metal resistor 10 by plating. Because there is no adverse effect of heat during welding, the distance between the first plated electrode 21 and the second plated electrode 22 can be reduced. It is possible to position a portion of the first plated electrode 21 and a portion of the second plated electrode 22 on the bottom surface of the top plate portion 13. Furthermore, no voids are generated due to welding. Therefore, the manufacturing method of the chip resistor 1 of this embodiment can manufacture a chip resistor 1 with lower electrical resistance. Furthermore, no voids or deformation of at least one of the metal resistor 10, the first plated electrode 21, or the second plated electrode 22 due to welding occurs. Therefore, the manufacturing method of the chip resistor 1 of this embodiment can manufacture a chip resistor 1 with more stable quality.

[0034] In the method for manufacturing the chip resistor 1 of this embodiment, the chip resistor 1 is a shunt resistor.

[0035] The chip resistor 1 of this embodiment has a lower electrical resistance. According to the method for manufacturing the chip resistor 1 of this embodiment, a shunt resistor capable of measuring a larger current can be manufactured.

[0036] (Embodiment 2) The chip resistor 1 of the second embodiment will be described with reference to Figures 11 to 13. The chip resistor 1 of the second embodiment has a similar configuration to the chip resistor 1 of the first embodiment, but differs from the chip resistor 1 of the first embodiment mainly in the following points.

[0037] The chip resistor 1 of this embodiment further includes a third plated electrode 23 and a fourth plated electrode 24. The third plated electrode 23 and the fourth plated electrode 24 are electrodes formed by plating. The third plated electrode 23 and the fourth plated electrode 24 are formed of a material having a lower electrical resistivity than the metal resistor 10. The third plated electrode 23 and the fourth plated electrode 24 are formed of, for example, copper (Cu) or a copper-based alloy.

[0038] The third plating electrode 23 and the fourth plating electrode 24 are spaced apart from each other. The third plating electrode 23 and the fourth plating electrode 24 are disposed on the top surface 16 of the metal resistor 10. Specifically, the third plating electrode 23 is disposed on the top surface of the first bottom plate portion 11, on the top surface of the first inclined leg portion 14, and on the top surface of the top plate portion 13. The fourth plating electrode 24 is disposed on the top surface of the second bottom plate portion 12, on the top surface of the second inclined leg portion 15, and on the top surface of the top plate portion 13.

[0039] An example of a method for manufacturing the chip resistor 1 of the present embodiment will be described with reference to Fig. 4 and Fig. 14 to Fig. 17. The method for manufacturing the chip resistor 1 of the present embodiment includes similar steps to those of the method for manufacturing the chip resistor 1 of the first embodiment, but differs from the method for manufacturing the chip resistor 1 of the first embodiment in the following points.

[0040] 4 and 14, the method for manufacturing the chip resistor 1 according to the present embodiment does not include step S12 (see FIG. 5) and step S15 (see FIG. 5).

[0041] 4, 14, and 15, in step S13 of the present embodiment, a first plating layer 37 is also formed on the second main surface 32 of the metal resistor plate 30 by plating. The first plating layer 37 is formed of the same material as the first plating electrode 21 (see FIGS. 12 and 13), the second plating electrode 22 (see FIGS. 12 and 13), the third plating electrode 23 (see FIGS. 11 and 13), and the fourth plating electrode 24 (see FIGS. 11 and 13). The first plating layer 37 includes a first plating partial layer formed on the first main surface 31 of the metal resistor plate 30 and a second plating partial layer formed on the second main surface 32 of the metal resistor plate 30. The first plating layer 37 may also be formed on side surfaces of the metal resistor plate 30 connected to the first and second main surfaces 31 and 32.

[0042] 4 and 16, in step S2 of the present embodiment, a portion of the first plating portion layer and a portion of the second plating portion layer are removed from the first laminate 36. Grooves 40, 41 are formed in the first laminate 36. Specifically, the groove 40 is formed in the first plating portion layer. The groove 41 is formed in the second plating portion layer. In the groove 40, the first main surface 31 of the metal resistor plate 30 is exposed from the first plating layer 37 (specifically, the first plating portion layer). In the groove 41, the second main surface 32 of the metal resistor plate 30 is exposed from the first plating layer 37 (specifically, the second plating portion layer). The method of removing the portion of the first laminate 36 is, for example, machining such as cutting using a cutting tool 42 or milling.

[0043] 4 and 17, in step S3 of the present embodiment, the first laminate 36 is punched out so as to cross the grooves 40, 41. A first plating electrode 21 and a second plating electrode 22 spaced apart from the first plating electrode 21 are formed from the first plating partial layer. A third plating electrode 23 and a fourth plating electrode 24 spaced apart from the third plating electrode 23 are formed from the second plating partial layer. In this way, a second laminate 43 is formed, which is a laminate of the metal resistor 10, the first plating electrode 21, the second plating electrode 22, the third plating electrode 23, and the fourth plating electrode 24.

[0044] 4, in step S4 of the present embodiment, the second laminate 43 is bent to form the first bottom plate portion 11, the second bottom plate portion 12, the top plate portion 13, the first inclined leg portion 14, and the second inclined leg portion 15 in the metal resistor 10. The third plated electrode 23 is disposed on the top surface of the first bottom plate portion 11, the top surface of the first inclined leg portion 14, and the top surface of the top plate portion 13. The fourth plated electrode 24 is disposed on the top surface of the second bottom plate portion 12, the top surface of the second inclined leg portion 15, and the top surface of the top plate portion 13. In this way, the chip resistor 1 of the present embodiment shown in FIGS. 11 to 13 is obtained.

[0045] The chip resistor 1 and the manufacturing method thereof according to this embodiment have the following advantages in addition to the advantages of the chip resistor 1 and the manufacturing method thereof according to the first embodiment.

[0046] The chip resistor 1 of this embodiment further includes a third plated electrode 23 and a fourth plated electrode 24. The third plated electrode 23 is arranged on the top surface of the first bottom plate portion 11, on the top surface of the first inclined leg portion 14, and on the top surface of the top plate portion 13. The fourth plated electrode 24 is arranged on the top surface of the second bottom plate portion 12, on the top surface of the second inclined leg portion 15, and on the top surface of the top plate portion 13.

[0047] The third plated electrode 23 and the fourth plated electrode 24 are formed on the metal resistor 10 by plating. Since there is no adverse effect of heat during welding, the distance between the third plated electrode 23 and the fourth plated electrode 24 can be reduced. It is possible to arrange a portion of the third plated electrode 23 and a portion of the fourth plated electrode 24 on the top surface of the top plate portion 13. In addition, no voids are generated due to welding. Heat generated in the chip resistor 1 while current is flowing through the chip resistor 1 is dissipated to the surroundings of the chip resistor 1 through the third plated electrode 23 and the fourth plated electrode 24. The rated power of the chip resistor 1 can be increased.

[0048] In the manufacturing method of the chip resistor 1 of this embodiment, the chip resistor 1 further includes a third plated electrode 23 disposed on the top surface 16 of the metal resistor 10 and a fourth plated electrode 24 disposed on the top surface 16 of the metal resistor 10. Forming the first laminate 36 (step S1) includes forming a first plating layer 37 also on the second main surface 32 of the metal resistor plate 30 opposite the first main surface 31. The first plating layer 37 includes a first plating partial layer formed on the first main surface 31 and a second plating partial layer formed on the second main surface 32. Removing a portion of the first laminate 36 (step S2) includes removing a portion of the first plating partial layer and a portion of the second plating partial layer from the first laminate 36. By punching out the first laminate 36 (step S3), the first plating electrode 21 and the second plating electrode 22 are formed from the first plating partial layer, and the third plating electrode 23 and the fourth plating electrode 24 are formed from the second plating partial layer. By bending the second laminate 43 (step S4), the third plating electrode 23 is arranged on the top surface of the first bottom plate portion 11, the top surface of the first inclined leg portion 14, and the top surface of the top plate portion 13, and the fourth plating electrode 24 is arranged on the top surface of the second bottom plate portion 12, the top surface of the second inclined leg portion 15, and the top surface of the top plate portion 13.

[0049] In the manufacturing method of the chip resistor 1 of this embodiment, the third plated electrode 23 and the fourth plated electrode 24 are formed on the metal resistor 10 by plating. Because there is no adverse effect of heat during welding, the distance between the third plated electrode 23 and the fourth plated electrode 24 can be reduced. It is possible to position a portion of the third plated electrode 23 and a portion of the fourth plated electrode 24 on the top surface of the top plate portion 13. Furthermore, no voids are generated due to welding. Heat generated in the chip resistor 1 while a current is flowing through the chip resistor 1 is dissipated to the surroundings of the chip resistor 1 through the third plated electrode 23 and the fourth plated electrode 24. According to the manufacturing method of the chip resistor 1 of this embodiment, a chip resistor 1 with an increased rated power can be manufactured.

[0050] (Embodiment 3) The chip resistor 1 of the third embodiment will be described with reference to Figures 18 and 19. The chip resistor 1 of the present embodiment has the same configuration as the chip resistor 1 of the first embodiment.

[0051] For example, the first plating electrode 21 has a first surface 21a opposite the metal resistor 10, a first inner end face 21b facing the second plating electrode 22, and a first outer end face 21c opposite the first inner end face 21b. The first surface 21a is connected to the first inner end face 21b and the first outer end face 21c. The first outer end face 21c may be flush with the first end face 18 of the metal resistor 10. The second plating electrode 22 has a second surface 22a opposite the metal resistor 10, a second inner end face 22b facing the first plating electrode 21, and a second outer end face 22c opposite the second inner end face 22b. The second surface 22a is connected to the second inner end face 22b and the second outer end face 22c. The second outer end face 22c may be flush with the second end face 19 of the metal resistor 10.

[0052] The chip resistor 1 of this embodiment differs from the chip resistor 1 of the first embodiment in that it further includes a first plating coating layer 25 and a second plating coating layer .

[0053] The first plating coating layer 25 is disposed on the first surface 21a of the first plating electrode 21. The first surface 21a is covered with the first plating coating layer 25. The first inner end face 21b is exposed from the first plating coating layer 25. The first outermost surface 25a of the first plating coating layer 25 has higher solder wettability than the first plating electrode 21. The first outermost surface 25a is formed of, for example, tin (Sn) or nickel (Ni). The first plating coating layer 25 may be formed as a single layer or as multiple layers. The first plating coating layer 25 may be formed as a single layer of tin (Sn), a single layer of nickel (Ni), or two layers of an Sn layer and an Ni layer.

[0054] The second plating coating layer 26 is disposed on the second surface 22a of the second plating electrode 22. The second surface 22a is covered with the second plating coating layer 26. The second inner end face 22b is exposed from the second plating coating layer 26. The second outermost surface 26a of the second plating coating layer 26 has higher solder wettability than the second plating electrode 22. The second outermost surface 26a is formed of, for example, tin (Sn) or nickel (Ni). The second plating coating layer 26 may be formed as a single layer or as multiple layers. The second plating coating layer 26 may be formed as a single layer of tin (Sn), a single layer of nickel (Ni), or two layers of an Sn layer and an Ni layer.

[0055] 19, the chip resistor 1 is mounted on a circuit board 50. Specifically, the circuit board 50 includes an insulating substrate 51 and electrical wiring 52, 53. The electrical wiring 52, 53 is formed on the insulating substrate 51. The first plating electrode 21 coated with the first plating coating layer 25 is joined to the electrical wiring 52 of the circuit board 50 using a conductive joining member 54 such as solder. The second plating electrode 22 coated with the second plating coating layer 26 is joined to the electrical wiring 53 of the circuit board 50 using a conductive joining member 55 such as solder.

[0056] An example of a method for manufacturing the chip resistor 1 of the present embodiment will be described with reference to Fig. 4 and Fig. 20 to Fig. 23. The method for manufacturing the chip resistor 1 of the present embodiment includes similar steps to those of the method for manufacturing the chip resistor 1 of the first embodiment, but differs from the method for manufacturing the chip resistor 1 of the first embodiment in the following points.

[0057] 4, 20, and 21, forming the first laminate 36 of the present embodiment (step S1) further includes forming a second plating layer 45 on the first plating layer 37 by plating (step S14). The second plating layer 45 is formed of the same material as the first plating coating layer 25 and the second plating coating layer 26. The outermost surface 45a of the second plating layer 45 has higher solder wettability than the first plating layer 37. The outermost surface 45a of the second plating layer 45 is formed of, for example, tin (Sn) or nickel (Ni). In this way, the first laminate 36 is formed, which is a laminate of the metal resistor plate 30, the first plating layer 37, and the second plating layer 45.

[0058] 4 and 22, in step S2 of the present embodiment, a portion of the first plating layer 37 and a portion of the second plating layer 45 are removed from the first laminate 36. A groove 40 is formed in the first laminate 36. In the groove 40, the first main surface 31 of the metal resistor plate 30 is exposed from the first plating layer 37. A method for removing the portion of the first laminate 36 is, for example, machining such as cutting or milling using a cutting tool 42 (see FIG. 9).

[0059] 4 and 23, in step S3 of the present embodiment, the first laminate 36 is punched out so as to cross the grooves 40. The first laminate 36 is punched out, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching out the first laminate 36, the first plating coating layer 25 and the second plating coating layer 26 spaced apart from the first plating coating layer 25 are formed from the second plating layer 45. The first plating coating layer 25 is formed on the first surface 21a of the first plating electrode 21. The second plating coating layer 26 is formed on the second surface 22a of the second plating electrode 22. In this way, the second laminate 43 is formed, which is a laminate of the metal resistor 10, the first plating electrode 21, the second plating electrode 22, the first plating coating layer 25, and the second plating coating layer 26.

[0060] 4, the second laminate 43 is folded (step S4), thereby obtaining the chip resistor 1 of the present embodiment shown in FIG.

[0061] A chip resistor 1 according to a modification of the present embodiment will be described with reference to Figures 24 and 25. The chip resistor 1 according to the modification of the present embodiment has a similar configuration to the chip resistor 1 according to the second embodiment, but differs from the chip resistor 1 according to the second embodiment in that it further includes a first plating coating layer 25 and a second plating coating layer 26.

[0062] 25, the chip resistor 1 is mounted on a circuit board 50. The first plated electrode 21 coated with the first plated coating layer 25 is joined to the electrical wiring 52 of the circuit board 50 using a conductive joining member 54 such as solder. The second plated electrode 22 coated with the second plated coating layer 26 is joined to the electrical wiring 53 of the circuit board 50 using a conductive joining member 55 such as solder.

[0063] An example of a method for manufacturing the chip resistor 1 according to a modified example of the present embodiment will be described with reference to Figures 4 and 26. The method for manufacturing the chip resistor 1 according to the modified example of the present embodiment includes similar steps to those of the method for manufacturing the chip resistor 1 according to the second embodiment, but differs from the method for manufacturing the chip resistor 1 according to the second embodiment in the following points.

[0064] 4 and 26, forming the first laminate 36 (step S1) in this modified example of the present embodiment further includes forming the second plating layer 45 on the first plating layer 37 by plating (step S14). The second plating layer 45 is made of the same material as the first plating coating layer 25 and the second plating coating layer 26. In this way, the first laminate 36, which is a laminate of the metal resistor plate 30, the first plating layer 37, and the second plating layer 45, is formed.

[0065] 4, in step S2 of the modification of the present embodiment, a portion of first plating layer 37 and a portion of second plating layer 45 are removed from first laminate 36. As in the second embodiment, grooves 40, 41 are formed in first laminate 36.

[0066] In step S3 of this modified example of the present embodiment, the first laminate 36 is punched out so as to cross the grooves 40, 41. The first plating electrode 21 and the second plating electrode 22 spaced apart from the first plating electrode 21 are formed from the first plating partial layer of the first plating layer 37. The first plating coating layer 25 and the second plating coating layer 26 spaced apart from the first plating coating layer 25 are formed from the second plating layer 45. The third plating electrode 23 and the fourth plating electrode 24 spaced apart from the third plating electrode 23 are formed from the second plating partial layer of the first plating layer 37. In this way, a second laminate 43 is formed, which is a laminate of the metal resistor 10, the first plating electrode 21, the second plating electrode 22, the first plating coating layer 25, the second plating coating layer 26, the third plating electrode 23, and the fourth plating electrode 24.

[0067] 4, the second laminate 43 is folded (step S4), thereby obtaining the chip resistor 1 according to the modified example of the present embodiment shown in FIG.

[0068] The chip resistor 1 and the manufacturing method thereof according to this embodiment have the following advantages in addition to the advantages of the chip resistor 1 and the manufacturing method thereof according to the first embodiment.

[0069] The chip resistor 1 of this embodiment further includes a first plating coating layer 25 and a second plating coating layer 26. The first plating coating layer 25 is disposed on the first plating electrode 21. The second plating coating layer 26 is disposed on the second plating electrode 22. A first outermost surface 25a of the first plating coating layer 25 has higher solder wettability than the first plating electrode 21. A second outermost surface 26a of the second plating coating layer 26 has higher solder wettability than the second plating electrode 22.

[0070] Since the chip resistor 1 includes the first plating coating layer 25 and the second plating coating layer 26, when mounting the chip resistor 1 on the circuit board 50, it is not necessary to form a layer on the first plating electrode 21 and the second plating electrode 22 that has higher solder wettability than the first plating electrode 21 and the second plating electrode 22. This improves the mountability of the chip resistor 1 on the circuit board 50.

[0071] In the chip resistor 1 of this embodiment, the first outermost surface 25a and the second outermost surface 26a are made of tin or nickel.

[0072] When mounting the chip resistor 1 on the circuit board 50, it is not necessary to form a layer on the first plated electrode 21 and the second plated electrode 22 that has higher solder wettability than the first plated electrode 21 and the second plated electrode 22. This improves the mountability of the chip resistor 1 on the circuit board 50.

[0073] In the manufacturing method of the chip resistor 1 of the present embodiment, the chip resistor 1 further includes a first plating coating layer 25 disposed on the first plating electrode 21 and a second plating coating layer 26 disposed on the second plating electrode 22. Forming the first laminate 36 (step S1) includes forming a second plating layer 45 on the first plating layer 37. An outermost surface 45a of the second plating layer 45 has higher solder wettability than the first plating layer 37. Removing a portion of the first laminate 36 (step S2) further includes removing a portion of the second plating layer 45 from the first laminate 36. By punching the first laminate 36, the first plating coating layer 25 and the second plating coating layer 26 are formed from the second plating layer 45.

[0074] Because the chip resistor 1 includes the first plating coating layer 25 and the second plating coating layer 26, when mounting the chip resistor 1 on the circuit board 50, it is not necessary to form a layer on the first plating electrode 21 and the second plating electrode 22 that has higher solder wettability than the first plating electrode 21 and the second plating electrode 22. According to the manufacturing method of the chip resistor 1 of this embodiment, a chip resistor 1 with improved mountability on the circuit board 50 can be manufactured.

[0075] In the method for manufacturing the chip resistor 1 of this embodiment, the outermost surface 45a of the second plating layer 45 is formed of tin or nickel.

[0076] When mounting the chip resistor 1 on the circuit board 50, it is not necessary to form a layer on the first plated electrode 21 and the second plated electrode 22 that has higher solder wettability than the first plated electrode 21 and the second plated electrode 22. According to the manufacturing method of the chip resistor 1 of this embodiment, a chip resistor 1 with improved mountability to the circuit board 50 can be manufactured.

[0077] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A metal resistor; a first plating electrode; a second plating electrode; the metal resistor includes a first bottom plate portion, a second bottom plate portion, a top plate portion disposed between the first bottom plate portion and the second bottom plate portion, a first inclined leg portion connected to the first bottom plate portion and the top plate portion, and a second inclined leg portion connected to the second bottom plate portion and the top plate portion; the first plating electrode is disposed on a bottom surface of the first bottom plate portion, on a bottom surface of the first inclined leg portion, and on a bottom surface of the top plate portion; A chip resistor, wherein the second plating electrodes are arranged on the bottom surface of the second bottom plate portion, on the bottom surface of the second inclined leg portion, and on the bottom surface of the top plate portion. (Appendix 2) a third plating electrode; and a fourth plating electrode. the third plating electrode is disposed on a top surface of the first bottom plate portion, on a top surface of the first inclined leg portion, and on a top surface of the top plate portion; A chip resistor as described in Appendix 1, wherein the fourth plated electrode is arranged on the top surface of the second bottom plate portion, on the top surface of the second inclined leg portion, and on the top surface of the top plate portion. (Appendix 3) a first plating coating layer disposed on the first plating electrode; a second plating coating layer disposed on the second plating electrode; a first outermost surface of the first plating coating layer has higher solder wettability than the first plating electrode; 3. The chip resistor according to claim 1, wherein the second outermost surface of the second plating coating layer has higher solder wettability than the second plating electrode. (Appendix 4) 4. The chip resistor according to claim 3, wherein the first outermost surface and the second outermost surface are formed of tin or nickel. (Appendix 5) 5. The chip resistor according to claim 1, wherein the chip resistor is a shunt resistor. (Appendix 6) 1. A method for manufacturing a chip resistor, the chip resistor including a metal resistive element having a top surface and a bottom surface, a first plating electrode disposed on the bottom surface, and a second plating electrode disposed on the bottom surface, the method comprising: forming a first laminate, the forming of the first laminate including forming a first plating layer on a first main surface of the metal resistor plate; removing a portion of the first laminate, wherein removing the portion of the first laminate includes removing a portion of the first plating layer from the first laminate; punching the first laminate from which the portion has been removed to form a second laminate, wherein by punching the first laminate, the metal resistor is formed from the metal resistor plate, and the first plated electrode and the second plated electrode are formed from the first plating layer; a first bottom plate portion, a second bottom plate portion, a top plate portion disposed between the first bottom plate portion and the second bottom plate portion, a first inclined leg portion connected to the first bottom plate portion and the top plate portion, and a second inclined leg portion connected to the second bottom plate portion and the top plate portion; the first plating electrode is disposed on the bottom surface of the first bottom plate portion, on the bottom surface of the first inclined leg, and on the bottom surface of the top plate portion; and the second plating electrode is disposed on the bottom surface of the second bottom plate portion, on the bottom surface of the second inclined leg, and on the bottom surface of the top plate portion. (Appendix 7) the chip resistor further includes a third plated electrode disposed on the top surface and a fourth plated electrode disposed on the top surface; forming the first laminate includes forming the first plating layer also on a second main surface of the metal resistor plate opposite to the first main surface, and the first plating layer includes a first plating portion layer formed on the first main surface and a second plating portion layer formed on the second main surface; removing the portion of the first laminate includes removing a portion of the first plated portion layer and a portion of the second plated portion layer from the first laminate; By punching out the first laminate, the first plated electrode and the second plated electrode are formed from the first plated portion layer, and the third plated electrode and the fourth plated electrode are formed from the second plated portion layer; A method for manufacturing a chip resistor as described in Appendix 6, wherein by bending the second laminate, the third plated electrode is arranged on the top surface of the first bottom plate portion, on the top surface of the first inclined leg portion, and on the top surface of the top plate portion, and the fourth plated electrode is arranged on the top surface of the second bottom plate portion, on the top surface of the second inclined leg portion, and on the top surface of the top plate portion. (Appendix 8) the chip resistor further includes a first plating coating layer disposed on the first plating electrode and a second plating coating layer disposed on the second plating electrode; forming the first laminate includes forming a second plating layer on the first plating layer, and an outermost surface of the second plating layer has higher solder wettability than the first plating layer; removing the portion of the first laminate further includes removing a portion of the second plating layer from the first laminate; A method for manufacturing a chip resistor described in Appendix 6 or Appendix 7, wherein the first plating coating layer and the second plating coating layer are formed from the second plating layer by punching out the first laminate. (Appendix 9) 9. The chip resistor according to claim 8, wherein the outermost surface of the second plating layer is formed of tin or nickel. (Appendix 10) 10. The method for manufacturing a chip resistor according to any one of Supplementary Note 6 to Supplementary Note 9, wherein the chip resistor is a shunt resistor.

[0078] The first to third embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0079] 1 chip resistor, 10 metal resistor, 11 first bottom plate portion, 12 second bottom plate portion, 13 top plate portion, 14 first inclined leg portion, 15 second inclined leg portion, 16 top surface, 17 bottom surface, 18 first end surface, 19 second end surface, 21 first plating electrode, 21a first surface, 21b first inner end surface, 21c first outer end surface, 22 second plating electrode, 22a second surface, 22b second inner end surface, 22c second outer end surface, 23 third plating electrode, 24 fourth plating electrode, 25 first plating coating layer, 25a first outermost surface, 26 second plating coating layer, 26a second outermost surface, 30 metal resistor plate, 31 first main surface, 32 second main surface, 35 mask, 36 first laminate, 37 first plating layer, 40, 41 groove, 42 cutting tool, 43 Second laminate, 45: second plating layer, 45a: outermost surface, 50: circuit board, 51: insulating substrate, 52, 53: electrical wiring, 54, 55: conductive joining member.

Claims

1. A metal resistor; a first plating electrode; a second plating electrode; the metal resistor includes a first bottom plate portion, a second bottom plate portion, a top plate portion disposed between the first bottom plate portion and the second bottom plate portion, a first inclined leg portion connected to the first bottom plate portion and the top plate portion, and a second inclined leg portion connected to the second bottom plate portion and the top plate portion; the first plating electrode is disposed on a bottom surface of the first bottom plate portion, on a bottom surface of the first inclined leg portion, and on a bottom surface of the top plate portion; A chip resistor, wherein the second plating electrodes are arranged on the bottom surface of the second bottom plate portion, on the bottom surface of the second inclined leg portion, and on the bottom surface of the top plate portion.

2. a third plating electrode; and a fourth plating electrode. the third plating electrode is disposed on a top surface of the first bottom plate portion, on a top surface of the first inclined leg portion, and on a top surface of the top plate portion; The chip resistor according to claim 1 , wherein the fourth plated electrode is arranged on the top surface of the second bottom plate portion, on the top surface of the second inclined leg portion, and on the top surface of the top plate portion.

3. a first plating coating layer disposed on the first plating electrode; a second plating coating layer disposed on the second plating electrode; a first outermost surface of the first plating coating layer has higher solder wettability than the first plating electrode; The chip resistor according to claim 1 , wherein a second outermost surface of the second plating coating layer has higher solder wettability than the second plating electrode.

4. The chip resistor according to claim 3 , wherein the first outermost surface and the second outermost surface are formed of tin or nickel.

5. The chip resistor according to claim 1 , wherein the chip resistor is a shunt resistor.

6. 1. A method for manufacturing a chip resistor, the chip resistor including a metal resistive element having a top surface and a bottom surface, a first plating electrode disposed on the bottom surface, and a second plating electrode disposed on the bottom surface, the method comprising: forming a first laminate, the forming of the first laminate including forming a first plating layer on a first main surface of the metal resistor plate; removing a portion of the first laminate, wherein removing the portion of the first laminate includes removing a portion of the first plating layer from the first laminate; punching the first laminate from which the portion has been removed to form a second laminate, wherein by punching the first laminate, the metal resistor is formed from the metal resistor plate, and the first plated electrode and the second plated electrode are formed from the first plated layer; a first bottom plate portion, a second bottom plate portion, a top plate portion disposed between the first bottom plate portion and the second bottom plate portion, a first inclined leg portion connected to the first bottom plate portion and the top plate portion, and a second inclined leg portion connected to the second bottom plate portion and the top plate portion; the first plating electrode is disposed on the bottom surface of the first bottom plate portion, on the bottom surface of the first inclined leg, and on the bottom surface of the top plate portion; and the second plating electrode is disposed on the bottom surface of the second bottom plate portion, on the bottom surface of the second inclined leg, and on the bottom surface of the top plate portion.

7. The chip resistor further includes a third plated electrode disposed on the top surface and a fourth plated electrode disposed on the top surface, forming the first laminate includes forming the first plating layer also on a second main surface of the metal resistor plate opposite to the first main surface, and the first plating layer includes a first plating portion layer formed on the first main surface and a second plating portion layer formed on the second main surface; removing the portion of the first laminate includes removing a portion of the first plated portion layer and a portion of the second plated portion layer from the first laminate; By punching out the first laminate, the first plated electrode and the second plated electrode are formed from the first plated portion layer, and the third plated electrode and the fourth plated electrode are formed from the second plated portion layer; 7. A method for manufacturing a chip resistor as described in claim 6, wherein by bending the second laminate, the third plating electrode is arranged on the top surface of the first bottom plate portion, on the top surface of the first inclined leg portion, and on the top surface of the top plate portion, and the fourth plating electrode is arranged on the top surface of the second bottom plate portion, on the top surface of the second inclined leg portion, and on the top surface of the top plate portion.

8. The chip resistor further includes a first plating coating layer disposed on the first plating electrode and a second plating coating layer disposed on the second plating electrode, forming the first laminate includes forming a second plating layer on the first plating layer, and an outermost surface of the second plating layer has higher solder wettability than the first plating layer; removing the portion of the first laminate further includes removing a portion of the second plating layer from the first laminate; 8. The method for manufacturing a chip resistor according to claim 6, wherein the first plated coating layer and the second plated coating layer are formed from the second plating layer by punching out the first laminate.

9. The chip resistor according to claim 8 , wherein the outermost surface of the second plating layer is formed of tin or nickel.

10. The method for manufacturing a chip resistor according to claim 6 or 7, wherein the chip resistor is a shunt resistor.

Images