Circuit device and switching regulator

Abstract

To provide a circuit device and the like capable of suppressing a transient decrease in output voltage when a load current of a switching regulator increases.SOLUTION: The circuit device 10 includes an error amplifier 13, a slope voltage generation circuit 14, an adder circuit 15, a comparator 16, and a switching control circuit 17. The error amplifier 13 amplifies an error between a comparison voltage VC corresponding to the output voltage VOUT and a reference voltage VREF, and outputs an error voltage COMP. The slope voltage generation circuit 14 generates a slope voltage RAMP1. The addition circuit 15 adds an addition voltage VA to the slope voltage RAMP1, and outputs an added slope voltage RAMP2. The comparators 16 compare the difference voltage COMP with the added slope voltage RAMP2, and outputs a comparison result signal COMPO. The switching control circuit 17 performs switching control of the switching element 20 based on the output signal COMPO.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit device, a switching regulator, and the like. [Background technology]

[0002] Conventionally, switching regulators that constitute DC-DC converters are known. Patent Document 1 discloses a method in which an error amplifier (feedback amplifier) ​​that compares an output voltage with a reference voltage detects the amount of error, and a PWM comparator compares the amount of error with a slope voltage, thereby adjusting the duty cycle of a drive signal for a power switch. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-032745 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional methods, the error amplifier includes an integrating capacitor, which slows down feedback in response to a sudden drop in output voltage, resulting in a large fluctuation range of the output voltage. Therefore, it is desirable to propose a method for switching regulators that can be applied to a wider range of electronic devices. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device used in a switching regulator that outputs an output voltage by regulating a power supply voltage using an inductor and a switching element that drives the inductor, the circuit device including: an error amplifier that amplifies an error between a comparison voltage corresponding to the output voltage and a reference voltage to output an error voltage; a slope voltage generation circuit that generates a slope voltage; an adder circuit that adds an adder voltage corresponding to the output voltage to the slope voltage to output a summed slope voltage; a comparator that compares the error voltage with the summed slope voltage and outputs a pulse signal that is the comparison result; and a switching control circuit that controls the switching of the switching element based on the pulse signal.

[0006] Another aspect of the present disclosure relates to a switching regulator including the above circuit device, the switching element, and the inductor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a switching regulator including a circuit device. [Figure 2] 1A and 1B are diagrams conceptually explaining the operation of a circuit device. [Figure 3] 10A and 10B are diagrams conceptually explaining the operation of the present embodiment; [Figure 4] 10A and 10B are diagrams conceptually explaining the effects of the present embodiment. [Figure 5] FIG. 2 is a diagram for explaining a first voltage divider circuit, a second voltage divider circuit, and an error amplifier in more detail. [Figure 6] FIG. 1 is a diagram illustrating an example of a contactless power system. [Figure 7] 1A to 1C illustrate examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0009] 1 shows an example of the configuration of a switching regulator 1 including a circuit device 10. The switching regulator 1 regulates a power supply voltage VIN to an output voltage VOUT and supplies the output voltage VOUT to a load 300 (not shown in FIG. 1). A power supply circuit (not shown) is provided outside or inside the circuit device 10, and the power supply voltage VIN is supplied from the power supply circuit to the circuit device 10. The load 300 will be described later with reference to FIG. 6.

[0010] As shown in FIG. 1, the switching regulator 1 of this embodiment includes a circuit device 10, a switching element 20, and an inductor 23. The switching regulator 1 may further include a capacitor 24. The switching regulator 1 is also called a DC-DC converter. An inductor is also called a coil. One end of the inductor 23 is connected to a node NSW, and the other end of the inductor 23 is connected to a node NVOUT, which is a node at which an output voltage VOUT is output. One end of the capacitor 24 is connected to the node NVOUT, and the other end of the capacitor 24 is connected to a ground node.

[0011] The circuit device 10 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. As shown in FIG. 1 , the circuit device 10 of this embodiment includes an error amplifier 13, a slope voltage generating circuit 14, an adder circuit 15, a comparator 16, and a switching control circuit 17.

[0012] The error amplifier 13 amplifies the error between the comparison voltage VC corresponding to the output voltage VOUT and the reference voltage VREF, and outputs the error voltage COMP. The comparison voltage VC will be described in detail later. The error amplifier 13 is an integrating circuit that integrates the difference between the comparison voltage VC and the reference voltage VREF, and includes an operational amplifier and an integrating capacitor. Specific examples of the operational amplifier and integrating capacitor will be described later with reference to FIG. 5. The reference voltage VREF is input to the positive input terminal of the operational amplifier, and the comparison voltage VC is input to the negative input terminal of the operational amplifier, with feedback via the integrating capacitor between the output terminal and the negative input terminal of the operational amplifier.

[0013] The slope voltage generation circuit 14 receives a pulse signal QOUT (described later) from the switching control circuit 17. When the received pulse signal QOUT is at a high level, the slope voltage generation circuit 14 generates a slope voltage RAMP1 whose voltage increases over time. When the pulse signal QOUT is at a low level, the slope voltage generation circuit 14 resets the slope voltage RAMP1. More specifically, the slope voltage generation circuit 14 generates a slope voltage RAMP1 that increases at a given slope from an initial voltage. For this reason, the slope voltage is also called a triangular wave. The initial voltage refers to the voltage at which the slope starts, and the specific value of the initial voltage is determined appropriately. Resetting the slope voltage RAMP1 means that the value of the slope voltage RAMP1 becomes the initial voltage value. Note that hereinafter, the "voltage value" may be simply referred to as "voltage," and the "current value" may be simply referred to as "current."

[0014] The adder circuit 15 is a voltage adder circuit that adds the sum voltage VA to the slope voltage RAMP1 to output the post-addition slope voltage RAMP2. The initial voltage of the post-addition slope voltage RAMP2 is the sum of the initial voltage of the slope voltage RAMP1 and the sum voltage VA. When the slope voltage RAMP1 increases at a given slope, the post-addition slope voltage RAMP2 also increases at the same slope. The sum voltage VA is a voltage that corresponds to the output voltage VOUT. As will be described in detail later, for example, as the output voltage VOUT increases, the sum voltage VA also increases, and as the output voltage VOUT decreases, the sum voltage VA also decreases. While not shown in detail, the adder circuit 15 may include, for example, multiple common-source circuits and current mirror circuits. For example, by connecting a first common-source circuit and a first current path based on the sum voltage VA and a second common-source circuit and a second current path based on the slope voltage RAMP1 in parallel via a predetermined node, the current at the predetermined node is the sum of the first current and the second current. Then, by connecting a predetermined node to a current mirror circuit and connecting the path of the mirrored current to a third common-source circuit, a post-addition slope voltage RAMP2, which is a voltage obtained by adding the addition voltage VA and the slope voltage RAMP1, is output from the third common-source circuit. Note that the above is an example in which the slope voltage RAMP1 and the addition voltage VA are added using a current addition method, but this is not limiting, and an example in which the slope voltage RAMP1 and the addition voltage VA are added using a voltage addition method using an operational amplifier and resistors, etc., is also possible. In this way, the adder circuit 15 of this embodiment adds the addition voltage VA corresponding to the output voltage VOUT to the slope voltage RAMP1 and outputs the post-addition slope voltage RAMP2.

[0015] The comparator 16 compares the error voltage COMP with the post-addition slope voltage RAMP2 and outputs the result as an output signal COMPO. More specifically, in FIG. 1, for example, the error voltage COMP is input to the negative input terminal of the comparator 16, and the post-addition slope voltage RAMP2 is input to the positive input terminal. In this way, the comparator 16 of this embodiment compares the error voltage COMP with the post-addition slope voltage RAMP2 and outputs the output signal COMPO, which is the comparison result.

[0016] Upon receiving the output signal COMPO, the switching control circuit 17 outputs a drive signal DRP to the switching element 20. In addition, the switching control circuit 17 outputs a pulse signal QOUT to the slope voltage generating circuit 14 described above.

[0017] The switching control circuit 17 includes, for example, a controller (not shown) and a pre-driver (not shown). The controller also includes, for example, an RS latch circuit (not shown) and an off-timer (not shown). For example, the length of the off-time during which the switching element 20 is off is set in the off-timer. The RS latch circuit receives a set signal SET from the off-timer as a set signal and an output signal COMPO from the comparator 16 as a reset signal, and outputs a pulse signal QOUT based on these set signal and reset signal. Although not shown, the pulse signal QOUT is transmitted to the pre-driver, the off-timer, and the slope voltage generation circuit 14, respectively. When the input pulse signal QOUT is at a high level, the pre-driver controls the drive signal DRP so that the switching element 20 is turned on. In other words, when the input pulse signal QOUT is at a low level, the pre-driver controls the drive signal DRP so that the switching element 20 is turned off.

[0018] The switching element 20 may be any element that can be switched under the control of the switching control circuit 17, but FIG. 1 shows a switching element 21 as one specific example. The switching element 21 is a P-type MOS transistor. The source of the switching element 21 is connected to a node of the power supply voltage VIN, and the drain is connected to a node NSW. A drive signal DRP from the switching control circuit 17 is input to the gate of the switching element 21. When the switching element 21 is on, the inductor 23 is driven by the power supply voltage VIN. Although detailed explanation of the specific operation will be omitted, the switching element 20 is not limited to the switching element 21 as a P-type MOS transistor, and can also be realized by, for example, an N-type MOS transistor or a bipolar transistor.

[0019] When the switching element 20 is a P-type MOS transistor switching element 21, the pre-driver sets the drive signal DRP to low level when the input pulse signal QOUT is high level, thereby turning on the switching element 21. Similarly, when the input pulse signal QOUT is low level, the pre-driver sets the drive signal DRP to high level, thereby turning off the switching element 21.

[0020] The switching regulator 1 of this embodiment may be either a synchronous type or an asynchronous type. FIG. 1 illustrates a synchronous type using the above-described switching elements 21 and 22. The switching element 22 is an N-type MOS transistor. The source of the switching element 22 is connected to the ground node, and the drain is connected to node NSW. A drive signal DRN from the switching control circuit 17 is input to the gate of the switching element 22. If the switching regulator 1 is an asynchronous type, the switching element 22 may be a diode. In this case, the anode of the switching element 22 is connected to the ground node, and the cathode is connected to node NSW. In the following description, the switching element 20 may be specifically referred to as the switching element 21. If the switching regulator 1 is a synchronous type, the pre-driver may control the drive signals DRP and DRN to be signals that exclusively indicate on or off based on the logic of the pulse signal QOUT. Specifically, for example, when the input pulse signal QOUT is at a high level, the pre-driver controls the drive signal DRP to be a signal indicating on and the drive signal DRN to be a signal indicating off. Also, when the input pulse signal QOUT is at a low level, the pre-driver controls the drive signal DRP to be a signal indicating off and the drive signal DRN to be a signal indicating on.

[0021] FIG. 2 shows waveform examples illustrating the operation of the circuit device 10 in a steady state. The steady state here refers to an ideal state in which the current flowing through the load 300 (hereinafter referred to as the "load current") and the output voltage VOUT are within a certain range. In the steady state, the error amplifier 13 outputs a constant error voltage COMP. For example, at timing t0 in FIG. 2, the set signal SET of the off timer included in the switching control circuit 17 goes high, causing the RS latch circuit to set the pulse signal QOUT to high. This causes the slope voltage generation circuit 14 to generate the slope voltage RAMP1, which increases. This also causes the post-addition slope voltage RAMP2 to increase. When the pulse signal QOUT goes high, the pre-driver sets the drive signal DRP to low, turning on the switching element 21. This stores energy in the inductor 23.

[0022] At timing t1, which is later than timing t0, the comparator 16 outputs a high-level output signal COMPO to the switching control circuit 17 when it determines that the post-addition slope voltage RAMP2 exceeds the error voltage COMP.

[0023] The RS latch circuit included in the switching control circuit 17 sets the pulse signal QOUT to low level based on the input high-level output signal COMPO. A delay period may be provided between the timing when the output signal COMPO goes high and the timing when the pulse signal QOUT goes low. In this embodiment, the pulse signal QOUT is set to low level at timing t2, which is after timing t1. This causes the pulse signal QOUT to go high for the period indicated by A2. When the pulse signal QOUT goes low at timing t2, the off-timer is started, the slope voltage RAMP1 is reset, and the output signal COMPO goes low. When the pulse signal QOUT goes low, the pre-driver also sets the drive signal DRP to high level to turn off the switching element 21. In this manner, the switching control circuit 17 of this embodiment switches the switching element 20 from on to off based on the comparator 16 determining that the post-addition slope voltage RAMP2 exceeds the error voltage COMP.

[0024] Then, from timing t2 until timing t3, which is a timing after timing t2, the off timer is activated, so the set signal SET is maintained at a low level. As a result, the pulse signal QOUT is also maintained at a low level, and the slope voltage generation circuit 14 outputs the slope voltage RAMP1 so as to maintain the initial voltage, and the slope voltage RAMP1 does not increase at a given slope. Therefore, from timing t2 to timing t3, the added slope voltage RAMP2 also does not increase at a given slope. Therefore, from timing t2 to timing t3, the pulse signal QOUT is also maintained at a low level, and the drive signal DRP is maintained at a high level, so the switching element 21 is maintained in an off state. In this way, in the circuit device 10 of this embodiment, during a given period (the period from timing t2 to timing t3) after the switching element 20 changes from on to off, the switching control circuit 17 turns off the switching element 20, and the slope voltage generation circuit 14 maintains the slope voltage RAMP1 at the initial voltage.

[0025] Then, at timing t3, the set signal SET of the off timer goes high, causing the RS latch circuit to set the pulse signal QOUT to high. This causes the slope voltage generation circuit 14 to generate the slope voltage RAMP1, which then rises. Timing t3 is the timing obtained by adding the period set by the off timer to timing t2. In other words, the period indicated by A1 in FIG. 2 is the period set by the off timer. Thus, the operations at timings t3, t4, and t5 shown in FIG. 2 correspond to the operations at timings t0, t1, and t2 described above, and similar operations are repeated. Therefore, for example, at timing t3, the slope voltage RAMP1 is increased at a given slope, and the resulting slope voltage RAMP2 also rises at a given slope. Similarly, for example, at timing t4, the comparator 16 sets the output signal COMPO to a high level, the pulse signal QOUT is at a high level between timing t4 and timing t5, and the comparator 16 sets the output signal COMPO to a low level at timing t5. Thus, in the circuit device 10 of this embodiment, after a given period has elapsed (after timing t3), the switching control circuit 17 turns the switching element 20 from off to on, and the slope voltage generation circuit 14 increases the slope voltage RAMP1 at a given slope.

[0026] The output voltage VOUT is determined based on the energy periodically stored in the inductor 23. Note that Figure 2 shows operation in a steady state, but if the output voltage VOUT fluctuates, for example, the error voltage COMP fluctuates, causing the width of the pulse signal QOUT to fluctuate and the time that the switching element 20 is on to fluctuate as well. As a result, feedback control is performed to keep the output voltage VOUT constant.

[0027] Although a configuration in which the switching element 20 is controlled by comparing the slope voltage RAMP1 and the error voltage COMP and the output voltage VOUT is feedback-controlled has been proposed in the past, the circuit device 10 of this embodiment further includes an adder circuit 15, which produces a unique function as shown in Fig. 3. Note that in Fig. 3, explanations of content that overlaps with the explanation of Fig. 2 will be omitted as appropriate.

[0028] For example, assume that at time t10 in FIG. 3 , the magnitude of the load 300 increases, causing an increase in the load current and starting a decrease in the output voltage VOUT. In this case, the error voltage COMP starts to rise. A10 in FIG. 3 is a hypothetical waveform example in which the slope voltage RAMP1 from the slope voltage generation circuit 14 is input to the comparator 16 without including the adder circuit 15 of this embodiment. On the other hand, A12 in FIG. 3 is a waveform example in which the adder circuit 15 of this embodiment is included and the post-addition slope voltage RAMP2 is input to the comparator 16. Note that, to facilitate understanding of the technique of this embodiment, the difference between the voltage of the error voltage COMP before time t10 in the waveform example A10 and the initial voltage of the slope voltage RAMP1 is assumed to be equal to the difference between the voltage of the error voltage COMP before time t10 and the initial voltage of the post-addition slope voltage RAMP2 in the waveform example A12.

[0029] At timing t11, the set signal SET (not shown in FIG. 3) goes high, causing the pulse signal QOUT to go high. In the waveform example shown in A10, at timing t12, which is after timing t11, the comparator 16 determines that the slope voltage RAMP1 is greater than the error voltage COMP and sets the output signal COMPO (not shown in FIG. 3) to high. This causes the RS latch circuit to set the pulse signal QOUT to low. This causes the pulse signal QOUT to go high for the period shown in A11. The period shown in A11 in FIG. 3 is longer than the period shown in A2 in FIG. 2. This is because, unlike in FIG. 2, the error voltage COMP is rising in FIG. 3. This causes the switching element 20 to be on for a longer period, storing more energy in the inductor 23. This causes the decreased output voltage VOUT to be fed back in an upward direction.

[0030] On the other hand, in the waveform example shown in A12, the added voltage VA is a voltage corresponding to the output voltage VOUT, so as shown in A13, the initial voltage of the added slope voltage RAMP2 starts to decrease from time t10 in response to the decrease in the output voltage VOUT. Then, at time t11, the added slope voltage RAMP2 starts to increase in response to the increase in the slope voltage RAMP1.

[0031] Then, at timing t13, the comparator 16 determines that the post-addition slope voltage RAMP2 is greater than the error voltage COMP and sets the output signal COMPO (not shown in FIG. 3) to high level. This causes the RS latch circuit to set the pulse signal QOUT to low level. As a result, the pulse signal QOUT remains high level only for the period indicated by A14. As such, because the initial voltage of the post-addition slope voltage RAMP2 temporarily drops and the slope voltage RAMP1 and the post-addition slope voltage RAMP2 rise at the same rate, timing t13 occurs after timing t12. Therefore, the period indicated by A14 is longer than the period indicated by A11.

[0032] In this way, by applying the method of this embodiment, the period during which the switching element 20 is on when the load current drops becomes longer than the period during which the switching element 20 is on in a case where the adder circuit 15 is not included. In the steady state described above in FIG. 2, there is no difference in the period during which the pulse signal QOUT is at a high level between the case shown by A10 and the case shown by A12.

[0033] For this reason, the technique of this embodiment achieves the effect conceptually illustrated in the waveform example of FIG. 4. In FIG. 4, assume that the load current increases at time t10, causing the output voltage VOUT to drop, and then the output voltage VOUT, which has dropped at time t20, is fed back to the value at time t10. A21 in FIG. 3 represents the hypothetical duty ratio of the pulse signal QOUT when the adder circuit 15 is not included, as described above for A10 in FIG. 2. A22 in FIG. 3 represents the duty ratio of the pulse signal QOUT when the adder circuit 15 is included, as described above for A12 in FIG. 2. The duty ratio of the pulse signal QOUT is the ratio of the period during which the pulse signal QOUT is at a high level to the total period during which the pulse signal QOUT is output. Comparing the waveforms A21 and A22 in FIG. 3, it can be seen that the duty ratio of the pulse signal QOUT increases earlier in the waveform A22. As described above with reference to FIG. 2, this is because the period during which the pulse signal QOUT is at a high level when the adder circuit 15 is included is longer than the period during which the pulse signal QOUT is at a high level when the adder circuit 15 is not included.

[0034] A31 in Fig. 3 is a hypothetical waveform example conceptually showing the behavior of the output voltage VOUT when it is assumed that the adder circuit 15 is not included, as described above in A10 in Fig. 2. A32 in Fig. 3 is a waveform example conceptually showing the behavior of the output voltage VOUT when it is assumed that the adder circuit 15 is included, as described above in A12 in Fig. 2. Comparing the waveform example A31 with the waveform example A32, it can be seen that the inclusion of the adder circuit 15 minimizes the decrease in the output voltage VOUT when the load current increases.

[0035] As described above, this embodiment relates to a circuit device 10 used in a switching regulator 1 that outputs an output voltage VOUT by regulating a power supply voltage V using an inductor 23 and a switching element 20 that drives the inductor 23. The circuit device 10 includes an error amplifier 13, a slope voltage generation circuit 14, an adder circuit 15, a comparator 16, and a switching control circuit 17. The error amplifier 13 amplifies the error between a comparison voltage VC corresponding to the output voltage VOUT and a reference voltage VREF to output an error voltage COMP. The slope voltage generation circuit 14 generates a slope voltage RAMP1. The adder circuit 15 adds an adder voltage VA corresponding to the output voltage VOUT to the slope voltage RAMP1 to output a post-addition slope voltage RAMP2. The comparator 16 compares the error voltage COMP with the post-addition slope voltage RAMP2 and outputs an output signal COMPO, which is the comparison result. The switching control circuit 17 controls the switching of the switching element 20 based on the output signal COMPO.

[0036] As described above, the circuit device 10 of this embodiment includes the error amplifier 13, the slope voltage generating circuit 14, the comparator 16, and the switching control circuit 17, and therefore can be used for switching control of the switching regulator 1. Furthermore, by including the adder circuit 15, the period during which the switching element 20 is turned on can be extended when the load current increases. This makes it possible to reduce the decrease in the output voltage VOUT when the load current increases.

[0037] Another possible approach is to lengthen the period during which the switching element 20 is turned on when the load current increases, for example, by increasing the rate of increase in the error voltage COMP. However, this would increase the amount of current flowing through the circuit device 10 and increase power consumption. In this regard, by applying the approach of this embodiment, it is possible to construct a circuit device 10 that reduces the fluctuation range of the output voltage VOUT while suppressing an increase in power consumption. This allows the circuit device 10 of this embodiment to be applied to a wider range of electronic devices.

[0038] The technique of this embodiment may also be realized as a switching regulator 1. That is, the switching regulator 1 of this embodiment includes a circuit device 10, a switching element 20, and an inductor 23. By doing so, the same effects as those described above can be obtained.

[0039] Furthermore, the added voltage VA may be lower as the output voltage VOUT decreases. In this way, when the output voltage VOUT decreases, the initial voltage of the added slope voltage RAMP2 can be lowered. This allows for the construction of a circuit device 10 that extends the period during which the switching element 20 is turned on when the output voltage VOUT decreases.

[0040] Alternatively, the slope voltage generating circuit 14 may generate a slope voltage RAMP1 that rises from an initial voltage at a given slope, and the adding circuit 15 may add the adding voltage VA to the slope voltage RAMP1 to output a post-addition slope voltage RAMP2. Alternatively, the switching control circuit 17 may switch the switching element 20 from on to off based on the determination by the comparator 16 that the post-addition slope voltage RAMP2 has exceeded the error voltage COMP. In this way, a circuit can be constructed that controls the period during which the switching element 20 is on by linearly changing the post-addition slope voltage RAMP2.

[0041] Furthermore, during a given period after the switching element 20 changes from on to off (the period from timing t2 to timing t3 in FIG. 2 ), the switching control circuit 17 may turn off the switching element 20, and the slope voltage generation circuit 14 may maintain the slope voltage RAMP1 at the initial voltage. Alternatively, after the given period has elapsed, the switching control circuit 17 may turn the switching element 20 from off to on, and the slope voltage generation circuit 14 may increase the slope voltage at a given slope. In this way, a circuit can be constructed that controls both the period during which the switching element 20 is on and the period during which the switching element 20 is off by linearly changing the post-addition slope voltage RAMP2.

[0042] The comparison voltage VC and the sum voltage VA will be described in more detail. For example, as shown in FIG. 1, the input node of the first voltage divider circuit 11 is connected to a node N1, and the input node of the second voltage divider circuit 12 is connected to the node N1. The node N1 is connected to a node NVOUT. The first voltage divider circuit 11 outputs the comparison voltage VC, and the second voltage divider circuit 12 outputs the sum voltage VA. In other words, the comparison voltage VC is a voltage generated by dividing the output voltage VOUT using the first voltage divider circuit 11, and the sum voltage VA is a voltage generated by dividing the output voltage VOUT using the second voltage divider circuit 12. The output node from which the comparison voltage VC is output is connected to the negative input node of the error amplifier 13, and the output node from which the sum voltage VA is output is connected to the input node of the adder circuit 15.

[0043] FIG. 5 is a diagram illustrating the first voltage divider circuit 11 and the second voltage divider circuit 12 in more detail. For ease of explanation, FIG. 5 also includes a diagram illustrating the error amplifier 13 in more detail. The first voltage divider circuit 11 includes a resistor 41, a capacitor 42, a resistor 43, and a resistor 44. The resistor 41 has one end connected to node N2, which is the input node of the first voltage divider circuit 11, and the other end connected to node N3. The capacitor 42 has one end connected to node N2 and the other end connected to one end of the resistor 43. The resistor 43 has one end connected to the other end of the capacitor 42 and the other end connected to node N3. The resistor 44 has one end connected to node N4 and the other end connected to a ground node. The node N4 is a node between node N3 and node N6, which is the negative input node of the error amplifier 13. The voltage division ratio of the first voltage dividing circuit 11 is determined by the magnitudes of the resistors 41, 43 and 44.

[0044] The error amplifier 13 includes a resistor 61, a capacitor 62, a capacitor 63, and an operational amplifier 64. The negative input terminal of the operational amplifier 64 is connected to node N6, a reference voltage VREF is input to the positive input terminal of the operational amplifier 64, and an output terminal of the operational amplifier 64 is connected to node N7. The feedback path of the error amplifier 13 includes a resistor 61, a capacitor 62, and a capacitor 63. One end of the resistor 61 is connected to node N8 and the other end is connected to one end of the capacitor 62. Node N8 is a connection node with node N6. One end of the capacitor 62 is connected to the other end of the resistor 61 and the other end is connected to node N9. One end of the capacitor 63 is connected to node N8 and the other end is connected to node N9. Node N9 is a connection node with node N7, which is the output node of the error amplifier 13. The capacitors 62 and 63 are phase compensation capacitors and also integral capacitors.

[0045] By configuring the first voltage divider circuit 11 and the error amplifier 13 in this manner, the reference voltage VREF input to the positive input node of the error amplifier 13 is equal to the value obtained by multiplying the magnitude of the output voltage VOUT by the voltage division ratio of the first voltage divider circuit 11. The error amplifier 13 then performs feedback so that the comparison voltage VC matches the reference voltage VREF. In other words, the output voltage VOUT is controlled by fixing the reference voltage VREF and varying the voltage division ratio of the first voltage divider circuit 11. Therefore, as shown in FIG. 5 , the resistor 44 included in the first voltage divider circuit 11 may be a variable resistor. In other words, in the circuit device 10 of this embodiment, the voltage division ratio of the first voltage divider circuit 11 is variable. This allows the output voltage VOUT to be variable, thereby enabling the circuit device 10 to be used in a wider range of applications.

[0046] The second voltage-dividing circuit 12 includes resistors 51 and 52. Resistor 51 has one end connected to node N1 and the other end connected to node N5. Resistor 52 has one end connected to node N5 and the other end connected to ground. Node N5 is connected to an input node of adder circuit 15 (not shown in FIG. 5). The voltage division ratio of second voltage-dividing circuit 12 is determined by the magnitudes of resistors 51 and 52. As a result, an added voltage VA is input to adder circuit 15 via a path that does not pass through error amplifier 13. From another perspective, for example, if the output voltage VOUT fluctuates, the fluctuation in the output voltage VOUT can be considered to be directly reflected as the added voltage VA output from second voltage-dividing circuit 12, and the reflected added voltage VA can be considered to be input to adder circuit 15.

[0047] In other words, when the output voltage VOUT fluctuates, the fluctuations in the output voltage VOUT are not directly reflected in the comparison voltage VC output from the first voltage divider circuit 11. Due to a virtual short of the operational amplifier of the error amplifier 13, the voltage at node N6 is controlled to be equal to the reference voltage VREF. Therefore, the voltage at node N4 is controlled to be equal to the voltage at node N6 (reference voltage VREF), and the voltage at node N4 no longer matches the voltage obtained by multiplying the output voltage VOUT by the voltage division ratio of the first voltage divider circuit 111. Therefore, the circuit device 10 of this embodiment includes a first voltage divider circuit 11 that divides the output voltage VOUT and outputs the comparison voltage VC to the error amplifier 13, and a second voltage divider circuit 12 that divides the output voltage VOUT and outputs the sum voltage VA to the adder circuit 15. This configuration allows the sum voltage VA, which is generated based on the second voltage divider circuit 12 and directly reflects fluctuations in the output voltage VOUT, to be input to the adder circuit 15. This allows for faster feedback of fluctuations in the output voltage VOUT.

[0048] Although not shown, the circuit device 10 of this embodiment may be configured in such a manner that the second voltage divider circuit 12 is omitted from the configuration example shown in Fig. 1. In this case, the output voltage VOUT and the slope voltage RAMP1 are input to the adder circuit 15, and the output voltage VOUT and the slope voltage RAMP1 are added together to output a post-addition slope voltage RAMP2.

[0049] Whether the second voltage divider circuit 12 is required may be determined appropriately depending on, for example, the specifications of the circuit device 10. Because each component included in the circuit device 10 operates based on the power supply voltage VIN, the allowable range of the voltage of the signal input to the comparator 16 depends on the specifications of the power supply voltage VIN of the circuit device 10. Therefore, if the power supply voltage VIN of the circuit device 10 is sufficiently larger than the sum of the output voltage VOUT and the slope voltage RAMP1, the second voltage divider circuit 12 may be omitted.

[0050] More specifically, consider a case where the circuit device 10 has an output voltage VOUT specification of 1 to 3 V, and the circuit device 10 is operated with the amplitude of the slope voltage RAMP1 set to 0 to 1 V and the output voltage VOUT set to 3 V. In this case, if the circuit device 10 does not include the second voltage-divider circuit 12, a post-addition slope voltage RAMP2 of up to 4 V is input to the comparator 16. Whether or not the circuit device 10 should include the second voltage-divider circuit 12 can be determined depending on whether or not the post-addition slope voltage RAMP2 calculated in this manner meets the specification of the power supply voltage VIN.

[0051] In this way, in the circuit device 10 of this embodiment, the sum voltage VA is a voltage obtained by dividing the output voltage VOUT or the output voltage VOUT itself. In this way, it is possible to configure a circuit device 10 that can handle both cases where the sum voltage VA is obtained by dividing the output voltage VOUT and where the sum voltage VA is the output voltage VOUT itself.

[0052] The switching regulator 1 of this embodiment may be applied to, for example, a contactless power transmission system shown in Fig. 6. The contactless power transmission system may also be referred to as a non-contact power transmission system. The contactless power transmission system of Fig. 6 includes, for example, a power receiving device 100, a power transmitting device 200, and a load 300.

[0053] The power transmitting device 200 is a device that transmits power to the power receiving device 100 in a contactless manner, and includes a power transmitting circuit 202 and a primary coil 204. The power transmitting circuit 202 includes a power transmitting driver that drives the primary coil 204, a power supply circuit that supplies power to the power transmitting driver, and a capacitor that forms a resonant circuit together with the primary coil 204. The power transmitting circuit 202 configured in this manner generates an AC voltage of a predetermined frequency during power transmission and supplies the AC voltage to the primary coil 204. The primary coil 204 is electromagnetically coupled to the secondary coil 104 to form a power transmission transformer. For example, when power transmission is required, the magnetic flux of the primary coil 204 is set to pass through the secondary coil 104. On the other hand, when power transmission is not required, the magnetic flux of the primary coil 204 is set to not pass through the secondary coil 104. Although not shown, the power transmitting device 200 further includes a power transmitting side control circuit that performs various controls on the power transmitting side. Specifically, for example, the power transmitting side control circuit includes a communication circuit, a power supply voltage control circuit, a clock generation circuit, a driver control circuit, etc. The communication circuit receives power transmitting voltage setting information from the power receiving side. The power supply voltage control circuit generates a drive voltage for driving the power transmitting driver based on the power transmitting voltage setting information. The clock generation circuit generates a drive clock signal that defines the power transmitting frequency. The driver control circuit controls the power transmitting driver based on the drive voltage and drive clock signal.

[0054] The power receiving device 100 is a device that receives power from the power transmitting device 200 in a contactless manner, and includes a power feeding circuit 101, a power receiving circuit 102, and a secondary coil 104. The power receiving circuit 102 converts the AC induced voltage of the secondary coil 104 into a DC rectified voltage. The power feeding circuit 101 includes the switching regulator 1 of this embodiment, and supplies power to a load 300 based on the power related to the rectified voltage converted by the power receiving circuit 102. Although not shown, the power receiving device 100 further includes a power receiving-side control circuit that performs various controls on the power receiving side. Specifically, for example, the power receiving-side control circuit includes a detection circuit, etc. The detection circuit detects over-discharge, over-voltage, over-current, temperature abnormalities, etc.

[0055] The load 300 includes, for example, a battery 310 and a power supply target 320 of the battery 310. The battery 310 is, for example, a rechargeable secondary battery, such as a lithium battery or a nickel battery. The power supply target 320 is provided in an electronic device that incorporates the power receiving device 100, and is, for example, a device that is a power supply target of the battery 310.

[0056] As described above, a contactless power transmission system incorporating the switching regulator 1 of this embodiment can be used, for example, to charge an electronic device. The electronic device is, for example, an earphone shown in A41 in FIG. 7. The earphone shown in A41 is, more specifically, a hearing aid earphone, but it may also be another type of wireless earphone, such as an earphone for listening to audio. The earphone shown in A41 can be stored in a charging case shown in A42. In this case, the earphone A41 in FIG. 7 corresponds to the power receiving device 100 and load 300 in FIG. 6, and the charging case shown in A42 in FIG. 7 corresponds to the power transmitting device 200 in FIG. 6. In other words, power is supplied to the charging case shown in A42 in FIG. 7 via a power adapter (not shown), and this power charges a battery built into the earphone shown in A41 via contactless power transmission, thereby operating the earphone.

[0057] The electronic devices to which the contactless power transmission system can be applied are not limited to those shown in Fig. 7, but various other devices are conceivable, such as wristwatches, biological information measuring devices, personal digital assistants, cordless telephones, shavers, electric toothbrushes, wrist computers, handy terminals, in-vehicle devices, hybrid cars, electric cars, electric motorcycles, and electric bicycles.

[0058] As described above, this embodiment relates to a circuit device used in a switching regulator that outputs an output voltage by regulating a power supply voltage using an inductor and a switching element that drives the inductor. The circuit device includes an error amplifier, a voltage generation circuit, an adder circuit, a comparator, and a switching control circuit. The error amplifier amplifies the error between a comparison voltage corresponding to the output voltage and a reference voltage to output an error voltage. The slope voltage generation circuit generates a slope voltage. The adder circuit adds an adder voltage corresponding to the output voltage to the slope voltage to output a post-addition slope voltage. The comparator compares the error voltage with the post-addition slope voltage and outputs a pulse signal representing the comparison result. The switching control circuit controls the switching of the switching element based on the pulse signal.

[0059] In this way, by including an adder circuit, the circuit device of this embodiment can lengthen the period during which the switching element is on when the load current increases. This can reduce the drop in output voltage when the load current increases. This allows the circuit device of this embodiment to be applied to a wider range of electronic devices.

[0060] The added voltage may also be lower as the output voltage is lower.

[0061] By doing so, when the output voltage drops, the initial voltage of the added slope voltage can be lowered, thereby constructing a circuit device that extends the period during which the switching element is on when the output voltage drops.

[0062] The added voltage may be a voltage obtained by dividing the output voltage or the output voltage itself.

[0063] In this way, it is possible to construct a circuit device that can handle both the case where the output voltage is divided to obtain the sum voltage, and the case where the output voltage itself is used as the sum voltage.

[0064] The circuit device may also include a first voltage dividing circuit that divides the output voltage and outputs a comparison voltage to the error amplifier, and a second voltage dividing circuit that divides the output voltage and outputs an added voltage to the adder circuit.

[0065] This allows the summation voltage generated based on the second voltage divider circuit, which directly reflects fluctuations in the output voltage, to be input to the summation circuit, allowing for faster feedback of fluctuations in the output voltage.

[0066] The voltage division ratio of the first voltage dividing circuit may be variable.

[0067] In this way, the output voltage can be made variable, and the circuit device can be used in a wider range of applications.

[0068] Furthermore, the slope voltage generation circuit may generate a slope voltage that rises from the initial voltage at a given slope, the adder circuit may add the adder voltage to the slope voltage and output the added slope voltage, and the switching control circuit may turn the switching element from on to off based on the comparator determining that the added slope voltage exceeds the error voltage.

[0069] In this way, a circuit can be constructed that controls the period during which the switching element is on by linearly changing the added slope voltage.

[0070] Furthermore, in a given period after the switching element is turned from on to off, the switching control circuit may turn the switching element off, and the slope voltage generation circuit may maintain the slope voltage at the initial voltage. Furthermore, after the given period has elapsed, the switching control circuit may turn the switching element from off to on, and the slope voltage generation circuit may increase the slope voltage at a given slope.

[0071] In this way, it is possible to construct a circuit that controls both the period during which the switching element is on and the period during which the switching element is off by linearly changing the added slope voltage.

[0072] The present embodiment also relates to a switching regulator including the above-described circuit device, a switching element, and an inductor.

[0073] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the circuit device, switching regulator, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0074] 1...switching regulator, 10...circuit device, 11...first voltage divider circuit, 12...second voltage divider circuit, 13...error amplifier, 14...slope generating circuit, 15...adder circuit, 16...comparator, 17...switching control circuit, 20...switching element, 21...first switching element, 22...second switching element, 23...inductor, 24, 42, 62, 63...capacitor, 41, 43, 44, 51, 52, 61...resistor, 64...operational amplifier, 100...power receiving device, 101...power supply circuit, 102...power receiving circuit, 104...secondary coil, 200...power transmitting device, 202...power transmitting circuit , 204...Primary coil, 300...Load, 310...Battery, 320...Power supply target, COMP...Error voltage, COMPO...Output signal, DRN, DRP...Drive signal, N1, N2, N3, N4, N5, N6, N7, N8, N9, NSW, NVOUT...Node, QOUT...Pulse signal, SET...Set signal, t0, t1, t2, t3, t4, t5, t10, t11, t12, t13, t20...Timing, RAMP1...Slope voltage, RAMP2...Slope voltage after addition, VA...Addition voltage, VC...Comparison voltage, VIN...Power supply voltage, VOUT...Output voltage, VREF...Reference voltage

Claims

1. A circuit device used in a switching regulator that outputs an output voltage by regulating a power supply voltage using an inductor and a switching element that drives the inductor, an error amplifier that amplifies an error between a comparison voltage corresponding to the output voltage and a reference voltage and outputs an error voltage; a slope voltage generating circuit that generates a slope voltage; an adder circuit that adds an addition voltage corresponding to the output voltage to the slope voltage and outputs the added slope voltage; a comparator that compares the error voltage with the added slope voltage and outputs a pulse signal that is the comparison result; a switching control circuit that controls the switching of the switching element based on the pulse signal; A circuit device comprising:

2. 2. The circuit device according to claim 1, The circuit device is characterized in that the lower the output voltage, the lower the added voltage.

3. 2. The circuit device according to claim 1, The circuit device is characterized in that the added voltage is a voltage obtained by dividing the output voltage or the output voltage itself.

4. 2. The circuit device according to claim 1, a first voltage dividing circuit that divides the output voltage and outputs the comparison voltage to the error amplifier; a second voltage dividing circuit that divides the output voltage and outputs the summed voltage to the adding circuit; A circuit device comprising:

5. 5. The circuit device according to claim 4, A circuit device characterized in that the voltage division ratio of the first voltage divider circuit is variable.

6. 2. The circuit device according to claim 1, the slope voltage generating circuit generates the slope voltage that rises from an initial voltage at a given slope; the adder circuit adds the sum voltage to the slope voltage and outputs the summed slope voltage; The circuit device is characterized in that the switching control circuit switches the switching element from on to off based on the fact that the comparator determines that the added slope voltage has exceeded the error voltage.

7. 7. The circuit device according to claim 6, During a given period after the switching element is turned from on to off, the switching control circuit turns off the switching element, and the slope voltage generation circuit maintains the slope voltage at the initial voltage; After the given period has elapsed, the switching control circuit switches the switching element from off to on, and the slope voltage generation circuit increases the slope voltage at the given slope.

8. A circuit arrangement according to any one of claims 1 to 7; the switching element; the inductor; A switching regulator comprising:

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