Circuit device and switching regulator

Abstract

To provide a circuit device and the like capable of suppressing a transient decrease in output voltage when a load current of a switching regulator increases.SOLUTION: The circuit device 100 includes the control circuit 120 that receives the first feedback voltage FBA corresponding to the output voltage VOUT, performs the pulse modulation control for controlling the output voltage VOUT to a given constant voltage based on the first feedback voltage FBA, and performs the switching control on the switching element 111 based on the result of the pulse modulation control, and the first comparator 150 that receives the second feedback voltage FBB corresponding to the output voltage VOUT, compares the second feedback voltage FBB with the reference voltage VREF, and outputs the detection signal CMPO that becomes active when the second feedback voltage FBB becomes equal to or lower than the reference voltage VREF. When the detection signal CMPO becomes active, the control circuit 120 turns on the switching element 111.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit device, a switching regulator, and the like. [Background technology]

[0002] Patent Document 1 discloses a DC-DC converter that includes an error amplifier that compares the output voltage with a reference voltage, a peak current comparator that compares the coil current with the output of the error amplifier to generate a peak detection voltage, an off-time timer circuit that generates an off-time signal that sets the off time, control logic that generates a signal that drives the power stage based on the peak detection voltage and the off-time signal, and a power stage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0083583 Summary of the Invention [Problem to be solved by the invention]

[0004] When the load current of a switching regulator increases suddenly, the output voltage drops transiently. For example, in Patent Document 1, delays in the error amplifier and other components can cause feedback delays, which can lead to a large transient drop in output voltage. [Means for solving the problem]

[0005] One aspect of the present disclosure is a circuit device used in a switching regulator that outputs an output voltage that regulates a power supply voltage using an inductor and a switching element that drives the inductor, the circuit device including: a control circuit that receives a first feedback voltage corresponding to the output voltage, performs pulse modulation control to control the output voltage to a given constant voltage based on the first feedback voltage, and controls the switching of the switching element based on the result of the pulse modulation control; and a first comparator that receives a second feedback voltage corresponding to the output voltage, compares the second feedback voltage with a reference voltage, and outputs a detection signal that becomes active when the second feedback voltage becomes equal to or lower than the reference voltage, and the control circuit is related to the circuit device that turns on the switching element when the detection signal becomes active.

[0006] Another aspect of the present disclosure relates to a switching regulator including the above circuit device, the switching element, and the inductor. [Brief explanation of the drawings]

[0007] [Figure 1] First example of a switching regulator configuration. [Figure 2] Second configuration example of a switching regulator. [Figure 3] FIG. 3 is a waveform diagram illustrating the operation of a switching regulator. [Figure 4] 10 shows an example of a detailed configuration of a control circuit. [Figure 5] A detailed example of the pre-driver configuration. [Figure 6] Truth table describing the operation of the pre-driver. [Figure 7] 10 is a detailed configuration example of a pulse modulation control circuit. [Figure 8] 10 shows a detailed configuration example of an off timer when the length of the off time is variable. [Figure 9] Example waveforms illustrating the continuous operation of a switching regulator. [Figure 10]Example waveforms illustrating the discontinuous operation of a switching regulator. [Figure 11] 10 is a waveform example for schematically explaining transient operation when the first comparator and the second voltage dividing circuit are not provided. [Figure 12] 10 is a waveform example for schematically explaining transient operation when a first comparator and a second voltage dividing circuit are provided. [Figure 13] Example of a waveform used to simulate the operation of a switching regulator. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0009] 1.Configuration example 1 shows a first example configuration of a switching regulator 200. The switching regulator 200 includes a circuit device 100, an inductor 10, and a capacitor 20. The switching regulator 200 is also called a DC-DC converter. The inductor 10 is also called a coil.

[0010] The switching regulator 200 regulates a power supply voltage VIN to an output voltage VOUT and supplies the output voltage VOUT to a load 30. A power supply circuit (not shown) is provided outside or inside the circuit device 100, and the power supply voltage VIN is supplied from the power supply circuit to the circuit device 100. The load 30 is, for example, a microcomputer that controls an electronic device including the switching regulator 200, but is not limited to this and may be various circuits.

[0011] The circuit device 100 includes a switching element 111, an N-type MOS transistor 112, a control circuit 120, a first voltage divider circuit 131, a second voltage divider circuit 132, and a first comparator 150. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. FIG. 1 shows an example in which the switching element 111 and the N-type MOS transistor 112 are built into the circuit device 100, but they may also be provided outside the circuit device 100. FIG. 1 also shows an example in which the inductor 10 and the capacitor 20 are provided outside the circuit device 100, but one or both of them may also be built into the circuit device 100.

[0012] The switching element 111 is a P-type MOS transistor. The source of the switching element 111 is connected to a node of a power supply voltage VIN, and the drain is connected to a node NSW. A drive signal DRP from the control circuit 120 is input to the gate of the switching element 111. When the switching element 111 is on, the inductor 10 is driven by the power supply voltage VIN. Note that the switching element 111 may be any element that can be switched under the control of the control circuit 120, and may be, for example, an N-type MOS transistor or a bipolar transistor.

[0013] The source of the N-type MOS transistor 112 is connected to the ground node, and the drain is connected to the node NSW. A drive signal DRN from the control circuit 120 is input to the gate of the N-type MOS transistor. Although an example in which the switching regulator 200 is a synchronous type has been described here, in the case of an asynchronous type, a diode may be provided instead of the N-type MOS transistor. The anode of the diode may be connected to the ground node, and the cathode may be connected to the node NSW.

[0014] One end of the inductor 10 is connected to the node NSW, and the other end is connected to an output node NVOUT at which the output voltage VOUT is output. One end of the capacitor 20 is connected to the output node NVOUT, and the other end is connected to the ground node.

[0015] The first voltage divider circuit 131 divides the output voltage VOUT and outputs the resulting first feedback voltage FBA to a node NFBA. The first voltage divider circuit 131 includes a resistor RA1 and a resistor RA2. One end of the resistor RA1 is connected to the output node NVOUT and the other end is connected to a node NFBA. One end of the resistor RA2 is connected to the node NFBA and the other end is connected to a ground node. The voltage division ratio is RA2 / (RA1+RA2), and FBA=VOUT×(RA2 / (RA1+RA2)).

[0016] The control circuit 120 pulse-modulates the drive signals DRP and DRN so that the first feedback voltage FBA is a constant voltage, i.e., so that the output voltage VOUT is a given constant voltage. Hereinafter, the given constant voltage may be referred to as a target voltage. Pulse modulation control is, for example, PWM (Pulse Width Modulation) or PFM (Pulse Frequency Modulation), but various similar modulation methods may also be used. For example, in FIG. 4 and subsequent figures, the off timer controls the off time depending on the current value of the load current Id flowing through the load 30 to switch between PFM and PWM, but a constant modulation method may also be used regardless of the load current Id.

[0017] The second voltage divider circuit 132 divides the output voltage VOUT and outputs the resulting second feedback voltage FBB to a node NFBB. The second voltage divider circuit 132 includes resistors RB1 and RB2. One end of the resistor RB1 is connected to the output node NVOUT, and the other end is connected to a node NFBB. One end of the resistor RB2 is connected to the node NFBB, and the other end is connected to a ground node. The voltage division ratio is RB2 / (RB1+RB2), and FBB = VOUT × (RB2 / (RB1+RB2)). The voltage division ratio RB2 / (RB1+RB2) is set so that FBB > VREF when the output voltage VOUT is not transiently changing, that is, when the output voltage VOUT is maintained at a given constant voltage.

[0018] The first comparator 150 compares the second feedback voltage FBB with the reference voltage VREF and outputs the result as a detection signal CMPO. The reference voltage VREF may be supplied, for example, from a voltage generating circuit (not shown) included in the circuit device 100, or may be supplied from outside the circuit device 100. The reference voltage VREF is, for example, a first reference voltage VR1 input to a pulse modulation control circuit 160 (described later with reference to FIG. 4). However, the reference voltage VREF may be different from the first reference voltage VR1.

[0019] FIG. 1 shows an example in which the second feedback voltage FBB is input to the negative input terminal of the first comparator 150 and the first reference voltage VR1 is input to the positive input terminal. The first comparator 150 has hysteresis, with the voltage width of the hysteresis being ΔVHis. When the output voltage VOUT transiently fluctuates, the second feedback voltage FBB also transiently fluctuates. In this case, the first comparator 150 operates as follows: That is, when the detection signal CMPO is at a low level, if the second feedback voltage FBB decreases and reaches the first reference voltage VR1, the detection signal CMPO becomes high. When the detection signal CMPO is at a high level, if the second feedback voltage FBB increases and reaches VR1+ΔVHis, the detection signal CMPO becomes low.

[0020] The control circuit 120 performs pulse modulation control based on the first feedback voltage FBA when the detection signal CMPO is at a low level, and fixes the switching element 111 on and the N-type MOS transistor 112 off when the detection signal CMPO is at a high level. That is, after the second feedback voltage FBB decreases and reaches the first reference voltage VR1, until the second feedback voltage FBB increases and reaches VR1+ΔVHis, the pulse modulation control is ignored, the switching element 111 is fixed on, and the inductor 10 is driven by the power supply voltage VIN.

[0021] 2 shows a second configuration example of the switching regulator 200. The following describes the differences from the first configuration example.

[0022] The circuit device 100 includes a third voltage divider circuit 133. The third voltage divider circuit 133 divides the third reference voltage VR3 and outputs the resulting second reference voltage VR2 to a node NC. The third voltage divider circuit 133 includes resistors RC1 and RC2. One end of the resistor RC1 is connected to the node of the third reference voltage VR3, and the other end is connected to the node NC. One end of the resistor RC2 is connected to the node NC, and the other end is connected to a ground node. The voltage division ratio is RC2 / (RC1+RC2), and VR2=VR3×(RC2 / (RC1+RC2)). The voltage division ratio RC2 / (RC1+RC2) is set so that VOUT>VR2 when the output voltage VOUT is not transiently changing, that is, when the output voltage VOUT is maintained at a given constant voltage.

[0023] The output voltage VOUT is input to the negative input terminal of the first comparator 150 as a second feedback voltage, and the second reference voltage VR2 is input to the positive input terminal as a reference voltage VREF. When the output voltage VOUT transiently fluctuates, the first comparator 150 operates as follows: When the detection signal CMPO is at a low level, the output voltage VOUT decreases and reaches the second reference voltage VR2, and the detection signal CMPO becomes a high level. When the detection signal CMPO is at a high level, the output voltage VOUT increases and reaches VR2+ΔVHis, and the detection signal CMPO becomes a low level.

[0024] The configuration shown in FIG. 2 is merely an example, and it is sufficient that VOUT>VR2 holds when the output voltage VOUT is maintained at a given constant voltage. For example, the first feedback voltage FBA and the second feedback voltage FBB may be configured to have the same potential. As an example of such a configuration, the first voltage divider circuit 131 may be omitted, and the output voltage VOUT may be used as the first feedback voltage FBA. For example, the control circuit 120 performs pulse modulation control so that VOUT=VR1 holds. At this time, the voltage division ratio of the third voltage divider circuit 133 is set so that VR1>VR2 holds. As a result, VOUT=VR1>VR2 holds. Furthermore, a voltage divider circuit that divides VR3 and outputs VR1 may be further provided.

[0025] 3 is a waveform diagram illustrating the operation of the switching regulator 200. Hereinafter, the feedback control via the first voltage dividing circuit 131 and the control circuit 120 will be referred to as the first feedback control, and the feedback control via the second voltage dividing circuit 132, the first comparator 150, and the control circuit 120 will be referred to as the second feedback control.

[0026] As shown in Figure 3, assume that the load current Id is constant and the output voltage VOUT is stable at the target voltage before time ta. The control circuit 120 performs pulse modulation control of the switching element 111 using the drive signal DRP based on the first feedback control. At this time, assume that the load current Id suddenly increases at time ta. The first feedback control responds to fluctuations in the load current Id to keep the output voltage VOUT constant, but the response of the first feedback control is delayed, causing a transient decrease in the output voltage VOUT. If there were no second feedback control, this decrease in the output voltage VOUT would continue until the first feedback control responded.

[0027] In this embodiment, when the output voltage VOUT reaches the first threshold voltage VT1, the second feedback control causes the detection signal CMPO to go high, and the control circuit 120 turns on the switching element 111 using the drive signal DRP based on the detection signal CMPO. The second feedback control then maintains the detection signal CMPO at a high level until the output voltage VOUT rises to the second threshold voltage VT2, and the control circuit 120 keeps the switching element 111 on. The first threshold voltage VT1 satisfies VT1 × (RA2 / (RA1 + RA2)) = VR1 in the configuration example of FIG. 1, and VT1 = VR2 in the configuration example of FIG. 2. The second threshold voltage VT2 satisfies VT2 × (RA2 / (RA1 + RA2)) = VR1 + ΔVHis in the configuration example of FIG. 2, and VT2 = VR2 + ΔVHis. ΔVHis is the voltage width of the hysteresis of the first comparator 150.

[0028] As described above, according to this embodiment, the second feedback control brings the lower limit of the output voltage VOUT close to the first threshold voltage VT1, so that even if the response of the first feedback control is delayed, a decrease in the output voltage VOUT is suppressed. Note that after the output voltage VOUT reaches the second threshold voltage VT2 through the second feedback control, the first feedback control is performed. At this time, it is possible that the output voltage VOUT will decrease again, but once the output voltage VOUT decreases to the first threshold voltage VT1, the second feedback control is performed again, so that the output voltage VOUT is maintained at or above the first threshold voltage VT1. Furthermore, when the operating point of the first feedback control sufficiently tracks fluctuations in the load current Id, the output voltage VOUT gradually approaches the target voltage and stabilizes.

[0029] The response delay of the first feedback control includes, for example, the time until the off-time of the switching element 111 ends when the control circuit 120 uses a timer to control the off-time. Alternatively, the delay includes the time required for the operating point to change when the control circuit 120 includes a circuit that takes time to change the operating point, such as an error amplifier. However, these are only examples of delays, and various delays may occur depending on the configuration of the pulse modulation control. The second feedback control is configured to respond faster than the pulse modulation control, thereby suppressing transient drops in the output voltage VOUT.

[0030] Although the above description has been given of an example in which the detection signal CMPO in the second feedback control is high active, the circuit device 100 may be configured so that the detection signal CMPO is low active.

[0031] Although the above description has been given of an example in which the switching regulator 200 is a step-down DC-DC converter, it may also be a step-up DC-DC converter. In this case, one end of the inductor 10 may be connected to the node of the power supply voltage VIN. The switching element 111 may be an N-type MOS transistor, with its source connected to the ground node and its drain connected to the other end of the inductor 10. In addition, taking an asynchronous type as an example, the anode of a diode may be connected to the other end of the inductor 10 and its cathode may be connected to the node of the output voltage VOUT. One end of the capacitor 20 may be connected to the node of the output voltage VOUT and the other end may be connected to the ground node.

[0032] In this embodiment, the circuit device 100 is used in a switching regulator 200. The switching regulator 200 outputs an output voltage VOUT by regulating a power supply voltage V using an inductor 10 and a switching element 111 that drives the inductor 10. The circuit device 100 includes a control circuit 120 and a first comparator 150. The control circuit 120 receives a first feedback voltage FBA corresponding to the output voltage VOUT, performs pulse modulation control based on the first feedback voltage FBA to maintain the output voltage VOUT at a given constant voltage, and controls the switching of the switching element 111 based on the results of the pulse modulation control. The first comparator 150 receives a second feedback voltage FBB corresponding to the output voltage VOUT, compares the second feedback voltage FBB with a reference voltage VREF, and outputs a detection signal CMPO that becomes active when the second feedback voltage FBB becomes equal to or lower than the reference voltage VREF. The control circuit 120 turns on the switching element 111 when the detection signal CMPO becomes active.

[0033] According to this embodiment, in addition to the first feedback control that controls the switching element 111 based on the first feedback voltage FBA, a second feedback control that controls the switching element 111 based on the second feedback voltage FBB is added. When only the first feedback control is used, there is a problem that the output voltage VOUT transiently drops due to delays in the first feedback control in response to fluctuations in the load current Id. In this regard, according to this embodiment, when the output voltage VOUT drops, the switching element 111 is turned on by high-speed second feedback control, i.e., comparison by the first comparator 150. This reduces the transient drop in the output voltage VOUT. Specifically, the lower limit of the output voltage VOUT can be set near the first threshold voltage VT1 corresponding to the reference voltage VREF.

[0034] Furthermore, in this embodiment, the first comparator 150 may output an active detection signal CMPO from the time when the output voltage VOUT becomes equal to or lower than a first threshold voltage VT1 corresponding to the reference voltage VREF until the output voltage VOUT exceeds a second threshold voltage VT2 defined by hysteresis of the first comparator 150. The control circuit 120 may keep the switching element 111 on while the detection signal CMPO is active.

[0035] According to this embodiment, when the output voltage VOUT drops to the first threshold voltage VT1, the switching element 111 turns on, driving the inductor 10 and increasing the output voltage VOUT. Then, by maintaining the switching element 111 on, the output voltage VOUT increases until it reaches the second threshold voltage VT2. In this way, by providing the second feedback control, the output voltage VOUT is controlled so as not to drop below approximately the first threshold voltage VT1.

[0036] 2. Detailed configuration example An example of the detailed configuration of the control circuit 120 and an example of the operation of the first feedback control and the second feedback control in this example will be described below. Fig. 4 shows an example of the detailed configuration of the control circuit 120. The control circuit 120 includes a pulse modulation control circuit 160, a pre-driver 170, and a backflow detection circuit 180.

[0037] The first feedback control path will now be described. The pulse modulation control circuit 160 performs pulse modulation control to match the first feedback voltage FBA with the first reference voltage VR1 and outputs the result as a pulse signal QOUT. The first reference voltage VR1 may be supplied, for example, from a voltage generation circuit (not shown) included in the circuit device 100, or from an external source. The reverse current detection circuit 180 detects the reverse current of the inductor current IL flowing through the inductor 10. Specifically, a sense resistor RSN is provided between the source of the N-type MOS transistor 112 and the ground node. The reverse current detection circuit 180 is a comparator that compares the voltage VRSN at one end of the sense resistor RSN with the ground voltage and outputs the result as a reverse current detection signal ZCMPO. Figure 4 shows an example in which the voltage VRSN is input to the negative input terminal of the comparator, which is the reverse current detection circuit, and the ground voltage is input to the positive input terminal. When VRSN<0V, a high-level reverse current detection signal ZCMPO is output. When the inductor current IL flows backward, VRSN becomes equal to or greater than 0 V, and a low-level reverse current detection signal ZCMPO is output. Note that the reverse current detection circuit 180 may disable reverse current detection and output a high-level reverse current detection signal ZCMPO when the detection signal CMPO is at a high level or the pulse signal QOUT is at a high level. The pre-driver 170 controls the switching of the switching element 111 and the N-type MOS transistor 112 based on the pulse signal QOUT and the reverse current detection signal ZCMPO.

[0038] The path of the second feedback control will now be described. While FIG. 4 shows an example in which the second feedback control configuration of FIG. 1 is applied, the second feedback control configuration of FIG. 2 can also be applied. When the detection signal CMPO of the first comparator 150 is at a low level, i.e., when a decrease in the output voltage VOUT is not detected, the pre-driver 170 drives the switching element 111 and the N-type MOS transistor 112 based on the first feedback control pulse signal QOUT and the backflow detection signal ZCMPO. When the detection signal CMPO of the first comparator 150 is at a high level, i.e., when a decrease in the output voltage VOUT is detected, the pre-driver 170 turns on the switching element 111 and turns off the N-type MOS transistor 112, ignoring the logical levels of the first feedback control pulse signal QOUT and the backflow detection signal ZCMPO.

[0039] 4 shows an example in which the reference voltage VREF of the first comparator 150 is the same as the first reference voltage VR1 input to the pulse modulation control circuit 160. In this case, the voltage division ratios of the first voltage divider circuit 131 and the second voltage divider circuit 132 are set so that FBB>FBA. In other words, RB2 / (RB1+RB2)>RA2 / (RA1+RA2). When the output voltage VOUT is not transiently changing, that is, when FBA=VR1, FBB>VR1. As a result, in a steady state, the first comparator 150 does not react and switching is controlled by the first feedback control, and when the output voltage VOUT drops, the second feedback control operates.

[0040] The voltage division ratio of the first voltage divider circuit 131 may be variable. For example, the resistor RA2 may be a variable resistor. Since the output voltage VOUT is controlled so that VOUT×(RA2 / (RA1+RA2))=VREF holds, the voltage value of the output voltage VOUT is variably set by variably setting the voltage division ratio. For example, the circuit device 100 may include a register or nonvolatile memory that stores setting information for the voltage division ratio, and the voltage division ratio of the first voltage divider circuit 131 may be set based on the setting information.

[0041] 5 shows a detailed configuration example of the pre-driver 170. The pre-driver 170 includes a NOR circuit 171, an AND circuit 172, and a dead time generation circuit 179.

[0042] The NOR circuit 171 receives the detection signal CMPO and the pulse signal QOUT, and outputs a signal ORQ, which is the NOR of these signals.

[0043] The dead time generation circuit 179 includes an inverting input AND circuit 173, an inverter circuit 174, an AND circuit 175, and a non-inverting buffer 176. The circuit connections are as shown in the figure. The dead time generation circuit 179 outputs drive signals DRP and signal DRNB at the same logical level as signal ORQ. The dead time generation circuit 179 also generates dead time when the logical level of signal ORQ transitions. The dead time is a period during which both the switching element 111 and the N-type MOS transistor 112 are temporarily turned off. Specifically, the dead time generation circuit 179 temporarily outputs a high-level drive signal DRP and a low-level signal DRNB when signal ORQ transitions between high and low levels.

[0044] The AND circuit 172 receives the signal DRNB and the reverse current detection signal ZCMPO, and outputs the logical product of these as the drive signal DRN.

[0045] FIG. 6 is a truth table explaining the operation of the pre-driver 170. Dead time is not taken into consideration here. In FIG. 6, "L" indicates a low level, "H" indicates a high level, and "*" indicates "Don't Care." Furthermore, for the drive signal DRP related to the on / off of the switching element 111, and the signals DRNB and DRN related to the on / off of the N-type MOS transistor 112, the logical level is indicated as "ON(H)" or "ON(H)."

[0046] As shown in the upper table, when the detection signal CMPO is at a low level, that is, when a decrease in the output voltage VOUT is not detected in the second feedback control, the drive signal DRP and the signal DRNB are exclusively on or off depending on the pulse signal QOUT. When the detection signal CMPO is at a high level, that is, when a decrease in the output voltage VOUT is detected in the second feedback control, the drive signal DRP is on and the signal DRNB is off, regardless of the logic level of the pulse signal QOUT.

[0047] As shown in the table below, when the backflow detection signal ZCMPO is at a high level, that is, when no backflow is detected, the drive signal DRN is output at the same logic level as the signal DRNB. When the backflow detection signal ZCMPO is at a low level, that is, when a backflow is detected, the drive signal DRN is a signal indicating off, regardless of the logic level of the signal DRNB.

[0048] 7 shows a detailed configuration example of the pulse modulation control circuit 160. The pulse modulation control circuit 160 includes an error amplifier 161, a second comparator 162, a slope voltage generation circuit 168, and a controller 169. The controller 169 includes an off timer 140 and an RS latch circuit 163.

[0049] Error amplifier 161 amplifies the error between the first feedback voltage FBA and the first reference voltage VR1, and outputs the result as an error voltage COMP. FIG. 7 shows an example in which the first feedback voltage FBA is input to the negative input terminal of the error amplifier 161 and the first reference voltage VR1 is input to the positive input terminal. In this case, the error amplifier 161 decreases the error voltage COMP when FBA > VR1 and increases the error voltage COMP when FBA < VR1. The error amplifier 161 is an integrating circuit that integrates the difference between the first feedback voltage FBA and the first reference voltage VR1, and includes, for example, an operational amplifier and an integrating capacitor. The first reference voltage VR1 is input to the positive input terminal of the operational amplifier, the first feedback voltage FBA is input to the negative input terminal of the operational amplifier, and the output terminal of the operational amplifier and the negative input terminal are fed back by the integrating capacitor.

[0050] Note that the first feedback voltage FBA output by the first voltage dividing circuit 131 is controlled to be near the first reference voltage VR1 by the virtual short of the operational amplifier, and the variation of the output voltage VOUT is not directly reflected. In this regard, by newly providing the second voltage dividing circuit 132, the variation of the output voltage VOUT is directly reflected in the second feedback voltage FBB. Thereby, in the second feedback control, the decrease of the output voltage VOUT is appropriately detected.

[0051] The slope voltage generation circuit 168 generates a slope voltage RAMP whose voltage rises with the passage of time when the pulse signal QOUT is at a high level, and resets the slope voltage RAMP when the pulse signal QOUT is at a low level. The slope voltage is also called a triangular wave. Resetting the slope voltage RAMP means initializing it to the initial voltage of the slope voltage RAMP, that is, the voltage at which the slope starts.

[0052] The second comparator 162 compares the error voltage COMP with the slope voltage RAMP and outputs the result as an output signal COMPO. Fig. 7 shows an example in which the error voltage COMP is input to the negative input terminal of the second comparator 162 and the slope voltage RAMP is input to the positive input terminal.

[0053] The off timer 140 starts when the pulse signal QOUT changes from high to low, that is, when the switching element 111 changes from on to off. When the off timer 140 measures the lapse of the off time, it changes the set signal SET of the RS latch circuit 163 from low to high. This changes the pulse signal QOUT from low to high, and in response, the off timer 140 resets the timer and changes the set signal SET from high to low. The off time measured by the off timer 140 is a period for setting the length of time the switching element 111 is off. The length of the off time may be fixed, or may be variably controlled according to the inductor current IL, as will be described later with reference to FIG. 8.

[0054] The RS latch circuit 163 receives the set signal SET from the off timer 140 and the output signal COMPO from the second comparator 162 as a reset signal, and outputs a pulse signal QOUT based on these set and reset signals.

[0055] 8 shows a detailed configuration example of the off timer 140 when the length of the off time is variable. When this configuration example is applied, the circuit device 100 further includes a current detection circuit 190.

[0056] The current detection circuit 190 detects the inductor current IL and outputs the result as a voltage VIL. The voltage VIL is a voltage that rises as the inductor current IL increases. As an example, the current detection circuit 190 includes a mirror transistor corresponding to the switching element 111. The current detection circuit 190 mirrors the drain current of the switching element 111 by inputting a drive signal DRP to the gate of the mirror transistor and setting the drain of the mirror transistor to the voltage SW of the node NSW. The current detection circuit 190 converts the mirror current to a voltage using a resistor or the like, peak-holds the converted voltage using a switch and a capacitor or the like, and outputs the voltage VIL based on the peak-held voltage.

[0057] The off timer 140 includes a current source 141 , a variable current source 142 , a capacitor 143 , a switch 144 , and a comparator 145 .

[0058] When the pulse signal QOUT is at a high level, that is, when the switching element 111 is on, the switch 144 is on. At this time, both ends of the capacitor 143 are shorted to ground, so the voltage DET1 becomes 0 V. Since VIN-VOUT>0 V in the step-down DC-DC converter, the comparator 145 outputs a low-level set signal SET.

[0059] When the pulse signal QOUT is at a low level, that is, when the switching element 111 is off, the switch 144 is off. Let the capacitance value of the capacitor 143 be Coff. The output current IB1 of the current source 141 is expressed as VIN / Roff. The output current IB2 of the variable current source 142 is 0 A when VIL≧VBS, and is g2×(VBS - VIL) when VIL<VBS. VBS is a bias voltage supplied from a voltage generation circuit not shown. g2 is the voltage-current conversion coefficient in the variable current source 142. At this time, the voltage DET1 is charged by the current (IB1 - IB2) and rises. When DET1>VIN - VOUT, the comparator 145 sets the SET signal from a low level to a high level. As a result, the pulse signal QOUT changes from a low level to a high level.

[0060] The time when the pulse signal QOUT is at a low level is the off time. Let the off time be Toff, then Toff = Coff×(VIN - VOUT) / (IB1 - IB2). When the load current Id is large, the inductor current IL becomes large and the voltage VIL becomes high. When VIL≧VBS, IB2 = 0 A, and at this time Toff=(1 - VOUT / VIN)×Roff×Coff. The length of the off time Toff is constant regardless of the inductor current IL. In the sense that only the on time is controlled, it corresponds to PWM control. When the load current Id is small, the inductor current IL becomes small and the voltage VIL becomes low. When VIL<VBS, IB2 = g2×(VBS - VIL). As the inductor current IL decreases, the voltage VIL decreases and the current IB2 increases, so the length of the off time Toff becomes longer. In the sense that the off time is controlled according to the inductor current IL, it corresponds to PFM control.

[0061] FIG. 9 shows example waveforms illustrating the continuous operation of the switching regulator 200 of FIGS. 4 to 8. Here, it is assumed that the load current Id does not fluctuate and pulse modulation control is performed in the first feedback control. Continuous operation is the operation when the load current Id is relatively large and no backflow of the inductor current IL occurs. Since no backflow occurs, the backflow detection signal ZCMPO is at a high level.

[0062] The period PA is a period during which the switching element 111 is on and the N-type MOS transistor 112 is off. During the period PA, the voltage SW at the node NSW becomes the power supply voltage VIN, the inductor current IL increases, and the output voltage VOUT rises. The period PB is a period during which the switching element 111 is off and the N-type MOS transistor 112 is on. During the period PB, the voltage SW at the node NSW becomes 0 V, the inductor current IL decreases, and the output voltage VOUT drops. In continuous operation, the periods PA and PB make up one switching cycle. Fluctuations in the output voltage VOUT and the inductor current IL due to switching are known as ripples.

[0063] In continuous operation, the off-time Toff corresponds to the period PB. When the off-time Toff ends, the off-timer 140 changes the set signal SET from the low level to the high level. In response to this, the RS latch circuit 163 changes the pulse signal QOUT from the low level to the high level. In response to this, the off-timer 140 changes the set signal SET from the high level to the low level, and the slope voltage generation circuit 168 starts generating the slope voltage RAMP. When the slope voltage RAMP reaches the error voltage COMP, the second comparator 162 changes the output signal COMPO from the low level to the high level. Receiving this as a reset signal, the RS latch circuit 163 changes the pulse signal QOUT from the high level to the low level. In response to this, the slope voltage generation circuit 168 resets the slope voltage RAMP, and the off-timer 140 starts measuring the off-time Toff. Receiving that the slope voltage RAMP has been reset and RAMP < COMP, the second comparator 162 changes the output signal COMPO from the high level to the low level. The off-timer 140 changes the set signal SET from the low level to the high level when the off-time Toff has elapsed. Hereinafter, the same operation is repeated.

[0064] FIG. 10 is an example of waveforms for explaining the discontinuous operation of the switching regulator 200 in FIGS. 4 to 8. Here, it is assumed that the load current Id does not vary and pulse modulation control in the first feedback control is being performed. Discontinuous operation is the operation when the load current Id is relatively small and reverse flow of the inductor current IL occurs. Hereinafter, mainly the differences from FIG. 9 will be described.

[0065] The period PC is the period when the switching element 111 is off and the N-type MOS transistor 112 is off. In the period PC, the node NSW becomes a high impedance state, and the inductor current IL is 0 A. In discontinuous operation, one cycle of switching consists of the periods PA, PB, and PC.

[0066] In discontinuous operation, the off-time Toff corresponds to periods PB and PC. During period PB, when the inductor current IL decreases and reaches 0 A, the reverse current detection signal ZCMPO changes from high to low. In response, the pre-driver 170 changes the N-type MOS transistor 112 from on to off. This initiates period PC, and the N-type MOS transistor 112 is off, preventing the inductor current IL from flowing backward. When the off-time Toff ends, the off-timer 140 changes the set signal SET from low to high. This initiates period PA, and operation is similar to the normal operation shown in FIG. 9 until period PB ends.

[0067] 11 shows waveform examples that schematically illustrate transient operation when the second feedback control is not provided in the configuration examples of FIGS. 4 to 8, i.e., when the first comparator 150 and the second voltage divider circuit 132 are not provided. Before time ta, the load current Id is relatively small, and discontinuous operation occurs. At time ta, the load current Id suddenly increases, and continuous operation occurs for the increased load current Id.

[0068] TonA is the on-time in discontinuous operation, and ToffA is the off-time in discontinuous operation. After the load current Id increases at time ta, the output voltage VOUT drops during the time Δta1 until the next time the switching element 111 is turned on, because the inductor 10 is not driven.

[0069] TonB1, TonB2, and TonB3 are the on-times in continuous operation, and ToffB is the off-time in discontinuous operation. Because the load current Id is large, the off-time ToffB is shorter than the off-time ToffA. Furthermore, as the output voltage VOUT decreases, the error voltage COMP increases, gradually lengthening the on-times TonB1, TonB2, and TonB3. However, because it takes some time for the error voltage COMP to increase, a sufficient on-time is not obtained for some time after time ta, and the output voltage VOUT continues to decrease. The time from when continuous operation begins until the output voltage VOUT stops decreasing is defined as Δta2. The amount of decrease in the output voltage VOUT is defined as ΔVa. As the error voltage COMP increases, a sufficient on-time is obtained, and the output voltage VOUT increases and returns to the target voltage. Note that Figure 11 is a schematic diagram for explaining operation; for example, the change in the error voltage COMP after time ta is actually much more gradual than in Figure 11. After time ta, the error voltage COMP changes slowly, and the ON time of the pulse signal QOUT in continuous operation also increases slowly.

[0070] In this way, the response of the first feedback control is delayed in response to a sudden change in the load current Id, causing the output voltage VOUT to temporarily drop. This drop in the output voltage VOUT may affect the operation of a circuit to which the output voltage VOUT is supplied.

[0071] 12 is a waveform example that schematically illustrates transient operation when a second feedback control is provided as in the configuration examples of FIGS. 4 to 8, that is, when a first comparator 150 and a second voltage dividing circuit 132 are provided. The operation before time ta is the same as in FIG. 11.

[0072] At time ta, when the load current Id increases, the output voltage VOUT decreases. When the output voltage VOUT reaches the first threshold voltage VT1, the first comparator 150 changes the detection signal CMPO from low to high. At this time, the pre-driver 170 turns on the switching element 111, ignoring the pulse signal QOUT generated by the first feedback control. This drives the inductor 10, causing the output voltage VOUT to increase. The time from time ta until the output voltage VOUT reaches the first threshold voltage VT1 is defined as Δtb. The difference between the target voltage of the output voltage VOUT and the first threshold voltage VT1, i.e., the decrease in the output voltage VOUT, is defined as ΔVb. Δtb is shorter than Δta1+Δta2 in FIG. 11, and ΔVb is smaller than ΔVa in FIG. 11.

[0073] The first comparator 150 maintains the detection signal CMPO at a high level until the output voltage VOUT increases and reaches the second threshold voltage VT2. During this time, the switching element 111 is maintained on, and the inductor 10 continues to be driven. Furthermore, since the output voltage VOUT is lower than the target voltage, the error voltage COMP increases.

[0074] After the detection signal CMPO goes low, continuous operation begins. TonC is the on-time during continuous operation, and ToffC is the off-time during continuous operation. Because the error voltage COMP rises while the detection signal CMPO is high, the on-time TonC is longer than the on-time TonB1 in Figure 11. If the on-time TonC is long enough, the output voltage VOUT will rise and return to the target voltage.

[0075] FIG. 13 shows example waveforms obtained by simulating the operation of the switching regulator 200. Line A1 shows the waveform of the output voltage VOUT when the second feedback control is not implemented. Line A2 shows the waveform of the output voltage VOUT when the second feedback control is implemented. The minimum value of the output voltage VOUT shown by line A1 is lower than the first threshold voltage VT1. On the other hand, the minimum value of the output voltage VOUT shown by line A2 is the first threshold voltage VT1, thereby suppressing transient drops in the output voltage VOUT. This waveform example shows an example in which the detection signal CMPO goes high for the first time, causing the output voltage VOUT to rise to the second threshold voltage VT2. However, the error voltage COMP does not rise sufficiently, causing the on-time of the switching element 111 to be insufficient, resulting in a drop in the output voltage VOUT again. Even in this case, when the output voltage VOUT drops to the first threshold voltage VT1, the detection signal CMPO goes high again, turning on the switching element 111. This process is repeated until the on-time is long enough, and the output voltage VOUT returns to the target voltage. FIG. 13 shows an example in which the detection signal CMPO goes high twice.

[0076] In this embodiment, the control circuit 120 includes a pulse modulation control circuit 160 that outputs a pulse signal QOUT under pulse modulation control, and a pre-driver 170 that controls the switching of the switching element 111 based on the pulse signal QOUT and the detection signal CMPO. The pre-driver 170 turns on the switching element 111 when the detection signal CMPO is active, even when the pulse modulation control circuit 160 is outputting the pulse signal QOUT that turns off the switching element 111.

[0077] According to this embodiment, the first feedback control is performed by pulse modulation control, which controls the output voltage VOUT to a given constant voltage based on the first feedback voltage FBA. Even if the switching element 111 is turned off by the first feedback control, the switching element 111 is turned on when a decrease in the output voltage VOUT is detected by the second feedback control, that is, when the detection signal CMPO is active. As a result, fluctuations in the load current Id are not affected by delays in the first feedback control, and the decrease in the output voltage VOUT can be suppressed.

[0078] In this embodiment, the second feedback voltage FBB may be a voltage obtained by dividing the output voltage VOUT, or may be the output voltage VOUT.

[0079] According to the present embodiment, a voltage obtained by dividing the output voltage VOUT or the output voltage VOUT itself is input to the first comparator 150. As a result, second feedback control is performed based on the second feedback voltage FBB according to the output voltage VOUT.

[0080] In addition, in this embodiment, the circuit device 100 may include a first voltage divider circuit 131 that divides the output voltage VOUT and outputs a first feedback voltage FBA to the control circuit 120, and a second voltage divider circuit 132 that divides the output voltage VOUT and outputs a second feedback voltage FBB to the first comparator 150.

[0081] By providing the second voltage divider circuit 132 separately from the first voltage divider circuit 131, it is possible to separate the first feedback voltage FBA used in the first feedback control from the second feedback voltage FBB used in the second feedback control. Depending on the circuit configuration of the first feedback control, it is possible to consider a configuration in which fluctuations in the output voltage VOUT are less likely to be reflected in the first feedback voltage FBA. In this regard, according to the present embodiment, it is possible to newly provide a second feedback voltage FBB that appropriately reflects fluctuations in the output voltage VOUT, and in the second feedback control using this second feedback control, a decrease in the output voltage VOUT is appropriately detected.

[0082] In this embodiment, the control circuit 120 may also include an error amplifier 161 that amplifies the error between the first feedback voltage FBA and the first reference voltage VR1 and outputs the error voltage COMP.

[0083] According to this embodiment, the first feedback voltage FBA is controlled to be close to the first reference voltage VR1 by feedback from the error amplifier 161, so that fluctuations in the output voltage VOUT are less likely to be reflected in the first feedback voltage FBA. In this regard, according to this embodiment, a decrease in the output voltage VOUT is appropriately detected based on the second feedback voltage FBB, which appropriately reflects fluctuations in the output voltage VOUT.

[0084] In this embodiment, a first reference voltage VR1 may be input as the reference voltage VREF to the first comparator 150. The voltage division ratio of the first voltage divider circuit 131 and the second voltage divider circuit 132 may be set so that the second feedback voltage FBB is higher than the first feedback voltage FBA.

[0085] According to this embodiment, when the output voltage VOUT is not transiently changing, the relationship (first feedback voltage FBA) = (first reference voltage VR1) holds. By setting the second feedback voltage FBB to be higher than the first feedback voltage FBA, the relationship (second feedback voltage FBB) > (first reference voltage VR1) holds. As a result, in a steady state, the first comparator 150 does not react and switching is controlled by the first feedback control, and when the output voltage VOUT drops, the second feedback control operates.

[0086] In this embodiment, the circuit device 100 may also include a third voltage divider circuit 133 that divides the third reference voltage VR3 and outputs a second reference voltage VR2. The output voltage VOUT may be input to the first comparator 150 as the second feedback voltage FBB, and the second reference voltage VR2 may be input to the first comparator 150 as the reference voltage VREF. The voltage division ratio of the third voltage divider circuit 133 may be set so that the second feedback voltage FBB is higher than the second reference voltage VR2 when the output voltage VOUT is a given constant voltage.

[0087] According to this embodiment, the output voltage VOUT itself can be used as the second feedback voltage FBB input to the first comparator 150. When the output voltage VOUT is not transiently changing, the voltage division ratio is set so that (second feedback voltage FBB)>(second reference voltage VR2). As a result, in a steady state, the first comparator 150 does not react and switching is controlled by the first feedback control, and when the output voltage VOUT drops, the second feedback control operates.

[0088] In this embodiment, the control circuit 120 may also include an error amplifier 161 that amplifies the error between the first feedback voltage FBA and the first reference voltage VR1 and outputs the error voltage COMP.

[0089] According to this embodiment, fluctuations in the output voltage VOUT are less likely to be reflected in the first feedback voltage FBA due to the feedback of the error amplifier 161. In this regard, according to this embodiment, the second feedback control is performed based on the output voltage VOUT itself, so that a decrease in the output voltage VOUT is appropriately detected.

[0090] In this embodiment, the pulse modulation control circuit 160 may also include an error amplifier 161 that amplifies the error between the first feedback voltage FBA and the first reference voltage VR1 and outputs the error voltage COMP, and a slope voltage generation circuit 168 that generates the slope voltage RAMP. The pulse modulation control circuit 160 may also include a second comparator 162 that compares the error voltage COMP with the slope voltage RAMP, and a controller 169 that outputs a pulse signal QOUT based on the output signal COMPO of the second comparator 162.

[0091] According to this embodiment, the pulse signal QOUT is output based on the output signal COMPO, which is the result of comparing the error voltage COMP with the slope voltage RAMP, and the switching of the switching element 111 is controlled based on the pulse signal QOUT. As a result, in the first feedback control, the pulse signal QOUT is modulated and controlled so that the output voltage VOUT becomes a given constant voltage.

[0092] In this embodiment, the controller 169 may also include an off timer 140 and an RS latch circuit 163. The off timer 140 may set the length of an off time during which the switching element 111 is off. The RS latch circuit 163 may output a pulse signal QOUT that changes the switching element 111 from off to on when the off time ends, and may output a pulse signal QOUT that changes the switching element 111 from on to off when the second comparator 162 determines that the slope voltage RAMP has reached the error voltage COMP.

[0093] According to this embodiment, the off-time is determined by the off-timer 140. The on-time is controlled based on a comparison between the error voltage COMP and the slope voltage RAMP so that the output voltage VOUT becomes a given constant voltage. This performs pulse modulation control of the first feedback control. Note that, as described with reference to FIG. 8, the off-time may vary depending on the inductor current IL.

[0094] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be within the scope of the present disclosure. For example, a term described at least once in the specification or drawings with a different, broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also within the scope of the present disclosure. Furthermore, the configurations and operations of the pulse modulation control circuit, pre-driver, control circuit, first voltage divider circuit, second voltage divider circuit, circuit device, load, and switching regulator are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0095] 10...inductor, 20...capacitor, 30...load, 100...circuit device, 111...switching element, 112...N-type MOS transistor, 120...control circuit, 131...first voltage divider circuit, 132...second voltage divider circuit, 133...third voltage divider circuit, 140...off timer, 150...first comparator, 160...pulse modulation control circuit, 161...error amplifier, 162...second comparator, 163...RS latch circuit, 168...slope voltage generation circuit, 170...pre-driver, 180...comparator 190...current detection circuit, 200...switching regulator, CMPO...detection signal, COMP...error voltage, FBA...first feedback voltage, FBB...second feedback voltage, IL...inductor current, Id...load current, RAMP...slope voltage, QOUT...pulse signal, Toff...off time, VIN...power supply voltage, VOUT...output voltage, VR1...first reference voltage, VR2...second reference voltage, VR3...third reference voltage, VREF...reference voltage, VT1...first threshold voltage, VT2...second threshold voltage

Claims

1. A circuit device used in a switching regulator that outputs an output voltage by regulating a power supply voltage using an inductor and a switching element that drives the inductor, a control circuit that receives a first feedback voltage corresponding to the output voltage, performs pulse modulation control based on the first feedback voltage to control the output voltage to a given constant voltage, and controls switching of the switching element based on a result of the pulse modulation control; a first comparator that receives a second feedback voltage corresponding to the output voltage, compares the second feedback voltage with a reference voltage, and outputs a detection signal that becomes active when the second feedback voltage becomes equal to or lower than the reference voltage; Including, The control circuit turns on the switching element when the detection signal becomes active.

2. 2. The circuit device according to claim 1, The control circuit a pulse modulation control circuit that outputs a pulse signal through the pulse modulation control; a pre-driver that controls the switching of the switching element based on the pulse signal and the detection signal; Including, The pre-driver turns on the switching element when the detection signal is active, even when the pulse modulation control circuit outputs the pulse signal that turns off the switching element.

3. 2. The circuit device according to claim 1, the first comparator outputs the detection signal that is active from when the output voltage becomes equal to or lower than a first threshold voltage corresponding to the reference voltage until the output voltage exceeds a second threshold voltage determined by hysteresis of the first comparator; The control circuit maintains the switching element on while the detection signal is active.

4. 2. The circuit device according to claim 1, The second feedback voltage is a voltage obtained by dividing the output voltage, or is the output voltage.

5. 2. The circuit device according to claim 1, a first voltage dividing circuit that divides the output voltage and outputs the first feedback voltage to the control circuit; a second voltage divider circuit that divides the output voltage and outputs the second feedback voltage to the first comparator; A circuit device comprising:

6. 6. The circuit device according to claim 5, The circuit device is characterized in that the control circuit includes an error amplifier that amplifies an error between the first feedback voltage and a first reference voltage and outputs an error voltage.

7. 7. The circuit device according to claim 6, The first reference voltage is input to the first comparator as the reference voltage, A circuit device according to claim 1, wherein a voltage division ratio of the first voltage divider circuit and the second voltage divider circuit is set so that the second feedback voltage is higher than the first feedback voltage.

8. 2. The circuit device according to claim 1, a third voltage dividing circuit that divides the third reference voltage and outputs the second reference voltage; the output voltage is input to the first comparator as the second feedback voltage, and the second reference voltage is input to the first comparator as the reference voltage; The voltage division ratio of the third voltage divider circuit is A circuit device, characterized in that the second feedback voltage is set to be higher than the second reference voltage when the output voltage is the given constant voltage.

9. 3. The circuit device according to claim 2, The pulse modulation control circuit an error amplifier that amplifies an error between the first feedback voltage and a first reference voltage and outputs an error voltage; a slope voltage generating circuit that generates a slope voltage; a second comparator that compares the error voltage with the slope voltage; a controller that outputs the pulse signal based on the output signal of the second comparator; A circuit device comprising:

10. 10. The circuit device according to claim 9, The controller an off timer that sets the length of an off time during which the switching element is off; an RS latch circuit that outputs the pulse signal that changes the switching element from off to on when the off time ends, and outputs the pulse signal that changes the switching element from on to off when the second comparator determines that the slope voltage has reached the error voltage; A circuit device comprising:

11. A circuit arrangement according to any one of claims 1 to 10; the switching element; the inductor; A switching regulator comprising:

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